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ayabusa
2025-09-05 10:30:26 +02:00
commit c144fcd356
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build/stm32f4xx_it.lst Normal file
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ARM GAS /tmp/ccjI409r.s page 1
1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 20, 1
5 .eabi_attribute 21, 1
6 .eabi_attribute 23, 3
7 .eabi_attribute 24, 1
8 .eabi_attribute 25, 1
9 .eabi_attribute 26, 1
10 .eabi_attribute 30, 1
11 .eabi_attribute 34, 1
12 .eabi_attribute 18, 4
13 .file "stm32f4xx_it.c"
14 .text
15 .Ltext0:
16 .cfi_sections .debug_frame
17 .section .text.NMI_Handler,"ax",%progbits
18 .align 1
19 .global NMI_Handler
20 .arch armv7e-m
21 .syntax unified
22 .thumb
23 .thumb_func
24 .fpu fpv4-sp-d16
26 NMI_Handler:
27 .LFB134:
28 .file 1 "Core/Src/stm32f4xx_it.c"
1:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Header */
2:Core/Src/stm32f4xx_it.c **** /**
3:Core/Src/stm32f4xx_it.c **** ******************************************************************************
4:Core/Src/stm32f4xx_it.c **** * @file stm32f4xx_it.c
5:Core/Src/stm32f4xx_it.c **** * @brief Interrupt Service Routines.
6:Core/Src/stm32f4xx_it.c **** ******************************************************************************
7:Core/Src/stm32f4xx_it.c **** * @attention
8:Core/Src/stm32f4xx_it.c **** *
9:Core/Src/stm32f4xx_it.c **** * Copyright (c) 2025 STMicroelectronics.
10:Core/Src/stm32f4xx_it.c **** * All rights reserved.
11:Core/Src/stm32f4xx_it.c **** *
12:Core/Src/stm32f4xx_it.c **** * This software is licensed under terms that can be found in the LICENSE file
13:Core/Src/stm32f4xx_it.c **** * in the root directory of this software component.
14:Core/Src/stm32f4xx_it.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
15:Core/Src/stm32f4xx_it.c **** *
16:Core/Src/stm32f4xx_it.c **** ******************************************************************************
17:Core/Src/stm32f4xx_it.c **** */
18:Core/Src/stm32f4xx_it.c **** /* USER CODE END Header */
19:Core/Src/stm32f4xx_it.c ****
20:Core/Src/stm32f4xx_it.c **** /* Includes ------------------------------------------------------------------*/
21:Core/Src/stm32f4xx_it.c **** #include "main.h"
22:Core/Src/stm32f4xx_it.c **** #include "stm32f4xx_it.h"
23:Core/Src/stm32f4xx_it.c **** /* Private includes ----------------------------------------------------------*/
24:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN Includes */
25:Core/Src/stm32f4xx_it.c **** /* USER CODE END Includes */
26:Core/Src/stm32f4xx_it.c ****
27:Core/Src/stm32f4xx_it.c **** /* Private typedef -----------------------------------------------------------*/
28:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN TD */
29:Core/Src/stm32f4xx_it.c ****
30:Core/Src/stm32f4xx_it.c **** /* USER CODE END TD */
ARM GAS /tmp/ccjI409r.s page 2
31:Core/Src/stm32f4xx_it.c ****
32:Core/Src/stm32f4xx_it.c **** /* Private define ------------------------------------------------------------*/
33:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PD */
34:Core/Src/stm32f4xx_it.c ****
35:Core/Src/stm32f4xx_it.c **** /* USER CODE END PD */
36:Core/Src/stm32f4xx_it.c ****
37:Core/Src/stm32f4xx_it.c **** /* Private macro -------------------------------------------------------------*/
38:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PM */
39:Core/Src/stm32f4xx_it.c ****
40:Core/Src/stm32f4xx_it.c **** /* USER CODE END PM */
41:Core/Src/stm32f4xx_it.c ****
42:Core/Src/stm32f4xx_it.c **** /* Private variables ---------------------------------------------------------*/
43:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PV */
44:Core/Src/stm32f4xx_it.c ****
45:Core/Src/stm32f4xx_it.c **** /* USER CODE END PV */
46:Core/Src/stm32f4xx_it.c ****
47:Core/Src/stm32f4xx_it.c **** /* Private function prototypes -----------------------------------------------*/
48:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PFP */
49:Core/Src/stm32f4xx_it.c ****
50:Core/Src/stm32f4xx_it.c **** /* USER CODE END PFP */
51:Core/Src/stm32f4xx_it.c ****
52:Core/Src/stm32f4xx_it.c **** /* Private user code ---------------------------------------------------------*/
53:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN 0 */
54:Core/Src/stm32f4xx_it.c ****
55:Core/Src/stm32f4xx_it.c **** /* USER CODE END 0 */
56:Core/Src/stm32f4xx_it.c ****
57:Core/Src/stm32f4xx_it.c **** /* External variables --------------------------------------------------------*/
58:Core/Src/stm32f4xx_it.c ****
59:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN EV */
60:Core/Src/stm32f4xx_it.c ****
61:Core/Src/stm32f4xx_it.c **** /* USER CODE END EV */
62:Core/Src/stm32f4xx_it.c ****
63:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
64:Core/Src/stm32f4xx_it.c **** /* Cortex-M4 Processor Interruption and Exception Handlers */
65:Core/Src/stm32f4xx_it.c **** /******************************************************************************/
66:Core/Src/stm32f4xx_it.c **** /**
67:Core/Src/stm32f4xx_it.c **** * @brief This function handles Non maskable interrupt.
68:Core/Src/stm32f4xx_it.c **** */
69:Core/Src/stm32f4xx_it.c **** void NMI_Handler(void)
70:Core/Src/stm32f4xx_it.c **** {
29 .loc 1 70 1 view -0
30 .cfi_startproc
31 @ Volatile: function does not return.
32 @ args = 0, pretend = 0, frame = 0
33 @ frame_needed = 0, uses_anonymous_args = 0
34 @ link register save eliminated.
35 .L2:
71:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
72:Core/Src/stm32f4xx_it.c ****
73:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 0 */
74:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
75:Core/Src/stm32f4xx_it.c **** while (1)
36 .loc 1 75 4 discriminator 1 view .LVU1
76:Core/Src/stm32f4xx_it.c **** {
77:Core/Src/stm32f4xx_it.c **** }
37 .loc 1 77 3 discriminator 1 view .LVU2
75:Core/Src/stm32f4xx_it.c **** {
ARM GAS /tmp/ccjI409r.s page 3
38 .loc 1 75 10 discriminator 1 view .LVU3
39 0000 FEE7 b .L2
40 .cfi_endproc
41 .LFE134:
43 .section .text.HardFault_Handler,"ax",%progbits
44 .align 1
45 .global HardFault_Handler
46 .syntax unified
47 .thumb
48 .thumb_func
49 .fpu fpv4-sp-d16
51 HardFault_Handler:
52 .LFB135:
78:Core/Src/stm32f4xx_it.c **** /* USER CODE END NonMaskableInt_IRQn 1 */
79:Core/Src/stm32f4xx_it.c **** }
80:Core/Src/stm32f4xx_it.c ****
81:Core/Src/stm32f4xx_it.c **** /**
82:Core/Src/stm32f4xx_it.c **** * @brief This function handles Hard fault interrupt.
83:Core/Src/stm32f4xx_it.c **** */
84:Core/Src/stm32f4xx_it.c **** void HardFault_Handler(void)
85:Core/Src/stm32f4xx_it.c **** {
53 .loc 1 85 1 view -0
54 .cfi_startproc
55 @ Volatile: function does not return.
56 @ args = 0, pretend = 0, frame = 0
57 @ frame_needed = 0, uses_anonymous_args = 0
58 @ link register save eliminated.
59 .L4:
86:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN HardFault_IRQn 0 */
87:Core/Src/stm32f4xx_it.c ****
88:Core/Src/stm32f4xx_it.c **** /* USER CODE END HardFault_IRQn 0 */
89:Core/Src/stm32f4xx_it.c **** while (1)
60 .loc 1 89 3 discriminator 1 view .LVU5
90:Core/Src/stm32f4xx_it.c **** {
91:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_HardFault_IRQn 0 */
92:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_HardFault_IRQn 0 */
93:Core/Src/stm32f4xx_it.c **** }
61 .loc 1 93 3 discriminator 1 view .LVU6
89:Core/Src/stm32f4xx_it.c **** {
62 .loc 1 89 9 discriminator 1 view .LVU7
63 0000 FEE7 b .L4
64 .cfi_endproc
65 .LFE135:
67 .section .text.MemManage_Handler,"ax",%progbits
68 .align 1
69 .global MemManage_Handler
70 .syntax unified
71 .thumb
72 .thumb_func
73 .fpu fpv4-sp-d16
75 MemManage_Handler:
76 .LFB136:
94:Core/Src/stm32f4xx_it.c **** }
95:Core/Src/stm32f4xx_it.c ****
96:Core/Src/stm32f4xx_it.c **** /**
97:Core/Src/stm32f4xx_it.c **** * @brief This function handles Memory management fault.
98:Core/Src/stm32f4xx_it.c **** */
ARM GAS /tmp/ccjI409r.s page 4
99:Core/Src/stm32f4xx_it.c **** void MemManage_Handler(void)
100:Core/Src/stm32f4xx_it.c **** {
77 .loc 1 100 1 view -0
78 .cfi_startproc
79 @ Volatile: function does not return.
80 @ args = 0, pretend = 0, frame = 0
81 @ frame_needed = 0, uses_anonymous_args = 0
82 @ link register save eliminated.
83 .L6:
101:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN MemoryManagement_IRQn 0 */
102:Core/Src/stm32f4xx_it.c ****
103:Core/Src/stm32f4xx_it.c **** /* USER CODE END MemoryManagement_IRQn 0 */
104:Core/Src/stm32f4xx_it.c **** while (1)
84 .loc 1 104 3 discriminator 1 view .LVU9
105:Core/Src/stm32f4xx_it.c **** {
106:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */
107:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_MemoryManagement_IRQn 0 */
108:Core/Src/stm32f4xx_it.c **** }
85 .loc 1 108 3 discriminator 1 view .LVU10
104:Core/Src/stm32f4xx_it.c **** {
86 .loc 1 104 9 discriminator 1 view .LVU11
87 0000 FEE7 b .L6
88 .cfi_endproc
89 .LFE136:
91 .section .text.BusFault_Handler,"ax",%progbits
92 .align 1
93 .global BusFault_Handler
94 .syntax unified
95 .thumb
96 .thumb_func
97 .fpu fpv4-sp-d16
99 BusFault_Handler:
100 .LFB137:
109:Core/Src/stm32f4xx_it.c **** }
110:Core/Src/stm32f4xx_it.c ****
111:Core/Src/stm32f4xx_it.c **** /**
112:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pre-fetch fault, memory access fault.
113:Core/Src/stm32f4xx_it.c **** */
114:Core/Src/stm32f4xx_it.c **** void BusFault_Handler(void)
115:Core/Src/stm32f4xx_it.c **** {
101 .loc 1 115 1 view -0
102 .cfi_startproc
103 @ Volatile: function does not return.
104 @ args = 0, pretend = 0, frame = 0
105 @ frame_needed = 0, uses_anonymous_args = 0
106 @ link register save eliminated.
107 .L8:
116:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN BusFault_IRQn 0 */
117:Core/Src/stm32f4xx_it.c ****
118:Core/Src/stm32f4xx_it.c **** /* USER CODE END BusFault_IRQn 0 */
119:Core/Src/stm32f4xx_it.c **** while (1)
108 .loc 1 119 3 discriminator 1 view .LVU13
120:Core/Src/stm32f4xx_it.c **** {
121:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_BusFault_IRQn 0 */
122:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_BusFault_IRQn 0 */
123:Core/Src/stm32f4xx_it.c **** }
109 .loc 1 123 3 discriminator 1 view .LVU14
ARM GAS /tmp/ccjI409r.s page 5
119:Core/Src/stm32f4xx_it.c **** {
110 .loc 1 119 9 discriminator 1 view .LVU15
111 0000 FEE7 b .L8
112 .cfi_endproc
113 .LFE137:
115 .section .text.UsageFault_Handler,"ax",%progbits
116 .align 1
117 .global UsageFault_Handler
118 .syntax unified
119 .thumb
120 .thumb_func
121 .fpu fpv4-sp-d16
123 UsageFault_Handler:
124 .LFB138:
124:Core/Src/stm32f4xx_it.c **** }
125:Core/Src/stm32f4xx_it.c ****
126:Core/Src/stm32f4xx_it.c **** /**
127:Core/Src/stm32f4xx_it.c **** * @brief This function handles Undefined instruction or illegal state.
128:Core/Src/stm32f4xx_it.c **** */
129:Core/Src/stm32f4xx_it.c **** void UsageFault_Handler(void)
130:Core/Src/stm32f4xx_it.c **** {
125 .loc 1 130 1 view -0
126 .cfi_startproc
127 @ Volatile: function does not return.
128 @ args = 0, pretend = 0, frame = 0
129 @ frame_needed = 0, uses_anonymous_args = 0
130 @ link register save eliminated.
131 .L10:
131:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN UsageFault_IRQn 0 */
132:Core/Src/stm32f4xx_it.c ****
133:Core/Src/stm32f4xx_it.c **** /* USER CODE END UsageFault_IRQn 0 */
134:Core/Src/stm32f4xx_it.c **** while (1)
132 .loc 1 134 3 discriminator 1 view .LVU17
135:Core/Src/stm32f4xx_it.c **** {
136:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN W1_UsageFault_IRQn 0 */
137:Core/Src/stm32f4xx_it.c **** /* USER CODE END W1_UsageFault_IRQn 0 */
138:Core/Src/stm32f4xx_it.c **** }
133 .loc 1 138 3 discriminator 1 view .LVU18
134:Core/Src/stm32f4xx_it.c **** {
134 .loc 1 134 9 discriminator 1 view .LVU19
135 0000 FEE7 b .L10
136 .cfi_endproc
137 .LFE138:
139 .section .text.SVC_Handler,"ax",%progbits
140 .align 1
141 .global SVC_Handler
142 .syntax unified
143 .thumb
144 .thumb_func
145 .fpu fpv4-sp-d16
147 SVC_Handler:
148 .LFB139:
139:Core/Src/stm32f4xx_it.c **** }
140:Core/Src/stm32f4xx_it.c ****
141:Core/Src/stm32f4xx_it.c **** /**
142:Core/Src/stm32f4xx_it.c **** * @brief This function handles System service call via SWI instruction.
143:Core/Src/stm32f4xx_it.c **** */
ARM GAS /tmp/ccjI409r.s page 6
144:Core/Src/stm32f4xx_it.c **** void SVC_Handler(void)
145:Core/Src/stm32f4xx_it.c **** {
149 .loc 1 145 1 view -0
150 .cfi_startproc
151 @ args = 0, pretend = 0, frame = 0
152 @ frame_needed = 0, uses_anonymous_args = 0
153 @ link register save eliminated.
146:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 0 */
147:Core/Src/stm32f4xx_it.c ****
148:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 0 */
149:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SVCall_IRQn 1 */
150:Core/Src/stm32f4xx_it.c ****
151:Core/Src/stm32f4xx_it.c **** /* USER CODE END SVCall_IRQn 1 */
152:Core/Src/stm32f4xx_it.c **** }
154 .loc 1 152 1 view .LVU21
155 0000 7047 bx lr
156 .cfi_endproc
157 .LFE139:
159 .section .text.DebugMon_Handler,"ax",%progbits
160 .align 1
161 .global DebugMon_Handler
162 .syntax unified
163 .thumb
164 .thumb_func
165 .fpu fpv4-sp-d16
167 DebugMon_Handler:
168 .LFB140:
153:Core/Src/stm32f4xx_it.c ****
154:Core/Src/stm32f4xx_it.c **** /**
155:Core/Src/stm32f4xx_it.c **** * @brief This function handles Debug monitor.
156:Core/Src/stm32f4xx_it.c **** */
157:Core/Src/stm32f4xx_it.c **** void DebugMon_Handler(void)
158:Core/Src/stm32f4xx_it.c **** {
169 .loc 1 158 1 view -0
170 .cfi_startproc
171 @ args = 0, pretend = 0, frame = 0
172 @ frame_needed = 0, uses_anonymous_args = 0
173 @ link register save eliminated.
159:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 0 */
160:Core/Src/stm32f4xx_it.c ****
161:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 0 */
162:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN DebugMonitor_IRQn 1 */
163:Core/Src/stm32f4xx_it.c ****
164:Core/Src/stm32f4xx_it.c **** /* USER CODE END DebugMonitor_IRQn 1 */
165:Core/Src/stm32f4xx_it.c **** }
174 .loc 1 165 1 view .LVU23
175 0000 7047 bx lr
176 .cfi_endproc
177 .LFE140:
179 .section .text.PendSV_Handler,"ax",%progbits
180 .align 1
181 .global PendSV_Handler
182 .syntax unified
183 .thumb
184 .thumb_func
185 .fpu fpv4-sp-d16
187 PendSV_Handler:
ARM GAS /tmp/ccjI409r.s page 7
188 .LFB141:
166:Core/Src/stm32f4xx_it.c ****
167:Core/Src/stm32f4xx_it.c **** /**
168:Core/Src/stm32f4xx_it.c **** * @brief This function handles Pendable request for system service.
169:Core/Src/stm32f4xx_it.c **** */
170:Core/Src/stm32f4xx_it.c **** void PendSV_Handler(void)
171:Core/Src/stm32f4xx_it.c **** {
189 .loc 1 171 1 view -0
190 .cfi_startproc
191 @ args = 0, pretend = 0, frame = 0
192 @ frame_needed = 0, uses_anonymous_args = 0
193 @ link register save eliminated.
172:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 0 */
173:Core/Src/stm32f4xx_it.c ****
174:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 0 */
175:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN PendSV_IRQn 1 */
176:Core/Src/stm32f4xx_it.c ****
177:Core/Src/stm32f4xx_it.c **** /* USER CODE END PendSV_IRQn 1 */
178:Core/Src/stm32f4xx_it.c **** }
194 .loc 1 178 1 view .LVU25
195 0000 7047 bx lr
196 .cfi_endproc
197 .LFE141:
199 .section .text.SysTick_Handler,"ax",%progbits
200 .align 1
201 .global SysTick_Handler
202 .syntax unified
203 .thumb
204 .thumb_func
205 .fpu fpv4-sp-d16
207 SysTick_Handler:
208 .LFB142:
179:Core/Src/stm32f4xx_it.c ****
180:Core/Src/stm32f4xx_it.c **** /**
181:Core/Src/stm32f4xx_it.c **** * @brief This function handles System tick timer.
182:Core/Src/stm32f4xx_it.c **** */
183:Core/Src/stm32f4xx_it.c **** void SysTick_Handler(void)
184:Core/Src/stm32f4xx_it.c **** {
209 .loc 1 184 1 view -0
210 .cfi_startproc
211 @ args = 0, pretend = 0, frame = 0
212 @ frame_needed = 0, uses_anonymous_args = 0
213 0000 08B5 push {r3, lr}
214 .LCFI0:
215 .cfi_def_cfa_offset 8
216 .cfi_offset 3, -8
217 .cfi_offset 14, -4
185:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 0 */
186:Core/Src/stm32f4xx_it.c ****
187:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 0 */
188:Core/Src/stm32f4xx_it.c **** HAL_IncTick();
218 .loc 1 188 3 view .LVU27
219 0002 FFF7FEFF bl HAL_IncTick
220 .LVL0:
189:Core/Src/stm32f4xx_it.c **** /* USER CODE BEGIN SysTick_IRQn 1 */
190:Core/Src/stm32f4xx_it.c ****
191:Core/Src/stm32f4xx_it.c **** /* USER CODE END SysTick_IRQn 1 */
ARM GAS /tmp/ccjI409r.s page 8
192:Core/Src/stm32f4xx_it.c **** }
221 .loc 1 192 1 is_stmt 0 view .LVU28
222 0006 08BD pop {r3, pc}
223 .cfi_endproc
224 .LFE142:
226 .text
227 .Letext0:
228 .file 2 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h"
ARM GAS /tmp/ccjI409r.s page 9
DEFINED SYMBOLS
*ABS*:0000000000000000 stm32f4xx_it.c
/tmp/ccjI409r.s:18 .text.NMI_Handler:0000000000000000 $t
/tmp/ccjI409r.s:26 .text.NMI_Handler:0000000000000000 NMI_Handler
/tmp/ccjI409r.s:44 .text.HardFault_Handler:0000000000000000 $t
/tmp/ccjI409r.s:51 .text.HardFault_Handler:0000000000000000 HardFault_Handler
/tmp/ccjI409r.s:68 .text.MemManage_Handler:0000000000000000 $t
/tmp/ccjI409r.s:75 .text.MemManage_Handler:0000000000000000 MemManage_Handler
/tmp/ccjI409r.s:92 .text.BusFault_Handler:0000000000000000 $t
/tmp/ccjI409r.s:99 .text.BusFault_Handler:0000000000000000 BusFault_Handler
/tmp/ccjI409r.s:116 .text.UsageFault_Handler:0000000000000000 $t
/tmp/ccjI409r.s:123 .text.UsageFault_Handler:0000000000000000 UsageFault_Handler
/tmp/ccjI409r.s:140 .text.SVC_Handler:0000000000000000 $t
/tmp/ccjI409r.s:147 .text.SVC_Handler:0000000000000000 SVC_Handler
/tmp/ccjI409r.s:160 .text.DebugMon_Handler:0000000000000000 $t
/tmp/ccjI409r.s:167 .text.DebugMon_Handler:0000000000000000 DebugMon_Handler
/tmp/ccjI409r.s:180 .text.PendSV_Handler:0000000000000000 $t
/tmp/ccjI409r.s:187 .text.PendSV_Handler:0000000000000000 PendSV_Handler
/tmp/ccjI409r.s:200 .text.SysTick_Handler:0000000000000000 $t
/tmp/ccjI409r.s:207 .text.SysTick_Handler:0000000000000000 SysTick_Handler
UNDEFINED SYMBOLS
HAL_IncTick