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ayabusa
2025-09-05 10:30:26 +02:00
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ARM GAS /tmp/cc9poKmu.s page 1
1 .cpu cortex-m4
2 .eabi_attribute 27, 1
3 .eabi_attribute 28, 1
4 .eabi_attribute 20, 1
5 .eabi_attribute 21, 1
6 .eabi_attribute 23, 3
7 .eabi_attribute 24, 1
8 .eabi_attribute 25, 1
9 .eabi_attribute 26, 1
10 .eabi_attribute 30, 1
11 .eabi_attribute 34, 1
12 .eabi_attribute 18, 4
13 .file "system_stm32f4xx.c"
14 .text
15 .Ltext0:
16 .cfi_sections .debug_frame
17 .section .text.SystemInit,"ax",%progbits
18 .align 1
19 .global SystemInit
20 .arch armv7e-m
21 .syntax unified
22 .thumb
23 .thumb_func
24 .fpu fpv4-sp-d16
26 SystemInit:
27 .LFB134:
28 .file 1 "Core/Src/system_stm32f4xx.c"
1:Core/Src/system_stm32f4xx.c **** /**
2:Core/Src/system_stm32f4xx.c **** ******************************************************************************
3:Core/Src/system_stm32f4xx.c **** * @file system_stm32f4xx.c
4:Core/Src/system_stm32f4xx.c **** * @author MCD Application Team
5:Core/Src/system_stm32f4xx.c **** * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
6:Core/Src/system_stm32f4xx.c **** *
7:Core/Src/system_stm32f4xx.c **** * This file provides two functions and one global variable to be called from
8:Core/Src/system_stm32f4xx.c **** * user application:
9:Core/Src/system_stm32f4xx.c **** * - SystemInit(): This function is called at startup just after reset and
10:Core/Src/system_stm32f4xx.c **** * before branch to main program. This call is made inside
11:Core/Src/system_stm32f4xx.c **** * the "startup_stm32f4xx.s" file.
12:Core/Src/system_stm32f4xx.c **** *
13:Core/Src/system_stm32f4xx.c **** * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
14:Core/Src/system_stm32f4xx.c **** * by the user application to setup the SysTick
15:Core/Src/system_stm32f4xx.c **** * timer or configure other parameters.
16:Core/Src/system_stm32f4xx.c **** *
17:Core/Src/system_stm32f4xx.c **** * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
18:Core/Src/system_stm32f4xx.c **** * be called whenever the core clock is changed
19:Core/Src/system_stm32f4xx.c **** * during program execution.
20:Core/Src/system_stm32f4xx.c **** *
21:Core/Src/system_stm32f4xx.c **** *
22:Core/Src/system_stm32f4xx.c **** ******************************************************************************
23:Core/Src/system_stm32f4xx.c **** * @attention
24:Core/Src/system_stm32f4xx.c **** *
25:Core/Src/system_stm32f4xx.c **** * Copyright (c) 2017 STMicroelectronics.
26:Core/Src/system_stm32f4xx.c **** * All rights reserved.
27:Core/Src/system_stm32f4xx.c **** *
28:Core/Src/system_stm32f4xx.c **** * This software is licensed under terms that can be found in the LICENSE file
29:Core/Src/system_stm32f4xx.c **** * in the root directory of this software component.
30:Core/Src/system_stm32f4xx.c **** * If no LICENSE file comes with this software, it is provided AS-IS.
ARM GAS /tmp/cc9poKmu.s page 2
31:Core/Src/system_stm32f4xx.c **** *
32:Core/Src/system_stm32f4xx.c **** ******************************************************************************
33:Core/Src/system_stm32f4xx.c **** */
34:Core/Src/system_stm32f4xx.c ****
35:Core/Src/system_stm32f4xx.c **** /** @addtogroup CMSIS
36:Core/Src/system_stm32f4xx.c **** * @{
37:Core/Src/system_stm32f4xx.c **** */
38:Core/Src/system_stm32f4xx.c ****
39:Core/Src/system_stm32f4xx.c **** /** @addtogroup stm32f4xx_system
40:Core/Src/system_stm32f4xx.c **** * @{
41:Core/Src/system_stm32f4xx.c **** */
42:Core/Src/system_stm32f4xx.c ****
43:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Includes
44:Core/Src/system_stm32f4xx.c **** * @{
45:Core/Src/system_stm32f4xx.c **** */
46:Core/Src/system_stm32f4xx.c ****
47:Core/Src/system_stm32f4xx.c ****
48:Core/Src/system_stm32f4xx.c **** #include "stm32f4xx.h"
49:Core/Src/system_stm32f4xx.c ****
50:Core/Src/system_stm32f4xx.c **** #if !defined (HSE_VALUE)
51:Core/Src/system_stm32f4xx.c **** #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */
52:Core/Src/system_stm32f4xx.c **** #endif /* HSE_VALUE */
53:Core/Src/system_stm32f4xx.c ****
54:Core/Src/system_stm32f4xx.c **** #if !defined (HSI_VALUE)
55:Core/Src/system_stm32f4xx.c **** #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
56:Core/Src/system_stm32f4xx.c **** #endif /* HSI_VALUE */
57:Core/Src/system_stm32f4xx.c ****
58:Core/Src/system_stm32f4xx.c **** /**
59:Core/Src/system_stm32f4xx.c **** * @}
60:Core/Src/system_stm32f4xx.c **** */
61:Core/Src/system_stm32f4xx.c ****
62:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
63:Core/Src/system_stm32f4xx.c **** * @{
64:Core/Src/system_stm32f4xx.c **** */
65:Core/Src/system_stm32f4xx.c ****
66:Core/Src/system_stm32f4xx.c **** /**
67:Core/Src/system_stm32f4xx.c **** * @}
68:Core/Src/system_stm32f4xx.c **** */
69:Core/Src/system_stm32f4xx.c ****
70:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Defines
71:Core/Src/system_stm32f4xx.c **** * @{
72:Core/Src/system_stm32f4xx.c **** */
73:Core/Src/system_stm32f4xx.c ****
74:Core/Src/system_stm32f4xx.c **** /************************* Miscellaneous Configuration ************************/
75:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */
76:Core/Src/system_stm32f4xx.c **** #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\
77:Core/Src/system_stm32f4xx.c **** || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
78:Core/Src/system_stm32f4xx.c **** || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx)
79:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSRAM */
80:Core/Src/system_stm32f4xx.c **** #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||
81:Core/Src/system_stm32f4xx.c **** STM32F412Zx || STM32F412Vx */
82:Core/Src/system_stm32f4xx.c ****
83:Core/Src/system_stm32f4xx.c **** #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\
84:Core/Src/system_stm32f4xx.c **** || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
85:Core/Src/system_stm32f4xx.c **** /* #define DATA_IN_ExtSDRAM */
86:Core/Src/system_stm32f4xx.c **** #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||
87:Core/Src/system_stm32f4xx.c **** STM32F479xx */
ARM GAS /tmp/cc9poKmu.s page 3
88:Core/Src/system_stm32f4xx.c ****
89:Core/Src/system_stm32f4xx.c **** /* Note: Following vector table addresses must be defined in line with linker
90:Core/Src/system_stm32f4xx.c **** configuration. */
91:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate the vector table
92:Core/Src/system_stm32f4xx.c **** anywhere in Flash or Sram, else the vector table is kept at the automatic
93:Core/Src/system_stm32f4xx.c **** remap of boot address selected */
94:Core/Src/system_stm32f4xx.c **** /* #define USER_VECT_TAB_ADDRESS */
95:Core/Src/system_stm32f4xx.c ****
96:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
97:Core/Src/system_stm32f4xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table
98:Core/Src/system_stm32f4xx.c **** in Sram else user remap will be done in Flash. */
99:Core/Src/system_stm32f4xx.c **** /* #define VECT_TAB_SRAM */
100:Core/Src/system_stm32f4xx.c **** #if defined(VECT_TAB_SRAM)
101:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field.
102:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
103:Core/Src/system_stm32f4xx.c **** #else
104:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field.
105:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
106:Core/Src/system_stm32f4xx.c **** #endif /* VECT_TAB_SRAM */
107:Core/Src/system_stm32f4xx.c **** #if !defined(VECT_TAB_OFFSET)
108:Core/Src/system_stm32f4xx.c **** #define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field.
109:Core/Src/system_stm32f4xx.c **** This value must be a multiple of 0x200. */
110:Core/Src/system_stm32f4xx.c **** #endif /* VECT_TAB_OFFSET */
111:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
112:Core/Src/system_stm32f4xx.c **** /******************************************************************************/
113:Core/Src/system_stm32f4xx.c ****
114:Core/Src/system_stm32f4xx.c **** /**
115:Core/Src/system_stm32f4xx.c **** * @}
116:Core/Src/system_stm32f4xx.c **** */
117:Core/Src/system_stm32f4xx.c ****
118:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Macros
119:Core/Src/system_stm32f4xx.c **** * @{
120:Core/Src/system_stm32f4xx.c **** */
121:Core/Src/system_stm32f4xx.c ****
122:Core/Src/system_stm32f4xx.c **** /**
123:Core/Src/system_stm32f4xx.c **** * @}
124:Core/Src/system_stm32f4xx.c **** */
125:Core/Src/system_stm32f4xx.c ****
126:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Variables
127:Core/Src/system_stm32f4xx.c **** * @{
128:Core/Src/system_stm32f4xx.c **** */
129:Core/Src/system_stm32f4xx.c **** /* This variable is updated in three ways:
130:Core/Src/system_stm32f4xx.c **** 1) by calling CMSIS function SystemCoreClockUpdate()
131:Core/Src/system_stm32f4xx.c **** 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
132:Core/Src/system_stm32f4xx.c **** 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
133:Core/Src/system_stm32f4xx.c **** Note: If you use this function to configure the system clock; then there
134:Core/Src/system_stm32f4xx.c **** is no need to call the 2 first functions listed above, since SystemCoreClock
135:Core/Src/system_stm32f4xx.c **** variable is updated automatically.
136:Core/Src/system_stm32f4xx.c **** */
137:Core/Src/system_stm32f4xx.c **** uint32_t SystemCoreClock = 16000000;
138:Core/Src/system_stm32f4xx.c **** const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
139:Core/Src/system_stm32f4xx.c **** const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
140:Core/Src/system_stm32f4xx.c **** /**
141:Core/Src/system_stm32f4xx.c **** * @}
142:Core/Src/system_stm32f4xx.c **** */
143:Core/Src/system_stm32f4xx.c ****
144:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
ARM GAS /tmp/cc9poKmu.s page 4
145:Core/Src/system_stm32f4xx.c **** * @{
146:Core/Src/system_stm32f4xx.c **** */
147:Core/Src/system_stm32f4xx.c ****
148:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
149:Core/Src/system_stm32f4xx.c **** static void SystemInit_ExtMemCtl(void);
150:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
151:Core/Src/system_stm32f4xx.c ****
152:Core/Src/system_stm32f4xx.c **** /**
153:Core/Src/system_stm32f4xx.c **** * @}
154:Core/Src/system_stm32f4xx.c **** */
155:Core/Src/system_stm32f4xx.c ****
156:Core/Src/system_stm32f4xx.c **** /** @addtogroup STM32F4xx_System_Private_Functions
157:Core/Src/system_stm32f4xx.c **** * @{
158:Core/Src/system_stm32f4xx.c **** */
159:Core/Src/system_stm32f4xx.c ****
160:Core/Src/system_stm32f4xx.c **** /**
161:Core/Src/system_stm32f4xx.c **** * @brief Setup the microcontroller system
162:Core/Src/system_stm32f4xx.c **** * Initialize the FPU setting, vector table location and External memory
163:Core/Src/system_stm32f4xx.c **** * configuration.
164:Core/Src/system_stm32f4xx.c **** * @param None
165:Core/Src/system_stm32f4xx.c **** * @retval None
166:Core/Src/system_stm32f4xx.c **** */
167:Core/Src/system_stm32f4xx.c **** void SystemInit(void)
168:Core/Src/system_stm32f4xx.c **** {
29 .loc 1 168 1 view -0
30 .cfi_startproc
31 @ args = 0, pretend = 0, frame = 0
32 @ frame_needed = 0, uses_anonymous_args = 0
33 @ link register save eliminated.
169:Core/Src/system_stm32f4xx.c **** /* FPU settings ------------------------------------------------------------*/
170:Core/Src/system_stm32f4xx.c **** #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
171:Core/Src/system_stm32f4xx.c **** SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
34 .loc 1 171 5 view .LVU1
35 .loc 1 171 16 is_stmt 0 view .LVU2
36 0000 034A ldr r2, .L2
37 0002 D2F88830 ldr r3, [r2, #136]
38 0006 43F47003 orr r3, r3, #15728640
39 000a C2F88830 str r3, [r2, #136]
172:Core/Src/system_stm32f4xx.c **** #endif
173:Core/Src/system_stm32f4xx.c ****
174:Core/Src/system_stm32f4xx.c **** #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
175:Core/Src/system_stm32f4xx.c **** SystemInit_ExtMemCtl();
176:Core/Src/system_stm32f4xx.c **** #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
177:Core/Src/system_stm32f4xx.c ****
178:Core/Src/system_stm32f4xx.c **** /* Configure the Vector Table location -------------------------------------*/
179:Core/Src/system_stm32f4xx.c **** #if defined(USER_VECT_TAB_ADDRESS)
180:Core/Src/system_stm32f4xx.c **** SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM
181:Core/Src/system_stm32f4xx.c **** #endif /* USER_VECT_TAB_ADDRESS */
182:Core/Src/system_stm32f4xx.c **** }
40 .loc 1 182 1 view .LVU3
41 000e 7047 bx lr
42 .L3:
43 .align 2
44 .L2:
45 0010 00ED00E0 .word -536810240
46 .cfi_endproc
47 .LFE134:
ARM GAS /tmp/cc9poKmu.s page 5
49 .section .text.SystemCoreClockUpdate,"ax",%progbits
50 .align 1
51 .global SystemCoreClockUpdate
52 .syntax unified
53 .thumb
54 .thumb_func
55 .fpu fpv4-sp-d16
57 SystemCoreClockUpdate:
58 .LFB135:
183:Core/Src/system_stm32f4xx.c ****
184:Core/Src/system_stm32f4xx.c **** /**
185:Core/Src/system_stm32f4xx.c **** * @brief Update SystemCoreClock variable according to Clock Register Values.
186:Core/Src/system_stm32f4xx.c **** * The SystemCoreClock variable contains the core clock (HCLK), it can
187:Core/Src/system_stm32f4xx.c **** * be used by the user application to setup the SysTick timer or configure
188:Core/Src/system_stm32f4xx.c **** * other parameters.
189:Core/Src/system_stm32f4xx.c **** *
190:Core/Src/system_stm32f4xx.c **** * @note Each time the core clock (HCLK) changes, this function must be called
191:Core/Src/system_stm32f4xx.c **** * to update SystemCoreClock variable value. Otherwise, any configuration
192:Core/Src/system_stm32f4xx.c **** * based on this variable will be incorrect.
193:Core/Src/system_stm32f4xx.c **** *
194:Core/Src/system_stm32f4xx.c **** * @note - The system frequency computed by this function is not the real
195:Core/Src/system_stm32f4xx.c **** * frequency in the chip. It is calculated based on the predefined
196:Core/Src/system_stm32f4xx.c **** * constant and the selected clock source:
197:Core/Src/system_stm32f4xx.c **** *
198:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
199:Core/Src/system_stm32f4xx.c **** *
200:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
201:Core/Src/system_stm32f4xx.c **** *
202:Core/Src/system_stm32f4xx.c **** * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
203:Core/Src/system_stm32f4xx.c **** * or HSI_VALUE(*) multiplied/divided by the PLL factors.
204:Core/Src/system_stm32f4xx.c **** *
205:Core/Src/system_stm32f4xx.c **** * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
206:Core/Src/system_stm32f4xx.c **** * 16 MHz) but the real value may vary depending on the variations
207:Core/Src/system_stm32f4xx.c **** * in voltage and temperature.
208:Core/Src/system_stm32f4xx.c **** *
209:Core/Src/system_stm32f4xx.c **** * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
210:Core/Src/system_stm32f4xx.c **** * depends on the application requirements), user has to ensure that HSE_VALUE
211:Core/Src/system_stm32f4xx.c **** * is same as the real frequency of the crystal used. Otherwise, this function
212:Core/Src/system_stm32f4xx.c **** * may have wrong result.
213:Core/Src/system_stm32f4xx.c **** *
214:Core/Src/system_stm32f4xx.c **** * - The result of this function could be not correct when using fractional
215:Core/Src/system_stm32f4xx.c **** * value for HSE crystal.
216:Core/Src/system_stm32f4xx.c **** *
217:Core/Src/system_stm32f4xx.c **** * @param None
218:Core/Src/system_stm32f4xx.c **** * @retval None
219:Core/Src/system_stm32f4xx.c **** */
220:Core/Src/system_stm32f4xx.c **** void SystemCoreClockUpdate(void)
221:Core/Src/system_stm32f4xx.c **** {
59 .loc 1 221 1 is_stmt 1 view -0
60 .cfi_startproc
61 @ args = 0, pretend = 0, frame = 0
62 @ frame_needed = 0, uses_anonymous_args = 0
63 @ link register save eliminated.
222:Core/Src/system_stm32f4xx.c **** uint32_t tmp, pllvco, pllp, pllsource, pllm;
64 .loc 1 222 3 view .LVU5
223:Core/Src/system_stm32f4xx.c ****
224:Core/Src/system_stm32f4xx.c **** /* Get SYSCLK source -------------------------------------------------------*/
ARM GAS /tmp/cc9poKmu.s page 6
225:Core/Src/system_stm32f4xx.c **** tmp = RCC->CFGR & RCC_CFGR_SWS;
65 .loc 1 225 3 view .LVU6
66 .loc 1 225 12 is_stmt 0 view .LVU7
67 0000 224B ldr r3, .L12
68 0002 9B68 ldr r3, [r3, #8]
69 .loc 1 225 7 view .LVU8
70 0004 03F00C03 and r3, r3, #12
71 .LVL0:
226:Core/Src/system_stm32f4xx.c ****
227:Core/Src/system_stm32f4xx.c **** switch (tmp)
72 .loc 1 227 3 is_stmt 1 view .LVU9
73 0008 042B cmp r3, #4
74 000a 14D0 beq .L5
75 000c 082B cmp r3, #8
76 000e 16D0 beq .L6
77 0010 1BB1 cbz r3, .L11
228:Core/Src/system_stm32f4xx.c **** {
229:Core/Src/system_stm32f4xx.c **** case 0x00: /* HSI used as system clock source */
230:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
231:Core/Src/system_stm32f4xx.c **** break;
232:Core/Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */
233:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSE_VALUE;
234:Core/Src/system_stm32f4xx.c **** break;
235:Core/Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
236:Core/Src/system_stm32f4xx.c ****
237:Core/Src/system_stm32f4xx.c **** /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
238:Core/Src/system_stm32f4xx.c **** SYSCLK = PLL_VCO / PLL_P
239:Core/Src/system_stm32f4xx.c **** */
240:Core/Src/system_stm32f4xx.c **** pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
241:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
242:Core/Src/system_stm32f4xx.c ****
243:Core/Src/system_stm32f4xx.c **** if (pllsource != 0)
244:Core/Src/system_stm32f4xx.c **** {
245:Core/Src/system_stm32f4xx.c **** /* HSE used as PLL clock source */
246:Core/Src/system_stm32f4xx.c **** pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
247:Core/Src/system_stm32f4xx.c **** }
248:Core/Src/system_stm32f4xx.c **** else
249:Core/Src/system_stm32f4xx.c **** {
250:Core/Src/system_stm32f4xx.c **** /* HSI used as PLL clock source */
251:Core/Src/system_stm32f4xx.c **** pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
252:Core/Src/system_stm32f4xx.c **** }
253:Core/Src/system_stm32f4xx.c ****
254:Core/Src/system_stm32f4xx.c **** pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
255:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
256:Core/Src/system_stm32f4xx.c **** break;
257:Core/Src/system_stm32f4xx.c **** default:
258:Core/Src/system_stm32f4xx.c **** SystemCoreClock = HSI_VALUE;
78 .loc 1 258 7 view .LVU10
79 .loc 1 258 23 is_stmt 0 view .LVU11
80 0012 1F4B ldr r3, .L12+4
81 .LVL1:
82 .loc 1 258 23 view .LVU12
83 0014 1F4A ldr r2, .L12+8
84 0016 1A60 str r2, [r3]
259:Core/Src/system_stm32f4xx.c **** break;
85 .loc 1 259 7 is_stmt 1 view .LVU13
86 0018 02E0 b .L8
ARM GAS /tmp/cc9poKmu.s page 7
87 .LVL2:
88 .L11:
230:Core/Src/system_stm32f4xx.c **** break;
89 .loc 1 230 7 view .LVU14
230:Core/Src/system_stm32f4xx.c **** break;
90 .loc 1 230 23 is_stmt 0 view .LVU15
91 001a 1D4B ldr r3, .L12+4
92 .LVL3:
230:Core/Src/system_stm32f4xx.c **** break;
93 .loc 1 230 23 view .LVU16
94 001c 1D4A ldr r2, .L12+8
95 001e 1A60 str r2, [r3]
231:Core/Src/system_stm32f4xx.c **** case 0x04: /* HSE used as system clock source */
96 .loc 1 231 7 is_stmt 1 view .LVU17
97 .L8:
260:Core/Src/system_stm32f4xx.c **** }
261:Core/Src/system_stm32f4xx.c **** /* Compute HCLK frequency --------------------------------------------------*/
262:Core/Src/system_stm32f4xx.c **** /* Get HCLK prescaler */
263:Core/Src/system_stm32f4xx.c **** tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
98 .loc 1 263 3 view .LVU18
99 .loc 1 263 28 is_stmt 0 view .LVU19
100 0020 1A4B ldr r3, .L12
101 0022 9B68 ldr r3, [r3, #8]
102 .loc 1 263 52 view .LVU20
103 0024 C3F30313 ubfx r3, r3, #4, #4
104 .loc 1 263 22 view .LVU21
105 0028 1B4A ldr r2, .L12+12
106 002a D15C ldrb r1, [r2, r3] @ zero_extendqisi2
107 .LVL4:
264:Core/Src/system_stm32f4xx.c **** /* HCLK frequency */
265:Core/Src/system_stm32f4xx.c **** SystemCoreClock >>= tmp;
108 .loc 1 265 3 is_stmt 1 view .LVU22
109 .loc 1 265 19 is_stmt 0 view .LVU23
110 002c 184A ldr r2, .L12+4
111 002e 1368 ldr r3, [r2]
112 0030 CB40 lsrs r3, r3, r1
113 0032 1360 str r3, [r2]
266:Core/Src/system_stm32f4xx.c **** }
114 .loc 1 266 1 view .LVU24
115 0034 7047 bx lr
116 .LVL5:
117 .L5:
233:Core/Src/system_stm32f4xx.c **** break;
118 .loc 1 233 7 is_stmt 1 view .LVU25
233:Core/Src/system_stm32f4xx.c **** break;
119 .loc 1 233 23 is_stmt 0 view .LVU26
120 0036 164B ldr r3, .L12+4
121 .LVL6:
233:Core/Src/system_stm32f4xx.c **** break;
122 .loc 1 233 23 view .LVU27
123 0038 184A ldr r2, .L12+16
124 003a 1A60 str r2, [r3]
234:Core/Src/system_stm32f4xx.c **** case 0x08: /* PLL used as system clock source */
125 .loc 1 234 7 is_stmt 1 view .LVU28
126 003c F0E7 b .L8
127 .LVL7:
128 .L6:
ARM GAS /tmp/cc9poKmu.s page 8
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
129 .loc 1 240 7 view .LVU29
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
130 .loc 1 240 23 is_stmt 0 view .LVU30
131 003e 134B ldr r3, .L12
132 .LVL8:
240:Core/Src/system_stm32f4xx.c **** pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
133 .loc 1 240 23 view .LVU31
134 0040 5968 ldr r1, [r3, #4]
135 .LVL9:
241:Core/Src/system_stm32f4xx.c ****
136 .loc 1 241 7 is_stmt 1 view .LVU32
241:Core/Src/system_stm32f4xx.c ****
137 .loc 1 241 17 is_stmt 0 view .LVU33
138 0042 5A68 ldr r2, [r3, #4]
241:Core/Src/system_stm32f4xx.c ****
139 .loc 1 241 12 view .LVU34
140 0044 02F03F02 and r2, r2, #63
141 .LVL10:
243:Core/Src/system_stm32f4xx.c **** {
142 .loc 1 243 7 is_stmt 1 view .LVU35
243:Core/Src/system_stm32f4xx.c **** {
143 .loc 1 243 10 is_stmt 0 view .LVU36
144 0048 11F4800F tst r1, #4194304
145 004c 13D0 beq .L9
246:Core/Src/system_stm32f4xx.c **** }
146 .loc 1 246 9 is_stmt 1 view .LVU37
246:Core/Src/system_stm32f4xx.c **** }
147 .loc 1 246 29 is_stmt 0 view .LVU38
148 004e 134B ldr r3, .L12+16
149 0050 B3FBF2F3 udiv r3, r3, r2
246:Core/Src/system_stm32f4xx.c **** }
150 .loc 1 246 44 view .LVU39
151 0054 0D4A ldr r2, .L12
152 .LVL11:
246:Core/Src/system_stm32f4xx.c **** }
153 .loc 1 246 44 view .LVU40
154 0056 5268 ldr r2, [r2, #4]
246:Core/Src/system_stm32f4xx.c **** }
155 .loc 1 246 74 view .LVU41
156 0058 C2F38812 ubfx r2, r2, #6, #9
246:Core/Src/system_stm32f4xx.c **** }
157 .loc 1 246 16 view .LVU42
158 005c 02FB03F3 mul r3, r2, r3
159 .LVL12:
160 .L10:
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
161 .loc 1 254 7 is_stmt 1 view .LVU43
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
162 .loc 1 254 20 is_stmt 0 view .LVU44
163 0060 0A4A ldr r2, .L12
164 0062 5268 ldr r2, [r2, #4]
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
165 .loc 1 254 50 view .LVU45
166 0064 C2F30142 ubfx r2, r2, #16, #2
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
167 .loc 1 254 56 view .LVU46
ARM GAS /tmp/cc9poKmu.s page 9
168 0068 0132 adds r2, r2, #1
254:Core/Src/system_stm32f4xx.c **** SystemCoreClock = pllvco/pllp;
169 .loc 1 254 12 view .LVU47
170 006a 5200 lsls r2, r2, #1
171 .LVL13:
255:Core/Src/system_stm32f4xx.c **** break;
172 .loc 1 255 7 is_stmt 1 view .LVU48
255:Core/Src/system_stm32f4xx.c **** break;
173 .loc 1 255 31 is_stmt 0 view .LVU49
174 006c B3FBF2F3 udiv r3, r3, r2
175 .LVL14:
255:Core/Src/system_stm32f4xx.c **** break;
176 .loc 1 255 23 view .LVU50
177 0070 074A ldr r2, .L12+4
178 .LVL15:
255:Core/Src/system_stm32f4xx.c **** break;
179 .loc 1 255 23 view .LVU51
180 0072 1360 str r3, [r2]
256:Core/Src/system_stm32f4xx.c **** default:
181 .loc 1 256 7 is_stmt 1 view .LVU52
182 0074 D4E7 b .L8
183 .LVL16:
184 .L9:
251:Core/Src/system_stm32f4xx.c **** }
185 .loc 1 251 9 view .LVU53
251:Core/Src/system_stm32f4xx.c **** }
186 .loc 1 251 29 is_stmt 0 view .LVU54
187 0076 074B ldr r3, .L12+8
188 0078 B3FBF2F3 udiv r3, r3, r2
251:Core/Src/system_stm32f4xx.c **** }
189 .loc 1 251 44 view .LVU55
190 007c 034A ldr r2, .L12
191 .LVL17:
251:Core/Src/system_stm32f4xx.c **** }
192 .loc 1 251 44 view .LVU56
193 007e 5268 ldr r2, [r2, #4]
251:Core/Src/system_stm32f4xx.c **** }
194 .loc 1 251 74 view .LVU57
195 0080 C2F38812 ubfx r2, r2, #6, #9
251:Core/Src/system_stm32f4xx.c **** }
196 .loc 1 251 16 view .LVU58
197 0084 02FB03F3 mul r3, r2, r3
198 .LVL18:
251:Core/Src/system_stm32f4xx.c **** }
199 .loc 1 251 16 view .LVU59
200 0088 EAE7 b .L10
201 .L13:
202 008a 00BF .align 2
203 .L12:
204 008c 00380240 .word 1073887232
205 0090 00000000 .word .LANCHOR0
206 0094 0024F400 .word 16000000
207 0098 00000000 .word .LANCHOR1
208 009c 00127A00 .word 8000000
209 .cfi_endproc
210 .LFE135:
212 .global APBPrescTable
ARM GAS /tmp/cc9poKmu.s page 10
213 .global AHBPrescTable
214 .global SystemCoreClock
215 .section .data.SystemCoreClock,"aw"
216 .align 2
217 .set .LANCHOR0,. + 0
220 SystemCoreClock:
221 0000 0024F400 .word 16000000
222 .section .rodata.AHBPrescTable,"a"
223 .align 2
224 .set .LANCHOR1,. + 0
227 AHBPrescTable:
228 0000 00000000 .ascii "\000\000\000\000\000\000\000\000\001\002\003\004\006"
228 00000000
228 01020304
228 06
229 000d 070809 .ascii "\007\010\011"
230 .section .rodata.APBPrescTable,"a"
231 .align 2
234 APBPrescTable:
235 0000 00000000 .ascii "\000\000\000\000\001\002\003\004"
235 01020304
236 .text
237 .Letext0:
238 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h"
239 .file 3 "Drivers/CMSIS/Include/core_cm4.h"
240 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h"
241 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h"
ARM GAS /tmp/cc9poKmu.s page 11
DEFINED SYMBOLS
*ABS*:0000000000000000 system_stm32f4xx.c
/tmp/cc9poKmu.s:18 .text.SystemInit:0000000000000000 $t
/tmp/cc9poKmu.s:26 .text.SystemInit:0000000000000000 SystemInit
/tmp/cc9poKmu.s:45 .text.SystemInit:0000000000000010 $d
/tmp/cc9poKmu.s:50 .text.SystemCoreClockUpdate:0000000000000000 $t
/tmp/cc9poKmu.s:57 .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
/tmp/cc9poKmu.s:204 .text.SystemCoreClockUpdate:000000000000008c $d
/tmp/cc9poKmu.s:234 .rodata.APBPrescTable:0000000000000000 APBPrescTable
/tmp/cc9poKmu.s:227 .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
/tmp/cc9poKmu.s:220 .data.SystemCoreClock:0000000000000000 SystemCoreClock
/tmp/cc9poKmu.s:216 .data.SystemCoreClock:0000000000000000 $d
/tmp/cc9poKmu.s:223 .rodata.AHBPrescTable:0000000000000000 $d
/tmp/cc9poKmu.s:231 .rodata.APBPrescTable:0000000000000000 $d
NO UNDEFINED SYMBOLS