ARM GAS /tmp/ccg6eVgO.s page 1 1 .cpu cortex-m4 2 .eabi_attribute 27, 1 3 .eabi_attribute 28, 1 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 1 12 .eabi_attribute 18, 4 13 .file "main.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .section .text.MX_GPIO_Init,"ax",%progbits 18 .align 1 19 .arch armv7e-m 20 .syntax unified 21 .thumb 22 .thumb_func 23 .fpu fpv4-sp-d16 25 MX_GPIO_Init: 26 .LFB151: 27 .file 1 "Core/Src/main.c" 1:Core/Src/main.c **** /** 2:Core/Src/main.c **** ****************************************************************************** 3:Core/Src/main.c **** * @file : main.c 4:Core/Src/main.c **** * @brief : Main program body 5:Core/Src/main.c **** ****************************************************************************** 6:Core/Src/main.c **** * @attention 7:Core/Src/main.c **** * 8:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics. 9:Core/Src/main.c **** * All rights reserved. 10:Core/Src/main.c **** * 11:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 12:Core/Src/main.c **** * in the root directory of this software component. 13:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 14:Core/Src/main.c **** * 15:Core/Src/main.c **** ****************************************************************************** 16:Core/Src/main.c **** */ 17:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 18:Core/Src/main.c **** #include "main.h" 19:Core/Src/main.c **** #include 20:Core/Src/main.c **** #include 21:Core/Src/main.c **** #include 22:Core/Src/main.c **** 23:Core/Src/main.c **** 24:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 25:Core/Src/main.c **** UART_HandleTypeDef huart2; 26:Core/Src/main.c **** 27:Core/Src/main.c **** 28:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 29:Core/Src/main.c **** void SystemClock_Config(void); 30:Core/Src/main.c **** static void MX_GPIO_Init(void); 31:Core/Src/main.c **** static void MX_USART2_UART_Init(void); ARM GAS /tmp/ccg6eVgO.s page 2 32:Core/Src/main.c **** 33:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 34:Core/Src/main.c **** 35:Core/Src/main.c **** /** 36:Core/Src/main.c **** * @brief The application entry point. 37:Core/Src/main.c **** * @retval int 38:Core/Src/main.c **** */ 39:Core/Src/main.c **** int main(void) 40:Core/Src/main.c **** { 41:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 42:Core/Src/main.c **** 43:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 44:Core/Src/main.c **** HAL_Init(); 45:Core/Src/main.c **** 46:Core/Src/main.c **** /* Configure the system clock */ 47:Core/Src/main.c **** SystemClock_Config(); 48:Core/Src/main.c **** 49:Core/Src/main.c **** /* Initialize all configured peripherals */ 50:Core/Src/main.c **** MX_GPIO_Init(); 51:Core/Src/main.c **** MX_USART2_UART_Init(); 52:Core/Src/main.c **** 53:Core/Src/main.c **** Data_Pins_Init(0); 54:Core/Src/main.c **** Address_Pins_Init(); 55:Core/Src/main.c **** Command_Pins_Init(); 56:Core/Src/main.c **** 57:Core/Src/main.c **** int man_id, dev_id; 58:Core/Src/main.c **** Enter_Device_ID(&man_id, &dev_id); 59:Core/Src/main.c **** 60:Core/Src/main.c **** char *manufacturer = (char*)malloc(13 * sizeof(char)); 61:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 62:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 63:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 64:Core/Src/main.c **** 65:Core/Src/main.c **** debug_print("Manufacturer ID = \r\n"); 66:Core/Src/main.c **** debug_print(manufacturer); 67:Core/Src/main.c **** debug_print("Device ID = \r\n"); 68:Core/Src/main.c **** debug_print(device); 69:Core/Src/main.c **** 70:Core/Src/main.c **** 71:Core/Src/main.c **** /* Infinite loop */ 72:Core/Src/main.c **** while (1) 73:Core/Src/main.c **** { 74:Core/Src/main.c **** //debug_print("Hello from STM32!\r\n"); 75:Core/Src/main.c **** } 76:Core/Src/main.c **** 77:Core/Src/main.c **** } 78:Core/Src/main.c **** 79:Core/Src/main.c **** void Write_Address(int address){ 80:Core/Src/main.c **** int pin_array[] = { 81:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 82:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 83:Core/Src/main.c **** GPIO_PIN_8, GPIO_PIN_9, GPIO_PIN_10, GPIO_PIN_11, 84:Core/Src/main.c **** GPIO_PIN_12, GPIO_PIN_13, 85:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, GPIO_PIN_4 // These last 3 are our PB pins not 86:Core/Src/main.c **** }; 87:Core/Src/main.c **** for(int i=0; i<19; i++){ 88:Core/Src/main.c **** if(i<14){ ARM GAS /tmp/ccg6eVgO.s page 3 89:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 90:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 91:Core/Src/main.c **** } 92:Core/Src/main.c **** else{ 93:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_SET); 94:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 95:Core/Src/main.c **** } 96:Core/Src/main.c **** } 97:Core/Src/main.c **** } 98:Core/Src/main.c **** 99:Core/Src/main.c **** int Receive_Data(void){ 100:Core/Src/main.c **** Data_Pins_Init(0); // We make sure it's in input mode 101:Core/Src/main.c **** int result = 0; 102:Core/Src/main.c **** int pin_array[] = { 103:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 104:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 105:Core/Src/main.c **** }; 106:Core/Src/main.c **** for(int i=0; i<8; i++){ 107:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 108:Core/Src/main.c **** result += 1 << i; 109:Core/Src/main.c **** } 110:Core/Src/main.c **** } 111:Core/Src/main.c **** return result; 112:Core/Src/main.c **** } 113:Core/Src/main.c **** 114:Core/Src/main.c **** void Write_Data(int value){ 115:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 116:Core/Src/main.c **** int pin_array[] = { 117:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 118:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 119:Core/Src/main.c **** }; 120:Core/Src/main.c **** for(int i=0; i<8; i++){ 121:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 122:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 123:Core/Src/main.c **** } 124:Core/Src/main.c **** } 125:Core/Src/main.c **** 126:Core/Src/main.c **** // All arguments must be 0 (low) or 1 (high) 127:Core/Src/main.c **** void Write_Command_Pins(int CE, int OE, int WE){ 128:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 129:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 130:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10,(WE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 131:Core/Src/main.c **** } 132:Core/Src/main.c **** 133:Core/Src/main.c **** void Write_Command(int addr, int data) { 134:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 135:Core/Src/main.c **** Write_Address(addr); 136:Core/Src/main.c **** Write_Data(data); 137:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); 138:Core/Src/main.c **** // 4. Pulse WE# low to latch data 139:Core/Src/main.c **** Write_Command_Pins(0, 1, 0); // WE low 140:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); // WE high 141:Core/Src/main.c **** 142:Core/Src/main.c **** // 5. Deassert CE# 143:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 144:Core/Src/main.c **** } 145:Core/Src/main.c **** ARM GAS /tmp/ccg6eVgO.s page 4 146:Core/Src/main.c **** int Flash_ReadByte(int addr) { 147:Core/Src/main.c **** Write_Address(addr); 148:Core/Src/main.c **** Data_Pins_Init(0); 149:Core/Src/main.c **** Write_Command_Pins(0, 0, 1); 150:Core/Src/main.c **** int data = Receive_Data(); 151:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 152:Core/Src/main.c **** return data; 153:Core/Src/main.c **** } 154:Core/Src/main.c **** 155:Core/Src/main.c **** void Enter_Device_ID(int *manufacturer, int *device){ 156:Core/Src/main.c **** // Enter ID mode 157:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 158:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 159:Core/Src/main.c **** Write_Command(0x5555, 0x90); 160:Core/Src/main.c **** 161:Core/Src/main.c **** // Read Manufacturer ID (it should be 0xBF) 162:Core/Src/main.c **** *manufacturer = Flash_ReadByte(0x0000); 163:Core/Src/main.c **** 164:Core/Src/main.c **** // Read Device ID (it should be 0xB7 for the SST39SF040) 165:Core/Src/main.c **** *device = Flash_ReadByte(0x0001); 166:Core/Src/main.c **** 167:Core/Src/main.c **** // Exit ID mode 168:Core/Src/main.c **** Write_Command(0x5555, 0xF0); 169:Core/Src/main.c **** } 170:Core/Src/main.c **** 171:Core/Src/main.c **** /** 172:Core/Src/main.c **** * @brief System Clock Configuration 173:Core/Src/main.c **** * @retval None 174:Core/Src/main.c **** */ 175:Core/Src/main.c **** void SystemClock_Config(void) 176:Core/Src/main.c **** { 177:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 178:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 179:Core/Src/main.c **** 180:Core/Src/main.c **** /** Configure the main internal regulator output voltage 181:Core/Src/main.c **** */ 182:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 183:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 184:Core/Src/main.c **** 185:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 186:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 187:Core/Src/main.c **** */ 188:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 189:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 190:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 191:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 192:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 193:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; 194:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 195:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 196:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 197:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 198:Core/Src/main.c **** { 199:Core/Src/main.c **** Error_Handler(); 200:Core/Src/main.c **** } 201:Core/Src/main.c **** 202:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks ARM GAS /tmp/ccg6eVgO.s page 5 203:Core/Src/main.c **** */ 204:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 205:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 206:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 207:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 208:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 209:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 210:Core/Src/main.c **** 211:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 212:Core/Src/main.c **** { 213:Core/Src/main.c **** Error_Handler(); 214:Core/Src/main.c **** } 215:Core/Src/main.c **** } 216:Core/Src/main.c **** 217:Core/Src/main.c **** /** 218:Core/Src/main.c **** * @brief USART2 Initialization Function 219:Core/Src/main.c **** * @param None 220:Core/Src/main.c **** * @retval None 221:Core/Src/main.c **** */ 222:Core/Src/main.c **** static void MX_USART2_UART_Init(void) 223:Core/Src/main.c **** { 224:Core/Src/main.c **** huart2.Instance = USART2; 225:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 226:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 227:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 228:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 229:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 230:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 231:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 232:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 233:Core/Src/main.c **** { 234:Core/Src/main.c **** Error_Handler(); 235:Core/Src/main.c **** } 236:Core/Src/main.c **** 237:Core/Src/main.c **** } 238:Core/Src/main.c **** 239:Core/Src/main.c **** // The argument must be 0 (input) or 1 (output) 240:Core/Src/main.c **** void Data_Pins_Init(int as_output){ 241:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 242:Core/Src/main.c **** 243:Core/Src/main.c **** // Configure PA0..PA7 as push-pull outputs 244:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_11 | GPIO_PIN_12 | 245:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 246:Core/Src/main.c **** if(as_output == 1){ 247:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 248:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 249:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 250:Core/Src/main.c **** }else{ 251:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; // Input mode 252:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; // No pull-up/down 253:Core/Src/main.c **** } 254:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 255:Core/Src/main.c **** } 256:Core/Src/main.c **** 257:Core/Src/main.c **** void Address_Pins_Init(void){ 258:Core/Src/main.c **** GPIO_InitTypeDef GPIOC_InitStruct = {0}; 259:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs ARM GAS /tmp/ccg6eVgO.s page 6 260:Core/Src/main.c **** GPIOC_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | 261:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 262:Core/Src/main.c **** GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10| GPIO_PIN_11| 263:Core/Src/main.c **** GPIO_PIN_12| GPIO_PIN_13| GPIO_PIN_14| GPIO_PIN_15; 264:Core/Src/main.c **** GPIOC_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 265:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 266:Core/Src/main.c **** GPIOC_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 267:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 268:Core/Src/main.c **** 269:Core/Src/main.c **** // Then we do the same for the remaining 270:Core/Src/main.c **** GPIO_InitTypeDef GPIOB_InitStruct = {0}; 271:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 272:Core/Src/main.c **** GPIOB_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4; 273:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 274:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 275:Core/Src/main.c **** GPIOB_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 276:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); 277:Core/Src/main.c **** } 278:Core/Src/main.c **** 279:Core/Src/main.c **** void Command_Pins_Init(void){ 280:Core/Src/main.c **** // PA8-10 as outputs pins 281:Core/Src/main.c **** GPIO_InitTypeDef GPIOA_InitStruct = {0}; 282:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; 283:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 284:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 285:Core/Src/main.c **** GPIOA_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 286:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 287:Core/Src/main.c **** } 288:Core/Src/main.c **** 289:Core/Src/main.c **** void debug_print(const char *msg) { 290:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 291:Core/Src/main.c **** } 292:Core/Src/main.c **** 293:Core/Src/main.c **** /** 294:Core/Src/main.c **** * @brief GPIO Initialization Function 295:Core/Src/main.c **** * @param None 296:Core/Src/main.c **** * @retval None 297:Core/Src/main.c **** */ 298:Core/Src/main.c **** static void MX_GPIO_Init(void) 299:Core/Src/main.c **** { 28 .loc 1 299 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 16 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 33 0000 84B0 sub sp, sp, #16 34 .LCFI0: 35 .cfi_def_cfa_offset 16 300:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 301:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 36 .loc 1 301 3 view .LVU1 37 .LBB4: 38 .loc 1 301 3 view .LVU2 39 0002 0022 movs r2, #0 40 0004 0092 str r2, [sp] 41 .loc 1 301 3 view .LVU3 42 0006 154B ldr r3, .L3 ARM GAS /tmp/ccg6eVgO.s page 7 43 0008 196B ldr r1, [r3, #48] 44 000a 41F00401 orr r1, r1, #4 45 000e 1963 str r1, [r3, #48] 46 .loc 1 301 3 view .LVU4 47 0010 196B ldr r1, [r3, #48] 48 0012 01F00401 and r1, r1, #4 49 0016 0091 str r1, [sp] 50 .loc 1 301 3 view .LVU5 51 0018 0099 ldr r1, [sp] 52 .LBE4: 53 .loc 1 301 3 view .LVU6 302:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 54 .loc 1 302 3 view .LVU7 55 .LBB5: 56 .loc 1 302 3 view .LVU8 57 001a 0192 str r2, [sp, #4] 58 .loc 1 302 3 view .LVU9 59 001c 196B ldr r1, [r3, #48] 60 001e 41F08001 orr r1, r1, #128 61 0022 1963 str r1, [r3, #48] 62 .loc 1 302 3 view .LVU10 63 0024 196B ldr r1, [r3, #48] 64 0026 01F08001 and r1, r1, #128 65 002a 0191 str r1, [sp, #4] 66 .loc 1 302 3 view .LVU11 67 002c 0199 ldr r1, [sp, #4] 68 .LBE5: 69 .loc 1 302 3 view .LVU12 303:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 70 .loc 1 303 3 view .LVU13 71 .LBB6: 72 .loc 1 303 3 view .LVU14 73 002e 0292 str r2, [sp, #8] 74 .loc 1 303 3 view .LVU15 75 0030 196B ldr r1, [r3, #48] 76 0032 41F00101 orr r1, r1, #1 77 0036 1963 str r1, [r3, #48] 78 .loc 1 303 3 view .LVU16 79 0038 196B ldr r1, [r3, #48] 80 003a 01F00101 and r1, r1, #1 81 003e 0291 str r1, [sp, #8] 82 .loc 1 303 3 view .LVU17 83 0040 0299 ldr r1, [sp, #8] 84 .LBE6: 85 .loc 1 303 3 view .LVU18 304:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 86 .loc 1 304 3 view .LVU19 87 .LBB7: 88 .loc 1 304 3 view .LVU20 89 0042 0392 str r2, [sp, #12] 90 .loc 1 304 3 view .LVU21 91 0044 1A6B ldr r2, [r3, #48] 92 0046 42F00202 orr r2, r2, #2 93 004a 1A63 str r2, [r3, #48] 94 .loc 1 304 3 view .LVU22 95 004c 1B6B ldr r3, [r3, #48] 96 004e 03F00203 and r3, r3, #2 ARM GAS /tmp/ccg6eVgO.s page 8 97 0052 0393 str r3, [sp, #12] 98 .loc 1 304 3 view .LVU23 99 0054 039B ldr r3, [sp, #12] 100 .LBE7: 101 .loc 1 304 3 view .LVU24 305:Core/Src/main.c **** 306:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 307:Core/Src/main.c **** // HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 308:Core/Src/main.c **** 309:Core/Src/main.c **** /*Configure GPIO pin : B1_Pin */ 310:Core/Src/main.c **** // GPIO_InitStruct.Pin = B1_Pin; 311:Core/Src/main.c **** // GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 312:Core/Src/main.c **** // GPIO_InitStruct.Pull = GPIO_NOPULL; 313:Core/Src/main.c **** // HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 314:Core/Src/main.c **** 315:Core/Src/main.c **** /*Configure GPIO pin : LD2_Pin */ 316:Core/Src/main.c **** // GPIO_InitStruct.Pin = LD2_Pin; 317:Core/Src/main.c **** // GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 318:Core/Src/main.c **** // GPIO_InitStruct.Pull = GPIO_NOPULL; 319:Core/Src/main.c **** // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 320:Core/Src/main.c **** // HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 321:Core/Src/main.c **** } 102 .loc 1 321 1 is_stmt 0 view .LVU25 103 0056 04B0 add sp, sp, #16 104 .LCFI1: 105 .cfi_def_cfa_offset 0 106 @ sp needed 107 0058 7047 bx lr 108 .L4: 109 005a 00BF .align 2 110 .L3: 111 005c 00380240 .word 1073887232 112 .cfi_endproc 113 .LFE151: 115 .section .text.Write_Address,"ax",%progbits 116 .align 1 117 .global Write_Address 118 .syntax unified 119 .thumb 120 .thumb_func 121 .fpu fpv4-sp-d16 123 Write_Address: 124 .LVL0: 125 .LFB138: 79:Core/Src/main.c **** int pin_array[] = { 126 .loc 1 79 32 is_stmt 1 view -0 127 .cfi_startproc 128 @ args = 0, pretend = 0, frame = 80 129 @ frame_needed = 0, uses_anonymous_args = 0 79:Core/Src/main.c **** int pin_array[] = { 130 .loc 1 79 32 is_stmt 0 view .LVU27 131 0000 30B5 push {r4, r5, lr} 132 .LCFI2: 133 .cfi_def_cfa_offset 12 134 .cfi_offset 4, -12 135 .cfi_offset 5, -8 136 .cfi_offset 14, -4 ARM GAS /tmp/ccg6eVgO.s page 9 137 0002 95B0 sub sp, sp, #84 138 .LCFI3: 139 .cfi_def_cfa_offset 96 140 0004 0546 mov r5, r0 80:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 141 .loc 1 80 3 is_stmt 1 view .LVU28 80:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 142 .loc 1 80 7 is_stmt 0 view .LVU29 143 0006 4C22 movs r2, #76 144 0008 1E49 ldr r1, .L14 145 000a 01A8 add r0, sp, #4 146 .LVL1: 80:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 147 .loc 1 80 7 view .LVU30 148 000c FFF7FEFF bl memcpy 149 .LVL2: 87:Core/Src/main.c **** if(i<14){ 150 .loc 1 87 3 is_stmt 1 view .LVU31 151 .LBB8: 87:Core/Src/main.c **** if(i<14){ 152 .loc 1 87 7 view .LVU32 87:Core/Src/main.c **** if(i<14){ 153 .loc 1 87 11 is_stmt 0 view .LVU33 154 0010 0024 movs r4, #0 87:Core/Src/main.c **** if(i<14){ 155 .loc 1 87 3 view .LVU34 156 0012 09E0 b .L6 157 .LVL3: 158 .L8: 90:Core/Src/main.c **** } 159 .loc 1 90 12 is_stmt 1 view .LVU35 160 0014 0022 movs r2, #0 161 0016 14AB add r3, sp, #80 162 0018 03EB8403 add r3, r3, r4, lsl #2 163 001c 33F84C1C ldrh r1, [r3, #-76] 164 0020 1948 ldr r0, .L14+4 165 0022 FFF7FEFF bl HAL_GPIO_WritePin 166 .LVL4: 167 .L9: 87:Core/Src/main.c **** if(i<14){ 168 .loc 1 87 22 discriminator 2 view .LVU36 87:Core/Src/main.c **** if(i<14){ 169 .loc 1 87 23 is_stmt 0 discriminator 2 view .LVU37 170 0026 0134 adds r4, r4, #1 171 .LVL5: 172 .L6: 87:Core/Src/main.c **** if(i<14){ 173 .loc 1 87 16 is_stmt 1 discriminator 1 view .LVU38 87:Core/Src/main.c **** if(i<14){ 174 .loc 1 87 3 is_stmt 0 discriminator 1 view .LVU39 175 0028 122C cmp r4, #18 176 002a 29DC bgt .L13 88:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 177 .loc 1 88 5 is_stmt 1 view .LVU40 88:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 178 .loc 1 88 7 is_stmt 0 view .LVU41 179 002c 0D2C cmp r4, #13 ARM GAS /tmp/ccg6eVgO.s page 10 180 002e 0EDC bgt .L7 89:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 181 .loc 1 89 7 is_stmt 1 view .LVU42 89:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 182 .loc 1 89 19 is_stmt 0 view .LVU43 183 0030 45FA04F3 asr r3, r5, r4 89:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 184 .loc 1 89 9 view .LVU44 185 0034 13F0010F tst r3, #1 186 0038 ECD0 beq .L8 89:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 187 .loc 1 89 30 is_stmt 1 discriminator 1 view .LVU45 188 003a 0122 movs r2, #1 189 003c 14AB add r3, sp, #80 190 003e 03EB8403 add r3, r3, r4, lsl #2 191 0042 33F84C1C ldrh r1, [r3, #-76] 192 0046 1048 ldr r0, .L14+4 193 0048 FFF7FEFF bl HAL_GPIO_WritePin 194 .LVL6: 195 004c EBE7 b .L9 196 .L7: 93:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 197 .loc 1 93 7 view .LVU46 93:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 198 .loc 1 93 19 is_stmt 0 view .LVU47 199 004e 45FA04F3 asr r3, r5, r4 93:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 200 .loc 1 93 9 view .LVU48 201 0052 13F0010F tst r3, #1 202 0056 09D0 beq .L10 93:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 203 .loc 1 93 30 is_stmt 1 discriminator 1 view .LVU49 204 0058 0122 movs r2, #1 205 005a 14AB add r3, sp, #80 206 005c 03EB8403 add r3, r3, r4, lsl #2 207 0060 33F84C1C ldrh r1, [r3, #-76] 208 0064 0948 ldr r0, .L14+8 209 0066 FFF7FEFF bl HAL_GPIO_WritePin 210 .LVL7: 211 006a DCE7 b .L9 212 .L10: 94:Core/Src/main.c **** } 213 .loc 1 94 12 view .LVU50 214 006c 0022 movs r2, #0 215 006e 14AB add r3, sp, #80 216 0070 03EB8403 add r3, r3, r4, lsl #2 217 0074 33F84C1C ldrh r1, [r3, #-76] 218 0078 0448 ldr r0, .L14+8 219 007a FFF7FEFF bl HAL_GPIO_WritePin 220 .LVL8: 221 007e D2E7 b .L9 222 .L13: 94:Core/Src/main.c **** } 223 .loc 1 94 12 is_stmt 0 view .LVU51 224 .LBE8: 97:Core/Src/main.c **** 225 .loc 1 97 1 view .LVU52 ARM GAS /tmp/ccg6eVgO.s page 11 226 0080 15B0 add sp, sp, #84 227 .LCFI4: 228 .cfi_def_cfa_offset 12 229 @ sp needed 230 0082 30BD pop {r4, r5, pc} 231 .LVL9: 232 .L15: 97:Core/Src/main.c **** 233 .loc 1 97 1 view .LVU53 234 .align 2 235 .L14: 236 0084 00000000 .word .LANCHOR0 237 0088 00080240 .word 1073874944 238 008c 00040240 .word 1073873920 239 .cfi_endproc 240 .LFE138: 242 .section .text.Write_Command_Pins,"ax",%progbits 243 .align 1 244 .global Write_Command_Pins 245 .syntax unified 246 .thumb 247 .thumb_func 248 .fpu fpv4-sp-d16 250 Write_Command_Pins: 251 .LVL10: 252 .LFB141: 127:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 253 .loc 1 127 48 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 0 256 @ frame_needed = 0, uses_anonymous_args = 0 127:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 257 .loc 1 127 48 is_stmt 0 view .LVU55 258 0000 70B5 push {r4, r5, r6, lr} 259 .LCFI5: 260 .cfi_def_cfa_offset 16 261 .cfi_offset 4, -16 262 .cfi_offset 5, -12 263 .cfi_offset 6, -8 264 .cfi_offset 14, -4 265 0002 0E46 mov r6, r1 266 0004 1546 mov r5, r2 128:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 267 .loc 1 128 3 is_stmt 1 view .LVU56 268 0006 0D4C ldr r4, .L18 269 0008 021E subs r2, r0, #0 270 .LVL11: 128:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 271 .loc 1 128 3 is_stmt 0 view .LVU57 272 000a 18BF it ne 273 000c 0122 movne r2, #1 274 000e 4FF48071 mov r1, #256 275 .LVL12: 128:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 276 .loc 1 128 3 view .LVU58 277 0012 2046 mov r0, r4 278 .LVL13: ARM GAS /tmp/ccg6eVgO.s page 12 128:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 279 .loc 1 128 3 view .LVU59 280 0014 FFF7FEFF bl HAL_GPIO_WritePin 281 .LVL14: 129:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10,(WE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 282 .loc 1 129 3 is_stmt 1 view .LVU60 283 0018 321E subs r2, r6, #0 284 001a 18BF it ne 285 001c 0122 movne r2, #1 286 001e 4FF40071 mov r1, #512 287 0022 2046 mov r0, r4 288 0024 FFF7FEFF bl HAL_GPIO_WritePin 289 .LVL15: 130:Core/Src/main.c **** } 290 .loc 1 130 3 view .LVU61 291 0028 2A1E subs r2, r5, #0 292 002a 18BF it ne 293 002c 0122 movne r2, #1 294 002e 4FF48061 mov r1, #1024 295 0032 2046 mov r0, r4 296 0034 FFF7FEFF bl HAL_GPIO_WritePin 297 .LVL16: 131:Core/Src/main.c **** 298 .loc 1 131 1 is_stmt 0 view .LVU62 299 0038 70BD pop {r4, r5, r6, pc} 300 .LVL17: 301 .L19: 131:Core/Src/main.c **** 302 .loc 1 131 1 view .LVU63 303 003a 00BF .align 2 304 .L18: 305 003c 00000240 .word 1073872896 306 .cfi_endproc 307 .LFE141: 309 .section .text.Data_Pins_Init,"ax",%progbits 310 .align 1 311 .global Data_Pins_Init 312 .syntax unified 313 .thumb 314 .thumb_func 315 .fpu fpv4-sp-d16 317 Data_Pins_Init: 318 .LVL18: 319 .LFB147: 240:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 320 .loc 1 240 35 is_stmt 1 view -0 321 .cfi_startproc 322 @ args = 0, pretend = 0, frame = 24 323 @ frame_needed = 0, uses_anonymous_args = 0 240:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 324 .loc 1 240 35 is_stmt 0 view .LVU65 325 0000 00B5 push {lr} 326 .LCFI6: 327 .cfi_def_cfa_offset 4 328 .cfi_offset 14, -4 329 0002 87B0 sub sp, sp, #28 330 .LCFI7: ARM GAS /tmp/ccg6eVgO.s page 13 331 .cfi_def_cfa_offset 32 241:Core/Src/main.c **** 332 .loc 1 241 3 is_stmt 1 view .LVU66 241:Core/Src/main.c **** 333 .loc 1 241 20 is_stmt 0 view .LVU67 334 0004 0023 movs r3, #0 335 0006 0193 str r3, [sp, #4] 336 0008 0293 str r3, [sp, #8] 337 000a 0393 str r3, [sp, #12] 338 000c 0493 str r3, [sp, #16] 339 000e 0593 str r3, [sp, #20] 244:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 340 .loc 1 244 3 is_stmt 1 view .LVU68 244:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 341 .loc 1 244 23 is_stmt 0 view .LVU69 342 0010 41F6F303 movw r3, #6387 343 0014 0193 str r3, [sp, #4] 246:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 344 .loc 1 246 3 is_stmt 1 view .LVU70 246:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 345 .loc 1 246 5 is_stmt 0 view .LVU71 346 0016 0128 cmp r0, #1 347 0018 08D0 beq .L24 251:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; // No pull-up/down 348 .loc 1 251 5 is_stmt 1 view .LVU72 252:Core/Src/main.c **** } 349 .loc 1 252 5 view .LVU73 252:Core/Src/main.c **** } 350 .loc 1 252 26 is_stmt 0 view .LVU74 351 001a 0223 movs r3, #2 352 001c 0393 str r3, [sp, #12] 353 .L22: 254:Core/Src/main.c **** } 354 .loc 1 254 3 is_stmt 1 view .LVU75 355 001e 01A9 add r1, sp, #4 356 0020 0548 ldr r0, .L25 357 .LVL19: 254:Core/Src/main.c **** } 358 .loc 1 254 3 is_stmt 0 view .LVU76 359 0022 FFF7FEFF bl HAL_GPIO_Init 360 .LVL20: 255:Core/Src/main.c **** 361 .loc 1 255 1 view .LVU77 362 0026 07B0 add sp, sp, #28 363 .LCFI8: 364 .cfi_remember_state 365 .cfi_def_cfa_offset 4 366 @ sp needed 367 0028 5DF804FB ldr pc, [sp], #4 368 .LVL21: 369 .L24: 370 .LCFI9: 371 .cfi_restore_state 247:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 372 .loc 1 247 5 is_stmt 1 view .LVU78 247:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 373 .loc 1 247 26 is_stmt 0 view .LVU79 ARM GAS /tmp/ccg6eVgO.s page 14 374 002c 0123 movs r3, #1 375 002e 0293 str r3, [sp, #8] 248:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 376 .loc 1 248 5 is_stmt 1 view .LVU80 249:Core/Src/main.c **** }else{ 377 .loc 1 249 5 view .LVU81 249:Core/Src/main.c **** }else{ 378 .loc 1 249 27 is_stmt 0 view .LVU82 379 0030 0223 movs r3, #2 380 0032 0493 str r3, [sp, #16] 381 0034 F3E7 b .L22 382 .L26: 383 0036 00BF .align 2 384 .L25: 385 0038 00000240 .word 1073872896 386 .cfi_endproc 387 .LFE147: 389 .section .text.Receive_Data,"ax",%progbits 390 .align 1 391 .global Receive_Data 392 .syntax unified 393 .thumb 394 .thumb_func 395 .fpu fpv4-sp-d16 397 Receive_Data: 398 .LFB139: 99:Core/Src/main.c **** Data_Pins_Init(0); // We make sure it's in input mode 399 .loc 1 99 23 is_stmt 1 view -0 400 .cfi_startproc 401 @ args = 0, pretend = 0, frame = 32 402 @ frame_needed = 0, uses_anonymous_args = 0 403 0000 30B5 push {r4, r5, lr} 404 .LCFI10: 405 .cfi_def_cfa_offset 12 406 .cfi_offset 4, -12 407 .cfi_offset 5, -8 408 .cfi_offset 14, -4 409 0002 89B0 sub sp, sp, #36 410 .LCFI11: 411 .cfi_def_cfa_offset 48 100:Core/Src/main.c **** int result = 0; 412 .loc 1 100 3 view .LVU84 413 0004 0020 movs r0, #0 414 0006 FFF7FEFF bl Data_Pins_Init 415 .LVL22: 101:Core/Src/main.c **** int pin_array[] = { 416 .loc 1 101 3 view .LVU85 102:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 417 .loc 1 102 3 view .LVU86 102:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 418 .loc 1 102 7 is_stmt 0 view .LVU87 419 000a 6C46 mov r4, sp 420 000c 0E4D ldr r5, .L33 421 000e 0FCD ldmia r5!, {r0, r1, r2, r3} 422 0010 0FC4 stmia r4!, {r0, r1, r2, r3} 423 0012 95E80F00 ldm r5, {r0, r1, r2, r3} 424 0016 84E80F00 stm r4, {r0, r1, r2, r3} ARM GAS /tmp/ccg6eVgO.s page 15 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 425 .loc 1 106 3 is_stmt 1 view .LVU88 426 .LBB9: 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 427 .loc 1 106 7 view .LVU89 428 .LVL23: 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 429 .loc 1 106 11 is_stmt 0 view .LVU90 430 001a 0024 movs r4, #0 431 .LBE9: 101:Core/Src/main.c **** int pin_array[] = { 432 .loc 1 101 7 view .LVU91 433 001c 2546 mov r5, r4 434 .LBB10: 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 435 .loc 1 106 3 view .LVU92 436 001e 00E0 b .L28 437 .LVL24: 438 .L29: 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 439 .loc 1 106 21 is_stmt 1 discriminator 2 view .LVU93 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 440 .loc 1 106 22 is_stmt 0 discriminator 2 view .LVU94 441 0020 0134 adds r4, r4, #1 442 .LVL25: 443 .L28: 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 444 .loc 1 106 16 is_stmt 1 discriminator 1 view .LVU95 106:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 445 .loc 1 106 3 is_stmt 0 discriminator 1 view .LVU96 446 0022 072C cmp r4, #7 447 0024 0DDC bgt .L32 107:Core/Src/main.c **** result += 1 << i; 448 .loc 1 107 5 is_stmt 1 view .LVU97 107:Core/Src/main.c **** result += 1 << i; 449 .loc 1 107 41 is_stmt 0 view .LVU98 450 0026 08AB add r3, sp, #32 451 0028 03EB8403 add r3, r3, r4, lsl #2 107:Core/Src/main.c **** result += 1 << i; 452 .loc 1 107 8 view .LVU99 453 002c 33F8201C ldrh r1, [r3, #-32] 454 0030 0648 ldr r0, .L33+4 455 0032 FFF7FEFF bl HAL_GPIO_ReadPin 456 .LVL26: 107:Core/Src/main.c **** result += 1 << i; 457 .loc 1 107 7 view .LVU100 458 0036 0128 cmp r0, #1 459 0038 F2D1 bne .L29 108:Core/Src/main.c **** } 460 .loc 1 108 7 is_stmt 1 view .LVU101 108:Core/Src/main.c **** } 461 .loc 1 108 19 is_stmt 0 view .LVU102 462 003a 0123 movs r3, #1 463 003c A340 lsls r3, r3, r4 108:Core/Src/main.c **** } 464 .loc 1 108 14 view .LVU103 465 003e 1D44 add r5, r5, r3 ARM GAS /tmp/ccg6eVgO.s page 16 466 .LVL27: 108:Core/Src/main.c **** } 467 .loc 1 108 14 view .LVU104 468 0040 EEE7 b .L29 469 .L32: 108:Core/Src/main.c **** } 470 .loc 1 108 14 view .LVU105 471 .LBE10: 111:Core/Src/main.c **** } 472 .loc 1 111 3 is_stmt 1 view .LVU106 112:Core/Src/main.c **** 473 .loc 1 112 1 is_stmt 0 view .LVU107 474 0042 2846 mov r0, r5 475 0044 09B0 add sp, sp, #36 476 .LCFI12: 477 .cfi_def_cfa_offset 12 478 @ sp needed 479 0046 30BD pop {r4, r5, pc} 480 .LVL28: 481 .L34: 112:Core/Src/main.c **** 482 .loc 1 112 1 view .LVU108 483 .align 2 484 .L33: 485 0048 4C000000 .word .LANCHOR0+76 486 004c 00000240 .word 1073872896 487 .cfi_endproc 488 .LFE139: 490 .section .text.Write_Data,"ax",%progbits 491 .align 1 492 .global Write_Data 493 .syntax unified 494 .thumb 495 .thumb_func 496 .fpu fpv4-sp-d16 498 Write_Data: 499 .LVL29: 500 .LFB140: 114:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 501 .loc 1 114 27 is_stmt 1 view -0 502 .cfi_startproc 503 @ args = 0, pretend = 0, frame = 32 504 @ frame_needed = 0, uses_anonymous_args = 0 114:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 505 .loc 1 114 27 is_stmt 0 view .LVU110 506 0000 70B5 push {r4, r5, r6, lr} 507 .LCFI13: 508 .cfi_def_cfa_offset 16 509 .cfi_offset 4, -16 510 .cfi_offset 5, -12 511 .cfi_offset 6, -8 512 .cfi_offset 14, -4 513 0002 88B0 sub sp, sp, #32 514 .LCFI14: 515 .cfi_def_cfa_offset 48 516 0004 0646 mov r6, r0 115:Core/Src/main.c **** int pin_array[] = { ARM GAS /tmp/ccg6eVgO.s page 17 517 .loc 1 115 3 is_stmt 1 view .LVU111 518 0006 0120 movs r0, #1 519 .LVL30: 115:Core/Src/main.c **** int pin_array[] = { 520 .loc 1 115 3 is_stmt 0 view .LVU112 521 0008 FFF7FEFF bl Data_Pins_Init 522 .LVL31: 116:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 523 .loc 1 116 3 is_stmt 1 view .LVU113 116:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 524 .loc 1 116 7 is_stmt 0 view .LVU114 525 000c 6C46 mov r4, sp 526 000e 134D ldr r5, .L42 527 0010 0FCD ldmia r5!, {r0, r1, r2, r3} 528 0012 0FC4 stmia r4!, {r0, r1, r2, r3} 529 0014 95E80F00 ldm r5, {r0, r1, r2, r3} 530 0018 84E80F00 stm r4, {r0, r1, r2, r3} 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 531 .loc 1 120 3 is_stmt 1 view .LVU115 532 .LBB11: 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 533 .loc 1 120 7 view .LVU116 534 .LVL32: 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 535 .loc 1 120 11 is_stmt 0 view .LVU117 536 001c 0024 movs r4, #0 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 537 .loc 1 120 3 view .LVU118 538 001e 09E0 b .L36 539 .LVL33: 540 .L37: 122:Core/Src/main.c **** } 541 .loc 1 122 10 is_stmt 1 view .LVU119 542 0020 0022 movs r2, #0 543 0022 08AB add r3, sp, #32 544 0024 03EB8403 add r3, r3, r4, lsl #2 545 0028 33F8201C ldrh r1, [r3, #-32] 546 002c 0C48 ldr r0, .L42+4 547 002e FFF7FEFF bl HAL_GPIO_WritePin 548 .LVL34: 549 .L38: 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 550 .loc 1 120 21 discriminator 2 view .LVU120 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 551 .loc 1 120 22 is_stmt 0 discriminator 2 view .LVU121 552 0032 0134 adds r4, r4, #1 553 .LVL35: 554 .L36: 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 555 .loc 1 120 16 is_stmt 1 discriminator 1 view .LVU122 120:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 556 .loc 1 120 3 is_stmt 0 discriminator 1 view .LVU123 557 0034 072C cmp r4, #7 558 0036 0EDC bgt .L41 121:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 559 .loc 1 121 5 is_stmt 1 view .LVU124 121:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); ARM GAS /tmp/ccg6eVgO.s page 18 560 .loc 1 121 15 is_stmt 0 view .LVU125 561 0038 46FA04F3 asr r3, r6, r4 121:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 562 .loc 1 121 7 view .LVU126 563 003c 13F0010F tst r3, #1 564 0040 EED0 beq .L37 121:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 565 .loc 1 121 26 is_stmt 1 discriminator 1 view .LVU127 566 0042 0122 movs r2, #1 567 0044 08AB add r3, sp, #32 568 0046 03EB8403 add r3, r3, r4, lsl #2 569 004a 33F8201C ldrh r1, [r3, #-32] 570 004e 0448 ldr r0, .L42+4 571 0050 FFF7FEFF bl HAL_GPIO_WritePin 572 .LVL36: 573 0054 EDE7 b .L38 574 .L41: 121:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 575 .loc 1 121 26 is_stmt 0 discriminator 1 view .LVU128 576 .LBE11: 124:Core/Src/main.c **** 577 .loc 1 124 1 view .LVU129 578 0056 08B0 add sp, sp, #32 579 .LCFI15: 580 .cfi_def_cfa_offset 16 581 @ sp needed 582 0058 70BD pop {r4, r5, r6, pc} 583 .LVL37: 584 .L43: 124:Core/Src/main.c **** 585 .loc 1 124 1 view .LVU130 586 005a 00BF .align 2 587 .L42: 588 005c 4C000000 .word .LANCHOR0+76 589 0060 00000240 .word 1073872896 590 .cfi_endproc 591 .LFE140: 593 .section .text.Write_Command,"ax",%progbits 594 .align 1 595 .global Write_Command 596 .syntax unified 597 .thumb 598 .thumb_func 599 .fpu fpv4-sp-d16 601 Write_Command: 602 .LVL38: 603 .LFB142: 133:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 604 .loc 1 133 40 is_stmt 1 view -0 605 .cfi_startproc 606 @ args = 0, pretend = 0, frame = 0 607 @ frame_needed = 0, uses_anonymous_args = 0 133:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 608 .loc 1 133 40 is_stmt 0 view .LVU132 609 0000 38B5 push {r3, r4, r5, lr} 610 .LCFI16: 611 .cfi_def_cfa_offset 16 ARM GAS /tmp/ccg6eVgO.s page 19 612 .cfi_offset 3, -16 613 .cfi_offset 4, -12 614 .cfi_offset 5, -8 615 .cfi_offset 14, -4 616 0002 0546 mov r5, r0 617 0004 0C46 mov r4, r1 134:Core/Src/main.c **** Write_Address(addr); 618 .loc 1 134 5 is_stmt 1 view .LVU133 619 0006 0122 movs r2, #1 620 0008 1146 mov r1, r2 621 .LVL39: 134:Core/Src/main.c **** Write_Address(addr); 622 .loc 1 134 5 is_stmt 0 view .LVU134 623 000a 1046 mov r0, r2 624 .LVL40: 134:Core/Src/main.c **** Write_Address(addr); 625 .loc 1 134 5 view .LVU135 626 000c FFF7FEFF bl Write_Command_Pins 627 .LVL41: 135:Core/Src/main.c **** Write_Data(data); 628 .loc 1 135 5 is_stmt 1 view .LVU136 629 0010 2846 mov r0, r5 630 0012 FFF7FEFF bl Write_Address 631 .LVL42: 136:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); 632 .loc 1 136 5 view .LVU137 633 0016 2046 mov r0, r4 634 0018 FFF7FEFF bl Write_Data 635 .LVL43: 137:Core/Src/main.c **** // 4. Pulse WE# low to latch data 636 .loc 1 137 5 view .LVU138 637 001c 0122 movs r2, #1 638 001e 1146 mov r1, r2 639 0020 0020 movs r0, #0 640 0022 FFF7FEFF bl Write_Command_Pins 641 .LVL44: 139:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); // WE high 642 .loc 1 139 5 view .LVU139 643 0026 0022 movs r2, #0 644 0028 0121 movs r1, #1 645 002a 1046 mov r0, r2 646 002c FFF7FEFF bl Write_Command_Pins 647 .LVL45: 140:Core/Src/main.c **** 648 .loc 1 140 5 view .LVU140 649 0030 0122 movs r2, #1 650 0032 1146 mov r1, r2 651 0034 0020 movs r0, #0 652 0036 FFF7FEFF bl Write_Command_Pins 653 .LVL46: 143:Core/Src/main.c **** } 654 .loc 1 143 5 view .LVU141 655 003a 0122 movs r2, #1 656 003c 1146 mov r1, r2 657 003e 1046 mov r0, r2 658 0040 FFF7FEFF bl Write_Command_Pins 659 .LVL47: ARM GAS /tmp/ccg6eVgO.s page 20 144:Core/Src/main.c **** 660 .loc 1 144 1 is_stmt 0 view .LVU142 661 0044 38BD pop {r3, r4, r5, pc} 144:Core/Src/main.c **** 662 .loc 1 144 1 view .LVU143 663 .cfi_endproc 664 .LFE142: 666 .section .text.Flash_ReadByte,"ax",%progbits 667 .align 1 668 .global Flash_ReadByte 669 .syntax unified 670 .thumb 671 .thumb_func 672 .fpu fpv4-sp-d16 674 Flash_ReadByte: 675 .LVL48: 676 .LFB143: 146:Core/Src/main.c **** Write_Address(addr); 677 .loc 1 146 30 is_stmt 1 view -0 678 .cfi_startproc 679 @ args = 0, pretend = 0, frame = 0 680 @ frame_needed = 0, uses_anonymous_args = 0 146:Core/Src/main.c **** Write_Address(addr); 681 .loc 1 146 30 is_stmt 0 view .LVU145 682 0000 10B5 push {r4, lr} 683 .LCFI17: 684 .cfi_def_cfa_offset 8 685 .cfi_offset 4, -8 686 .cfi_offset 14, -4 147:Core/Src/main.c **** Data_Pins_Init(0); 687 .loc 1 147 5 is_stmt 1 view .LVU146 688 0002 FFF7FEFF bl Write_Address 689 .LVL49: 148:Core/Src/main.c **** Write_Command_Pins(0, 0, 1); 690 .loc 1 148 5 view .LVU147 691 0006 0020 movs r0, #0 692 0008 FFF7FEFF bl Data_Pins_Init 693 .LVL50: 149:Core/Src/main.c **** int data = Receive_Data(); 694 .loc 1 149 5 view .LVU148 695 000c 0122 movs r2, #1 696 000e 0021 movs r1, #0 697 0010 0846 mov r0, r1 698 0012 FFF7FEFF bl Write_Command_Pins 699 .LVL51: 150:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 700 .loc 1 150 5 view .LVU149 150:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 701 .loc 1 150 16 is_stmt 0 view .LVU150 702 0016 FFF7FEFF bl Receive_Data 703 .LVL52: 704 001a 0446 mov r4, r0 705 .LVL53: 151:Core/Src/main.c **** return data; 706 .loc 1 151 5 is_stmt 1 view .LVU151 707 001c 0122 movs r2, #1 708 001e 1146 mov r1, r2 ARM GAS /tmp/ccg6eVgO.s page 21 709 0020 1046 mov r0, r2 710 .LVL54: 151:Core/Src/main.c **** return data; 711 .loc 1 151 5 is_stmt 0 view .LVU152 712 0022 FFF7FEFF bl Write_Command_Pins 713 .LVL55: 152:Core/Src/main.c **** } 714 .loc 1 152 5 is_stmt 1 view .LVU153 153:Core/Src/main.c **** 715 .loc 1 153 1 is_stmt 0 view .LVU154 716 0026 2046 mov r0, r4 717 0028 10BD pop {r4, pc} 153:Core/Src/main.c **** 718 .loc 1 153 1 view .LVU155 719 .cfi_endproc 720 .LFE143: 722 .section .text.Enter_Device_ID,"ax",%progbits 723 .align 1 724 .global Enter_Device_ID 725 .syntax unified 726 .thumb 727 .thumb_func 728 .fpu fpv4-sp-d16 730 Enter_Device_ID: 731 .LVL56: 732 .LFB144: 155:Core/Src/main.c **** // Enter ID mode 733 .loc 1 155 53 is_stmt 1 view -0 734 .cfi_startproc 735 @ args = 0, pretend = 0, frame = 0 736 @ frame_needed = 0, uses_anonymous_args = 0 155:Core/Src/main.c **** // Enter ID mode 737 .loc 1 155 53 is_stmt 0 view .LVU157 738 0000 38B5 push {r3, r4, r5, lr} 739 .LCFI18: 740 .cfi_def_cfa_offset 16 741 .cfi_offset 3, -16 742 .cfi_offset 4, -12 743 .cfi_offset 5, -8 744 .cfi_offset 14, -4 745 0002 0546 mov r5, r0 746 0004 0C46 mov r4, r1 157:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 747 .loc 1 157 3 is_stmt 1 view .LVU158 748 0006 AA21 movs r1, #170 749 .LVL57: 157:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 750 .loc 1 157 3 is_stmt 0 view .LVU159 751 0008 45F25550 movw r0, #21845 752 .LVL58: 157:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 753 .loc 1 157 3 view .LVU160 754 000c FFF7FEFF bl Write_Command 755 .LVL59: 158:Core/Src/main.c **** Write_Command(0x5555, 0x90); 756 .loc 1 158 3 is_stmt 1 view .LVU161 757 0010 5521 movs r1, #85 ARM GAS /tmp/ccg6eVgO.s page 22 758 0012 42F6AA20 movw r0, #10922 759 0016 FFF7FEFF bl Write_Command 760 .LVL60: 159:Core/Src/main.c **** 761 .loc 1 159 3 view .LVU162 762 001a 9021 movs r1, #144 763 001c 45F25550 movw r0, #21845 764 0020 FFF7FEFF bl Write_Command 765 .LVL61: 162:Core/Src/main.c **** 766 .loc 1 162 3 view .LVU163 162:Core/Src/main.c **** 767 .loc 1 162 19 is_stmt 0 view .LVU164 768 0024 0020 movs r0, #0 769 0026 FFF7FEFF bl Flash_ReadByte 770 .LVL62: 162:Core/Src/main.c **** 771 .loc 1 162 17 view .LVU165 772 002a 2860 str r0, [r5] 165:Core/Src/main.c **** 773 .loc 1 165 3 is_stmt 1 view .LVU166 165:Core/Src/main.c **** 774 .loc 1 165 13 is_stmt 0 view .LVU167 775 002c 0120 movs r0, #1 776 002e FFF7FEFF bl Flash_ReadByte 777 .LVL63: 165:Core/Src/main.c **** 778 .loc 1 165 11 view .LVU168 779 0032 2060 str r0, [r4] 168:Core/Src/main.c **** } 780 .loc 1 168 3 is_stmt 1 view .LVU169 781 0034 F021 movs r1, #240 782 0036 45F25550 movw r0, #21845 783 003a FFF7FEFF bl Write_Command 784 .LVL64: 169:Core/Src/main.c **** 785 .loc 1 169 1 is_stmt 0 view .LVU170 786 003e 38BD pop {r3, r4, r5, pc} 169:Core/Src/main.c **** 787 .loc 1 169 1 view .LVU171 788 .cfi_endproc 789 .LFE144: 791 .section .text.Address_Pins_Init,"ax",%progbits 792 .align 1 793 .global Address_Pins_Init 794 .syntax unified 795 .thumb 796 .thumb_func 797 .fpu fpv4-sp-d16 799 Address_Pins_Init: 800 .LFB148: 257:Core/Src/main.c **** GPIO_InitTypeDef GPIOC_InitStruct = {0}; 801 .loc 1 257 29 is_stmt 1 view -0 802 .cfi_startproc 803 @ args = 0, pretend = 0, frame = 40 804 @ frame_needed = 0, uses_anonymous_args = 0 805 0000 70B5 push {r4, r5, r6, lr} ARM GAS /tmp/ccg6eVgO.s page 23 806 .LCFI19: 807 .cfi_def_cfa_offset 16 808 .cfi_offset 4, -16 809 .cfi_offset 5, -12 810 .cfi_offset 6, -8 811 .cfi_offset 14, -4 812 0002 8AB0 sub sp, sp, #40 813 .LCFI20: 814 .cfi_def_cfa_offset 56 258:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs 815 .loc 1 258 3 view .LVU173 258:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs 816 .loc 1 258 20 is_stmt 0 view .LVU174 817 0004 0024 movs r4, #0 818 0006 0594 str r4, [sp, #20] 819 0008 0694 str r4, [sp, #24] 820 000a 0794 str r4, [sp, #28] 821 000c 0894 str r4, [sp, #32] 822 000e 0994 str r4, [sp, #36] 260:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 823 .loc 1 260 3 is_stmt 1 view .LVU175 260:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 824 .loc 1 260 24 is_stmt 0 view .LVU176 825 0010 4FF6FF73 movw r3, #65535 826 0014 0593 str r3, [sp, #20] 264:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 827 .loc 1 264 3 is_stmt 1 view .LVU177 264:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 828 .loc 1 264 25 is_stmt 0 view .LVU178 829 0016 0126 movs r6, #1 830 0018 0696 str r6, [sp, #24] 265:Core/Src/main.c **** GPIOC_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 831 .loc 1 265 3 is_stmt 1 view .LVU179 266:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 832 .loc 1 266 3 view .LVU180 266:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 833 .loc 1 266 26 is_stmt 0 view .LVU181 834 001a 0225 movs r5, #2 835 001c 0895 str r5, [sp, #32] 267:Core/Src/main.c **** 836 .loc 1 267 3 is_stmt 1 view .LVU182 837 001e 05A9 add r1, sp, #20 838 0020 0848 ldr r0, .L52 839 0022 FFF7FEFF bl HAL_GPIO_Init 840 .LVL65: 270:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 841 .loc 1 270 3 view .LVU183 270:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 842 .loc 1 270 20 is_stmt 0 view .LVU184 843 0026 0094 str r4, [sp] 844 0028 0194 str r4, [sp, #4] 845 002a 0294 str r4, [sp, #8] 846 002c 0394 str r4, [sp, #12] 847 002e 0494 str r4, [sp, #16] 272:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 848 .loc 1 272 3 is_stmt 1 view .LVU185 272:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output ARM GAS /tmp/ccg6eVgO.s page 24 849 .loc 1 272 24 is_stmt 0 view .LVU186 850 0030 1F23 movs r3, #31 851 0032 0093 str r3, [sp] 273:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 852 .loc 1 273 3 is_stmt 1 view .LVU187 273:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 853 .loc 1 273 25 is_stmt 0 view .LVU188 854 0034 0196 str r6, [sp, #4] 274:Core/Src/main.c **** GPIOB_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 855 .loc 1 274 3 is_stmt 1 view .LVU189 275:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); 856 .loc 1 275 3 view .LVU190 275:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); 857 .loc 1 275 26 is_stmt 0 view .LVU191 858 0036 0395 str r5, [sp, #12] 276:Core/Src/main.c **** } 859 .loc 1 276 3 is_stmt 1 view .LVU192 860 0038 6946 mov r1, sp 861 003a 0348 ldr r0, .L52+4 862 003c FFF7FEFF bl HAL_GPIO_Init 863 .LVL66: 277:Core/Src/main.c **** 864 .loc 1 277 1 is_stmt 0 view .LVU193 865 0040 0AB0 add sp, sp, #40 866 .LCFI21: 867 .cfi_def_cfa_offset 16 868 @ sp needed 869 0042 70BD pop {r4, r5, r6, pc} 870 .L53: 871 .align 2 872 .L52: 873 0044 00080240 .word 1073874944 874 0048 00040240 .word 1073873920 875 .cfi_endproc 876 .LFE148: 878 .section .text.Command_Pins_Init,"ax",%progbits 879 .align 1 880 .global Command_Pins_Init 881 .syntax unified 882 .thumb 883 .thumb_func 884 .fpu fpv4-sp-d16 886 Command_Pins_Init: 887 .LFB149: 279:Core/Src/main.c **** // PA8-10 as outputs pins 888 .loc 1 279 29 is_stmt 1 view -0 889 .cfi_startproc 890 @ args = 0, pretend = 0, frame = 24 891 @ frame_needed = 0, uses_anonymous_args = 0 892 0000 00B5 push {lr} 893 .LCFI22: 894 .cfi_def_cfa_offset 4 895 .cfi_offset 14, -4 896 0002 87B0 sub sp, sp, #28 897 .LCFI23: 898 .cfi_def_cfa_offset 32 281:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; ARM GAS /tmp/ccg6eVgO.s page 25 899 .loc 1 281 3 view .LVU195 281:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; 900 .loc 1 281 20 is_stmt 0 view .LVU196 901 0004 0023 movs r3, #0 902 0006 0193 str r3, [sp, #4] 903 0008 0293 str r3, [sp, #8] 904 000a 0393 str r3, [sp, #12] 905 000c 0493 str r3, [sp, #16] 906 000e 0593 str r3, [sp, #20] 282:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 907 .loc 1 282 3 is_stmt 1 view .LVU197 282:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 908 .loc 1 282 24 is_stmt 0 view .LVU198 909 0010 4FF4E063 mov r3, #1792 910 0014 0193 str r3, [sp, #4] 283:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 911 .loc 1 283 3 is_stmt 1 view .LVU199 283:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 912 .loc 1 283 25 is_stmt 0 view .LVU200 913 0016 0123 movs r3, #1 914 0018 0293 str r3, [sp, #8] 284:Core/Src/main.c **** GPIOA_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 915 .loc 1 284 3 is_stmt 1 view .LVU201 285:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 916 .loc 1 285 3 view .LVU202 285:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 917 .loc 1 285 26 is_stmt 0 view .LVU203 918 001a 0223 movs r3, #2 919 001c 0493 str r3, [sp, #16] 286:Core/Src/main.c **** } 920 .loc 1 286 3 is_stmt 1 view .LVU204 921 001e 01A9 add r1, sp, #4 922 0020 0248 ldr r0, .L56 923 0022 FFF7FEFF bl HAL_GPIO_Init 924 .LVL67: 287:Core/Src/main.c **** 925 .loc 1 287 1 is_stmt 0 view .LVU205 926 0026 07B0 add sp, sp, #28 927 .LCFI24: 928 .cfi_def_cfa_offset 4 929 @ sp needed 930 0028 5DF804FB ldr pc, [sp], #4 931 .L57: 932 .align 2 933 .L56: 934 002c 00000240 .word 1073872896 935 .cfi_endproc 936 .LFE149: 938 .section .text.debug_print,"ax",%progbits 939 .align 1 940 .global debug_print 941 .syntax unified 942 .thumb 943 .thumb_func 944 .fpu fpv4-sp-d16 946 debug_print: 947 .LVL68: ARM GAS /tmp/ccg6eVgO.s page 26 948 .LFB150: 289:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 949 .loc 1 289 35 is_stmt 1 view -0 950 .cfi_startproc 951 @ args = 0, pretend = 0, frame = 0 952 @ frame_needed = 0, uses_anonymous_args = 0 289:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 953 .loc 1 289 35 is_stmt 0 view .LVU207 954 0000 10B5 push {r4, lr} 955 .LCFI25: 956 .cfi_def_cfa_offset 8 957 .cfi_offset 4, -8 958 .cfi_offset 14, -4 959 0002 0446 mov r4, r0 290:Core/Src/main.c **** } 960 .loc 1 290 3 is_stmt 1 view .LVU208 290:Core/Src/main.c **** } 961 .loc 1 290 45 is_stmt 0 view .LVU209 962 0004 FFF7FEFF bl strlen 963 .LVL69: 290:Core/Src/main.c **** } 964 .loc 1 290 3 view .LVU210 965 0008 4FF0FF33 mov r3, #-1 966 000c 82B2 uxth r2, r0 967 000e 2146 mov r1, r4 968 0010 0148 ldr r0, .L60 969 0012 FFF7FEFF bl HAL_UART_Transmit 970 .LVL70: 291:Core/Src/main.c **** 971 .loc 1 291 1 view .LVU211 972 0016 10BD pop {r4, pc} 973 .LVL71: 974 .L61: 291:Core/Src/main.c **** 975 .loc 1 291 1 view .LVU212 976 .align 2 977 .L60: 978 0018 00000000 .word .LANCHOR1 979 .cfi_endproc 980 .LFE150: 982 .section .text.Error_Handler,"ax",%progbits 983 .align 1 984 .global Error_Handler 985 .syntax unified 986 .thumb 987 .thumb_func 988 .fpu fpv4-sp-d16 990 Error_Handler: 991 .LFB152: 322:Core/Src/main.c **** 323:Core/Src/main.c **** 324:Core/Src/main.c **** /** 325:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 326:Core/Src/main.c **** * @retval None 327:Core/Src/main.c **** */ 328:Core/Src/main.c **** void Error_Handler(void) 329:Core/Src/main.c **** { ARM GAS /tmp/ccg6eVgO.s page 27 992 .loc 1 329 1 is_stmt 1 view -0 993 .cfi_startproc 994 @ Volatile: function does not return. 995 @ args = 0, pretend = 0, frame = 0 996 @ frame_needed = 0, uses_anonymous_args = 0 997 @ link register save eliminated. 330:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 331:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 332:Core/Src/main.c **** __disable_irq(); 998 .loc 1 332 3 view .LVU214 999 .LBB12: 1000 .LBI12: 1001 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.4.1 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 27. May 2021 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline ARM GAS /tmp/ccg6eVgO.s page 28 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccg6eVgO.s page 29 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { ARM GAS /tmp/ccg6eVgO.s page 30 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL __StackSeal 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE 8U 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201:Drivers/CMSIS/Include/cmsis_gcc.h **** } 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 207:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 208:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 212:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 213:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) ARM GAS /tmp/ccg6eVgO.s page 31 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 225:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 226:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 227:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 232:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 233:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi":::"memory") 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 241:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe":::"memory") 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 247:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 248:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 254:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 255:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 257:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** { 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 261:Drivers/CMSIS/Include/cmsis_gcc.h **** } 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 265:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 266:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 267:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 268:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 270:Drivers/CMSIS/Include/cmsis_gcc.h **** { 271:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 272:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccg6eVgO.s page 32 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 277:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 278:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 279:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 281:Drivers/CMSIS/Include/cmsis_gcc.h **** { 282:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 283:Drivers/CMSIS/Include/cmsis_gcc.h **** } 284:Drivers/CMSIS/Include/cmsis_gcc.h **** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** 286:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 288:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 289:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 290:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 291:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 293:Drivers/CMSIS/Include/cmsis_gcc.h **** { 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 298:Drivers/CMSIS/Include/cmsis_gcc.h **** 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 300:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 306:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 307:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 308:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 309:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 310:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 312:Drivers/CMSIS/Include/cmsis_gcc.h **** { 313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** } 318:Drivers/CMSIS/Include/cmsis_gcc.h **** 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 321:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 322:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 323:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 324:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 325:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 327:Drivers/CMSIS/Include/cmsis_gcc.h **** { 328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 329:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); ARM GAS /tmp/ccg6eVgO.s page 33 330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 331:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 336:Drivers/CMSIS/Include/cmsis_gcc.h **** } 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 343:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 344:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 345:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 347:Drivers/CMSIS/Include/cmsis_gcc.h **** { 348:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; 349:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 350:Drivers/CMSIS/Include/cmsis_gcc.h **** { 351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 352:Drivers/CMSIS/Include/cmsis_gcc.h **** } 353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 354:Drivers/CMSIS/Include/cmsis_gcc.h **** } 355:Drivers/CMSIS/Include/cmsis_gcc.h **** 356:Drivers/CMSIS/Include/cmsis_gcc.h **** 357:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 358:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 359:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 360:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 361:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 362:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 363:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 365:Drivers/CMSIS/Include/cmsis_gcc.h **** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** 367:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 369:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { 375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 379:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); 381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 382:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** 384:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 386:Drivers/CMSIS/Include/cmsis_gcc.h **** { ARM GAS /tmp/ccg6eVgO.s page 34 387:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 388:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 389:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 390:Drivers/CMSIS/Include/cmsis_gcc.h **** } 391:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 393:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 394:Drivers/CMSIS/Include/cmsis_gcc.h **** } 395:Drivers/CMSIS/Include/cmsis_gcc.h **** 396:Drivers/CMSIS/Include/cmsis_gcc.h **** 397:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 398:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 399:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 400:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 402:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 404:Drivers/CMSIS/Include/cmsis_gcc.h **** { 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially. 407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any 409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it 410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. 413:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U) 415:Drivers/CMSIS/Include/cmsis_gcc.h **** { 416:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U; 417:Drivers/CMSIS/Include/cmsis_gcc.h **** } 418:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value); 419:Drivers/CMSIS/Include/cmsis_gcc.h **** } 420:Drivers/CMSIS/Include/cmsis_gcc.h **** 421:Drivers/CMSIS/Include/cmsis_gcc.h **** 422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 426:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 431:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 433:Drivers/CMSIS/Include/cmsis_gcc.h **** { 434:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 435:Drivers/CMSIS/Include/cmsis_gcc.h **** 436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 439:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 440:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 441:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccg6eVgO.s page 35 444:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** } 446:Drivers/CMSIS/Include/cmsis_gcc.h **** 447:Drivers/CMSIS/Include/cmsis_gcc.h **** 448:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 449:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 451:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 452:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 453:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 455:Drivers/CMSIS/Include/cmsis_gcc.h **** { 456:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 459:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 461:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 462:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 471:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 490:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 491:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 492:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 494:Drivers/CMSIS/Include/cmsis_gcc.h **** { 495:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 498:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 499:Drivers/CMSIS/Include/cmsis_gcc.h **** } 500:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccg6eVgO.s page 36 501:Drivers/CMSIS/Include/cmsis_gcc.h **** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 506:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 507:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 508:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 509:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 511:Drivers/CMSIS/Include/cmsis_gcc.h **** { 512:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 513:Drivers/CMSIS/Include/cmsis_gcc.h **** 514:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 515:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 516:Drivers/CMSIS/Include/cmsis_gcc.h **** } 517:Drivers/CMSIS/Include/cmsis_gcc.h **** 518:Drivers/CMSIS/Include/cmsis_gcc.h **** 519:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 520:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Remove the exclusive lock 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Removes the exclusive lock which is created by LDREX. 539:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void) 541:Drivers/CMSIS/Include/cmsis_gcc.h **** { 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory"); 543:Drivers/CMSIS/Include/cmsis_gcc.h **** } 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 547:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 554:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 557:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated ARM GAS /tmp/ccg6eVgO.s page 37 558:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (1..32) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 560:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** int32_t __RES, __ARG1 = (ARG1); \ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 566:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 567:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 568:Drivers/CMSIS/Include/cmsis_gcc.h **** 569:Drivers/CMSIS/Include/cmsis_gcc.h **** 570:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 571:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 572:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 573:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 574:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (0..31) 575:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 576:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** 585:Drivers/CMSIS/Include/cmsis_gcc.h **** 586:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 587:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right with Extend (32 bit) 588:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Moves each bit of a bitstring right by one bit. 589:Drivers/CMSIS/Include/cmsis_gcc.h **** The carry input is shifted in at the left end of the bitstring. 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to rotate 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 592:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 594:Drivers/CMSIS/Include/cmsis_gcc.h **** { 595:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 596:Drivers/CMSIS/Include/cmsis_gcc.h **** 597:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** } 600:Drivers/CMSIS/Include/cmsis_gcc.h **** 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 8 bit value. 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 607:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 609:Drivers/CMSIS/Include/cmsis_gcc.h **** { 610:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 611:Drivers/CMSIS/Include/cmsis_gcc.h **** 612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else ARM GAS /tmp/ccg6eVgO.s page 38 615:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 616:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 617:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 620:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 621:Drivers/CMSIS/Include/cmsis_gcc.h **** } 622:Drivers/CMSIS/Include/cmsis_gcc.h **** 623:Drivers/CMSIS/Include/cmsis_gcc.h **** 624:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 625:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (16 bit) 626:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 16 bit values. 627:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 628:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 629:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** { 632:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 633:Drivers/CMSIS/Include/cmsis_gcc.h **** 634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 639:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 642:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** } 644:Drivers/CMSIS/Include/cmsis_gcc.h **** 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (32 bit) 648:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 32 bit values. 649:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 650:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 651:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 653:Drivers/CMSIS/Include/cmsis_gcc.h **** { 654:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 658:Drivers/CMSIS/Include/cmsis_gcc.h **** } 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 660:Drivers/CMSIS/Include/cmsis_gcc.h **** 661:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 662:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (8 bit) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 8 bit values. 664:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 665:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 666:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 668:Drivers/CMSIS/Include/cmsis_gcc.h **** { 669:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccg6eVgO.s page 39 672:Drivers/CMSIS/Include/cmsis_gcc.h **** 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (16 bit) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 16 bit values. 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 682:Drivers/CMSIS/Include/cmsis_gcc.h **** } 683:Drivers/CMSIS/Include/cmsis_gcc.h **** 684:Drivers/CMSIS/Include/cmsis_gcc.h **** 685:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 686:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (32 bit) 687:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 32 bit values. 688:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 689:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 690:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 692:Drivers/CMSIS/Include/cmsis_gcc.h **** { 693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 694:Drivers/CMSIS/Include/cmsis_gcc.h **** } 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 699:Drivers/CMSIS/Include/cmsis_gcc.h **** 700:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 703:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 704:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (1..32) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 706:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** { 709:Drivers/CMSIS/Include/cmsis_gcc.h **** if ((sat >= 1U) && (sat <= 32U)) 710:Drivers/CMSIS/Include/cmsis_gcc.h **** { 711:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ; 713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max) 714:Drivers/CMSIS/Include/cmsis_gcc.h **** { 715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 716:Drivers/CMSIS/Include/cmsis_gcc.h **** } 717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min) 718:Drivers/CMSIS/Include/cmsis_gcc.h **** { 719:Drivers/CMSIS/Include/cmsis_gcc.h **** return min; 720:Drivers/CMSIS/Include/cmsis_gcc.h **** } 721:Drivers/CMSIS/Include/cmsis_gcc.h **** } 722:Drivers/CMSIS/Include/cmsis_gcc.h **** return val; 723:Drivers/CMSIS/Include/cmsis_gcc.h **** } 724:Drivers/CMSIS/Include/cmsis_gcc.h **** 725:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 726:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 727:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 728:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated ARM GAS /tmp/ccg6eVgO.s page 40 729:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (0..31) 730:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 731:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 733:Drivers/CMSIS/Include/cmsis_gcc.h **** { 734:Drivers/CMSIS/Include/cmsis_gcc.h **** if (sat <= 31U) 735:Drivers/CMSIS/Include/cmsis_gcc.h **** { 736:Drivers/CMSIS/Include/cmsis_gcc.h **** const uint32_t max = ((1U << sat) - 1U); 737:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > (int32_t)max) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** { 739:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 740:Drivers/CMSIS/Include/cmsis_gcc.h **** } 741:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < 0) 742:Drivers/CMSIS/Include/cmsis_gcc.h **** { 743:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 744:Drivers/CMSIS/Include/cmsis_gcc.h **** } 745:Drivers/CMSIS/Include/cmsis_gcc.h **** } 746:Drivers/CMSIS/Include/cmsis_gcc.h **** return (uint32_t)val; 747:Drivers/CMSIS/Include/cmsis_gcc.h **** } 748:Drivers/CMSIS/Include/cmsis_gcc.h **** 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 756:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (8 bit) 758:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB instruction for 8 bit value. 759:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 760:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** { 764:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 767:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 768:Drivers/CMSIS/Include/cmsis_gcc.h **** } 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values. 774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 775:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 776:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 778:Drivers/CMSIS/Include/cmsis_gcc.h **** { 779:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 780:Drivers/CMSIS/Include/cmsis_gcc.h **** 781:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** } 784:Drivers/CMSIS/Include/cmsis_gcc.h **** 785:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccg6eVgO.s page 41 786:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (32 bit) 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA instruction for 32 bit values. 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 795:Drivers/CMSIS/Include/cmsis_gcc.h **** 796:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 797:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 798:Drivers/CMSIS/Include/cmsis_gcc.h **** } 799:Drivers/CMSIS/Include/cmsis_gcc.h **** 800:Drivers/CMSIS/Include/cmsis_gcc.h **** 801:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 802:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (8 bit) 803:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB instruction for 8 bit values. 804:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 805:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 806:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 808:Drivers/CMSIS/Include/cmsis_gcc.h **** { 809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810:Drivers/CMSIS/Include/cmsis_gcc.h **** } 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 814:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (16 bit) 815:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH instruction for 16 bit values. 816:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 817:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 818:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 820:Drivers/CMSIS/Include/cmsis_gcc.h **** { 821:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 822:Drivers/CMSIS/Include/cmsis_gcc.h **** } 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** 825:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit) 827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values. 828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 830:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 832:Drivers/CMSIS/Include/cmsis_gcc.h **** { 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 834:Drivers/CMSIS/Include/cmsis_gcc.h **** } 835:Drivers/CMSIS/Include/cmsis_gcc.h **** 836:Drivers/CMSIS/Include/cmsis_gcc.h **** 837:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (8 bit) 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB exclusive instruction for 8 bit value. 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 841:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 842:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccg6eVgO.s page 42 843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) 844:Drivers/CMSIS/Include/cmsis_gcc.h **** { 845:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 846:Drivers/CMSIS/Include/cmsis_gcc.h **** 847:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 848:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 849:Drivers/CMSIS/Include/cmsis_gcc.h **** } 850:Drivers/CMSIS/Include/cmsis_gcc.h **** 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (16 bit) 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH exclusive instruction for 16 bit values. 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 857:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) 859:Drivers/CMSIS/Include/cmsis_gcc.h **** { 860:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 861:Drivers/CMSIS/Include/cmsis_gcc.h **** 862:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 864:Drivers/CMSIS/Include/cmsis_gcc.h **** } 865:Drivers/CMSIS/Include/cmsis_gcc.h **** 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit) 869:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA exclusive instruction for 32 bit values. 870:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 871:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 872:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) 874:Drivers/CMSIS/Include/cmsis_gcc.h **** { 875:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 878:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } 880:Drivers/CMSIS/Include/cmsis_gcc.h **** 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit) 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values. 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 889:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** { 892:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 895:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 896:Drivers/CMSIS/Include/cmsis_gcc.h **** } 897:Drivers/CMSIS/Include/cmsis_gcc.h **** 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccg6eVgO.s page 43 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (16 bit) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH exclusive instruction for 16 bit values. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 903:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 904:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 905:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 906:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 908:Drivers/CMSIS/Include/cmsis_gcc.h **** { 909:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 912:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 913:Drivers/CMSIS/Include/cmsis_gcc.h **** } 914:Drivers/CMSIS/Include/cmsis_gcc.h **** 915:Drivers/CMSIS/Include/cmsis_gcc.h **** 916:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (32 bit) 918:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL exclusive instruction for 32 bit values. 919:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925:Drivers/CMSIS/Include/cmsis_gcc.h **** { 926:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo 929:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 930:Drivers/CMSIS/Include/cmsis_gcc.h **** } 931:Drivers/CMSIS/Include/cmsis_gcc.h **** 932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** 935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 942:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 946:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 947:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 948:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 950:Drivers/CMSIS/Include/cmsis_gcc.h **** { 951:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 952:Drivers/CMSIS/Include/cmsis_gcc.h **** } 953:Drivers/CMSIS/Include/cmsis_gcc.h **** 954:Drivers/CMSIS/Include/cmsis_gcc.h **** 955:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 956:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts ARM GAS /tmp/ccg6eVgO.s page 44 957:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 958:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 959:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 1002 .loc 2 960 27 view .LVU215 1003 .LBB13: 961:Drivers/CMSIS/Include/cmsis_gcc.h **** { 962:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 1004 .loc 2 962 3 view .LVU216 1005 .syntax unified 1006 @ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1007 0000 72B6 cpsid i 1008 @ 0 "" 2 1009 .thumb 1010 .syntax unified 1011 .L63: 1012 .LBE13: 1013 .LBE12: 333:Core/Src/main.c **** while (1) 1014 .loc 1 333 3 discriminator 1 view .LVU217 334:Core/Src/main.c **** { 335:Core/Src/main.c **** } 1015 .loc 1 335 3 discriminator 1 view .LVU218 333:Core/Src/main.c **** while (1) 1016 .loc 1 333 9 discriminator 1 view .LVU219 1017 0002 FEE7 b .L63 1018 .cfi_endproc 1019 .LFE152: 1021 .section .text.MX_USART2_UART_Init,"ax",%progbits 1022 .align 1 1023 .syntax unified 1024 .thumb 1025 .thumb_func 1026 .fpu fpv4-sp-d16 1028 MX_USART2_UART_Init: 1029 .LFB146: 223:Core/Src/main.c **** huart2.Instance = USART2; 1030 .loc 1 223 1 view -0 1031 .cfi_startproc 1032 @ args = 0, pretend = 0, frame = 0 1033 @ frame_needed = 0, uses_anonymous_args = 0 1034 0000 08B5 push {r3, lr} 1035 .LCFI26: 1036 .cfi_def_cfa_offset 8 1037 .cfi_offset 3, -8 1038 .cfi_offset 14, -4 224:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 1039 .loc 1 224 3 view .LVU221 224:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 1040 .loc 1 224 19 is_stmt 0 view .LVU222 1041 0002 0A48 ldr r0, .L68 1042 0004 0A4B ldr r3, .L68+4 1043 0006 0360 str r3, [r0] 225:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 1044 .loc 1 225 3 is_stmt 1 view .LVU223 225:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 1045 .loc 1 225 24 is_stmt 0 view .LVU224 ARM GAS /tmp/ccg6eVgO.s page 45 1046 0008 4FF4E133 mov r3, #115200 1047 000c 4360 str r3, [r0, #4] 226:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 1048 .loc 1 226 3 is_stmt 1 view .LVU225 226:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 1049 .loc 1 226 26 is_stmt 0 view .LVU226 1050 000e 0023 movs r3, #0 1051 0010 8360 str r3, [r0, #8] 227:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 1052 .loc 1 227 3 is_stmt 1 view .LVU227 227:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 1053 .loc 1 227 24 is_stmt 0 view .LVU228 1054 0012 C360 str r3, [r0, #12] 228:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 1055 .loc 1 228 3 is_stmt 1 view .LVU229 228:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 1056 .loc 1 228 22 is_stmt 0 view .LVU230 1057 0014 0361 str r3, [r0, #16] 229:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 1058 .loc 1 229 3 is_stmt 1 view .LVU231 229:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 1059 .loc 1 229 20 is_stmt 0 view .LVU232 1060 0016 0C22 movs r2, #12 1061 0018 4261 str r2, [r0, #20] 230:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 1062 .loc 1 230 3 is_stmt 1 view .LVU233 230:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 1063 .loc 1 230 25 is_stmt 0 view .LVU234 1064 001a 8361 str r3, [r0, #24] 231:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 1065 .loc 1 231 3 is_stmt 1 view .LVU235 231:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 1066 .loc 1 231 28 is_stmt 0 view .LVU236 1067 001c C361 str r3, [r0, #28] 232:Core/Src/main.c **** { 1068 .loc 1 232 3 is_stmt 1 view .LVU237 232:Core/Src/main.c **** { 1069 .loc 1 232 7 is_stmt 0 view .LVU238 1070 001e FFF7FEFF bl HAL_UART_Init 1071 .LVL72: 232:Core/Src/main.c **** { 1072 .loc 1 232 6 view .LVU239 1073 0022 00B9 cbnz r0, .L67 237:Core/Src/main.c **** 1074 .loc 1 237 1 view .LVU240 1075 0024 08BD pop {r3, pc} 1076 .L67: 234:Core/Src/main.c **** } 1077 .loc 1 234 5 is_stmt 1 view .LVU241 1078 0026 FFF7FEFF bl Error_Handler 1079 .LVL73: 1080 .L69: 1081 002a 00BF .align 2 1082 .L68: 1083 002c 00000000 .word .LANCHOR1 1084 0030 00440040 .word 1073759232 1085 .cfi_endproc ARM GAS /tmp/ccg6eVgO.s page 46 1086 .LFE146: 1088 .section .text.SystemClock_Config,"ax",%progbits 1089 .align 1 1090 .global SystemClock_Config 1091 .syntax unified 1092 .thumb 1093 .thumb_func 1094 .fpu fpv4-sp-d16 1096 SystemClock_Config: 1097 .LFB145: 176:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 1098 .loc 1 176 1 view -0 1099 .cfi_startproc 1100 @ args = 0, pretend = 0, frame = 80 1101 @ frame_needed = 0, uses_anonymous_args = 0 1102 0000 00B5 push {lr} 1103 .LCFI27: 1104 .cfi_def_cfa_offset 4 1105 .cfi_offset 14, -4 1106 0002 95B0 sub sp, sp, #84 1107 .LCFI28: 1108 .cfi_def_cfa_offset 88 177:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1109 .loc 1 177 3 view .LVU243 177:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1110 .loc 1 177 22 is_stmt 0 view .LVU244 1111 0004 3022 movs r2, #48 1112 0006 0021 movs r1, #0 1113 0008 08A8 add r0, sp, #32 1114 000a FFF7FEFF bl memset 1115 .LVL74: 178:Core/Src/main.c **** 1116 .loc 1 178 3 is_stmt 1 view .LVU245 178:Core/Src/main.c **** 1117 .loc 1 178 22 is_stmt 0 view .LVU246 1118 000e 0023 movs r3, #0 1119 0010 0393 str r3, [sp, #12] 1120 0012 0493 str r3, [sp, #16] 1121 0014 0593 str r3, [sp, #20] 1122 0016 0693 str r3, [sp, #24] 1123 0018 0793 str r3, [sp, #28] 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1124 .loc 1 182 3 is_stmt 1 view .LVU247 1125 .LBB14: 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1126 .loc 1 182 3 view .LVU248 1127 001a 0193 str r3, [sp, #4] 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1128 .loc 1 182 3 view .LVU249 1129 001c 1F4A ldr r2, .L76 1130 001e 116C ldr r1, [r2, #64] 1131 0020 41F08051 orr r1, r1, #268435456 1132 0024 1164 str r1, [r2, #64] 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1133 .loc 1 182 3 view .LVU250 1134 0026 126C ldr r2, [r2, #64] 1135 0028 02F08052 and r2, r2, #268435456 ARM GAS /tmp/ccg6eVgO.s page 47 1136 002c 0192 str r2, [sp, #4] 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1137 .loc 1 182 3 view .LVU251 1138 002e 019A ldr r2, [sp, #4] 1139 .LBE14: 182:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1140 .loc 1 182 3 view .LVU252 183:Core/Src/main.c **** 1141 .loc 1 183 3 view .LVU253 1142 .LBB15: 183:Core/Src/main.c **** 1143 .loc 1 183 3 view .LVU254 1144 0030 0293 str r3, [sp, #8] 183:Core/Src/main.c **** 1145 .loc 1 183 3 view .LVU255 1146 0032 1B49 ldr r1, .L76+4 1147 0034 0A68 ldr r2, [r1] 1148 0036 22F44042 bic r2, r2, #49152 1149 003a 42F40042 orr r2, r2, #32768 1150 003e 0A60 str r2, [r1] 183:Core/Src/main.c **** 1151 .loc 1 183 3 view .LVU256 1152 0040 0A68 ldr r2, [r1] 1153 0042 02F44042 and r2, r2, #49152 1154 0046 0292 str r2, [sp, #8] 183:Core/Src/main.c **** 1155 .loc 1 183 3 view .LVU257 1156 0048 029A ldr r2, [sp, #8] 1157 .LBE15: 183:Core/Src/main.c **** 1158 .loc 1 183 3 view .LVU258 188:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1159 .loc 1 188 3 view .LVU259 188:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1160 .loc 1 188 36 is_stmt 0 view .LVU260 1161 004a 0221 movs r1, #2 1162 004c 0891 str r1, [sp, #32] 189:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1163 .loc 1 189 3 is_stmt 1 view .LVU261 189:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1164 .loc 1 189 30 is_stmt 0 view .LVU262 1165 004e 0122 movs r2, #1 1166 0050 0B92 str r2, [sp, #44] 190:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1167 .loc 1 190 3 is_stmt 1 view .LVU263 190:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1168 .loc 1 190 41 is_stmt 0 view .LVU264 1169 0052 1022 movs r2, #16 1170 0054 0C92 str r2, [sp, #48] 191:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 1171 .loc 1 191 3 is_stmt 1 view .LVU265 191:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 1172 .loc 1 191 34 is_stmt 0 view .LVU266 1173 0056 0E91 str r1, [sp, #56] 192:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; 1174 .loc 1 192 3 is_stmt 1 view .LVU267 192:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; ARM GAS /tmp/ccg6eVgO.s page 48 1175 .loc 1 192 35 is_stmt 0 view .LVU268 1176 0058 0F93 str r3, [sp, #60] 193:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 1177 .loc 1 193 3 is_stmt 1 view .LVU269 193:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 1178 .loc 1 193 30 is_stmt 0 view .LVU270 1179 005a 1092 str r2, [sp, #64] 194:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 1180 .loc 1 194 3 is_stmt 1 view .LVU271 194:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 1181 .loc 1 194 30 is_stmt 0 view .LVU272 1182 005c 4FF4A873 mov r3, #336 1183 0060 1193 str r3, [sp, #68] 195:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 1184 .loc 1 195 3 is_stmt 1 view .LVU273 195:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 1185 .loc 1 195 30 is_stmt 0 view .LVU274 1186 0062 0423 movs r3, #4 1187 0064 1293 str r3, [sp, #72] 196:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1188 .loc 1 196 3 is_stmt 1 view .LVU275 196:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1189 .loc 1 196 30 is_stmt 0 view .LVU276 1190 0066 0723 movs r3, #7 1191 0068 1393 str r3, [sp, #76] 197:Core/Src/main.c **** { 1192 .loc 1 197 3 is_stmt 1 view .LVU277 197:Core/Src/main.c **** { 1193 .loc 1 197 7 is_stmt 0 view .LVU278 1194 006a 08A8 add r0, sp, #32 1195 006c FFF7FEFF bl HAL_RCC_OscConfig 1196 .LVL75: 197:Core/Src/main.c **** { 1197 .loc 1 197 6 view .LVU279 1198 0070 80B9 cbnz r0, .L74 204:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1199 .loc 1 204 3 is_stmt 1 view .LVU280 204:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1200 .loc 1 204 31 is_stmt 0 view .LVU281 1201 0072 0F23 movs r3, #15 1202 0074 0393 str r3, [sp, #12] 206:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1203 .loc 1 206 3 is_stmt 1 view .LVU282 206:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1204 .loc 1 206 34 is_stmt 0 view .LVU283 1205 0076 0221 movs r1, #2 1206 0078 0491 str r1, [sp, #16] 207:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 1207 .loc 1 207 3 is_stmt 1 view .LVU284 207:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 1208 .loc 1 207 35 is_stmt 0 view .LVU285 1209 007a 0023 movs r3, #0 1210 007c 0593 str r3, [sp, #20] 208:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1211 .loc 1 208 3 is_stmt 1 view .LVU286 208:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1212 .loc 1 208 36 is_stmt 0 view .LVU287 ARM GAS /tmp/ccg6eVgO.s page 49 1213 007e 4FF48052 mov r2, #4096 1214 0082 0692 str r2, [sp, #24] 209:Core/Src/main.c **** 1215 .loc 1 209 3 is_stmt 1 view .LVU288 209:Core/Src/main.c **** 1216 .loc 1 209 36 is_stmt 0 view .LVU289 1217 0084 0793 str r3, [sp, #28] 211:Core/Src/main.c **** { 1218 .loc 1 211 3 is_stmt 1 view .LVU290 211:Core/Src/main.c **** { 1219 .loc 1 211 7 is_stmt 0 view .LVU291 1220 0086 03A8 add r0, sp, #12 1221 0088 FFF7FEFF bl HAL_RCC_ClockConfig 1222 .LVL76: 211:Core/Src/main.c **** { 1223 .loc 1 211 6 view .LVU292 1224 008c 20B9 cbnz r0, .L75 215:Core/Src/main.c **** 1225 .loc 1 215 1 view .LVU293 1226 008e 15B0 add sp, sp, #84 1227 .LCFI29: 1228 .cfi_remember_state 1229 .cfi_def_cfa_offset 4 1230 @ sp needed 1231 0090 5DF804FB ldr pc, [sp], #4 1232 .L74: 1233 .LCFI30: 1234 .cfi_restore_state 199:Core/Src/main.c **** } 1235 .loc 1 199 5 is_stmt 1 view .LVU294 1236 0094 FFF7FEFF bl Error_Handler 1237 .LVL77: 1238 .L75: 213:Core/Src/main.c **** } 1239 .loc 1 213 5 view .LVU295 1240 0098 FFF7FEFF bl Error_Handler 1241 .LVL78: 1242 .L77: 1243 .align 2 1244 .L76: 1245 009c 00380240 .word 1073887232 1246 00a0 00700040 .word 1073770496 1247 .cfi_endproc 1248 .LFE145: 1250 .section .rodata.main.str1.4,"aMS",%progbits,1 1251 .align 2 1252 .LC2: 1253 0000 30782530 .ascii "0x%02X \015\012\000" 1253 3258200D 1253 0A00 1254 000a 0000 .align 2 1255 .LC3: 1256 000c 4D616E75 .ascii "Manufacturer ID = \015\012\000" 1256 66616374 1256 75726572 1256 20494420 1256 3D200D0A ARM GAS /tmp/ccg6eVgO.s page 50 1257 0021 000000 .align 2 1258 .LC4: 1259 0024 44657669 .ascii "Device ID = \015\012\000" 1259 63652049 1259 44203D20 1259 0D0A00 1260 .section .text.main,"ax",%progbits 1261 .align 1 1262 .global main 1263 .syntax unified 1264 .thumb 1265 .thumb_func 1266 .fpu fpv4-sp-d16 1268 main: 1269 .LFB137: 40:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 1270 .loc 1 40 1 view -0 1271 .cfi_startproc 1272 @ args = 0, pretend = 0, frame = 8 1273 @ frame_needed = 0, uses_anonymous_args = 0 1274 0000 70B5 push {r4, r5, r6, lr} 1275 .LCFI31: 1276 .cfi_def_cfa_offset 16 1277 .cfi_offset 4, -16 1278 .cfi_offset 5, -12 1279 .cfi_offset 6, -8 1280 .cfi_offset 14, -4 1281 0002 82B0 sub sp, sp, #8 1282 .LCFI32: 1283 .cfi_def_cfa_offset 24 44:Core/Src/main.c **** 1284 .loc 1 44 3 view .LVU297 1285 0004 FFF7FEFF bl HAL_Init 1286 .LVL79: 47:Core/Src/main.c **** 1287 .loc 1 47 3 view .LVU298 1288 0008 FFF7FEFF bl SystemClock_Config 1289 .LVL80: 50:Core/Src/main.c **** MX_USART2_UART_Init(); 1290 .loc 1 50 3 view .LVU299 1291 000c FFF7FEFF bl MX_GPIO_Init 1292 .LVL81: 51:Core/Src/main.c **** 1293 .loc 1 51 3 view .LVU300 1294 0010 FFF7FEFF bl MX_USART2_UART_Init 1295 .LVL82: 53:Core/Src/main.c **** Address_Pins_Init(); 1296 .loc 1 53 3 view .LVU301 1297 0014 0020 movs r0, #0 1298 0016 FFF7FEFF bl Data_Pins_Init 1299 .LVL83: 54:Core/Src/main.c **** Command_Pins_Init(); 1300 .loc 1 54 3 view .LVU302 1301 001a FFF7FEFF bl Address_Pins_Init 1302 .LVL84: 55:Core/Src/main.c **** 1303 .loc 1 55 3 view .LVU303 ARM GAS /tmp/ccg6eVgO.s page 51 1304 001e FFF7FEFF bl Command_Pins_Init 1305 .LVL85: 57:Core/Src/main.c **** Enter_Device_ID(&man_id, &dev_id); 1306 .loc 1 57 3 view .LVU304 58:Core/Src/main.c **** 1307 .loc 1 58 3 view .LVU305 1308 0022 6946 mov r1, sp 1309 0024 01A8 add r0, sp, #4 1310 0026 FFF7FEFF bl Enter_Device_ID 1311 .LVL86: 60:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 1312 .loc 1 60 3 view .LVU306 60:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 1313 .loc 1 60 31 is_stmt 0 view .LVU307 1314 002a 0D20 movs r0, #13 1315 002c FFF7FEFF bl malloc 1316 .LVL87: 1317 0030 0546 mov r5, r0 1318 .LVL88: 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1319 .loc 1 61 3 is_stmt 1 view .LVU308 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1320 .loc 1 61 25 is_stmt 0 view .LVU309 1321 0032 0D20 movs r0, #13 1322 .LVL89: 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1323 .loc 1 61 25 view .LVU310 1324 0034 FFF7FEFF bl malloc 1325 .LVL90: 1326 0038 0446 mov r4, r0 1327 .LVL91: 62:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 1328 .loc 1 62 3 is_stmt 1 view .LVU311 1329 003a 0C4E ldr r6, .L81 1330 003c 019A ldr r2, [sp, #4] 1331 003e 3146 mov r1, r6 1332 0040 2846 mov r0, r5 1333 .LVL92: 62:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 1334 .loc 1 62 3 is_stmt 0 view .LVU312 1335 0042 FFF7FEFF bl sprintf 1336 .LVL93: 63:Core/Src/main.c **** 1337 .loc 1 63 3 is_stmt 1 view .LVU313 1338 0046 009A ldr r2, [sp] 1339 0048 3146 mov r1, r6 1340 004a 2046 mov r0, r4 1341 004c FFF7FEFF bl sprintf 1342 .LVL94: 65:Core/Src/main.c **** debug_print(manufacturer); 1343 .loc 1 65 3 view .LVU314 1344 0050 0748 ldr r0, .L81+4 1345 0052 FFF7FEFF bl debug_print 1346 .LVL95: 66:Core/Src/main.c **** debug_print("Device ID = \r\n"); 1347 .loc 1 66 3 view .LVU315 1348 0056 2846 mov r0, r5 ARM GAS /tmp/ccg6eVgO.s page 52 1349 0058 FFF7FEFF bl debug_print 1350 .LVL96: 67:Core/Src/main.c **** debug_print(device); 1351 .loc 1 67 3 view .LVU316 1352 005c 0548 ldr r0, .L81+8 1353 005e FFF7FEFF bl debug_print 1354 .LVL97: 68:Core/Src/main.c **** 1355 .loc 1 68 3 view .LVU317 1356 0062 2046 mov r0, r4 1357 0064 FFF7FEFF bl debug_print 1358 .LVL98: 1359 .L79: 72:Core/Src/main.c **** { 1360 .loc 1 72 3 discriminator 1 view .LVU318 75:Core/Src/main.c **** 1361 .loc 1 75 3 discriminator 1 view .LVU319 72:Core/Src/main.c **** { 1362 .loc 1 72 9 discriminator 1 view .LVU320 1363 0068 FEE7 b .L79 1364 .L82: 1365 006a 00BF .align 2 1366 .L81: 1367 006c 00000000 .word .LC2 1368 0070 0C000000 .word .LC3 1369 0074 24000000 .word .LC4 1370 .cfi_endproc 1371 .LFE137: 1373 .global huart2 1374 .section .rodata 1375 .align 2 1376 .set .LANCHOR0,. + 0 1377 .LC0: 1378 0000 01000000 .word 1 1379 0004 02000000 .word 2 1380 0008 04000000 .word 4 1381 000c 08000000 .word 8 1382 0010 10000000 .word 16 1383 0014 20000000 .word 32 1384 0018 40000000 .word 64 1385 001c 80000000 .word 128 1386 0020 00010000 .word 256 1387 0024 00020000 .word 512 1388 0028 00040000 .word 1024 1389 002c 00080000 .word 2048 1390 0030 00100000 .word 4096 1391 0034 00200000 .word 8192 1392 0038 01000000 .word 1 1393 003c 02000000 .word 2 1394 0040 04000000 .word 4 1395 0044 08000000 .word 8 1396 0048 10000000 .word 16 1397 .LC1: 1398 004c 01000000 .word 1 1399 0050 02000000 .word 2 1400 0054 00080000 .word 2048 1401 0058 00100000 .word 4096 ARM GAS /tmp/ccg6eVgO.s page 53 1402 005c 10000000 .word 16 1403 0060 20000000 .word 32 1404 0064 40000000 .word 64 1405 0068 80000000 .word 128 1406 .section .bss.huart2,"aw",%nobits 1407 .align 2 1408 .set .LANCHOR1,. + 0 1411 huart2: 1412 0000 00000000 .space 72 1412 00000000 1412 00000000 1412 00000000 1412 00000000 1413 .text 1414 .Letext0: 1415 .file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 1416 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h" 1417 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" 1418 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" 1419 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" 1420 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" 1421 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" 1422 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h" 1423 .file 11 "/usr/include/newlib/string.h" 1424 .file 12 "" 1425 .file 13 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" 1426 .file 14 "/usr/include/newlib/stdlib.h" 1427 .file 15 "/usr/include/newlib/stdio.h" ARM GAS /tmp/ccg6eVgO.s page 54 DEFINED SYMBOLS *ABS*:0000000000000000 main.c /tmp/ccg6eVgO.s:18 .text.MX_GPIO_Init:0000000000000000 $t /tmp/ccg6eVgO.s:25 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init /tmp/ccg6eVgO.s:111 .text.MX_GPIO_Init:000000000000005c $d /tmp/ccg6eVgO.s:116 .text.Write_Address:0000000000000000 $t /tmp/ccg6eVgO.s:123 .text.Write_Address:0000000000000000 Write_Address /tmp/ccg6eVgO.s:236 .text.Write_Address:0000000000000084 $d /tmp/ccg6eVgO.s:243 .text.Write_Command_Pins:0000000000000000 $t /tmp/ccg6eVgO.s:250 .text.Write_Command_Pins:0000000000000000 Write_Command_Pins /tmp/ccg6eVgO.s:305 .text.Write_Command_Pins:000000000000003c $d /tmp/ccg6eVgO.s:310 .text.Data_Pins_Init:0000000000000000 $t /tmp/ccg6eVgO.s:317 .text.Data_Pins_Init:0000000000000000 Data_Pins_Init /tmp/ccg6eVgO.s:385 .text.Data_Pins_Init:0000000000000038 $d /tmp/ccg6eVgO.s:390 .text.Receive_Data:0000000000000000 $t /tmp/ccg6eVgO.s:397 .text.Receive_Data:0000000000000000 Receive_Data /tmp/ccg6eVgO.s:485 .text.Receive_Data:0000000000000048 $d /tmp/ccg6eVgO.s:491 .text.Write_Data:0000000000000000 $t /tmp/ccg6eVgO.s:498 .text.Write_Data:0000000000000000 Write_Data /tmp/ccg6eVgO.s:588 .text.Write_Data:000000000000005c $d /tmp/ccg6eVgO.s:594 .text.Write_Command:0000000000000000 $t /tmp/ccg6eVgO.s:601 .text.Write_Command:0000000000000000 Write_Command /tmp/ccg6eVgO.s:667 .text.Flash_ReadByte:0000000000000000 $t /tmp/ccg6eVgO.s:674 .text.Flash_ReadByte:0000000000000000 Flash_ReadByte /tmp/ccg6eVgO.s:723 .text.Enter_Device_ID:0000000000000000 $t /tmp/ccg6eVgO.s:730 .text.Enter_Device_ID:0000000000000000 Enter_Device_ID /tmp/ccg6eVgO.s:792 .text.Address_Pins_Init:0000000000000000 $t /tmp/ccg6eVgO.s:799 .text.Address_Pins_Init:0000000000000000 Address_Pins_Init /tmp/ccg6eVgO.s:873 .text.Address_Pins_Init:0000000000000044 $d /tmp/ccg6eVgO.s:879 .text.Command_Pins_Init:0000000000000000 $t /tmp/ccg6eVgO.s:886 .text.Command_Pins_Init:0000000000000000 Command_Pins_Init /tmp/ccg6eVgO.s:934 .text.Command_Pins_Init:000000000000002c $d /tmp/ccg6eVgO.s:939 .text.debug_print:0000000000000000 $t /tmp/ccg6eVgO.s:946 .text.debug_print:0000000000000000 debug_print /tmp/ccg6eVgO.s:978 .text.debug_print:0000000000000018 $d /tmp/ccg6eVgO.s:983 .text.Error_Handler:0000000000000000 $t /tmp/ccg6eVgO.s:990 .text.Error_Handler:0000000000000000 Error_Handler /tmp/ccg6eVgO.s:1022 .text.MX_USART2_UART_Init:0000000000000000 $t /tmp/ccg6eVgO.s:1028 .text.MX_USART2_UART_Init:0000000000000000 MX_USART2_UART_Init /tmp/ccg6eVgO.s:1083 .text.MX_USART2_UART_Init:000000000000002c $d /tmp/ccg6eVgO.s:1089 .text.SystemClock_Config:0000000000000000 $t /tmp/ccg6eVgO.s:1096 .text.SystemClock_Config:0000000000000000 SystemClock_Config /tmp/ccg6eVgO.s:1245 .text.SystemClock_Config:000000000000009c $d /tmp/ccg6eVgO.s:1251 .rodata.main.str1.4:0000000000000000 $d /tmp/ccg6eVgO.s:1261 .text.main:0000000000000000 $t /tmp/ccg6eVgO.s:1268 .text.main:0000000000000000 main /tmp/ccg6eVgO.s:1367 .text.main:000000000000006c $d /tmp/ccg6eVgO.s:1411 .bss.huart2:0000000000000000 huart2 /tmp/ccg6eVgO.s:1375 .rodata:0000000000000000 $d /tmp/ccg6eVgO.s:1407 .bss.huart2:0000000000000000 $d UNDEFINED SYMBOLS memcpy HAL_GPIO_WritePin HAL_GPIO_Init HAL_GPIO_ReadPin strlen ARM GAS /tmp/ccg6eVgO.s page 55 HAL_UART_Transmit HAL_UART_Init memset HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_Init malloc sprintf