ARM GAS /tmp/ccPu6jg6.s page 1 1 .cpu cortex-m4 2 .eabi_attribute 27, 1 3 .eabi_attribute 28, 1 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 1 12 .eabi_attribute 18, 4 13 .file "stm32f4xx_hal_pwr.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .section .text.HAL_PWR_DeInit,"ax",%progbits 18 .align 1 19 .global HAL_PWR_DeInit 20 .arch armv7e-m 21 .syntax unified 22 .thumb 23 .thumb_func 24 .fpu fpv4-sp-d16 26 HAL_PWR_DeInit: 27 .LFB134: 28 .file 1 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 2:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 3:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @file stm32f4xx_hal_pwr.c 4:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @author MCD Application Team 5:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver. 6:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This file provides firmware functions to manage the following 7:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * functionalities of the Power Controller (PWR) peripheral: 8:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Initialization and de-initialization functions 9:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * + Peripheral Control functions 10:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 11:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 12:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @attention 13:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 14:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Copyright (c) 2017 STMicroelectronics. 15:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * All rights reserved. 16:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 17:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This software is licensed under terms that can be found in the LICENSE file in 18:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the root directory of this software component. 19:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 20:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ****************************************************************************** 21:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 22:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 23:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Includes ------------------------------------------------------------------*/ 24:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #include "stm32f4xx_hal.h" 25:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 26:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup STM32F4xx_HAL_Driver 27:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 28:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 29:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 30:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR PWR ARM GAS /tmp/ccPu6jg6.s page 2 31:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR HAL module driver 32:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 33:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 34:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 35:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #ifdef HAL_PWR_MODULE_ENABLED 36:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 37:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private typedef -----------------------------------------------------------*/ 38:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private define ------------------------------------------------------------*/ 39:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @addtogroup PWR_Private_Constants 40:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 41:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 42:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 43:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask 44:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 45:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 46:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_IT 0x00010000U 47:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_MODE_EVT 0x00020000U 48:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_RISING_EDGE 0x00000001U 49:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #define PVD_FALLING_EDGE 0x00000002U 50:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 51:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 52:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 53:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 54:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 55:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 56:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 57:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private macro -------------------------------------------------------------*/ 58:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private variables ---------------------------------------------------------*/ 59:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private function prototypes -----------------------------------------------*/ 60:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Private functions ---------------------------------------------------------*/ 61:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 62:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions PWR Exported Functions 63:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 64:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 65:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 66:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 67:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Initialization and de-initialization functions 68:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 69:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 70:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 71:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Initialization and de-initialization functions ##### 72:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 73:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 74:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** After reset, the backup domain (RTC registers, RTC backup data 75:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** registers and backup SRAM) is protected against possible unwanted 76:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** write accesses. 77:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To enable access to the RTC Domain and RTC registers, proceed as follows: 78:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable the Power Controller (PWR) APB1 interface clock using the 79:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_CLK_ENABLE() macro. 80:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function. 81:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 82:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 83:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 84:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 85:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 86:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 87:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Deinitializes the HAL PWR peripheral registers to their default reset values. ARM GAS /tmp/ccPu6jg6.s page 3 88:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 89:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 90:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DeInit(void) 91:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 29 .loc 1 91 1 view -0 30 .cfi_startproc 31 @ args = 0, pretend = 0, frame = 0 32 @ frame_needed = 0, uses_anonymous_args = 0 33 @ link register save eliminated. 92:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_FORCE_RESET(); 34 .loc 1 92 3 view .LVU1 35 0000 044B ldr r3, .L2 36 0002 1A6A ldr r2, [r3, #32] 37 0004 42F08052 orr r2, r2, #268435456 38 0008 1A62 str r2, [r3, #32] 93:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_RCC_PWR_RELEASE_RESET(); 39 .loc 1 93 3 view .LVU2 40 000a 1A6A ldr r2, [r3, #32] 41 000c 22F08052 bic r2, r2, #268435456 42 0010 1A62 str r2, [r3, #32] 94:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 43 .loc 1 94 1 is_stmt 0 view .LVU3 44 0012 7047 bx lr 45 .L3: 46 .align 2 47 .L2: 48 0014 00380240 .word 1073887232 49 .cfi_endproc 50 .LFE134: 52 .section .text.HAL_PWR_EnableBkUpAccess,"ax",%progbits 53 .align 1 54 .global HAL_PWR_EnableBkUpAccess 55 .syntax unified 56 .thumb 57 .thumb_func 58 .fpu fpv4-sp-d16 60 HAL_PWR_EnableBkUpAccess: 61 .LFB135: 95:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 96:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 97:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables access to the backup domain (RTC registers, RTC 98:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 99:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 100:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 101:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note The following sequence is required to bypass the delay between 102:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit programming and the effective enabling of the backup domain. 103:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Please check the Errata Sheet for more details under "Possible delay 104:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * in backup domain protection disabling/enabling after programming the 105:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit" section. 106:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 107:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 108:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableBkUpAccess(void) 109:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 62 .loc 1 109 1 is_stmt 1 view -0 63 .cfi_startproc 64 @ args = 0, pretend = 0, frame = 8 65 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccPu6jg6.s page 4 66 @ link register save eliminated. 67 0000 82B0 sub sp, sp, #8 68 .LCFI0: 69 .cfi_def_cfa_offset 8 110:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __IO uint32_t dummyread; 70 .loc 1 110 3 view .LVU5 111:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE; 71 .loc 1 111 3 view .LVU6 72 .loc 1 111 32 is_stmt 0 view .LVU7 73 0002 044B ldr r3, .L6 74 0004 0122 movs r2, #1 75 0006 1A62 str r2, [r3, #32] 112:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** dummyread = PWR->CR; 76 .loc 1 112 3 is_stmt 1 view .LVU8 77 .loc 1 112 18 is_stmt 0 view .LVU9 78 0008 034B ldr r3, .L6+4 79 000a 1B68 ldr r3, [r3] 80 .loc 1 112 13 view .LVU10 81 000c 0193 str r3, [sp, #4] 113:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** UNUSED(dummyread); 82 .loc 1 113 3 is_stmt 1 view .LVU11 83 000e 019B ldr r3, [sp, #4] 114:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 84 .loc 1 114 1 is_stmt 0 view .LVU12 85 0010 02B0 add sp, sp, #8 86 .LCFI1: 87 .cfi_def_cfa_offset 0 88 @ sp needed 89 0012 7047 bx lr 90 .L7: 91 .align 2 92 .L6: 93 0014 00000E42 .word 1108213760 94 0018 00700040 .word 1073770496 95 .cfi_endproc 96 .LFE135: 98 .section .text.HAL_PWR_DisableBkUpAccess,"ax",%progbits 99 .align 1 100 .global HAL_PWR_DisableBkUpAccess 101 .syntax unified 102 .thumb 103 .thumb_func 104 .fpu fpv4-sp-d16 106 HAL_PWR_DisableBkUpAccess: 107 .LFB136: 115:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 116:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 117:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables access to the backup domain (RTC registers, RTC 118:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * backup data registers and backup SRAM). 119:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 120:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Backup Domain Access should be kept enabled. 121:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note The following sequence is required to bypass the delay between 122:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit programming and the effective disabling of the backup domain. 123:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Please check the Errata Sheet for more details under "Possible delay 124:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * in backup domain protection disabling/enabling after programming the 125:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * DBP bit" section. 126:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None ARM GAS /tmp/ccPu6jg6.s page 5 127:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 128:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableBkUpAccess(void) 129:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 108 .loc 1 129 1 is_stmt 1 view -0 109 .cfi_startproc 110 @ args = 0, pretend = 0, frame = 8 111 @ frame_needed = 0, uses_anonymous_args = 0 112 @ link register save eliminated. 113 0000 82B0 sub sp, sp, #8 114 .LCFI2: 115 .cfi_def_cfa_offset 8 130:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __IO uint32_t dummyread; 116 .loc 1 130 3 view .LVU14 131:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE; 117 .loc 1 131 3 view .LVU15 118 .loc 1 131 32 is_stmt 0 view .LVU16 119 0002 044B ldr r3, .L10 120 0004 0022 movs r2, #0 121 0006 1A62 str r2, [r3, #32] 132:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** dummyread = PWR->CR; 122 .loc 1 132 3 is_stmt 1 view .LVU17 123 .loc 1 132 18 is_stmt 0 view .LVU18 124 0008 034B ldr r3, .L10+4 125 000a 1B68 ldr r3, [r3] 126 .loc 1 132 13 view .LVU19 127 000c 0193 str r3, [sp, #4] 133:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** UNUSED(dummyread); 128 .loc 1 133 3 is_stmt 1 view .LVU20 129 000e 019B ldr r3, [sp, #4] 134:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 130 .loc 1 134 1 is_stmt 0 view .LVU21 131 0010 02B0 add sp, sp, #8 132 .LCFI3: 133 .cfi_def_cfa_offset 0 134 @ sp needed 135 0012 7047 bx lr 136 .L11: 137 .align 2 138 .L10: 139 0014 00000E42 .word 1108213760 140 0018 00700040 .word 1073770496 141 .cfi_endproc 142 .LFE136: 144 .section .text.HAL_PWR_ConfigPVD,"ax",%progbits 145 .align 1 146 .global HAL_PWR_ConfigPVD 147 .syntax unified 148 .thumb 149 .thumb_func 150 .fpu fpv4-sp-d16 152 HAL_PWR_ConfigPVD: 153 .LVL0: 154 .LFB137: 135:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 136:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 137:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @} 138:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ ARM GAS /tmp/ccPu6jg6.s page 6 139:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 140:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 141:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Low Power modes configuration functions 142:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 143:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @verbatim 144:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 145:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 146:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ##### Peripheral Control functions ##### 147:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** =============================================================================== 148:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 149:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** PVD configuration *** 150:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ========================= 151:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 152:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is used to monitor the VDD power supply by comparing it to a 153:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 154:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 155:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** than the PVD threshold. This event is internally connected to the EXTI 156:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** line16 and can generate an interrupt if enabled. This is done through 157:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. 158:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The PVD is stopped in Standby mode. 159:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 160:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Wake-up pin configuration *** 161:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================================ 162:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 163:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Wake-up pin is used to wake up the system from Standby mode. This pin is 164:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** forced in input pull-down configuration and is active on rising edges. 165:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) There is one Wake-up pin: Wake-up Pin 1 on PA.00. 166:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13 167:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: 168:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 169:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Low Power modes configuration *** 170:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ===================================== 171:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 172:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The devices feature 3 low-power modes: 173:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Sleep mode: Cortex-M4 core stopped, peripherals kept running. 174:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Stop mode: all clocks are stopped, regulator running, regulator 175:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** in low power mode 176:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Standby mode: 1.2V domain powered off. 177:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 178:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Sleep mode *** 179:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================== 180:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 181:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 182:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(Regulator, SLEEPEntry) 183:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** functions with 184:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction 185:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction 186:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and 187:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** no clear of pending event before. 188:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 189:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** -@@- The Regulator parameter is not used for the STM32F4 family 190:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and is kept as parameter just to maintain compatibility with the 191:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** lower power families (STM32L). 192:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 193:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any peripheral interrupt acknowledged by the nested vectored interrupt 194:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** controller (NVIC) can wake up the device from Sleep mode. 195:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ARM GAS /tmp/ccPu6jg6.s page 7 196:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Stop mode *** 197:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ================= 198:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 199:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI, 200:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** and the HSE RC oscillators are disabled. Internal SRAM and register contents 201:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** are preserved. 202:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator can be configured either in normal or low-power mode. 203:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** To minimize the consumption In Stop mode, FLASH can be powered off before 204:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** entering the Stop mode using the HAL_PWREx_EnableFlashPowerDown() function. 205:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** It can be switched on again by software after exiting the Stop mode using 206:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWREx_DisableFlashPowerDown() function. 207:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 208:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Entry: 209:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Stop mode is entered using the HAL_PWR_EnterSTOPMode(Regulator, STOPEntry) 210:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** function with: 211:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Regulator: 212:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) Main regulator ON. 213:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) Low Power regulator ON. 214:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) STOPEntry: 215:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. 216:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and 217:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** clear of pending events before. 218:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and 219:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** no clear of pending event before. 220:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) Exit: 221:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Any EXTI Line (Internal or External) configured in Interrupt/Event mode. 222:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 223:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Standby mode *** 224:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ==================== 225:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 226:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) 227:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The Standby mode allows to achieve the lowest power consumption. It is based 228:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** on the Cortex-M4 deep sleep mode, with the voltage regulator disabled. 229:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 230:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HSE oscillator are also switched off. SRAM and register contents are lost 231:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** except for the RTC registers, RTC backup registers, backup SRAM and Standby 232:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** circuitry. 233:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 234:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** The voltage regulator is OFF. 235:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 236:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Entry: 237:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function. 238:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) Exit: 239:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wake-up, 240:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** tamper event, time-stamp event, external reset in NRST pin, IWDG reset. 241:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 242:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *** Auto-wake-up (AWU) from low-power mode *** 243:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** ============================================= 244:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** [..] 245:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 246:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 247:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** Wake-up event, a tamper event or a time-stamp event, without depending on 248:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** an external interrupt (Auto-wake-up mode). 249:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 250:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (+) RTC auto-wake-up (AWU) from the Stop and Standby modes 251:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 252:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to ARM GAS /tmp/ccPu6jg6.s page 8 253:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC alarm using the HAL_RTC_SetAlarm_IT() function. 254:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 255:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 256:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** is necessary to configure the RTC to detect the tamper or time stamp event using the 257:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_RTCEx_SetTimeStamp_IT() or HAL_RTCEx_SetTamper_IT() functions. 258:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 259:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** (++) To wake up from the Stop mode with an RTC Wake-up event, it is necessary to 260:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** configure the RTC to generate the RTC Wake-up event using the HAL_RTCEx_SetWakeUpTime 261:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 262:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** @endverbatim 263:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @{ 264:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 265:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 266:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 267:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 268:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 269:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * information for the PVD. 270:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Refer to the electrical characteristics of your device datasheet for 271:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * more details about the voltage threshold corresponding to each 272:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * detection level. 273:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 274:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 275:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 276:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 155 .loc 1 276 1 is_stmt 1 view -0 156 .cfi_startproc 157 @ args = 0, pretend = 0, frame = 0 158 @ frame_needed = 0, uses_anonymous_args = 0 159 @ link register save eliminated. 277:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 278:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 160 .loc 1 278 3 view .LVU23 279:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 161 .loc 1 279 3 view .LVU24 280:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 281:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set PLS[7:5] bits according to PVDLevel value */ 282:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 162 .loc 1 282 3 view .LVU25 163 0000 1E4A ldr r2, .L17 164 0002 1368 ldr r3, [r2] 165 0004 23F0E003 bic r3, r3, #224 166 0008 0168 ldr r1, [r0] 167 000a 0B43 orrs r3, r3, r1 168 000c 1360 str r3, [r2] 283:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 284:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 285:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 169 .loc 1 285 3 view .LVU26 170 000e 1C4B ldr r3, .L17+4 171 0010 5A68 ldr r2, [r3, #4] 172 0012 22F48032 bic r2, r2, #65536 173 0016 5A60 str r2, [r3, #4] 286:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_IT(); 174 .loc 1 286 3 view .LVU27 175 0018 1A68 ldr r2, [r3] 176 001a 22F48032 bic r2, r2, #65536 177 001e 1A60 str r2, [r3] ARM GAS /tmp/ccPu6jg6.s page 9 287:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); 178 .loc 1 287 3 view .LVU28 179 0020 9A68 ldr r2, [r3, #8] 180 0022 22F48032 bic r2, r2, #65536 181 0026 9A60 str r2, [r3, #8] 288:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 182 .loc 1 288 3 view .LVU29 183 0028 DA68 ldr r2, [r3, #12] 184 002a 22F48032 bic r2, r2, #65536 185 002e DA60 str r2, [r3, #12] 289:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 290:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure interrupt mode */ 291:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 186 .loc 1 291 3 view .LVU30 187 .loc 1 291 17 is_stmt 0 view .LVU31 188 0030 4368 ldr r3, [r0, #4] 189 .loc 1 291 5 view .LVU32 190 0032 13F4803F tst r3, #65536 191 0036 04D0 beq .L13 292:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 293:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_IT(); 192 .loc 1 293 5 is_stmt 1 view .LVU33 193 0038 114A ldr r2, .L17+4 194 003a 1368 ldr r3, [r2] 195 003c 43F48033 orr r3, r3, #65536 196 0040 1360 str r3, [r2] 197 .L13: 294:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 295:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 296:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure event mode */ 297:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 198 .loc 1 297 3 view .LVU34 199 .loc 1 297 17 is_stmt 0 view .LVU35 200 0042 4368 ldr r3, [r0, #4] 201 .loc 1 297 5 view .LVU36 202 0044 13F4003F tst r3, #131072 203 0048 04D0 beq .L14 298:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 299:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 204 .loc 1 299 5 is_stmt 1 view .LVU37 205 004a 0D4A ldr r2, .L17+4 206 004c 5368 ldr r3, [r2, #4] 207 004e 43F48033 orr r3, r3, #65536 208 0052 5360 str r3, [r2, #4] 209 .L14: 300:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 301:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 302:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Configure the edge */ 303:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 210 .loc 1 303 3 view .LVU38 211 .loc 1 303 17 is_stmt 0 view .LVU39 212 0054 4368 ldr r3, [r0, #4] 213 .loc 1 303 5 view .LVU40 214 0056 13F0010F tst r3, #1 215 005a 04D0 beq .L15 304:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 305:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); ARM GAS /tmp/ccPu6jg6.s page 10 216 .loc 1 305 5 is_stmt 1 view .LVU41 217 005c 084A ldr r2, .L17+4 218 005e 9368 ldr r3, [r2, #8] 219 0060 43F48033 orr r3, r3, #65536 220 0064 9360 str r3, [r2, #8] 221 .L15: 306:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 307:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 308:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 222 .loc 1 308 3 view .LVU42 223 .loc 1 308 17 is_stmt 0 view .LVU43 224 0066 4368 ldr r3, [r0, #4] 225 .loc 1 308 5 view .LVU44 226 0068 13F0020F tst r3, #2 227 006c 04D0 beq .L12 309:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 310:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 228 .loc 1 310 5 is_stmt 1 view .LVU45 229 006e 044A ldr r2, .L17+4 230 0070 D368 ldr r3, [r2, #12] 231 0072 43F48033 orr r3, r3, #65536 232 0076 D360 str r3, [r2, #12] 233 .L12: 311:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 312:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 234 .loc 1 312 1 is_stmt 0 view .LVU46 235 0078 7047 bx lr 236 .L18: 237 007a 00BF .align 2 238 .L17: 239 007c 00700040 .word 1073770496 240 0080 003C0140 .word 1073822720 241 .cfi_endproc 242 .LFE137: 244 .section .text.HAL_PWR_EnablePVD,"ax",%progbits 245 .align 1 246 .global HAL_PWR_EnablePVD 247 .syntax unified 248 .thumb 249 .thumb_func 250 .fpu fpv4-sp-d16 252 HAL_PWR_EnablePVD: 253 .LFB138: 313:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 314:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 315:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Power Voltage Detector(PVD). 316:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 317:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 318:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnablePVD(void) 319:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 254 .loc 1 319 1 is_stmt 1 view -0 255 .cfi_startproc 256 @ args = 0, pretend = 0, frame = 0 257 @ frame_needed = 0, uses_anonymous_args = 0 258 @ link register save eliminated. 320:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE; 259 .loc 1 320 3 view .LVU48 ARM GAS /tmp/ccPu6jg6.s page 11 260 .loc 1 320 33 is_stmt 0 view .LVU49 261 0000 014B ldr r3, .L20 262 0002 0122 movs r2, #1 263 0004 1A61 str r2, [r3, #16] 321:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 264 .loc 1 321 1 view .LVU50 265 0006 7047 bx lr 266 .L21: 267 .align 2 268 .L20: 269 0008 00000E42 .word 1108213760 270 .cfi_endproc 271 .LFE138: 273 .section .text.HAL_PWR_DisablePVD,"ax",%progbits 274 .align 1 275 .global HAL_PWR_DisablePVD 276 .syntax unified 277 .thumb 278 .thumb_func 279 .fpu fpv4-sp-d16 281 HAL_PWR_DisablePVD: 282 .LFB139: 322:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 323:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 324:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Power Voltage Detector(PVD). 325:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 326:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 327:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisablePVD(void) 328:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 283 .loc 1 328 1 is_stmt 1 view -0 284 .cfi_startproc 285 @ args = 0, pretend = 0, frame = 0 286 @ frame_needed = 0, uses_anonymous_args = 0 287 @ link register save eliminated. 329:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE; 288 .loc 1 329 3 view .LVU52 289 .loc 1 329 33 is_stmt 0 view .LVU53 290 0000 014B ldr r3, .L23 291 0002 0022 movs r2, #0 292 0004 1A61 str r2, [r3, #16] 330:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 293 .loc 1 330 1 view .LVU54 294 0006 7047 bx lr 295 .L24: 296 .align 2 297 .L23: 298 0008 00000E42 .word 1108213760 299 .cfi_endproc 300 .LFE139: 302 .section .text.HAL_PWR_EnableWakeUpPin,"ax",%progbits 303 .align 1 304 .global HAL_PWR_EnableWakeUpPin 305 .syntax unified 306 .thumb 307 .thumb_func 308 .fpu fpv4-sp-d16 310 HAL_PWR_EnableWakeUpPin: ARM GAS /tmp/ccPu6jg6.s page 12 311 .LVL1: 312 .LFB140: 331:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 332:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 333:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables the Wake-up PINx functionality. 334:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to enable. 335:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 336:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 337:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 338:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x 339:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 340:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 341:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx) 342:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 313 .loc 1 342 1 is_stmt 1 view -0 314 .cfi_startproc 315 @ args = 0, pretend = 0, frame = 0 316 @ frame_needed = 0, uses_anonymous_args = 0 317 @ link register save eliminated. 343:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 344:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 318 .loc 1 344 3 view .LVU56 345:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 346:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Enable the wake up pin */ 347:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CSR, WakeUpPinx); 319 .loc 1 347 3 view .LVU57 320 0000 024A ldr r2, .L26 321 0002 5368 ldr r3, [r2, #4] 322 0004 0343 orrs r3, r3, r0 323 0006 5360 str r3, [r2, #4] 348:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 324 .loc 1 348 1 is_stmt 0 view .LVU58 325 0008 7047 bx lr 326 .L27: 327 000a 00BF .align 2 328 .L26: 329 000c 00700040 .word 1073770496 330 .cfi_endproc 331 .LFE140: 333 .section .text.HAL_PWR_DisableWakeUpPin,"ax",%progbits 334 .align 1 335 .global HAL_PWR_DisableWakeUpPin 336 .syntax unified 337 .thumb 338 .thumb_func 339 .fpu fpv4-sp-d16 341 HAL_PWR_DisableWakeUpPin: 342 .LVL2: 343 .LFB141: 349:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 350:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 351:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables the Wake-up PINx functionality. 352:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param WakeUpPinx Specifies the Power Wake-Up pin to disable. 353:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 354:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN1 355:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413x 356:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423x ARM GAS /tmp/ccPu6jg6.s page 13 357:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 358:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 359:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx) 360:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 344 .loc 1 360 1 is_stmt 1 view -0 345 .cfi_startproc 346 @ args = 0, pretend = 0, frame = 0 347 @ frame_needed = 0, uses_anonymous_args = 0 348 @ link register save eliminated. 361:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameter */ 362:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx)); 349 .loc 1 362 3 view .LVU60 363:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 364:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Disable the wake up pin */ 365:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(PWR->CSR, WakeUpPinx); 350 .loc 1 365 3 view .LVU61 351 0000 024A ldr r2, .L29 352 0002 5368 ldr r3, [r2, #4] 353 0004 23EA0003 bic r3, r3, r0 354 0008 5360 str r3, [r2, #4] 366:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 355 .loc 1 366 1 is_stmt 0 view .LVU62 356 000a 7047 bx lr 357 .L30: 358 .align 2 359 .L29: 360 000c 00700040 .word 1073770496 361 .cfi_endproc 362 .LFE141: 364 .section .text.HAL_PWR_EnterSLEEPMode,"ax",%progbits 365 .align 1 366 .global HAL_PWR_EnterSLEEPMode 367 .syntax unified 368 .thumb 369 .thumb_func 370 .fpu fpv4-sp-d16 372 HAL_PWR_EnterSLEEPMode: 373 .LVL3: 374 .LFB142: 367:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 368:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 369:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Sleep mode. 370:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 371:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, all I/O pins keep the same state as in Run mode. 372:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 373:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Sleep mode, the systick is stopped to avoid exit from this mode with 374:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * systick interrupt when used as time base for Timeout 375:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * 376:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in SLEEP mode. 377:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 378:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON 379:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON 380:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This parameter is not used for the STM32F4 family and is kept as parameter 381:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * just to maintain compatibility with the lower power families. 382:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction. 383:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 384:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction ARM GAS /tmp/ccPu6jg6.s page 14 385:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and 386:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * clear of pending events before. 387:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and 388:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * no clear of pending event before. 389:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 390:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 391:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) 392:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 375 .loc 1 392 1 is_stmt 1 view -0 376 .cfi_startproc 377 @ args = 0, pretend = 0, frame = 0 378 @ frame_needed = 0, uses_anonymous_args = 0 379 @ link register save eliminated. 393:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Prevent unused argument(s) compilation warning */ 394:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** UNUSED(Regulator); 380 .loc 1 394 3 view .LVU64 395:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 396:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 397:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 381 .loc 1 397 3 view .LVU65 398:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); 382 .loc 1 398 3 view .LVU66 399:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 400:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPDEEP bit of Cortex System Control Register */ 401:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 383 .loc 1 401 3 view .LVU67 384 0000 074A ldr r2, .L36 385 0002 1369 ldr r3, [r2, #16] 386 0004 23F00403 bic r3, r3, #4 387 0008 1361 str r3, [r2, #16] 402:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 403:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select SLEEP mode entry -------------------------------------------------*/ 404:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(SLEEPEntry == PWR_SLEEPENTRY_WFI) 388 .loc 1 404 3 view .LVU68 389 .loc 1 404 5 is_stmt 0 view .LVU69 390 000a 0129 cmp r1, #1 391 000c 05D0 beq .L35 405:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 406:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 408:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 409:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 410:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 411:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(SLEEPEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) 392 .loc 1 411 5 is_stmt 1 view .LVU70 393 .loc 1 411 7 is_stmt 0 view .LVU71 394 000e 0329 cmp r1, #3 395 0010 01D0 beq .L34 412:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 413:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear all pending event */ 414:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 396 .loc 1 414 7 is_stmt 1 view .LVU72 397 .syntax unified 398 @ 414 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 399 0012 40BF sev 400 @ 0 "" 2 415:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); ARM GAS /tmp/ccPu6jg6.s page 15 401 .loc 1 415 7 view .LVU73 402 @ 415 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 403 0014 20BF wfe 404 @ 0 "" 2 405 .thumb 406 .syntax unified 407 .L34: 416:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 417:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 418:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 419:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 408 .loc 1 419 5 view .LVU74 409 .syntax unified 410 @ 419 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 411 0016 20BF wfe 412 @ 0 "" 2 420:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 421:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 413 .loc 1 421 1 is_stmt 0 view .LVU75 414 .thumb 415 .syntax unified 416 0018 7047 bx lr 417 .L35: 407:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 418 .loc 1 407 5 is_stmt 1 view .LVU76 419 .syntax unified 420 @ 407 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 421 001a 30BF wfi 422 @ 0 "" 2 423 .thumb 424 .syntax unified 425 001c 7047 bx lr 426 .L37: 427 001e 00BF .align 2 428 .L36: 429 0020 00ED00E0 .word -536810240 430 .cfi_endproc 431 .LFE142: 433 .section .text.HAL_PWR_EnterSTOPMode,"ax",%progbits 434 .align 1 435 .global HAL_PWR_EnterSTOPMode 436 .syntax unified 437 .thumb 438 .thumb_func 439 .fpu fpv4-sp-d16 441 HAL_PWR_EnterSTOPMode: 442 .LVL4: 443 .LFB143: 422:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 423:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 424:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Stop mode. 425:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Stop mode, all I/O pins keep the same state as in Run mode. 426:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 427:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * the HSI RC oscillator is selected as system clock. 428:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note When the voltage regulator operates in low power mode, an additional 429:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * startup delay is incurred when waking up from Stop mode. 430:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * By keeping the internal regulator ON during Stop mode, the consumption ARM GAS /tmp/ccPu6jg6.s page 16 431:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * is higher although the startup time is reduced. 432:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param Regulator Specifies the regulator state in Stop mode. 433:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 434:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON 435:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON 436:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction. 437:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * This parameter can be one of the following values: 438:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFI : Enter Stop mode with WFI instruction 439:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE : Enter Stop mode with WFE instruction and 440:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * clear of pending events before. 441:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and 442:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * no clear of pending event before. 443:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 444:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 445:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 446:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 444 .loc 1 446 1 view -0 445 .cfi_startproc 446 @ args = 0, pretend = 0, frame = 0 447 @ frame_needed = 0, uses_anonymous_args = 0 448 @ link register save eliminated. 447:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check the parameters */ 448:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_REGULATOR(Regulator)); 449 .loc 1 448 3 view .LVU78 449:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 450 .loc 1 449 3 view .LVU79 450:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 451:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select the regulator state in Stop mode: Set PDDS and LPDS bits according to PWR_Regulator val 452:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPDS), Regulator); 451 .loc 1 452 3 view .LVU80 452 0000 0C4A ldr r2, .L43 453 0002 1368 ldr r3, [r2] 454 0004 23F00303 bic r3, r3, #3 455 0008 0343 orrs r3, r3, r0 456 000a 1360 str r3, [r2] 453:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 454:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 455:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 457 .loc 1 455 3 view .LVU81 458 000c 0A4A ldr r2, .L43+4 459 000e 1369 ldr r3, [r2, #16] 460 0010 43F00403 orr r3, r3, #4 461 0014 1361 str r3, [r2, #16] 456:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 457:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Stop mode entry --------------------------------------------------*/ 458:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(STOPEntry == PWR_STOPENTRY_WFI) 462 .loc 1 458 3 view .LVU82 463 .loc 1 458 5 is_stmt 0 view .LVU83 464 0016 0129 cmp r1, #1 465 0018 0AD0 beq .L42 459:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 460:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 462:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 463:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** else 464:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 465:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(STOPEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) ARM GAS /tmp/ccPu6jg6.s page 17 466 .loc 1 465 5 is_stmt 1 view .LVU84 467 .loc 1 465 7 is_stmt 0 view .LVU85 468 001a 0329 cmp r1, #3 469 001c 01D0 beq .L41 466:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 467:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear all pending event */ 468:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __SEV(); 470 .loc 1 468 7 is_stmt 1 view .LVU86 471 .syntax unified 472 @ 468 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 473 001e 40BF sev 474 @ 0 "" 2 469:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 475 .loc 1 469 7 view .LVU87 476 @ 469 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 477 0020 20BF wfe 478 @ 0 "" 2 479 .thumb 480 .syntax unified 481 .L41: 470:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 471:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Event */ 472:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFE(); 482 .loc 1 472 5 view .LVU88 483 .syntax unified 484 @ 472 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 485 0022 20BF wfe 486 @ 0 "" 2 487 .thumb 488 .syntax unified 489 .L40: 473:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 474:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Reset SLEEPDEEP bit of Cortex System Control Register */ 475:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 490 .loc 1 475 3 view .LVU89 491 0024 044A ldr r2, .L43+4 492 0026 1369 ldr r3, [r2, #16] 493 0028 23F00403 bic r3, r3, #4 494 002c 1361 str r3, [r2, #16] 476:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 495 .loc 1 476 1 is_stmt 0 view .LVU90 496 002e 7047 bx lr 497 .L42: 461:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 498 .loc 1 461 5 is_stmt 1 view .LVU91 499 .syntax unified 500 @ 461 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 501 0030 30BF wfi 502 @ 0 "" 2 503 .thumb 504 .syntax unified 505 0032 F7E7 b .L40 506 .L44: 507 .align 2 508 .L43: 509 0034 00700040 .word 1073770496 510 0038 00ED00E0 .word -536810240 ARM GAS /tmp/ccPu6jg6.s page 18 511 .cfi_endproc 512 .LFE143: 514 .section .text.HAL_PWR_EnterSTANDBYMode,"ax",%progbits 515 .align 1 516 .global HAL_PWR_EnterSTANDBYMode 517 .syntax unified 518 .thumb 519 .thumb_func 520 .fpu fpv4-sp-d16 522 HAL_PWR_EnterSTANDBYMode: 523 .LFB144: 477:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 478:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 479:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enters Standby mode. 480:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note In Standby mode, all I/O pins are high impedance except for: 481:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - Reset pad (still available) 482:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 483:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Alarm out, or RTC clock calibration out. 484:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - RTC_AF2 pin (PI8) if configured for tamper or time-stamp. 485:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * - WKUP pin 1 (PA0) if enabled. 486:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 487:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 488:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnterSTANDBYMode(void) 489:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 524 .loc 1 489 1 view -0 525 .cfi_startproc 526 @ args = 0, pretend = 0, frame = 0 527 @ frame_needed = 0, uses_anonymous_args = 0 528 @ link register save eliminated. 490:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Select Standby mode */ 491:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(PWR->CR, PWR_CR_PDDS); 529 .loc 1 491 3 view .LVU93 530 0000 054A ldr r2, .L46 531 0002 1368 ldr r3, [r2] 532 0004 43F00203 orr r3, r3, #2 533 0008 1360 str r3, [r2] 492:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 493:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPDEEP bit of Cortex System Control Register */ 494:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 534 .loc 1 494 3 view .LVU94 535 000a 044A ldr r2, .L46+4 536 000c 1369 ldr r3, [r2, #16] 537 000e 43F00403 orr r3, r3, #4 538 0012 1361 str r3, [r2, #16] 495:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 496:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* This option is used to ensure that store operations are completed */ 497:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #if defined ( __CC_ARM) 498:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __force_stores(); 499:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** #endif 500:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Request Wait For Interrupt */ 501:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __WFI(); 539 .loc 1 501 3 view .LVU95 540 .syntax unified 541 @ 501 "Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c" 1 542 0014 30BF wfi 543 @ 0 "" 2 502:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } ARM GAS /tmp/ccPu6jg6.s page 19 544 .loc 1 502 1 is_stmt 0 view .LVU96 545 .thumb 546 .syntax unified 547 0016 7047 bx lr 548 .L47: 549 .align 2 550 .L46: 551 0018 00700040 .word 1073770496 552 001c 00ED00E0 .word -536810240 553 .cfi_endproc 554 .LFE144: 556 .section .text.HAL_PWR_PVDCallback,"ax",%progbits 557 .align 1 558 .weak HAL_PWR_PVDCallback 559 .syntax unified 560 .thumb 561 .thumb_func 562 .fpu fpv4-sp-d16 564 HAL_PWR_PVDCallback: 565 .LFB146: 503:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 504:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 505:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief This function handles the PWR PVD interrupt request. 506:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note This API should be called under the PVD_IRQHandler(). 507:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 508:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 509:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_PVD_IRQHandler(void) 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 511:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 513:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 514:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* PWR PVD interrupt user callback */ 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** HAL_PWR_PVDCallback(); 516:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 517:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear PWR Exti pending bit */ 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 519:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 521:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 522:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 523:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief PWR PVD interrupt callback 524:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 525:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 526:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** __weak void HAL_PWR_PVDCallback(void) 527:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 566 .loc 1 527 1 is_stmt 1 view -0 567 .cfi_startproc 568 @ args = 0, pretend = 0, frame = 0 569 @ frame_needed = 0, uses_anonymous_args = 0 570 @ link register save eliminated. 528:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* NOTE : This function Should not be modified, when the callback is needed, 529:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** the HAL_PWR_PVDCallback could be implemented in the user file 530:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 531:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 571 .loc 1 531 1 view .LVU98 572 0000 7047 bx lr 573 .cfi_endproc ARM GAS /tmp/ccPu6jg6.s page 20 574 .LFE146: 576 .section .text.HAL_PWR_PVD_IRQHandler,"ax",%progbits 577 .align 1 578 .global HAL_PWR_PVD_IRQHandler 579 .syntax unified 580 .thumb 581 .thumb_func 582 .fpu fpv4-sp-d16 584 HAL_PWR_PVD_IRQHandler: 585 .LFB145: 510:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Check PWR Exti flag */ 586 .loc 1 510 1 view -0 587 .cfi_startproc 588 @ args = 0, pretend = 0, frame = 0 589 @ frame_needed = 0, uses_anonymous_args = 0 590 0000 08B5 push {r3, lr} 591 .LCFI4: 592 .cfi_def_cfa_offset 8 593 .cfi_offset 3, -8 594 .cfi_offset 14, -4 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 595 .loc 1 512 3 view .LVU100 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 596 .loc 1 512 6 is_stmt 0 view .LVU101 597 0002 064B ldr r3, .L53 598 0004 5B69 ldr r3, [r3, #20] 512:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 599 .loc 1 512 5 view .LVU102 600 0006 13F4803F tst r3, #65536 601 000a 00D1 bne .L52 602 .L49: 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 603 .loc 1 520 1 view .LVU103 604 000c 08BD pop {r3, pc} 605 .L52: 515:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 606 .loc 1 515 5 is_stmt 1 view .LVU104 607 000e FFF7FEFF bl HAL_PWR_PVDCallback 608 .LVL5: 518:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 609 .loc 1 518 5 view .LVU105 610 0012 024B ldr r3, .L53 611 0014 4FF48032 mov r2, #65536 612 0018 5A61 str r2, [r3, #20] 520:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 613 .loc 1 520 1 is_stmt 0 view .LVU106 614 001a F7E7 b .L49 615 .L54: 616 .align 2 617 .L53: 618 001c 003C0140 .word 1073822720 619 .cfi_endproc 620 .LFE145: 622 .section .text.HAL_PWR_EnableSleepOnExit,"ax",%progbits 623 .align 1 624 .global HAL_PWR_EnableSleepOnExit 625 .syntax unified ARM GAS /tmp/ccPu6jg6.s page 21 626 .thumb 627 .thumb_func 628 .fpu fpv4-sp-d16 630 HAL_PWR_EnableSleepOnExit: 631 .LFB147: 532:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 533:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 534:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Indicates Sleep-On-Exit when returning from Handler mode to Thread mode. 535:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the processor 536:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 537:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * Setting this bit is useful when the processor is expected to run only on 538:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * interruptions handling. 539:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 540:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 541:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void) 542:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 632 .loc 1 542 1 is_stmt 1 view -0 633 .cfi_startproc 634 @ args = 0, pretend = 0, frame = 0 635 @ frame_needed = 0, uses_anonymous_args = 0 636 @ link register save eliminated. 543:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SLEEPONEXIT bit of Cortex System Control Register */ 544:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 637 .loc 1 544 3 view .LVU108 638 0000 024A ldr r2, .L56 639 0002 1369 ldr r3, [r2, #16] 640 0004 43F00203 orr r3, r3, #2 641 0008 1361 str r3, [r2, #16] 545:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 642 .loc 1 545 1 is_stmt 0 view .LVU109 643 000a 7047 bx lr 644 .L57: 645 .align 2 646 .L56: 647 000c 00ED00E0 .word -536810240 648 .cfi_endproc 649 .LFE147: 651 .section .text.HAL_PWR_DisableSleepOnExit,"ax",%progbits 652 .align 1 653 .global HAL_PWR_DisableSleepOnExit 654 .syntax unified 655 .thumb 656 .thumb_func 657 .fpu fpv4-sp-d16 659 HAL_PWR_DisableSleepOnExit: 660 .LFB148: 546:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 547:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 548:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables Sleep-On-Exit feature when returning from Handler mode to Thread mode. 549:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the processor 550:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * re-enters SLEEP mode when an interruption handling is over. 551:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 552:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 553:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSleepOnExit(void) 554:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 661 .loc 1 554 1 is_stmt 1 view -0 662 .cfi_startproc ARM GAS /tmp/ccPu6jg6.s page 22 663 @ args = 0, pretend = 0, frame = 0 664 @ frame_needed = 0, uses_anonymous_args = 0 665 @ link register save eliminated. 555:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 556:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 666 .loc 1 556 3 view .LVU111 667 0000 024A ldr r2, .L59 668 0002 1369 ldr r3, [r2, #16] 669 0004 23F00203 bic r3, r3, #2 670 0008 1361 str r3, [r2, #16] 557:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 671 .loc 1 557 1 is_stmt 0 view .LVU112 672 000a 7047 bx lr 673 .L60: 674 .align 2 675 .L59: 676 000c 00ED00E0 .word -536810240 677 .cfi_endproc 678 .LFE148: 680 .section .text.HAL_PWR_EnableSEVOnPend,"ax",%progbits 681 .align 1 682 .global HAL_PWR_EnableSEVOnPend 683 .syntax unified 684 .thumb 685 .thumb_func 686 .fpu fpv4-sp-d16 688 HAL_PWR_EnableSEVOnPend: 689 .LFB149: 558:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 559:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 560:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Enables CORTEX M4 SEVONPEND bit. 561:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Sets SEVONPEND bit of SCR register. When this bit is set, this causes 562:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 563:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 564:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 565:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_EnableSEVOnPend(void) 566:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 690 .loc 1 566 1 is_stmt 1 view -0 691 .cfi_startproc 692 @ args = 0, pretend = 0, frame = 0 693 @ frame_needed = 0, uses_anonymous_args = 0 694 @ link register save eliminated. 567:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Set SEVONPEND bit of Cortex System Control Register */ 568:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 695 .loc 1 568 3 view .LVU114 696 0000 024A ldr r2, .L62 697 0002 1369 ldr r3, [r2, #16] 698 0004 43F01003 orr r3, r3, #16 699 0008 1361 str r3, [r2, #16] 569:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 700 .loc 1 569 1 is_stmt 0 view .LVU115 701 000a 7047 bx lr 702 .L63: 703 .align 2 704 .L62: 705 000c 00ED00E0 .word -536810240 706 .cfi_endproc ARM GAS /tmp/ccPu6jg6.s page 23 707 .LFE149: 709 .section .text.HAL_PWR_DisableSEVOnPend,"ax",%progbits 710 .align 1 711 .global HAL_PWR_DisableSEVOnPend 712 .syntax unified 713 .thumb 714 .thumb_func 715 .fpu fpv4-sp-d16 717 HAL_PWR_DisableSEVOnPend: 718 .LFB150: 570:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** 571:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /** 572:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @brief Disables CORTEX M4 SEVONPEND bit. 573:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 574:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * WFE to wake up when an interrupt moves from inactive to pended. 575:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** * @retval None 576:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** */ 577:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** void HAL_PWR_DisableSEVOnPend(void) 578:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** { 719 .loc 1 578 1 is_stmt 1 view -0 720 .cfi_startproc 721 @ args = 0, pretend = 0, frame = 0 722 @ frame_needed = 0, uses_anonymous_args = 0 723 @ link register save eliminated. 579:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** /* Clear SEVONPEND bit of Cortex System Control Register */ 580:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 724 .loc 1 580 3 view .LVU117 725 0000 024A ldr r2, .L65 726 0002 1369 ldr r3, [r2, #16] 727 0004 23F01003 bic r3, r3, #16 728 0008 1361 str r3, [r2, #16] 581:Drivers/STM32F4xx_HAL_Driver/Src/stm32f4xx_hal_pwr.c **** } 729 .loc 1 581 1 is_stmt 0 view .LVU118 730 000a 7047 bx lr 731 .L66: 732 .align 2 733 .L65: 734 000c 00ED00E0 .word -536810240 735 .cfi_endproc 736 .LFE150: 738 .text 739 .Letext0: 740 .file 2 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 741 .file 3 "Drivers/CMSIS/Include/core_cm4.h" 742 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h" 743 .file 5 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" 744 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_pwr.h" ARM GAS /tmp/ccPu6jg6.s page 24 DEFINED SYMBOLS *ABS*:0000000000000000 stm32f4xx_hal_pwr.c /tmp/ccPu6jg6.s:18 .text.HAL_PWR_DeInit:0000000000000000 $t /tmp/ccPu6jg6.s:26 .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit /tmp/ccPu6jg6.s:48 .text.HAL_PWR_DeInit:0000000000000014 $d /tmp/ccPu6jg6.s:53 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t /tmp/ccPu6jg6.s:60 .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess /tmp/ccPu6jg6.s:93 .text.HAL_PWR_EnableBkUpAccess:0000000000000014 $d /tmp/ccPu6jg6.s:99 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t /tmp/ccPu6jg6.s:106 .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess /tmp/ccPu6jg6.s:139 .text.HAL_PWR_DisableBkUpAccess:0000000000000014 $d /tmp/ccPu6jg6.s:145 .text.HAL_PWR_ConfigPVD:0000000000000000 $t /tmp/ccPu6jg6.s:152 .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD /tmp/ccPu6jg6.s:239 .text.HAL_PWR_ConfigPVD:000000000000007c $d /tmp/ccPu6jg6.s:245 .text.HAL_PWR_EnablePVD:0000000000000000 $t /tmp/ccPu6jg6.s:252 .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD /tmp/ccPu6jg6.s:269 .text.HAL_PWR_EnablePVD:0000000000000008 $d /tmp/ccPu6jg6.s:274 .text.HAL_PWR_DisablePVD:0000000000000000 $t /tmp/ccPu6jg6.s:281 .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD /tmp/ccPu6jg6.s:298 .text.HAL_PWR_DisablePVD:0000000000000008 $d /tmp/ccPu6jg6.s:303 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t /tmp/ccPu6jg6.s:310 .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin /tmp/ccPu6jg6.s:329 .text.HAL_PWR_EnableWakeUpPin:000000000000000c $d /tmp/ccPu6jg6.s:334 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t /tmp/ccPu6jg6.s:341 .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin /tmp/ccPu6jg6.s:360 .text.HAL_PWR_DisableWakeUpPin:000000000000000c $d /tmp/ccPu6jg6.s:365 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t /tmp/ccPu6jg6.s:372 .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode /tmp/ccPu6jg6.s:429 .text.HAL_PWR_EnterSLEEPMode:0000000000000020 $d /tmp/ccPu6jg6.s:434 .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t /tmp/ccPu6jg6.s:441 .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode /tmp/ccPu6jg6.s:509 .text.HAL_PWR_EnterSTOPMode:0000000000000034 $d /tmp/ccPu6jg6.s:515 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t /tmp/ccPu6jg6.s:522 .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode /tmp/ccPu6jg6.s:551 .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d /tmp/ccPu6jg6.s:557 .text.HAL_PWR_PVDCallback:0000000000000000 $t /tmp/ccPu6jg6.s:564 .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback /tmp/ccPu6jg6.s:577 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t /tmp/ccPu6jg6.s:584 .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler /tmp/ccPu6jg6.s:618 .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d /tmp/ccPu6jg6.s:623 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t /tmp/ccPu6jg6.s:630 .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit /tmp/ccPu6jg6.s:647 .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d /tmp/ccPu6jg6.s:652 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t /tmp/ccPu6jg6.s:659 .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit /tmp/ccPu6jg6.s:676 .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d /tmp/ccPu6jg6.s:681 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t /tmp/ccPu6jg6.s:688 .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend /tmp/ccPu6jg6.s:705 .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d /tmp/ccPu6jg6.s:710 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t /tmp/ccPu6jg6.s:717 .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend /tmp/ccPu6jg6.s:734 .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d NO UNDEFINED SYMBOLS