ARM GAS /tmp/ccwcoXyi.s page 1 1 .cpu cortex-m4 2 .eabi_attribute 27, 1 3 .eabi_attribute 28, 1 4 .eabi_attribute 20, 1 5 .eabi_attribute 21, 1 6 .eabi_attribute 23, 3 7 .eabi_attribute 24, 1 8 .eabi_attribute 25, 1 9 .eabi_attribute 26, 1 10 .eabi_attribute 30, 1 11 .eabi_attribute 34, 1 12 .eabi_attribute 18, 4 13 .file "main.c" 14 .text 15 .Ltext0: 16 .cfi_sections .debug_frame 17 .section .text.MX_GPIO_Init,"ax",%progbits 18 .align 1 19 .arch armv7e-m 20 .syntax unified 21 .thumb 22 .thumb_func 23 .fpu fpv4-sp-d16 25 MX_GPIO_Init: 26 .LFB155: 27 .file 1 "Core/Src/main.c" 1:Core/Src/main.c **** /** 2:Core/Src/main.c **** ****************************************************************************** 3:Core/Src/main.c **** * @file : main.c 4:Core/Src/main.c **** * @brief : Main program body 5:Core/Src/main.c **** ****************************************************************************** 6:Core/Src/main.c **** * @attention 7:Core/Src/main.c **** * 8:Core/Src/main.c **** * Copyright (c) 2025 STMicroelectronics. 9:Core/Src/main.c **** * All rights reserved. 10:Core/Src/main.c **** * 11:Core/Src/main.c **** * This software is licensed under terms that can be found in the LICENSE file 12:Core/Src/main.c **** * in the root directory of this software component. 13:Core/Src/main.c **** * If no LICENSE file comes with this software, it is provided AS-IS. 14:Core/Src/main.c **** * 15:Core/Src/main.c **** ****************************************************************************** 16:Core/Src/main.c **** */ 17:Core/Src/main.c **** /* Includes ------------------------------------------------------------------*/ 18:Core/Src/main.c **** #include "main.h" 19:Core/Src/main.c **** #include 20:Core/Src/main.c **** #include 21:Core/Src/main.c **** #include 22:Core/Src/main.c **** 23:Core/Src/main.c **** 24:Core/Src/main.c **** /* Private variables ---------------------------------------------------------*/ 25:Core/Src/main.c **** UART_HandleTypeDef huart2; 26:Core/Src/main.c **** 27:Core/Src/main.c **** 28:Core/Src/main.c **** /* Private function prototypes -----------------------------------------------*/ 29:Core/Src/main.c **** void SystemClock_Config(void); 30:Core/Src/main.c **** static void MX_GPIO_Init(void); 31:Core/Src/main.c **** static void MX_USART2_UART_Init(void); ARM GAS /tmp/ccwcoXyi.s page 2 32:Core/Src/main.c **** 33:Core/Src/main.c **** /* Private user code ---------------------------------------------------------*/ 34:Core/Src/main.c **** 35:Core/Src/main.c **** /** 36:Core/Src/main.c **** * @brief The application entry point. 37:Core/Src/main.c **** * @retval int 38:Core/Src/main.c **** */ 39:Core/Src/main.c **** int main(void) 40:Core/Src/main.c **** { 41:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 42:Core/Src/main.c **** 43:Core/Src/main.c **** /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 44:Core/Src/main.c **** HAL_Init(); 45:Core/Src/main.c **** 46:Core/Src/main.c **** /* Configure the system clock */ 47:Core/Src/main.c **** SystemClock_Config(); 48:Core/Src/main.c **** 49:Core/Src/main.c **** /* Initialize all configured peripherals */ 50:Core/Src/main.c **** MX_GPIO_Init(); 51:Core/Src/main.c **** MX_USART2_UART_Init(); 52:Core/Src/main.c **** 53:Core/Src/main.c **** Data_Pins_Init(0); 54:Core/Src/main.c **** Address_Pins_Init(); 55:Core/Src/main.c **** Command_Pins_Init(); 56:Core/Src/main.c **** 57:Core/Src/main.c **** int man_id, dev_id; 58:Core/Src/main.c **** Enter_Device_ID(&man_id, &dev_id); 59:Core/Src/main.c **** 60:Core/Src/main.c **** char *manufacturer = (char*)malloc(13 * sizeof(char)); 61:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 62:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 63:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 64:Core/Src/main.c **** 65:Core/Src/main.c **** debug_print("==================================================================================== 66:Core/Src/main.c **** debug_print(" _____ _____ _____ _____ _____ _____\r\n"); 67:Core/Src/main.c **** debug_print("| __| __| _ | __ | | | ___ ___ ___ ___ ___ ___ _____ _____ ___ ___\ 68:Core/Src/main.c **** debug_print("| __| __| __| -| | | | | | | . | _| . | . | _| .'| | | -_| _| 69:Core/Src/main.c **** debug_print("|_____|_____|__| |__|__|_____|_|_|_| | _|_| |___|_ |_| |__,|_|_|_|_|_|_|___|_|\r 70:Core/Src/main.c **** debug_print(" - Ayabusa 2025 |_| |___|\r\n"); 71:Core/Src/main.c **** debug_print("==================================================================================== 72:Core/Src/main.c **** 73:Core/Src/main.c **** /* Infinite loop */ 74:Core/Src/main.c **** while (1) 75:Core/Src/main.c **** { 76:Core/Src/main.c **** debug_print("Hello welcome to the EEPROM programmer! What would you like to do?\r\n"); 77:Core/Src/main.c **** debug_print("[1] Dump Rom as char\r\n"); 78:Core/Src/main.c **** debug_print("[2] Erase chip\r\n"); 79:Core/Src/main.c **** debug_print("[3] Program chip via UART (ASCII mode)\r\n"); 80:Core/Src/main.c **** debug_print("[4] Identify device\r\n"); 81:Core/Src/main.c **** debug_print("[5] Dump Rom as file (ASCII mode)\r\n"); 82:Core/Src/main.c **** uint8_t resp; 83:Core/Src/main.c **** HAL_UART_Receive(&huart2, &resp, 1, HAL_MAX_DELAY); 84:Core/Src/main.c **** 85:Core/Src/main.c **** switch (resp) 86:Core/Src/main.c **** { 87:Core/Src/main.c **** case 0x31: 88:Core/Src/main.c **** debug_print("Dumping ROM...\r\n"); ARM GAS /tmp/ccwcoXyi.s page 3 89:Core/Src/main.c **** Dump_Flash_UART(1); 90:Core/Src/main.c **** break; 91:Core/Src/main.c **** case 0x32: 92:Core/Src/main.c **** debug_print("Erasing Chip...\r\n"); 93:Core/Src/main.c **** Chip_Erase(); 94:Core/Src/main.c **** break; 95:Core/Src/main.c **** case 0x33: 96:Core/Src/main.c **** debug_print("Launching programming sequence...\r\n"); 97:Core/Src/main.c **** Flash_From_UART(); 98:Core/Src/main.c **** break; 99:Core/Src/main.c **** case 0x34: 100:Core/Src/main.c **** debug_print("Identifying device...\r\n"); 101:Core/Src/main.c **** debug_print("Manufacturer ID = \r\n"); 102:Core/Src/main.c **** debug_print(manufacturer); 103:Core/Src/main.c **** debug_print("Device ID = \r\n"); 104:Core/Src/main.c **** debug_print(device); 105:Core/Src/main.c **** break; 106:Core/Src/main.c **** case 0x35: 107:Core/Src/main.c **** debug_print("Dumping ROM as file, press any key...\r\n"); 108:Core/Src/main.c **** uint8_t byte; 109:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 110:Core/Src/main.c **** Dump_Flash_UART(0); 111:Core/Src/main.c **** while(1){} 112:Core/Src/main.c **** default: 113:Core/Src/main.c **** debug_print("Invalid input!\r\n"); 114:Core/Src/main.c **** break; 115:Core/Src/main.c **** } 116:Core/Src/main.c **** } 117:Core/Src/main.c **** 118:Core/Src/main.c **** } 119:Core/Src/main.c **** 120:Core/Src/main.c **** void Write_Address(int address){ 121:Core/Src/main.c **** int pin_array[] = { 122:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 123:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 124:Core/Src/main.c **** GPIO_PIN_8, GPIO_PIN_9, GPIO_PIN_10, GPIO_PIN_11, 125:Core/Src/main.c **** GPIO_PIN_12, GPIO_PIN_13, 126:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, GPIO_PIN_4 // These last 3 are our PB pins not 127:Core/Src/main.c **** }; 128:Core/Src/main.c **** for(int i=0; i<19; i++){ 129:Core/Src/main.c **** if(i<14){ 130:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 131:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 132:Core/Src/main.c **** } 133:Core/Src/main.c **** else{ 134:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_SET); 135:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 136:Core/Src/main.c **** } 137:Core/Src/main.c **** } 138:Core/Src/main.c **** } 139:Core/Src/main.c **** 140:Core/Src/main.c **** int Receive_Data(void){ 141:Core/Src/main.c **** Data_Pins_Init(0); // We make sure it's in input mode 142:Core/Src/main.c **** int result = 0; 143:Core/Src/main.c **** int pin_array[] = { 144:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 145:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, ARM GAS /tmp/ccwcoXyi.s page 4 146:Core/Src/main.c **** }; 147:Core/Src/main.c **** for(int i=0; i<8; i++){ 148:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 149:Core/Src/main.c **** result += 1 << i; 150:Core/Src/main.c **** } 151:Core/Src/main.c **** } 152:Core/Src/main.c **** return result; 153:Core/Src/main.c **** } 154:Core/Src/main.c **** 155:Core/Src/main.c **** void Write_Data(int value){ 156:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 157:Core/Src/main.c **** int pin_array[] = { 158:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 159:Core/Src/main.c **** GPIO_PIN_4, GPIO_PIN_5, GPIO_PIN_6, GPIO_PIN_7, 160:Core/Src/main.c **** }; 161:Core/Src/main.c **** for(int i=0; i<8; i++){ 162:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 163:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 164:Core/Src/main.c **** } 165:Core/Src/main.c **** } 166:Core/Src/main.c **** 167:Core/Src/main.c **** // All arguments must be 0 (low) or 1 (high) 168:Core/Src/main.c **** void Write_Command_Pins(int CE, int OE, int WE){ 169:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 170:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 171:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10,(WE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 172:Core/Src/main.c **** } 173:Core/Src/main.c **** 174:Core/Src/main.c **** void Write_Command(int addr, int data) { 175:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 176:Core/Src/main.c **** Write_Address(addr); 177:Core/Src/main.c **** Write_Data(data); 178:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); 179:Core/Src/main.c **** // 4. Pulse WE# low to latch data 180:Core/Src/main.c **** Write_Command_Pins(0, 1, 0); // WE low 181:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); // WE high 182:Core/Src/main.c **** 183:Core/Src/main.c **** // 5. Deassert CE# 184:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 185:Core/Src/main.c **** } 186:Core/Src/main.c **** 187:Core/Src/main.c **** int Flash_ReadByte(int addr) { 188:Core/Src/main.c **** Write_Address(addr); 189:Core/Src/main.c **** Data_Pins_Init(0); 190:Core/Src/main.c **** Write_Command_Pins(0, 0, 1); 191:Core/Src/main.c **** int data = Receive_Data(); 192:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 193:Core/Src/main.c **** return data; 194:Core/Src/main.c **** } 195:Core/Src/main.c **** 196:Core/Src/main.c **** void Enter_Device_ID(int *manufacturer, int *device){ 197:Core/Src/main.c **** // Enter ID mode 198:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 199:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 200:Core/Src/main.c **** Write_Command(0x5555, 0x90); 201:Core/Src/main.c **** 202:Core/Src/main.c **** // Read Manufacturer ID (it should be 0xBF) ARM GAS /tmp/ccwcoXyi.s page 5 203:Core/Src/main.c **** *manufacturer = Flash_ReadByte(0x0000); 204:Core/Src/main.c **** 205:Core/Src/main.c **** // Read Device ID (it should be 0xB7 for the SST39SF040) 206:Core/Src/main.c **** *device = Flash_ReadByte(0x0001); 207:Core/Src/main.c **** 208:Core/Src/main.c **** // Exit ID mode 209:Core/Src/main.c **** Write_Command(0x5555, 0xF0); 210:Core/Src/main.c **** } 211:Core/Src/main.c **** 212:Core/Src/main.c **** void Dump_Flash_UART(int visual_format){ 213:Core/Src/main.c **** uint8_t byte; 214:Core/Src/main.c **** char buf[8]; 215:Core/Src/main.c **** 216:Core/Src/main.c **** for (int addr = 0; addr < 0x7FFFF; addr++) { // 512 KB 217:Core/Src/main.c **** byte = Flash_ReadByte(addr); 218:Core/Src/main.c **** 219:Core/Src/main.c **** if(visual_format==0){ 220:Core/Src/main.c **** // Send as raw byte: 221:Core/Src/main.c **** HAL_UART_Transmit(&huart2, &byte, 1, HAL_MAX_DELAY); 222:Core/Src/main.c **** }else{ 223:Core/Src/main.c **** // Send as str 224:Core/Src/main.c **** sprintf(buf, "%02X ", byte); 225:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)buf, strlen(buf), HAL_MAX_DELAY); 226:Core/Src/main.c **** if ((addr & 0x0F) == 0x0F) { 227:Core/Src/main.c **** char newline[] = "\r\n"; 228:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)newline, 2, HAL_MAX_DELAY); 229:Core/Src/main.c **** } 230:Core/Src/main.c **** } 231:Core/Src/main.c **** } 232:Core/Src/main.c **** } 233:Core/Src/main.c **** 234:Core/Src/main.c **** void Chip_Erase(void){ 235:Core/Src/main.c **** // Erase sequence 236:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 237:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 238:Core/Src/main.c **** Write_Command(0x5555, 0x80); 239:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 240:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 241:Core/Src/main.c **** Write_Command(0x5555, 0x10); 242:Core/Src/main.c **** 243:Core/Src/main.c **** HAL_Delay(150); // it's 100ms max but by precaution 244:Core/Src/main.c **** } 245:Core/Src/main.c **** 246:Core/Src/main.c **** void Chip_Program_Byte(int addr, int data){ 247:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 248:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 249:Core/Src/main.c **** Write_Command(0x5555, 0xA0); 250:Core/Src/main.c **** Write_Command(addr, data); 251:Core/Src/main.c **** } 252:Core/Src/main.c **** 253:Core/Src/main.c **** void Flash_From_UART(void){ 254:Core/Src/main.c **** debug_print("Waiting for file to flash...\r\n"); 255:Core/Src/main.c **** uint8_t byte; 256:Core/Src/main.c **** for(int i=0; i<8; i++){ 257:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 258:Core/Src/main.c **** Chip_Program_Byte(i, (int)byte); 259:Core/Src/main.c **** } ARM GAS /tmp/ccwcoXyi.s page 6 260:Core/Src/main.c **** debug_print("finished\r\n"); 261:Core/Src/main.c **** } 262:Core/Src/main.c **** 263:Core/Src/main.c **** /** 264:Core/Src/main.c **** * @brief System Clock Configuration 265:Core/Src/main.c **** * @retval None 266:Core/Src/main.c **** */ 267:Core/Src/main.c **** void SystemClock_Config(void) 268:Core/Src/main.c **** { 269:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 270:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 271:Core/Src/main.c **** 272:Core/Src/main.c **** /** Configure the main internal regulator output voltage 273:Core/Src/main.c **** */ 274:Core/Src/main.c **** __HAL_RCC_PWR_CLK_ENABLE(); 275:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 276:Core/Src/main.c **** 277:Core/Src/main.c **** /** Initializes the RCC Oscillators according to the specified parameters 278:Core/Src/main.c **** * in the RCC_OscInitTypeDef structure. 279:Core/Src/main.c **** */ 280:Core/Src/main.c **** RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 281:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 282:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 283:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 284:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 285:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; 286:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 287:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 288:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 289:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 290:Core/Src/main.c **** { 291:Core/Src/main.c **** Error_Handler(); 292:Core/Src/main.c **** } 293:Core/Src/main.c **** 294:Core/Src/main.c **** /** Initializes the CPU, AHB and APB buses clocks 295:Core/Src/main.c **** */ 296:Core/Src/main.c **** RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 297:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 298:Core/Src/main.c **** RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; 299:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 300:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 301:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 302:Core/Src/main.c **** 303:Core/Src/main.c **** if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) 304:Core/Src/main.c **** { 305:Core/Src/main.c **** Error_Handler(); 306:Core/Src/main.c **** } 307:Core/Src/main.c **** } 308:Core/Src/main.c **** 309:Core/Src/main.c **** /** 310:Core/Src/main.c **** * @brief USART2 Initialization Function 311:Core/Src/main.c **** * @param None 312:Core/Src/main.c **** * @retval None 313:Core/Src/main.c **** */ 314:Core/Src/main.c **** static void MX_USART2_UART_Init(void) 315:Core/Src/main.c **** { 316:Core/Src/main.c **** huart2.Instance = USART2; ARM GAS /tmp/ccwcoXyi.s page 7 317:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 318:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 319:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 320:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 321:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 322:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 323:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 324:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 325:Core/Src/main.c **** { 326:Core/Src/main.c **** Error_Handler(); 327:Core/Src/main.c **** } 328:Core/Src/main.c **** 329:Core/Src/main.c **** } 330:Core/Src/main.c **** 331:Core/Src/main.c **** // The argument must be 0 (input) or 1 (output) 332:Core/Src/main.c **** void Data_Pins_Init(int as_output){ 333:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 334:Core/Src/main.c **** 335:Core/Src/main.c **** // Configure PA0..PA7 as push-pull outputs 336:Core/Src/main.c **** GPIO_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_11 | GPIO_PIN_12 | 337:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 338:Core/Src/main.c **** if(as_output == 1){ 339:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 340:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 341:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 342:Core/Src/main.c **** }else{ 343:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_INPUT; // Input mode 344:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; // No pull-up/down 345:Core/Src/main.c **** } 346:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 347:Core/Src/main.c **** } 348:Core/Src/main.c **** 349:Core/Src/main.c **** void Address_Pins_Init(void){ 350:Core/Src/main.c **** GPIO_InitTypeDef GPIOC_InitStruct = {0}; 351:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs 352:Core/Src/main.c **** GPIOC_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | 353:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 354:Core/Src/main.c **** GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10| GPIO_PIN_11| 355:Core/Src/main.c **** GPIO_PIN_12| GPIO_PIN_13| GPIO_PIN_14| GPIO_PIN_15; 356:Core/Src/main.c **** GPIOC_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 357:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 358:Core/Src/main.c **** GPIOC_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 359:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 360:Core/Src/main.c **** 361:Core/Src/main.c **** // Then we do the same for the remaining 362:Core/Src/main.c **** GPIO_InitTypeDef GPIOB_InitStruct = {0}; 363:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 364:Core/Src/main.c **** GPIOB_InitStruct.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4; 365:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 366:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 367:Core/Src/main.c **** GPIOB_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 368:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); 369:Core/Src/main.c **** } 370:Core/Src/main.c **** 371:Core/Src/main.c **** void Command_Pins_Init(void){ 372:Core/Src/main.c **** // PA8-10 as outputs pins 373:Core/Src/main.c **** GPIO_InitTypeDef GPIOA_InitStruct = {0}; ARM GAS /tmp/ccwcoXyi.s page 8 374:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; 375:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 376:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 377:Core/Src/main.c **** GPIOA_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 378:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 379:Core/Src/main.c **** } 380:Core/Src/main.c **** 381:Core/Src/main.c **** void debug_print(const char *msg) { 382:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 383:Core/Src/main.c **** } 384:Core/Src/main.c **** 385:Core/Src/main.c **** /** 386:Core/Src/main.c **** * @brief GPIO Initialization Function 387:Core/Src/main.c **** * @param None 388:Core/Src/main.c **** * @retval None 389:Core/Src/main.c **** */ 390:Core/Src/main.c **** static void MX_GPIO_Init(void) 391:Core/Src/main.c **** { 28 .loc 1 391 1 view -0 29 .cfi_startproc 30 @ args = 0, pretend = 0, frame = 16 31 @ frame_needed = 0, uses_anonymous_args = 0 32 @ link register save eliminated. 33 0000 84B0 sub sp, sp, #16 34 .LCFI0: 35 .cfi_def_cfa_offset 16 392:Core/Src/main.c **** /* GPIO Ports Clock Enable */ 393:Core/Src/main.c **** __HAL_RCC_GPIOC_CLK_ENABLE(); 36 .loc 1 393 3 view .LVU1 37 .LBB4: 38 .loc 1 393 3 view .LVU2 39 0002 0022 movs r2, #0 40 0004 0092 str r2, [sp] 41 .loc 1 393 3 view .LVU3 42 0006 154B ldr r3, .L3 43 0008 196B ldr r1, [r3, #48] 44 000a 41F00401 orr r1, r1, #4 45 000e 1963 str r1, [r3, #48] 46 .loc 1 393 3 view .LVU4 47 0010 196B ldr r1, [r3, #48] 48 0012 01F00401 and r1, r1, #4 49 0016 0091 str r1, [sp] 50 .loc 1 393 3 view .LVU5 51 0018 0099 ldr r1, [sp] 52 .LBE4: 53 .loc 1 393 3 view .LVU6 394:Core/Src/main.c **** __HAL_RCC_GPIOH_CLK_ENABLE(); 54 .loc 1 394 3 view .LVU7 55 .LBB5: 56 .loc 1 394 3 view .LVU8 57 001a 0192 str r2, [sp, #4] 58 .loc 1 394 3 view .LVU9 59 001c 196B ldr r1, [r3, #48] 60 001e 41F08001 orr r1, r1, #128 61 0022 1963 str r1, [r3, #48] 62 .loc 1 394 3 view .LVU10 63 0024 196B ldr r1, [r3, #48] ARM GAS /tmp/ccwcoXyi.s page 9 64 0026 01F08001 and r1, r1, #128 65 002a 0191 str r1, [sp, #4] 66 .loc 1 394 3 view .LVU11 67 002c 0199 ldr r1, [sp, #4] 68 .LBE5: 69 .loc 1 394 3 view .LVU12 395:Core/Src/main.c **** __HAL_RCC_GPIOA_CLK_ENABLE(); 70 .loc 1 395 3 view .LVU13 71 .LBB6: 72 .loc 1 395 3 view .LVU14 73 002e 0292 str r2, [sp, #8] 74 .loc 1 395 3 view .LVU15 75 0030 196B ldr r1, [r3, #48] 76 0032 41F00101 orr r1, r1, #1 77 0036 1963 str r1, [r3, #48] 78 .loc 1 395 3 view .LVU16 79 0038 196B ldr r1, [r3, #48] 80 003a 01F00101 and r1, r1, #1 81 003e 0291 str r1, [sp, #8] 82 .loc 1 395 3 view .LVU17 83 0040 0299 ldr r1, [sp, #8] 84 .LBE6: 85 .loc 1 395 3 view .LVU18 396:Core/Src/main.c **** __HAL_RCC_GPIOB_CLK_ENABLE(); 86 .loc 1 396 3 view .LVU19 87 .LBB7: 88 .loc 1 396 3 view .LVU20 89 0042 0392 str r2, [sp, #12] 90 .loc 1 396 3 view .LVU21 91 0044 1A6B ldr r2, [r3, #48] 92 0046 42F00202 orr r2, r2, #2 93 004a 1A63 str r2, [r3, #48] 94 .loc 1 396 3 view .LVU22 95 004c 1B6B ldr r3, [r3, #48] 96 004e 03F00203 and r3, r3, #2 97 0052 0393 str r3, [sp, #12] 98 .loc 1 396 3 view .LVU23 99 0054 039B ldr r3, [sp, #12] 100 .LBE7: 101 .loc 1 396 3 view .LVU24 397:Core/Src/main.c **** 398:Core/Src/main.c **** /*Configure GPIO pin Output Level */ 399:Core/Src/main.c **** // HAL_GPIO_WritePin(LD2_GPIO_Port, LD2_Pin, GPIO_PIN_RESET); 400:Core/Src/main.c **** 401:Core/Src/main.c **** /*Configure GPIO pin : B1_Pin */ 402:Core/Src/main.c **** // GPIO_InitStruct.Pin = B1_Pin; 403:Core/Src/main.c **** // GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 404:Core/Src/main.c **** // GPIO_InitStruct.Pull = GPIO_NOPULL; 405:Core/Src/main.c **** // HAL_GPIO_Init(B1_GPIO_Port, &GPIO_InitStruct); 406:Core/Src/main.c **** 407:Core/Src/main.c **** /*Configure GPIO pin : LD2_Pin */ 408:Core/Src/main.c **** // GPIO_InitStruct.Pin = LD2_Pin; 409:Core/Src/main.c **** // GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 410:Core/Src/main.c **** // GPIO_InitStruct.Pull = GPIO_NOPULL; 411:Core/Src/main.c **** // GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 412:Core/Src/main.c **** // HAL_GPIO_Init(LD2_GPIO_Port, &GPIO_InitStruct); 413:Core/Src/main.c **** } ARM GAS /tmp/ccwcoXyi.s page 10 102 .loc 1 413 1 is_stmt 0 view .LVU25 103 0056 04B0 add sp, sp, #16 104 .LCFI1: 105 .cfi_def_cfa_offset 0 106 @ sp needed 107 0058 7047 bx lr 108 .L4: 109 005a 00BF .align 2 110 .L3: 111 005c 00380240 .word 1073887232 112 .cfi_endproc 113 .LFE155: 115 .section .text.Write_Address,"ax",%progbits 116 .align 1 117 .global Write_Address 118 .syntax unified 119 .thumb 120 .thumb_func 121 .fpu fpv4-sp-d16 123 Write_Address: 124 .LVL0: 125 .LFB138: 120:Core/Src/main.c **** int pin_array[] = { 126 .loc 1 120 32 is_stmt 1 view -0 127 .cfi_startproc 128 @ args = 0, pretend = 0, frame = 80 129 @ frame_needed = 0, uses_anonymous_args = 0 120:Core/Src/main.c **** int pin_array[] = { 130 .loc 1 120 32 is_stmt 0 view .LVU27 131 0000 30B5 push {r4, r5, lr} 132 .LCFI2: 133 .cfi_def_cfa_offset 12 134 .cfi_offset 4, -12 135 .cfi_offset 5, -8 136 .cfi_offset 14, -4 137 0002 95B0 sub sp, sp, #84 138 .LCFI3: 139 .cfi_def_cfa_offset 96 140 0004 0546 mov r5, r0 121:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 141 .loc 1 121 3 is_stmt 1 view .LVU28 121:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 142 .loc 1 121 7 is_stmt 0 view .LVU29 143 0006 4C22 movs r2, #76 144 0008 1E49 ldr r1, .L14 145 000a 01A8 add r0, sp, #4 146 .LVL1: 121:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_2, GPIO_PIN_3, 147 .loc 1 121 7 view .LVU30 148 000c FFF7FEFF bl memcpy 149 .LVL2: 128:Core/Src/main.c **** if(i<14){ 150 .loc 1 128 3 is_stmt 1 view .LVU31 151 .LBB8: 128:Core/Src/main.c **** if(i<14){ 152 .loc 1 128 7 view .LVU32 128:Core/Src/main.c **** if(i<14){ ARM GAS /tmp/ccwcoXyi.s page 11 153 .loc 1 128 11 is_stmt 0 view .LVU33 154 0010 0024 movs r4, #0 128:Core/Src/main.c **** if(i<14){ 155 .loc 1 128 3 view .LVU34 156 0012 09E0 b .L6 157 .LVL3: 158 .L8: 131:Core/Src/main.c **** } 159 .loc 1 131 12 is_stmt 1 view .LVU35 160 0014 0022 movs r2, #0 161 0016 14AB add r3, sp, #80 162 0018 03EB8403 add r3, r3, r4, lsl #2 163 001c 33F84C1C ldrh r1, [r3, #-76] 164 0020 1948 ldr r0, .L14+4 165 0022 FFF7FEFF bl HAL_GPIO_WritePin 166 .LVL4: 167 .L9: 128:Core/Src/main.c **** if(i<14){ 168 .loc 1 128 22 discriminator 2 view .LVU36 128:Core/Src/main.c **** if(i<14){ 169 .loc 1 128 23 is_stmt 0 discriminator 2 view .LVU37 170 0026 0134 adds r4, r4, #1 171 .LVL5: 172 .L6: 128:Core/Src/main.c **** if(i<14){ 173 .loc 1 128 16 is_stmt 1 discriminator 1 view .LVU38 128:Core/Src/main.c **** if(i<14){ 174 .loc 1 128 3 is_stmt 0 discriminator 1 view .LVU39 175 0028 122C cmp r4, #18 176 002a 29DC bgt .L13 129:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 177 .loc 1 129 5 is_stmt 1 view .LVU40 129:Core/Src/main.c **** if((address >> i) & 1) HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_SET); 178 .loc 1 129 7 is_stmt 0 view .LVU41 179 002c 0D2C cmp r4, #13 180 002e 0EDC bgt .L7 130:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 181 .loc 1 130 7 is_stmt 1 view .LVU42 130:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 182 .loc 1 130 19 is_stmt 0 view .LVU43 183 0030 45FA04F3 asr r3, r5, r4 130:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 184 .loc 1 130 9 view .LVU44 185 0034 13F0010F tst r3, #1 186 0038 ECD0 beq .L8 130:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOC, pin_array[i], GPIO_PIN_RESET); 187 .loc 1 130 30 is_stmt 1 discriminator 1 view .LVU45 188 003a 0122 movs r2, #1 189 003c 14AB add r3, sp, #80 190 003e 03EB8403 add r3, r3, r4, lsl #2 191 0042 33F84C1C ldrh r1, [r3, #-76] 192 0046 1048 ldr r0, .L14+4 193 0048 FFF7FEFF bl HAL_GPIO_WritePin 194 .LVL6: 195 004c EBE7 b .L9 196 .L7: 134:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); ARM GAS /tmp/ccwcoXyi.s page 12 197 .loc 1 134 7 view .LVU46 134:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 198 .loc 1 134 19 is_stmt 0 view .LVU47 199 004e 45FA04F3 asr r3, r5, r4 134:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 200 .loc 1 134 9 view .LVU48 201 0052 13F0010F tst r3, #1 202 0056 09D0 beq .L10 134:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOB, pin_array[i], GPIO_PIN_RESET); 203 .loc 1 134 30 is_stmt 1 discriminator 1 view .LVU49 204 0058 0122 movs r2, #1 205 005a 14AB add r3, sp, #80 206 005c 03EB8403 add r3, r3, r4, lsl #2 207 0060 33F84C1C ldrh r1, [r3, #-76] 208 0064 0948 ldr r0, .L14+8 209 0066 FFF7FEFF bl HAL_GPIO_WritePin 210 .LVL7: 211 006a DCE7 b .L9 212 .L10: 135:Core/Src/main.c **** } 213 .loc 1 135 12 view .LVU50 214 006c 0022 movs r2, #0 215 006e 14AB add r3, sp, #80 216 0070 03EB8403 add r3, r3, r4, lsl #2 217 0074 33F84C1C ldrh r1, [r3, #-76] 218 0078 0448 ldr r0, .L14+8 219 007a FFF7FEFF bl HAL_GPIO_WritePin 220 .LVL8: 221 007e D2E7 b .L9 222 .L13: 135:Core/Src/main.c **** } 223 .loc 1 135 12 is_stmt 0 view .LVU51 224 .LBE8: 138:Core/Src/main.c **** 225 .loc 1 138 1 view .LVU52 226 0080 15B0 add sp, sp, #84 227 .LCFI4: 228 .cfi_def_cfa_offset 12 229 @ sp needed 230 0082 30BD pop {r4, r5, pc} 231 .LVL9: 232 .L15: 138:Core/Src/main.c **** 233 .loc 1 138 1 view .LVU53 234 .align 2 235 .L14: 236 0084 00000000 .word .LANCHOR0 237 0088 00080240 .word 1073874944 238 008c 00040240 .word 1073873920 239 .cfi_endproc 240 .LFE138: 242 .section .text.Write_Command_Pins,"ax",%progbits 243 .align 1 244 .global Write_Command_Pins 245 .syntax unified 246 .thumb 247 .thumb_func ARM GAS /tmp/ccwcoXyi.s page 13 248 .fpu fpv4-sp-d16 250 Write_Command_Pins: 251 .LVL10: 252 .LFB141: 168:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 253 .loc 1 168 48 is_stmt 1 view -0 254 .cfi_startproc 255 @ args = 0, pretend = 0, frame = 0 256 @ frame_needed = 0, uses_anonymous_args = 0 168:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_8, (CE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 257 .loc 1 168 48 is_stmt 0 view .LVU55 258 0000 70B5 push {r4, r5, r6, lr} 259 .LCFI5: 260 .cfi_def_cfa_offset 16 261 .cfi_offset 4, -16 262 .cfi_offset 5, -12 263 .cfi_offset 6, -8 264 .cfi_offset 14, -4 265 0002 0E46 mov r6, r1 266 0004 1546 mov r5, r2 169:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 267 .loc 1 169 3 is_stmt 1 view .LVU56 268 0006 0D4C ldr r4, .L18 269 0008 021E subs r2, r0, #0 270 .LVL11: 169:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 271 .loc 1 169 3 is_stmt 0 view .LVU57 272 000a 18BF it ne 273 000c 0122 movne r2, #1 274 000e 4FF48071 mov r1, #256 275 .LVL12: 169:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 276 .loc 1 169 3 view .LVU58 277 0012 2046 mov r0, r4 278 .LVL13: 169:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_9, (OE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 279 .loc 1 169 3 view .LVU59 280 0014 FFF7FEFF bl HAL_GPIO_WritePin 281 .LVL14: 170:Core/Src/main.c **** HAL_GPIO_WritePin(GPIOA, GPIO_PIN_10,(WE) ? GPIO_PIN_SET : GPIO_PIN_RESET); 282 .loc 1 170 3 is_stmt 1 view .LVU60 283 0018 321E subs r2, r6, #0 284 001a 18BF it ne 285 001c 0122 movne r2, #1 286 001e 4FF40071 mov r1, #512 287 0022 2046 mov r0, r4 288 0024 FFF7FEFF bl HAL_GPIO_WritePin 289 .LVL15: 171:Core/Src/main.c **** } 290 .loc 1 171 3 view .LVU61 291 0028 2A1E subs r2, r5, #0 292 002a 18BF it ne 293 002c 0122 movne r2, #1 294 002e 4FF48061 mov r1, #1024 295 0032 2046 mov r0, r4 296 0034 FFF7FEFF bl HAL_GPIO_WritePin 297 .LVL16: ARM GAS /tmp/ccwcoXyi.s page 14 172:Core/Src/main.c **** 298 .loc 1 172 1 is_stmt 0 view .LVU62 299 0038 70BD pop {r4, r5, r6, pc} 300 .LVL17: 301 .L19: 172:Core/Src/main.c **** 302 .loc 1 172 1 view .LVU63 303 003a 00BF .align 2 304 .L18: 305 003c 00000240 .word 1073872896 306 .cfi_endproc 307 .LFE141: 309 .section .text.Data_Pins_Init,"ax",%progbits 310 .align 1 311 .global Data_Pins_Init 312 .syntax unified 313 .thumb 314 .thumb_func 315 .fpu fpv4-sp-d16 317 Data_Pins_Init: 318 .LVL18: 319 .LFB151: 332:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 320 .loc 1 332 35 is_stmt 1 view -0 321 .cfi_startproc 322 @ args = 0, pretend = 0, frame = 24 323 @ frame_needed = 0, uses_anonymous_args = 0 332:Core/Src/main.c **** GPIO_InitTypeDef GPIO_InitStruct = {0}; 324 .loc 1 332 35 is_stmt 0 view .LVU65 325 0000 00B5 push {lr} 326 .LCFI6: 327 .cfi_def_cfa_offset 4 328 .cfi_offset 14, -4 329 0002 87B0 sub sp, sp, #28 330 .LCFI7: 331 .cfi_def_cfa_offset 32 333:Core/Src/main.c **** 332 .loc 1 333 3 is_stmt 1 view .LVU66 333:Core/Src/main.c **** 333 .loc 1 333 20 is_stmt 0 view .LVU67 334 0004 0023 movs r3, #0 335 0006 0193 str r3, [sp, #4] 336 0008 0293 str r3, [sp, #8] 337 000a 0393 str r3, [sp, #12] 338 000c 0493 str r3, [sp, #16] 339 000e 0593 str r3, [sp, #20] 336:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 340 .loc 1 336 3 is_stmt 1 view .LVU68 336:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 341 .loc 1 336 23 is_stmt 0 view .LVU69 342 0010 41F6F303 movw r3, #6387 343 0014 0193 str r3, [sp, #4] 338:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 344 .loc 1 338 3 is_stmt 1 view .LVU70 338:Core/Src/main.c **** GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 345 .loc 1 338 5 is_stmt 0 view .LVU71 346 0016 0128 cmp r0, #1 ARM GAS /tmp/ccwcoXyi.s page 15 347 0018 08D0 beq .L24 343:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_PULLDOWN; // No pull-up/down 348 .loc 1 343 5 is_stmt 1 view .LVU72 344:Core/Src/main.c **** } 349 .loc 1 344 5 view .LVU73 344:Core/Src/main.c **** } 350 .loc 1 344 26 is_stmt 0 view .LVU74 351 001a 0223 movs r3, #2 352 001c 0393 str r3, [sp, #12] 353 .L22: 346:Core/Src/main.c **** } 354 .loc 1 346 3 is_stmt 1 view .LVU75 355 001e 01A9 add r1, sp, #4 356 0020 0548 ldr r0, .L25 357 .LVL19: 346:Core/Src/main.c **** } 358 .loc 1 346 3 is_stmt 0 view .LVU76 359 0022 FFF7FEFF bl HAL_GPIO_Init 360 .LVL20: 347:Core/Src/main.c **** 361 .loc 1 347 1 view .LVU77 362 0026 07B0 add sp, sp, #28 363 .LCFI8: 364 .cfi_remember_state 365 .cfi_def_cfa_offset 4 366 @ sp needed 367 0028 5DF804FB ldr pc, [sp], #4 368 .LVL21: 369 .L24: 370 .LCFI9: 371 .cfi_restore_state 339:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 372 .loc 1 339 5 is_stmt 1 view .LVU78 339:Core/Src/main.c **** GPIO_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 373 .loc 1 339 26 is_stmt 0 view .LVU79 374 002c 0123 movs r3, #1 375 002e 0293 str r3, [sp, #8] 340:Core/Src/main.c **** GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 376 .loc 1 340 5 is_stmt 1 view .LVU80 341:Core/Src/main.c **** }else{ 377 .loc 1 341 5 view .LVU81 341:Core/Src/main.c **** }else{ 378 .loc 1 341 27 is_stmt 0 view .LVU82 379 0030 0223 movs r3, #2 380 0032 0493 str r3, [sp, #16] 381 0034 F3E7 b .L22 382 .L26: 383 0036 00BF .align 2 384 .L25: 385 0038 00000240 .word 1073872896 386 .cfi_endproc 387 .LFE151: 389 .section .text.Receive_Data,"ax",%progbits 390 .align 1 391 .global Receive_Data 392 .syntax unified 393 .thumb ARM GAS /tmp/ccwcoXyi.s page 16 394 .thumb_func 395 .fpu fpv4-sp-d16 397 Receive_Data: 398 .LFB139: 140:Core/Src/main.c **** Data_Pins_Init(0); // We make sure it's in input mode 399 .loc 1 140 23 is_stmt 1 view -0 400 .cfi_startproc 401 @ args = 0, pretend = 0, frame = 32 402 @ frame_needed = 0, uses_anonymous_args = 0 403 0000 30B5 push {r4, r5, lr} 404 .LCFI10: 405 .cfi_def_cfa_offset 12 406 .cfi_offset 4, -12 407 .cfi_offset 5, -8 408 .cfi_offset 14, -4 409 0002 89B0 sub sp, sp, #36 410 .LCFI11: 411 .cfi_def_cfa_offset 48 141:Core/Src/main.c **** int result = 0; 412 .loc 1 141 3 view .LVU84 413 0004 0020 movs r0, #0 414 0006 FFF7FEFF bl Data_Pins_Init 415 .LVL22: 142:Core/Src/main.c **** int pin_array[] = { 416 .loc 1 142 3 view .LVU85 143:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 417 .loc 1 143 3 view .LVU86 143:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 418 .loc 1 143 7 is_stmt 0 view .LVU87 419 000a 6C46 mov r4, sp 420 000c 0E4D ldr r5, .L33 421 000e 0FCD ldmia r5!, {r0, r1, r2, r3} 422 0010 0FC4 stmia r4!, {r0, r1, r2, r3} 423 0012 95E80F00 ldm r5, {r0, r1, r2, r3} 424 0016 84E80F00 stm r4, {r0, r1, r2, r3} 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 425 .loc 1 147 3 is_stmt 1 view .LVU88 426 .LBB9: 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 427 .loc 1 147 7 view .LVU89 428 .LVL23: 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 429 .loc 1 147 11 is_stmt 0 view .LVU90 430 001a 0024 movs r4, #0 431 .LBE9: 142:Core/Src/main.c **** int pin_array[] = { 432 .loc 1 142 7 view .LVU91 433 001c 2546 mov r5, r4 434 .LBB10: 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 435 .loc 1 147 3 view .LVU92 436 001e 00E0 b .L28 437 .LVL24: 438 .L29: 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 439 .loc 1 147 21 is_stmt 1 discriminator 2 view .LVU93 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ ARM GAS /tmp/ccwcoXyi.s page 17 440 .loc 1 147 22 is_stmt 0 discriminator 2 view .LVU94 441 0020 0134 adds r4, r4, #1 442 .LVL25: 443 .L28: 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 444 .loc 1 147 16 is_stmt 1 discriminator 1 view .LVU95 147:Core/Src/main.c **** if(HAL_GPIO_ReadPin(GPIOA, pin_array[i]) == GPIO_PIN_SET){ 445 .loc 1 147 3 is_stmt 0 discriminator 1 view .LVU96 446 0022 072C cmp r4, #7 447 0024 0DDC bgt .L32 148:Core/Src/main.c **** result += 1 << i; 448 .loc 1 148 5 is_stmt 1 view .LVU97 148:Core/Src/main.c **** result += 1 << i; 449 .loc 1 148 41 is_stmt 0 view .LVU98 450 0026 08AB add r3, sp, #32 451 0028 03EB8403 add r3, r3, r4, lsl #2 148:Core/Src/main.c **** result += 1 << i; 452 .loc 1 148 8 view .LVU99 453 002c 33F8201C ldrh r1, [r3, #-32] 454 0030 0648 ldr r0, .L33+4 455 0032 FFF7FEFF bl HAL_GPIO_ReadPin 456 .LVL26: 148:Core/Src/main.c **** result += 1 << i; 457 .loc 1 148 7 view .LVU100 458 0036 0128 cmp r0, #1 459 0038 F2D1 bne .L29 149:Core/Src/main.c **** } 460 .loc 1 149 7 is_stmt 1 view .LVU101 149:Core/Src/main.c **** } 461 .loc 1 149 19 is_stmt 0 view .LVU102 462 003a 0123 movs r3, #1 463 003c A340 lsls r3, r3, r4 149:Core/Src/main.c **** } 464 .loc 1 149 14 view .LVU103 465 003e 1D44 add r5, r5, r3 466 .LVL27: 149:Core/Src/main.c **** } 467 .loc 1 149 14 view .LVU104 468 0040 EEE7 b .L29 469 .L32: 149:Core/Src/main.c **** } 470 .loc 1 149 14 view .LVU105 471 .LBE10: 152:Core/Src/main.c **** } 472 .loc 1 152 3 is_stmt 1 view .LVU106 153:Core/Src/main.c **** 473 .loc 1 153 1 is_stmt 0 view .LVU107 474 0042 2846 mov r0, r5 475 0044 09B0 add sp, sp, #36 476 .LCFI12: 477 .cfi_def_cfa_offset 12 478 @ sp needed 479 0046 30BD pop {r4, r5, pc} 480 .LVL28: 481 .L34: 153:Core/Src/main.c **** 482 .loc 1 153 1 view .LVU108 ARM GAS /tmp/ccwcoXyi.s page 18 483 .align 2 484 .L33: 485 0048 4C000000 .word .LANCHOR0+76 486 004c 00000240 .word 1073872896 487 .cfi_endproc 488 .LFE139: 490 .section .text.Write_Data,"ax",%progbits 491 .align 1 492 .global Write_Data 493 .syntax unified 494 .thumb 495 .thumb_func 496 .fpu fpv4-sp-d16 498 Write_Data: 499 .LVL29: 500 .LFB140: 155:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 501 .loc 1 155 27 is_stmt 1 view -0 502 .cfi_startproc 503 @ args = 0, pretend = 0, frame = 32 504 @ frame_needed = 0, uses_anonymous_args = 0 155:Core/Src/main.c **** Data_Pins_Init(1); // We make sure it's in output mode 505 .loc 1 155 27 is_stmt 0 view .LVU110 506 0000 70B5 push {r4, r5, r6, lr} 507 .LCFI13: 508 .cfi_def_cfa_offset 16 509 .cfi_offset 4, -16 510 .cfi_offset 5, -12 511 .cfi_offset 6, -8 512 .cfi_offset 14, -4 513 0002 88B0 sub sp, sp, #32 514 .LCFI14: 515 .cfi_def_cfa_offset 48 516 0004 0646 mov r6, r0 156:Core/Src/main.c **** int pin_array[] = { 517 .loc 1 156 3 is_stmt 1 view .LVU111 518 0006 0120 movs r0, #1 519 .LVL30: 156:Core/Src/main.c **** int pin_array[] = { 520 .loc 1 156 3 is_stmt 0 view .LVU112 521 0008 FFF7FEFF bl Data_Pins_Init 522 .LVL31: 157:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 523 .loc 1 157 3 is_stmt 1 view .LVU113 157:Core/Src/main.c **** GPIO_PIN_0, GPIO_PIN_1, GPIO_PIN_11, GPIO_PIN_12, 524 .loc 1 157 7 is_stmt 0 view .LVU114 525 000c 6C46 mov r4, sp 526 000e 134D ldr r5, .L42 527 0010 0FCD ldmia r5!, {r0, r1, r2, r3} 528 0012 0FC4 stmia r4!, {r0, r1, r2, r3} 529 0014 95E80F00 ldm r5, {r0, r1, r2, r3} 530 0018 84E80F00 stm r4, {r0, r1, r2, r3} 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 531 .loc 1 161 3 is_stmt 1 view .LVU115 532 .LBB11: 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 533 .loc 1 161 7 view .LVU116 ARM GAS /tmp/ccwcoXyi.s page 19 534 .LVL32: 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 535 .loc 1 161 11 is_stmt 0 view .LVU117 536 001c 0024 movs r4, #0 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 537 .loc 1 161 3 view .LVU118 538 001e 09E0 b .L36 539 .LVL33: 540 .L37: 163:Core/Src/main.c **** } 541 .loc 1 163 10 is_stmt 1 view .LVU119 542 0020 0022 movs r2, #0 543 0022 08AB add r3, sp, #32 544 0024 03EB8403 add r3, r3, r4, lsl #2 545 0028 33F8201C ldrh r1, [r3, #-32] 546 002c 0C48 ldr r0, .L42+4 547 002e FFF7FEFF bl HAL_GPIO_WritePin 548 .LVL34: 549 .L38: 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 550 .loc 1 161 21 discriminator 2 view .LVU120 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 551 .loc 1 161 22 is_stmt 0 discriminator 2 view .LVU121 552 0032 0134 adds r4, r4, #1 553 .LVL35: 554 .L36: 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 555 .loc 1 161 16 is_stmt 1 discriminator 1 view .LVU122 161:Core/Src/main.c **** if((value >> i) & 1) HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_SET); 556 .loc 1 161 3 is_stmt 0 discriminator 1 view .LVU123 557 0034 072C cmp r4, #7 558 0036 0EDC bgt .L41 162:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 559 .loc 1 162 5 is_stmt 1 view .LVU124 162:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 560 .loc 1 162 15 is_stmt 0 view .LVU125 561 0038 46FA04F3 asr r3, r6, r4 162:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 562 .loc 1 162 7 view .LVU126 563 003c 13F0010F tst r3, #1 564 0040 EED0 beq .L37 162:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 565 .loc 1 162 26 is_stmt 1 discriminator 1 view .LVU127 566 0042 0122 movs r2, #1 567 0044 08AB add r3, sp, #32 568 0046 03EB8403 add r3, r3, r4, lsl #2 569 004a 33F8201C ldrh r1, [r3, #-32] 570 004e 0448 ldr r0, .L42+4 571 0050 FFF7FEFF bl HAL_GPIO_WritePin 572 .LVL36: 573 0054 EDE7 b .L38 574 .L41: 162:Core/Src/main.c **** else HAL_GPIO_WritePin(GPIOA, pin_array[i], GPIO_PIN_RESET); 575 .loc 1 162 26 is_stmt 0 discriminator 1 view .LVU128 576 .LBE11: 165:Core/Src/main.c **** 577 .loc 1 165 1 view .LVU129 ARM GAS /tmp/ccwcoXyi.s page 20 578 0056 08B0 add sp, sp, #32 579 .LCFI15: 580 .cfi_def_cfa_offset 16 581 @ sp needed 582 0058 70BD pop {r4, r5, r6, pc} 583 .LVL37: 584 .L43: 165:Core/Src/main.c **** 585 .loc 1 165 1 view .LVU130 586 005a 00BF .align 2 587 .L42: 588 005c 4C000000 .word .LANCHOR0+76 589 0060 00000240 .word 1073872896 590 .cfi_endproc 591 .LFE140: 593 .section .text.Write_Command,"ax",%progbits 594 .align 1 595 .global Write_Command 596 .syntax unified 597 .thumb 598 .thumb_func 599 .fpu fpv4-sp-d16 601 Write_Command: 602 .LVL38: 603 .LFB142: 174:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 604 .loc 1 174 40 is_stmt 1 view -0 605 .cfi_startproc 606 @ args = 0, pretend = 0, frame = 0 607 @ frame_needed = 0, uses_anonymous_args = 0 174:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 608 .loc 1 174 40 is_stmt 0 view .LVU132 609 0000 38B5 push {r3, r4, r5, lr} 610 .LCFI16: 611 .cfi_def_cfa_offset 16 612 .cfi_offset 3, -16 613 .cfi_offset 4, -12 614 .cfi_offset 5, -8 615 .cfi_offset 14, -4 616 0002 0546 mov r5, r0 617 0004 0C46 mov r4, r1 175:Core/Src/main.c **** Write_Address(addr); 618 .loc 1 175 5 is_stmt 1 view .LVU133 619 0006 0122 movs r2, #1 620 0008 1146 mov r1, r2 621 .LVL39: 175:Core/Src/main.c **** Write_Address(addr); 622 .loc 1 175 5 is_stmt 0 view .LVU134 623 000a 1046 mov r0, r2 624 .LVL40: 175:Core/Src/main.c **** Write_Address(addr); 625 .loc 1 175 5 view .LVU135 626 000c FFF7FEFF bl Write_Command_Pins 627 .LVL41: 176:Core/Src/main.c **** Write_Data(data); 628 .loc 1 176 5 is_stmt 1 view .LVU136 629 0010 2846 mov r0, r5 ARM GAS /tmp/ccwcoXyi.s page 21 630 0012 FFF7FEFF bl Write_Address 631 .LVL42: 177:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); 632 .loc 1 177 5 view .LVU137 633 0016 2046 mov r0, r4 634 0018 FFF7FEFF bl Write_Data 635 .LVL43: 178:Core/Src/main.c **** // 4. Pulse WE# low to latch data 636 .loc 1 178 5 view .LVU138 637 001c 0122 movs r2, #1 638 001e 1146 mov r1, r2 639 0020 0020 movs r0, #0 640 0022 FFF7FEFF bl Write_Command_Pins 641 .LVL44: 180:Core/Src/main.c **** Write_Command_Pins(0, 1, 1); // WE high 642 .loc 1 180 5 view .LVU139 643 0026 0022 movs r2, #0 644 0028 0121 movs r1, #1 645 002a 1046 mov r0, r2 646 002c FFF7FEFF bl Write_Command_Pins 647 .LVL45: 181:Core/Src/main.c **** 648 .loc 1 181 5 view .LVU140 649 0030 0122 movs r2, #1 650 0032 1146 mov r1, r2 651 0034 0020 movs r0, #0 652 0036 FFF7FEFF bl Write_Command_Pins 653 .LVL46: 184:Core/Src/main.c **** } 654 .loc 1 184 5 view .LVU141 655 003a 0122 movs r2, #1 656 003c 1146 mov r1, r2 657 003e 1046 mov r0, r2 658 0040 FFF7FEFF bl Write_Command_Pins 659 .LVL47: 185:Core/Src/main.c **** 660 .loc 1 185 1 is_stmt 0 view .LVU142 661 0044 38BD pop {r3, r4, r5, pc} 185:Core/Src/main.c **** 662 .loc 1 185 1 view .LVU143 663 .cfi_endproc 664 .LFE142: 666 .section .text.Chip_Erase,"ax",%progbits 667 .align 1 668 .global Chip_Erase 669 .syntax unified 670 .thumb 671 .thumb_func 672 .fpu fpv4-sp-d16 674 Chip_Erase: 675 .LFB146: 234:Core/Src/main.c **** // Erase sequence 676 .loc 1 234 22 is_stmt 1 view -0 677 .cfi_startproc 678 @ args = 0, pretend = 0, frame = 0 679 @ frame_needed = 0, uses_anonymous_args = 0 680 0000 08B5 push {r3, lr} ARM GAS /tmp/ccwcoXyi.s page 22 681 .LCFI17: 682 .cfi_def_cfa_offset 8 683 .cfi_offset 3, -8 684 .cfi_offset 14, -4 236:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 685 .loc 1 236 3 view .LVU145 686 0002 AA21 movs r1, #170 687 0004 45F25550 movw r0, #21845 688 0008 FFF7FEFF bl Write_Command 689 .LVL48: 237:Core/Src/main.c **** Write_Command(0x5555, 0x80); 690 .loc 1 237 3 view .LVU146 691 000c 5521 movs r1, #85 692 000e 42F6AA20 movw r0, #10922 693 0012 FFF7FEFF bl Write_Command 694 .LVL49: 238:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 695 .loc 1 238 3 view .LVU147 696 0016 8021 movs r1, #128 697 0018 45F25550 movw r0, #21845 698 001c FFF7FEFF bl Write_Command 699 .LVL50: 239:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 700 .loc 1 239 3 view .LVU148 701 0020 AA21 movs r1, #170 702 0022 45F25550 movw r0, #21845 703 0026 FFF7FEFF bl Write_Command 704 .LVL51: 240:Core/Src/main.c **** Write_Command(0x5555, 0x10); 705 .loc 1 240 3 view .LVU149 706 002a 5521 movs r1, #85 707 002c 42F6AA20 movw r0, #10922 708 0030 FFF7FEFF bl Write_Command 709 .LVL52: 241:Core/Src/main.c **** 710 .loc 1 241 3 view .LVU150 711 0034 1021 movs r1, #16 712 0036 45F25550 movw r0, #21845 713 003a FFF7FEFF bl Write_Command 714 .LVL53: 243:Core/Src/main.c **** } 715 .loc 1 243 3 view .LVU151 716 003e 9620 movs r0, #150 717 0040 FFF7FEFF bl HAL_Delay 718 .LVL54: 244:Core/Src/main.c **** 719 .loc 1 244 1 is_stmt 0 view .LVU152 720 0044 08BD pop {r3, pc} 721 .cfi_endproc 722 .LFE146: 724 .section .text.Chip_Program_Byte,"ax",%progbits 725 .align 1 726 .global Chip_Program_Byte 727 .syntax unified 728 .thumb 729 .thumb_func 730 .fpu fpv4-sp-d16 ARM GAS /tmp/ccwcoXyi.s page 23 732 Chip_Program_Byte: 733 .LVL55: 734 .LFB147: 246:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 735 .loc 1 246 43 is_stmt 1 view -0 736 .cfi_startproc 737 @ args = 0, pretend = 0, frame = 0 738 @ frame_needed = 0, uses_anonymous_args = 0 246:Core/Src/main.c **** Write_Command(0x5555, 0xAA); 739 .loc 1 246 43 is_stmt 0 view .LVU154 740 0000 38B5 push {r3, r4, r5, lr} 741 .LCFI18: 742 .cfi_def_cfa_offset 16 743 .cfi_offset 3, -16 744 .cfi_offset 4, -12 745 .cfi_offset 5, -8 746 .cfi_offset 14, -4 747 0002 0446 mov r4, r0 748 0004 0D46 mov r5, r1 247:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 749 .loc 1 247 3 is_stmt 1 view .LVU155 750 0006 AA21 movs r1, #170 751 .LVL56: 247:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 752 .loc 1 247 3 is_stmt 0 view .LVU156 753 0008 45F25550 movw r0, #21845 754 .LVL57: 247:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 755 .loc 1 247 3 view .LVU157 756 000c FFF7FEFF bl Write_Command 757 .LVL58: 248:Core/Src/main.c **** Write_Command(0x5555, 0xA0); 758 .loc 1 248 3 is_stmt 1 view .LVU158 759 0010 5521 movs r1, #85 760 0012 42F6AA20 movw r0, #10922 761 0016 FFF7FEFF bl Write_Command 762 .LVL59: 249:Core/Src/main.c **** Write_Command(addr, data); 763 .loc 1 249 3 view .LVU159 764 001a A021 movs r1, #160 765 001c 45F25550 movw r0, #21845 766 0020 FFF7FEFF bl Write_Command 767 .LVL60: 250:Core/Src/main.c **** } 768 .loc 1 250 3 view .LVU160 769 0024 2946 mov r1, r5 770 0026 2046 mov r0, r4 771 0028 FFF7FEFF bl Write_Command 772 .LVL61: 251:Core/Src/main.c **** 773 .loc 1 251 1 is_stmt 0 view .LVU161 774 002c 38BD pop {r3, r4, r5, pc} 251:Core/Src/main.c **** 775 .loc 1 251 1 view .LVU162 776 .cfi_endproc 777 .LFE147: 779 .section .text.Flash_ReadByte,"ax",%progbits ARM GAS /tmp/ccwcoXyi.s page 24 780 .align 1 781 .global Flash_ReadByte 782 .syntax unified 783 .thumb 784 .thumb_func 785 .fpu fpv4-sp-d16 787 Flash_ReadByte: 788 .LVL62: 789 .LFB143: 187:Core/Src/main.c **** Write_Address(addr); 790 .loc 1 187 30 is_stmt 1 view -0 791 .cfi_startproc 792 @ args = 0, pretend = 0, frame = 0 793 @ frame_needed = 0, uses_anonymous_args = 0 187:Core/Src/main.c **** Write_Address(addr); 794 .loc 1 187 30 is_stmt 0 view .LVU164 795 0000 10B5 push {r4, lr} 796 .LCFI19: 797 .cfi_def_cfa_offset 8 798 .cfi_offset 4, -8 799 .cfi_offset 14, -4 188:Core/Src/main.c **** Data_Pins_Init(0); 800 .loc 1 188 5 is_stmt 1 view .LVU165 801 0002 FFF7FEFF bl Write_Address 802 .LVL63: 189:Core/Src/main.c **** Write_Command_Pins(0, 0, 1); 803 .loc 1 189 5 view .LVU166 804 0006 0020 movs r0, #0 805 0008 FFF7FEFF bl Data_Pins_Init 806 .LVL64: 190:Core/Src/main.c **** int data = Receive_Data(); 807 .loc 1 190 5 view .LVU167 808 000c 0122 movs r2, #1 809 000e 0021 movs r1, #0 810 0010 0846 mov r0, r1 811 0012 FFF7FEFF bl Write_Command_Pins 812 .LVL65: 191:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 813 .loc 1 191 5 view .LVU168 191:Core/Src/main.c **** Write_Command_Pins(1, 1, 1); 814 .loc 1 191 16 is_stmt 0 view .LVU169 815 0016 FFF7FEFF bl Receive_Data 816 .LVL66: 817 001a 0446 mov r4, r0 818 .LVL67: 192:Core/Src/main.c **** return data; 819 .loc 1 192 5 is_stmt 1 view .LVU170 820 001c 0122 movs r2, #1 821 001e 1146 mov r1, r2 822 0020 1046 mov r0, r2 823 .LVL68: 192:Core/Src/main.c **** return data; 824 .loc 1 192 5 is_stmt 0 view .LVU171 825 0022 FFF7FEFF bl Write_Command_Pins 826 .LVL69: 193:Core/Src/main.c **** } 827 .loc 1 193 5 is_stmt 1 view .LVU172 ARM GAS /tmp/ccwcoXyi.s page 25 194:Core/Src/main.c **** 828 .loc 1 194 1 is_stmt 0 view .LVU173 829 0026 2046 mov r0, r4 830 0028 10BD pop {r4, pc} 194:Core/Src/main.c **** 831 .loc 1 194 1 view .LVU174 832 .cfi_endproc 833 .LFE143: 835 .section .text.Enter_Device_ID,"ax",%progbits 836 .align 1 837 .global Enter_Device_ID 838 .syntax unified 839 .thumb 840 .thumb_func 841 .fpu fpv4-sp-d16 843 Enter_Device_ID: 844 .LVL70: 845 .LFB144: 196:Core/Src/main.c **** // Enter ID mode 846 .loc 1 196 53 is_stmt 1 view -0 847 .cfi_startproc 848 @ args = 0, pretend = 0, frame = 0 849 @ frame_needed = 0, uses_anonymous_args = 0 196:Core/Src/main.c **** // Enter ID mode 850 .loc 1 196 53 is_stmt 0 view .LVU176 851 0000 38B5 push {r3, r4, r5, lr} 852 .LCFI20: 853 .cfi_def_cfa_offset 16 854 .cfi_offset 3, -16 855 .cfi_offset 4, -12 856 .cfi_offset 5, -8 857 .cfi_offset 14, -4 858 0002 0546 mov r5, r0 859 0004 0C46 mov r4, r1 198:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 860 .loc 1 198 3 is_stmt 1 view .LVU177 861 0006 AA21 movs r1, #170 862 .LVL71: 198:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 863 .loc 1 198 3 is_stmt 0 view .LVU178 864 0008 45F25550 movw r0, #21845 865 .LVL72: 198:Core/Src/main.c **** Write_Command(0x2AAA, 0x55); 866 .loc 1 198 3 view .LVU179 867 000c FFF7FEFF bl Write_Command 868 .LVL73: 199:Core/Src/main.c **** Write_Command(0x5555, 0x90); 869 .loc 1 199 3 is_stmt 1 view .LVU180 870 0010 5521 movs r1, #85 871 0012 42F6AA20 movw r0, #10922 872 0016 FFF7FEFF bl Write_Command 873 .LVL74: 200:Core/Src/main.c **** 874 .loc 1 200 3 view .LVU181 875 001a 9021 movs r1, #144 876 001c 45F25550 movw r0, #21845 877 0020 FFF7FEFF bl Write_Command ARM GAS /tmp/ccwcoXyi.s page 26 878 .LVL75: 203:Core/Src/main.c **** 879 .loc 1 203 3 view .LVU182 203:Core/Src/main.c **** 880 .loc 1 203 19 is_stmt 0 view .LVU183 881 0024 0020 movs r0, #0 882 0026 FFF7FEFF bl Flash_ReadByte 883 .LVL76: 203:Core/Src/main.c **** 884 .loc 1 203 17 view .LVU184 885 002a 2860 str r0, [r5] 206:Core/Src/main.c **** 886 .loc 1 206 3 is_stmt 1 view .LVU185 206:Core/Src/main.c **** 887 .loc 1 206 13 is_stmt 0 view .LVU186 888 002c 0120 movs r0, #1 889 002e FFF7FEFF bl Flash_ReadByte 890 .LVL77: 206:Core/Src/main.c **** 891 .loc 1 206 11 view .LVU187 892 0032 2060 str r0, [r4] 209:Core/Src/main.c **** } 893 .loc 1 209 3 is_stmt 1 view .LVU188 894 0034 F021 movs r1, #240 895 0036 45F25550 movw r0, #21845 896 003a FFF7FEFF bl Write_Command 897 .LVL78: 210:Core/Src/main.c **** 898 .loc 1 210 1 is_stmt 0 view .LVU189 899 003e 38BD pop {r3, r4, r5, pc} 210:Core/Src/main.c **** 900 .loc 1 210 1 view .LVU190 901 .cfi_endproc 902 .LFE144: 904 .section .rodata.Dump_Flash_UART.str1.4,"aMS",%progbits,1 905 .align 2 906 .LC2: 907 0000 25303258 .ascii "%02X \000" 907 2000 908 0006 0000 .align 2 909 .LC3: 910 0008 0D0A00 .ascii "\015\012\000" 911 .section .text.Dump_Flash_UART,"ax",%progbits 912 .align 1 913 .global Dump_Flash_UART 914 .syntax unified 915 .thumb 916 .thumb_func 917 .fpu fpv4-sp-d16 919 Dump_Flash_UART: 920 .LVL79: 921 .LFB145: 212:Core/Src/main.c **** uint8_t byte; 922 .loc 1 212 40 is_stmt 1 view -0 923 .cfi_startproc 924 @ args = 0, pretend = 0, frame = 16 925 @ frame_needed = 0, uses_anonymous_args = 0 ARM GAS /tmp/ccwcoXyi.s page 27 212:Core/Src/main.c **** uint8_t byte; 926 .loc 1 212 40 is_stmt 0 view .LVU192 927 0000 30B5 push {r4, r5, lr} 928 .LCFI21: 929 .cfi_def_cfa_offset 12 930 .cfi_offset 4, -12 931 .cfi_offset 5, -8 932 .cfi_offset 14, -4 933 0002 85B0 sub sp, sp, #20 934 .LCFI22: 935 .cfi_def_cfa_offset 32 936 0004 0546 mov r5, r0 213:Core/Src/main.c **** char buf[8]; 937 .loc 1 213 3 is_stmt 1 view .LVU193 214:Core/Src/main.c **** 938 .loc 1 214 3 view .LVU194 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 939 .loc 1 216 3 view .LVU195 940 .LBB12: 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 941 .loc 1 216 8 view .LVU196 942 .LVL80: 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 943 .loc 1 216 12 is_stmt 0 view .LVU197 944 0006 0024 movs r4, #0 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 945 .loc 1 216 3 view .LVU198 946 0008 12E0 b .L55 947 .LVL81: 948 .L56: 224:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)buf, strlen(buf), HAL_MAX_DELAY); 949 .loc 1 224 7 is_stmt 1 view .LVU199 950 000a 1C49 ldr r1, .L62 951 000c 01A8 add r0, sp, #4 952 000e FFF7FEFF bl sprintf 953 .LVL82: 225:Core/Src/main.c **** if ((addr & 0x0F) == 0x0F) { 954 .loc 1 225 7 view .LVU200 225:Core/Src/main.c **** if ((addr & 0x0F) == 0x0F) { 955 .loc 1 225 49 is_stmt 0 view .LVU201 956 0012 01A8 add r0, sp, #4 957 0014 FFF7FEFF bl strlen 958 .LVL83: 225:Core/Src/main.c **** if ((addr & 0x0F) == 0x0F) { 959 .loc 1 225 7 view .LVU202 960 0018 4FF0FF33 mov r3, #-1 961 001c 82B2 uxth r2, r0 962 001e 01A9 add r1, sp, #4 963 0020 1748 ldr r0, .L62+4 964 0022 FFF7FEFF bl HAL_UART_Transmit 965 .LVL84: 226:Core/Src/main.c **** char newline[] = "\r\n"; 966 .loc 1 226 7 is_stmt 1 view .LVU203 226:Core/Src/main.c **** char newline[] = "\r\n"; 967 .loc 1 226 17 is_stmt 0 view .LVU204 968 0026 04F00F03 and r3, r4, #15 226:Core/Src/main.c **** char newline[] = "\r\n"; ARM GAS /tmp/ccwcoXyi.s page 28 969 .loc 1 226 10 view .LVU205 970 002a 0F2B cmp r3, #15 971 002c 14D0 beq .L60 972 .L57: 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 973 .loc 1 216 38 is_stmt 1 discriminator 2 view .LVU206 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 974 .loc 1 216 42 is_stmt 0 discriminator 2 view .LVU207 975 002e 0134 adds r4, r4, #1 976 .LVL85: 977 .L55: 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 978 .loc 1 216 22 is_stmt 1 discriminator 1 view .LVU208 216:Core/Src/main.c **** byte = Flash_ReadByte(addr); 979 .loc 1 216 3 is_stmt 0 discriminator 1 view .LVU209 980 0030 144B ldr r3, .L62+8 981 0032 9C42 cmp r4, r3 982 0034 1FDC bgt .L61 217:Core/Src/main.c **** 983 .loc 1 217 5 is_stmt 1 view .LVU210 217:Core/Src/main.c **** 984 .loc 1 217 12 is_stmt 0 view .LVU211 985 0036 2046 mov r0, r4 986 0038 FFF7FEFF bl Flash_ReadByte 987 .LVL86: 217:Core/Src/main.c **** 988 .loc 1 217 10 view .LVU212 989 003c C2B2 uxtb r2, r0 990 003e 8DF80F20 strb r2, [sp, #15] 219:Core/Src/main.c **** // Send as raw byte: 991 .loc 1 219 5 is_stmt 1 view .LVU213 219:Core/Src/main.c **** // Send as raw byte: 992 .loc 1 219 7 is_stmt 0 view .LVU214 993 0042 002D cmp r5, #0 994 0044 E1D1 bne .L56 221:Core/Src/main.c **** }else{ 995 .loc 1 221 7 is_stmt 1 view .LVU215 996 0046 4FF0FF33 mov r3, #-1 997 004a 0122 movs r2, #1 998 004c 0DF10F01 add r1, sp, #15 999 0050 0B48 ldr r0, .L62+4 1000 0052 FFF7FEFF bl HAL_UART_Transmit 1001 .LVL87: 1002 0056 EAE7 b .L57 1003 .L60: 1004 .LBB13: 227:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)newline, 2, HAL_MAX_DELAY); 1005 .loc 1 227 9 view .LVU216 227:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)newline, 2, HAL_MAX_DELAY); 1006 .loc 1 227 14 is_stmt 0 view .LVU217 1007 0058 0B4B ldr r3, .L62+12 1008 005a 1B68 ldr r3, [r3] 1009 005c ADF80030 strh r3, [sp] @ movhi 1010 0060 1B0C lsrs r3, r3, #16 1011 0062 8DF80230 strb r3, [sp, #2] 228:Core/Src/main.c **** } 1012 .loc 1 228 9 is_stmt 1 view .LVU218 ARM GAS /tmp/ccwcoXyi.s page 29 1013 0066 4FF0FF33 mov r3, #-1 1014 006a 0222 movs r2, #2 1015 006c 6946 mov r1, sp 1016 006e 0448 ldr r0, .L62+4 1017 0070 FFF7FEFF bl HAL_UART_Transmit 1018 .LVL88: 1019 0074 DBE7 b .L57 1020 .L61: 228:Core/Src/main.c **** } 1021 .loc 1 228 9 is_stmt 0 view .LVU219 1022 .LBE13: 1023 .LBE12: 232:Core/Src/main.c **** 1024 .loc 1 232 1 view .LVU220 1025 0076 05B0 add sp, sp, #20 1026 .LCFI23: 1027 .cfi_def_cfa_offset 12 1028 @ sp needed 1029 0078 30BD pop {r4, r5, pc} 1030 .LVL89: 1031 .L63: 232:Core/Src/main.c **** 1032 .loc 1 232 1 view .LVU221 1033 007a 00BF .align 2 1034 .L62: 1035 007c 00000000 .word .LC2 1036 0080 00000000 .word .LANCHOR1 1037 0084 FEFF0700 .word 524286 1038 0088 08000000 .word .LC3 1039 .cfi_endproc 1040 .LFE145: 1042 .section .text.Address_Pins_Init,"ax",%progbits 1043 .align 1 1044 .global Address_Pins_Init 1045 .syntax unified 1046 .thumb 1047 .thumb_func 1048 .fpu fpv4-sp-d16 1050 Address_Pins_Init: 1051 .LFB152: 349:Core/Src/main.c **** GPIO_InitTypeDef GPIOC_InitStruct = {0}; 1052 .loc 1 349 29 is_stmt 1 view -0 1053 .cfi_startproc 1054 @ args = 0, pretend = 0, frame = 40 1055 @ frame_needed = 0, uses_anonymous_args = 0 1056 0000 70B5 push {r4, r5, r6, lr} 1057 .LCFI24: 1058 .cfi_def_cfa_offset 16 1059 .cfi_offset 4, -16 1060 .cfi_offset 5, -12 1061 .cfi_offset 6, -8 1062 .cfi_offset 14, -4 1063 0002 8AB0 sub sp, sp, #40 1064 .LCFI25: 1065 .cfi_def_cfa_offset 56 350:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs 1066 .loc 1 350 3 view .LVU223 ARM GAS /tmp/ccwcoXyi.s page 30 350:Core/Src/main.c **** // Configure PC0..PC15 as push-pull outputs 1067 .loc 1 350 20 is_stmt 0 view .LVU224 1068 0004 0024 movs r4, #0 1069 0006 0594 str r4, [sp, #20] 1070 0008 0694 str r4, [sp, #24] 1071 000a 0794 str r4, [sp, #28] 1072 000c 0894 str r4, [sp, #32] 1073 000e 0994 str r4, [sp, #36] 352:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 1074 .loc 1 352 3 is_stmt 1 view .LVU225 352:Core/Src/main.c **** GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7 | 1075 .loc 1 352 24 is_stmt 0 view .LVU226 1076 0010 4FF6FF73 movw r3, #65535 1077 0014 0593 str r3, [sp, #20] 356:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1078 .loc 1 356 3 is_stmt 1 view .LVU227 356:Core/Src/main.c **** GPIOC_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1079 .loc 1 356 25 is_stmt 0 view .LVU228 1080 0016 0126 movs r6, #1 1081 0018 0696 str r6, [sp, #24] 357:Core/Src/main.c **** GPIOC_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 1082 .loc 1 357 3 is_stmt 1 view .LVU229 358:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 1083 .loc 1 358 3 view .LVU230 358:Core/Src/main.c **** HAL_GPIO_Init(GPIOC, &GPIOC_InitStruct); 1084 .loc 1 358 26 is_stmt 0 view .LVU231 1085 001a 0225 movs r5, #2 1086 001c 0895 str r5, [sp, #32] 359:Core/Src/main.c **** 1087 .loc 1 359 3 is_stmt 1 view .LVU232 1088 001e 05A9 add r1, sp, #20 1089 0020 0848 ldr r0, .L66 1090 0022 FFF7FEFF bl HAL_GPIO_Init 1091 .LVL90: 362:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 1092 .loc 1 362 3 view .LVU233 362:Core/Src/main.c **** // Configure PB0..PB2 as push-pull outputs 1093 .loc 1 362 20 is_stmt 0 view .LVU234 1094 0026 0094 str r4, [sp] 1095 0028 0194 str r4, [sp, #4] 1096 002a 0294 str r4, [sp, #8] 1097 002c 0394 str r4, [sp, #12] 1098 002e 0494 str r4, [sp, #16] 364:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 1099 .loc 1 364 3 is_stmt 1 view .LVU235 364:Core/Src/main.c **** GPIOB_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 1100 .loc 1 364 24 is_stmt 0 view .LVU236 1101 0030 1F23 movs r3, #31 1102 0032 0093 str r3, [sp] 365:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1103 .loc 1 365 3 is_stmt 1 view .LVU237 365:Core/Src/main.c **** GPIOB_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1104 .loc 1 365 25 is_stmt 0 view .LVU238 1105 0034 0196 str r6, [sp, #4] 366:Core/Src/main.c **** GPIOB_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 1106 .loc 1 366 3 is_stmt 1 view .LVU239 367:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); ARM GAS /tmp/ccwcoXyi.s page 31 1107 .loc 1 367 3 view .LVU240 367:Core/Src/main.c **** HAL_GPIO_Init(GPIOB, &GPIOB_InitStruct); 1108 .loc 1 367 26 is_stmt 0 view .LVU241 1109 0036 0395 str r5, [sp, #12] 368:Core/Src/main.c **** } 1110 .loc 1 368 3 is_stmt 1 view .LVU242 1111 0038 6946 mov r1, sp 1112 003a 0348 ldr r0, .L66+4 1113 003c FFF7FEFF bl HAL_GPIO_Init 1114 .LVL91: 369:Core/Src/main.c **** 1115 .loc 1 369 1 is_stmt 0 view .LVU243 1116 0040 0AB0 add sp, sp, #40 1117 .LCFI26: 1118 .cfi_def_cfa_offset 16 1119 @ sp needed 1120 0042 70BD pop {r4, r5, r6, pc} 1121 .L67: 1122 .align 2 1123 .L66: 1124 0044 00080240 .word 1073874944 1125 0048 00040240 .word 1073873920 1126 .cfi_endproc 1127 .LFE152: 1129 .section .text.Command_Pins_Init,"ax",%progbits 1130 .align 1 1131 .global Command_Pins_Init 1132 .syntax unified 1133 .thumb 1134 .thumb_func 1135 .fpu fpv4-sp-d16 1137 Command_Pins_Init: 1138 .LFB153: 371:Core/Src/main.c **** // PA8-10 as outputs pins 1139 .loc 1 371 29 is_stmt 1 view -0 1140 .cfi_startproc 1141 @ args = 0, pretend = 0, frame = 24 1142 @ frame_needed = 0, uses_anonymous_args = 0 1143 0000 00B5 push {lr} 1144 .LCFI27: 1145 .cfi_def_cfa_offset 4 1146 .cfi_offset 14, -4 1147 0002 87B0 sub sp, sp, #28 1148 .LCFI28: 1149 .cfi_def_cfa_offset 32 373:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; 1150 .loc 1 373 3 view .LVU245 373:Core/Src/main.c **** GPIOA_InitStruct.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10; 1151 .loc 1 373 20 is_stmt 0 view .LVU246 1152 0004 0023 movs r3, #0 1153 0006 0193 str r3, [sp, #4] 1154 0008 0293 str r3, [sp, #8] 1155 000a 0393 str r3, [sp, #12] 1156 000c 0493 str r3, [sp, #16] 1157 000e 0593 str r3, [sp, #20] 374:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 1158 .loc 1 374 3 is_stmt 1 view .LVU247 ARM GAS /tmp/ccwcoXyi.s page 32 374:Core/Src/main.c **** GPIOA_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; // Push-pull output 1159 .loc 1 374 24 is_stmt 0 view .LVU248 1160 0010 4FF4E063 mov r3, #1792 1161 0014 0193 str r3, [sp, #4] 375:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1162 .loc 1 375 3 is_stmt 1 view .LVU249 375:Core/Src/main.c **** GPIOA_InitStruct.Pull = GPIO_NOPULL; // No pull-up/down 1163 .loc 1 375 25 is_stmt 0 view .LVU250 1164 0016 0123 movs r3, #1 1165 0018 0293 str r3, [sp, #8] 376:Core/Src/main.c **** GPIOA_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; // Fast switching 1166 .loc 1 376 3 is_stmt 1 view .LVU251 377:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 1167 .loc 1 377 3 view .LVU252 377:Core/Src/main.c **** HAL_GPIO_Init(GPIOA, &GPIOA_InitStruct); 1168 .loc 1 377 26 is_stmt 0 view .LVU253 1169 001a 0223 movs r3, #2 1170 001c 0493 str r3, [sp, #16] 378:Core/Src/main.c **** } 1171 .loc 1 378 3 is_stmt 1 view .LVU254 1172 001e 01A9 add r1, sp, #4 1173 0020 0248 ldr r0, .L70 1174 0022 FFF7FEFF bl HAL_GPIO_Init 1175 .LVL92: 379:Core/Src/main.c **** 1176 .loc 1 379 1 is_stmt 0 view .LVU255 1177 0026 07B0 add sp, sp, #28 1178 .LCFI29: 1179 .cfi_def_cfa_offset 4 1180 @ sp needed 1181 0028 5DF804FB ldr pc, [sp], #4 1182 .L71: 1183 .align 2 1184 .L70: 1185 002c 00000240 .word 1073872896 1186 .cfi_endproc 1187 .LFE153: 1189 .section .text.debug_print,"ax",%progbits 1190 .align 1 1191 .global debug_print 1192 .syntax unified 1193 .thumb 1194 .thumb_func 1195 .fpu fpv4-sp-d16 1197 debug_print: 1198 .LVL93: 1199 .LFB154: 381:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 1200 .loc 1 381 35 is_stmt 1 view -0 1201 .cfi_startproc 1202 @ args = 0, pretend = 0, frame = 0 1203 @ frame_needed = 0, uses_anonymous_args = 0 381:Core/Src/main.c **** HAL_UART_Transmit(&huart2, (uint8_t*)msg, strlen(msg), HAL_MAX_DELAY); 1204 .loc 1 381 35 is_stmt 0 view .LVU257 1205 0000 10B5 push {r4, lr} 1206 .LCFI30: 1207 .cfi_def_cfa_offset 8 ARM GAS /tmp/ccwcoXyi.s page 33 1208 .cfi_offset 4, -8 1209 .cfi_offset 14, -4 1210 0002 0446 mov r4, r0 382:Core/Src/main.c **** } 1211 .loc 1 382 3 is_stmt 1 view .LVU258 382:Core/Src/main.c **** } 1212 .loc 1 382 45 is_stmt 0 view .LVU259 1213 0004 FFF7FEFF bl strlen 1214 .LVL94: 382:Core/Src/main.c **** } 1215 .loc 1 382 3 view .LVU260 1216 0008 4FF0FF33 mov r3, #-1 1217 000c 82B2 uxth r2, r0 1218 000e 2146 mov r1, r4 1219 0010 0148 ldr r0, .L74 1220 0012 FFF7FEFF bl HAL_UART_Transmit 1221 .LVL95: 383:Core/Src/main.c **** 1222 .loc 1 383 1 view .LVU261 1223 0016 10BD pop {r4, pc} 1224 .LVL96: 1225 .L75: 383:Core/Src/main.c **** 1226 .loc 1 383 1 view .LVU262 1227 .align 2 1228 .L74: 1229 0018 00000000 .word .LANCHOR1 1230 .cfi_endproc 1231 .LFE154: 1233 .section .rodata.Flash_From_UART.str1.4,"aMS",%progbits,1 1234 .align 2 1235 .LC4: 1236 0000 57616974 .ascii "Waiting for file to flash...\015\012\000" 1236 696E6720 1236 666F7220 1236 66696C65 1236 20746F20 1237 001f 00 .align 2 1238 .LC5: 1239 0020 66696E69 .ascii "finished\015\012\000" 1239 73686564 1239 0D0A00 1240 .section .text.Flash_From_UART,"ax",%progbits 1241 .align 1 1242 .global Flash_From_UART 1243 .syntax unified 1244 .thumb 1245 .thumb_func 1246 .fpu fpv4-sp-d16 1248 Flash_From_UART: 1249 .LFB148: 253:Core/Src/main.c **** debug_print("Waiting for file to flash...\r\n"); 1250 .loc 1 253 27 is_stmt 1 view -0 1251 .cfi_startproc 1252 @ args = 0, pretend = 0, frame = 8 1253 @ frame_needed = 0, uses_anonymous_args = 0 1254 0000 10B5 push {r4, lr} ARM GAS /tmp/ccwcoXyi.s page 34 1255 .LCFI31: 1256 .cfi_def_cfa_offset 8 1257 .cfi_offset 4, -8 1258 .cfi_offset 14, -4 1259 0002 82B0 sub sp, sp, #8 1260 .LCFI32: 1261 .cfi_def_cfa_offset 16 254:Core/Src/main.c **** uint8_t byte; 1262 .loc 1 254 3 view .LVU264 1263 0004 0C48 ldr r0, .L80 1264 0006 FFF7FEFF bl debug_print 1265 .LVL97: 255:Core/Src/main.c **** for(int i=0; i<8; i++){ 1266 .loc 1 255 3 view .LVU265 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1267 .loc 1 256 3 view .LVU266 1268 .LBB14: 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1269 .loc 1 256 7 view .LVU267 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1270 .loc 1 256 11 is_stmt 0 view .LVU268 1271 000a 0024 movs r4, #0 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1272 .loc 1 256 3 view .LVU269 1273 000c 0DE0 b .L77 1274 .LVL98: 1275 .L78: 257:Core/Src/main.c **** Chip_Program_Byte(i, (int)byte); 1276 .loc 1 257 5 is_stmt 1 discriminator 3 view .LVU270 1277 000e 4FF0FF33 mov r3, #-1 1278 0012 0122 movs r2, #1 1279 0014 0DF10701 add r1, sp, #7 1280 0018 0848 ldr r0, .L80+4 1281 001a FFF7FEFF bl HAL_UART_Receive 1282 .LVL99: 258:Core/Src/main.c **** } 1283 .loc 1 258 5 discriminator 3 view .LVU271 1284 001e 9DF80710 ldrb r1, [sp, #7] @ zero_extendqisi2 1285 0022 2046 mov r0, r4 1286 0024 FFF7FEFF bl Chip_Program_Byte 1287 .LVL100: 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1288 .loc 1 256 21 discriminator 3 view .LVU272 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1289 .loc 1 256 22 is_stmt 0 discriminator 3 view .LVU273 1290 0028 0134 adds r4, r4, #1 1291 .LVL101: 1292 .L77: 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1293 .loc 1 256 16 is_stmt 1 discriminator 1 view .LVU274 256:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1294 .loc 1 256 3 is_stmt 0 discriminator 1 view .LVU275 1295 002a 072C cmp r4, #7 1296 002c EFDD ble .L78 1297 .LBE14: 260:Core/Src/main.c **** } 1298 .loc 1 260 3 is_stmt 1 view .LVU276 ARM GAS /tmp/ccwcoXyi.s page 35 1299 002e 0448 ldr r0, .L80+8 1300 0030 FFF7FEFF bl debug_print 1301 .LVL102: 261:Core/Src/main.c **** 1302 .loc 1 261 1 is_stmt 0 view .LVU277 1303 0034 02B0 add sp, sp, #8 1304 .LCFI33: 1305 .cfi_def_cfa_offset 8 1306 @ sp needed 1307 0036 10BD pop {r4, pc} 1308 .LVL103: 1309 .L81: 261:Core/Src/main.c **** 1310 .loc 1 261 1 view .LVU278 1311 .align 2 1312 .L80: 1313 0038 00000000 .word .LC4 1314 003c 00000000 .word .LANCHOR1 1315 0040 20000000 .word .LC5 1316 .cfi_endproc 1317 .LFE148: 1319 .section .text.Error_Handler,"ax",%progbits 1320 .align 1 1321 .global Error_Handler 1322 .syntax unified 1323 .thumb 1324 .thumb_func 1325 .fpu fpv4-sp-d16 1327 Error_Handler: 1328 .LFB156: 414:Core/Src/main.c **** 415:Core/Src/main.c **** 416:Core/Src/main.c **** /** 417:Core/Src/main.c **** * @brief This function is executed in case of error occurrence. 418:Core/Src/main.c **** * @retval None 419:Core/Src/main.c **** */ 420:Core/Src/main.c **** void Error_Handler(void) 421:Core/Src/main.c **** { 1329 .loc 1 421 1 is_stmt 1 view -0 1330 .cfi_startproc 1331 @ Volatile: function does not return. 1332 @ args = 0, pretend = 0, frame = 0 1333 @ frame_needed = 0, uses_anonymous_args = 0 1334 @ link register save eliminated. 422:Core/Src/main.c **** /* USER CODE BEGIN Error_Handler_Debug */ 423:Core/Src/main.c **** /* User can add his own implementation to report the HAL error return state */ 424:Core/Src/main.c **** __disable_irq(); 1335 .loc 1 424 3 view .LVU280 1336 .LBB15: 1337 .LBI15: 1338 .file 2 "Drivers/CMSIS/Include/cmsis_gcc.h" 1:Drivers/CMSIS/Include/cmsis_gcc.h **** /**************************************************************************//** 2:Drivers/CMSIS/Include/cmsis_gcc.h **** * @file cmsis_gcc.h 3:Drivers/CMSIS/Include/cmsis_gcc.h **** * @brief CMSIS compiler GCC header file 4:Drivers/CMSIS/Include/cmsis_gcc.h **** * @version V5.4.1 5:Drivers/CMSIS/Include/cmsis_gcc.h **** * @date 27. May 2021 6:Drivers/CMSIS/Include/cmsis_gcc.h **** ******************************************************************************/ ARM GAS /tmp/ccwcoXyi.s page 36 7:Drivers/CMSIS/Include/cmsis_gcc.h **** /* 8:Drivers/CMSIS/Include/cmsis_gcc.h **** * Copyright (c) 2009-2021 Arm Limited. All rights reserved. 9:Drivers/CMSIS/Include/cmsis_gcc.h **** * 10:Drivers/CMSIS/Include/cmsis_gcc.h **** * SPDX-License-Identifier: Apache-2.0 11:Drivers/CMSIS/Include/cmsis_gcc.h **** * 12:Drivers/CMSIS/Include/cmsis_gcc.h **** * Licensed under the Apache License, Version 2.0 (the License); you may 13:Drivers/CMSIS/Include/cmsis_gcc.h **** * not use this file except in compliance with the License. 14:Drivers/CMSIS/Include/cmsis_gcc.h **** * You may obtain a copy of the License at 15:Drivers/CMSIS/Include/cmsis_gcc.h **** * 16:Drivers/CMSIS/Include/cmsis_gcc.h **** * www.apache.org/licenses/LICENSE-2.0 17:Drivers/CMSIS/Include/cmsis_gcc.h **** * 18:Drivers/CMSIS/Include/cmsis_gcc.h **** * Unless required by applicable law or agreed to in writing, software 19:Drivers/CMSIS/Include/cmsis_gcc.h **** * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20:Drivers/CMSIS/Include/cmsis_gcc.h **** * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21:Drivers/CMSIS/Include/cmsis_gcc.h **** * See the License for the specific language governing permissions and 22:Drivers/CMSIS/Include/cmsis_gcc.h **** * limitations under the License. 23:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 24:Drivers/CMSIS/Include/cmsis_gcc.h **** 25:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __CMSIS_GCC_H 26:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_H 27:Drivers/CMSIS/Include/cmsis_gcc.h **** 28:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ignore some GCC warnings */ 29:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 30:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wsign-conversion" 31:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wconversion" 32:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wunused-parameter" 33:Drivers/CMSIS/Include/cmsis_gcc.h **** 34:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Fallback for __has_builtin */ 35:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __has_builtin 36:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __has_builtin(x) (0) 37:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 38:Drivers/CMSIS/Include/cmsis_gcc.h **** 39:Drivers/CMSIS/Include/cmsis_gcc.h **** /* CMSIS compiler specific defines */ 40:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ASM 41:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ASM __asm 42:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 43:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INLINE 44:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INLINE inline 45:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 46:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_INLINE 47:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_INLINE static inline 48:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STATIC_FORCEINLINE 50:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline 51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __NO_RETURN 53:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NO_RETURN __attribute__((__noreturn__)) 54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __USED 56:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USED __attribute__((used)) 57:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 58:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __WEAK 59:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WEAK __attribute__((weak)) 60:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 61:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED 62:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED __attribute__((packed, aligned(1))) 63:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif ARM GAS /tmp/ccwcoXyi.s page 37 64:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_STRUCT 65:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) 66:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 67:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PACKED_UNION 68:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PACKED_UNION union __attribute__((packed, aligned(1))) 69:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 70:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32 /* deprecated */ 71:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 72:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 73:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 74:Drivers/CMSIS/Include/cmsis_gcc.h **** struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 75:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 76:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 77:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 78:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_WRITE 79:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 80:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 81:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 82:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 83:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 84:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))- 85:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 86:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT16_READ 87:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 88:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 89:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 90:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 91:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 92:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(add 93:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 94:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_WRITE 95:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 96:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 97:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 98:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 99:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 100:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))- 101:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 102:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __UNALIGNED_UINT32_READ 103:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic push 104:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wpacked" 105:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic ignored "-Wattributes" 106:Drivers/CMSIS/Include/cmsis_gcc.h **** __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 107:Drivers/CMSIS/Include/cmsis_gcc.h **** #pragma GCC diagnostic pop 108:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(add 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __ALIGNED 111:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __ALIGNED(x) __attribute__((aligned(x))) 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __RESTRICT 114:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __RESTRICT __restrict 115:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 116:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __COMPILER_BARRIER 117:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __COMPILER_BARRIER() __ASM volatile("":::"memory") 118:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 119:Drivers/CMSIS/Include/cmsis_gcc.h **** 120:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ######################### Startup and Lowlevel Init ######################## */ ARM GAS /tmp/ccwcoXyi.s page 38 121:Drivers/CMSIS/Include/cmsis_gcc.h **** 122:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __PROGRAM_START 123:Drivers/CMSIS/Include/cmsis_gcc.h **** 124:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 125:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Initializes data and bss sections 126:Drivers/CMSIS/Include/cmsis_gcc.h **** \details This default implementations initialized all data and additional bss 127:Drivers/CMSIS/Include/cmsis_gcc.h **** sections relying on .copy.table and .zero.table specified properly 128:Drivers/CMSIS/Include/cmsis_gcc.h **** in the used linker script. 129:Drivers/CMSIS/Include/cmsis_gcc.h **** 130:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 131:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) 132:Drivers/CMSIS/Include/cmsis_gcc.h **** { 133:Drivers/CMSIS/Include/cmsis_gcc.h **** extern void _start(void) __NO_RETURN; 134:Drivers/CMSIS/Include/cmsis_gcc.h **** 135:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 136:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t const* src; 137:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 138:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 139:Drivers/CMSIS/Include/cmsis_gcc.h **** } __copy_table_t; 140:Drivers/CMSIS/Include/cmsis_gcc.h **** 141:Drivers/CMSIS/Include/cmsis_gcc.h **** typedef struct { 142:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t* dest; 143:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t wlen; 144:Drivers/CMSIS/Include/cmsis_gcc.h **** } __zero_table_t; 145:Drivers/CMSIS/Include/cmsis_gcc.h **** 146:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_start__; 147:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __copy_table_t __copy_table_end__; 148:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_start__; 149:Drivers/CMSIS/Include/cmsis_gcc.h **** extern const __zero_table_t __zero_table_end__; 150:Drivers/CMSIS/Include/cmsis_gcc.h **** 151:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable 152:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 153:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = pTable->src[i]; 154:Drivers/CMSIS/Include/cmsis_gcc.h **** } 155:Drivers/CMSIS/Include/cmsis_gcc.h **** } 156:Drivers/CMSIS/Include/cmsis_gcc.h **** 157:Drivers/CMSIS/Include/cmsis_gcc.h **** for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable 158:Drivers/CMSIS/Include/cmsis_gcc.h **** for(uint32_t i=0u; iwlen; ++i) { 159:Drivers/CMSIS/Include/cmsis_gcc.h **** pTable->dest[i] = 0u; 160:Drivers/CMSIS/Include/cmsis_gcc.h **** } 161:Drivers/CMSIS/Include/cmsis_gcc.h **** } 162:Drivers/CMSIS/Include/cmsis_gcc.h **** 163:Drivers/CMSIS/Include/cmsis_gcc.h **** _start(); 164:Drivers/CMSIS/Include/cmsis_gcc.h **** } 165:Drivers/CMSIS/Include/cmsis_gcc.h **** 166:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __PROGRAM_START __cmsis_start 167:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 168:Drivers/CMSIS/Include/cmsis_gcc.h **** 169:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __INITIAL_SP 170:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __INITIAL_SP __StackTop 171:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 172:Drivers/CMSIS/Include/cmsis_gcc.h **** 173:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_LIMIT 174:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_LIMIT __StackLimit 175:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 176:Drivers/CMSIS/Include/cmsis_gcc.h **** 177:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE ARM GAS /tmp/ccwcoXyi.s page 39 178:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE __Vectors 179:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 180:Drivers/CMSIS/Include/cmsis_gcc.h **** 181:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __VECTOR_TABLE_ATTRIBUTE 182:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) 183:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 184:Drivers/CMSIS/Include/cmsis_gcc.h **** 185:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) 186:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __STACK_SEAL 187:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __STACK_SEAL __StackSeal 188:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 189:Drivers/CMSIS/Include/cmsis_gcc.h **** 190:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_SIZE 191:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_SIZE 8U 192:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 193:Drivers/CMSIS/Include/cmsis_gcc.h **** 194:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef __TZ_STACK_SEAL_VALUE 195:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL 196:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 197:Drivers/CMSIS/Include/cmsis_gcc.h **** 198:Drivers/CMSIS/Include/cmsis_gcc.h **** 199:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { 200:Drivers/CMSIS/Include/cmsis_gcc.h **** *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; 201:Drivers/CMSIS/Include/cmsis_gcc.h **** } 202:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 203:Drivers/CMSIS/Include/cmsis_gcc.h **** 204:Drivers/CMSIS/Include/cmsis_gcc.h **** 205:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################## Core Instruction Access ######################### */ 206:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface 207:Drivers/CMSIS/Include/cmsis_gcc.h **** Access to dedicated instructions 208:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 209:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 210:Drivers/CMSIS/Include/cmsis_gcc.h **** 211:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Define macros for porting to both thumb1 and thumb2. 212:Drivers/CMSIS/Include/cmsis_gcc.h **** * For thumb1, use low register (r0-r7), specified by constraint "l" 213:Drivers/CMSIS/Include/cmsis_gcc.h **** * Otherwise, use general registers, specified by constraint "r" */ 214:Drivers/CMSIS/Include/cmsis_gcc.h **** #if defined (__thumb__) && !defined (__thumb2__) 215:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=l" (r) 216:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+l" (r) 217:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "l" (r) 218:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 219:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_OUT_REG(r) "=r" (r) 220:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_RW_REG(r) "+r" (r) 221:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __CMSIS_GCC_USE_REG(r) "r" (r) 222:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 223:Drivers/CMSIS/Include/cmsis_gcc.h **** 224:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 225:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief No Operation 226:Drivers/CMSIS/Include/cmsis_gcc.h **** \details No Operation does nothing. This instruction can be used for code alignment purposes. 227:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 228:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __NOP() __ASM volatile ("nop") 229:Drivers/CMSIS/Include/cmsis_gcc.h **** 230:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 231:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Interrupt 232:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Interrupt is a hint instruction that suspends execution until one of a number o 233:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 234:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFI() __ASM volatile ("wfi":::"memory") ARM GAS /tmp/ccwcoXyi.s page 40 235:Drivers/CMSIS/Include/cmsis_gcc.h **** 236:Drivers/CMSIS/Include/cmsis_gcc.h **** 237:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 238:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Wait For Event 239:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Wait For Event is a hint instruction that permits the processor to enter 240:Drivers/CMSIS/Include/cmsis_gcc.h **** a low-power state until one of a number of events occurs. 241:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 242:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE() __ASM volatile ("wfe":::"memory") 243:Drivers/CMSIS/Include/cmsis_gcc.h **** 244:Drivers/CMSIS/Include/cmsis_gcc.h **** 245:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 246:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Send Event 247:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. 248:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 249:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SEV() __ASM volatile ("sev") 250:Drivers/CMSIS/Include/cmsis_gcc.h **** 251:Drivers/CMSIS/Include/cmsis_gcc.h **** 252:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 253:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Instruction Synchronization Barrier 254:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Instruction Synchronization Barrier flushes the pipeline in the processor, 255:Drivers/CMSIS/Include/cmsis_gcc.h **** so that all instructions following the ISB are fetched from cache or memory, 256:Drivers/CMSIS/Include/cmsis_gcc.h **** after the instruction has been completed. 257:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 258:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __ISB(void) 259:Drivers/CMSIS/Include/cmsis_gcc.h **** { 260:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("isb 0xF":::"memory"); 261:Drivers/CMSIS/Include/cmsis_gcc.h **** } 262:Drivers/CMSIS/Include/cmsis_gcc.h **** 263:Drivers/CMSIS/Include/cmsis_gcc.h **** 264:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 265:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Synchronization Barrier 266:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Acts as a special kind of Data Memory Barrier. 267:Drivers/CMSIS/Include/cmsis_gcc.h **** It completes when all explicit memory accesses before this instruction complete. 268:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 269:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DSB(void) 270:Drivers/CMSIS/Include/cmsis_gcc.h **** { 271:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dsb 0xF":::"memory"); 272:Drivers/CMSIS/Include/cmsis_gcc.h **** } 273:Drivers/CMSIS/Include/cmsis_gcc.h **** 274:Drivers/CMSIS/Include/cmsis_gcc.h **** 275:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 276:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Data Memory Barrier 277:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Ensures the apparent order of the explicit memory operations before 278:Drivers/CMSIS/Include/cmsis_gcc.h **** and after the instruction, without ensuring their completion. 279:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 280:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __DMB(void) 281:Drivers/CMSIS/Include/cmsis_gcc.h **** { 282:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("dmb 0xF":::"memory"); 283:Drivers/CMSIS/Include/cmsis_gcc.h **** } 284:Drivers/CMSIS/Include/cmsis_gcc.h **** 285:Drivers/CMSIS/Include/cmsis_gcc.h **** 286:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 287:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (32 bit) 288:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x785 289:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 290:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 291:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccwcoXyi.s page 41 292:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV(uint32_t value) 293:Drivers/CMSIS/Include/cmsis_gcc.h **** { 294:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) 295:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_bswap32(value); 296:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 297:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 298:Drivers/CMSIS/Include/cmsis_gcc.h **** 299:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 300:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 301:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 302:Drivers/CMSIS/Include/cmsis_gcc.h **** } 303:Drivers/CMSIS/Include/cmsis_gcc.h **** 304:Drivers/CMSIS/Include/cmsis_gcc.h **** 305:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 306:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 307:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 308:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 309:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 310:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 311:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) 312:Drivers/CMSIS/Include/cmsis_gcc.h **** { 313:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 314:Drivers/CMSIS/Include/cmsis_gcc.h **** 315:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 316:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 317:Drivers/CMSIS/Include/cmsis_gcc.h **** } 318:Drivers/CMSIS/Include/cmsis_gcc.h **** 319:Drivers/CMSIS/Include/cmsis_gcc.h **** 320:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 321:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse byte order (16 bit) 322:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For exam 323:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 324:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 325:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 326:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int16_t __REVSH(int16_t value) 327:Drivers/CMSIS/Include/cmsis_gcc.h **** { 328:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 329:Drivers/CMSIS/Include/cmsis_gcc.h **** return (int16_t)__builtin_bswap16(value); 330:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 331:Drivers/CMSIS/Include/cmsis_gcc.h **** int16_t result; 332:Drivers/CMSIS/Include/cmsis_gcc.h **** 333:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 334:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 335:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 336:Drivers/CMSIS/Include/cmsis_gcc.h **** } 337:Drivers/CMSIS/Include/cmsis_gcc.h **** 338:Drivers/CMSIS/Include/cmsis_gcc.h **** 339:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 340:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right in unsigned value (32 bit) 341:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Rotate Right (immediate) provides the value of the contents of a register rotated by a v 342:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op1 Value to rotate 343:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] op2 Number of Bits to rotate 344:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 345:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 346:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) 347:Drivers/CMSIS/Include/cmsis_gcc.h **** { 348:Drivers/CMSIS/Include/cmsis_gcc.h **** op2 %= 32U; ARM GAS /tmp/ccwcoXyi.s page 42 349:Drivers/CMSIS/Include/cmsis_gcc.h **** if (op2 == 0U) 350:Drivers/CMSIS/Include/cmsis_gcc.h **** { 351:Drivers/CMSIS/Include/cmsis_gcc.h **** return op1; 352:Drivers/CMSIS/Include/cmsis_gcc.h **** } 353:Drivers/CMSIS/Include/cmsis_gcc.h **** return (op1 >> op2) | (op1 << (32U - op2)); 354:Drivers/CMSIS/Include/cmsis_gcc.h **** } 355:Drivers/CMSIS/Include/cmsis_gcc.h **** 356:Drivers/CMSIS/Include/cmsis_gcc.h **** 357:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 358:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Breakpoint 359:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Causes the processor to enter Debug state. 360:Drivers/CMSIS/Include/cmsis_gcc.h **** Debug tools can use this to investigate system state when the instruction at a particula 361:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value is ignored by the processor. 362:Drivers/CMSIS/Include/cmsis_gcc.h **** If required, a debugger can use it to store additional information about the break 363:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 364:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __BKPT(value) __ASM volatile ("bkpt "#value) 365:Drivers/CMSIS/Include/cmsis_gcc.h **** 366:Drivers/CMSIS/Include/cmsis_gcc.h **** 367:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 368:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Reverse bit order of value 369:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Reverses the bit order of the given value. 370:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to reverse 371:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Reversed value 372:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 373:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) 374:Drivers/CMSIS/Include/cmsis_gcc.h **** { 375:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 376:Drivers/CMSIS/Include/cmsis_gcc.h **** 377:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 378:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 379:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 380:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); 381:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 382:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ 383:Drivers/CMSIS/Include/cmsis_gcc.h **** 384:Drivers/CMSIS/Include/cmsis_gcc.h **** result = value; /* r will be reversed bits of v; first get LSB of v */ 385:Drivers/CMSIS/Include/cmsis_gcc.h **** for (value >>= 1U; value != 0U; value >>= 1U) 386:Drivers/CMSIS/Include/cmsis_gcc.h **** { 387:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= 1U; 388:Drivers/CMSIS/Include/cmsis_gcc.h **** result |= value & 1U; 389:Drivers/CMSIS/Include/cmsis_gcc.h **** s--; 390:Drivers/CMSIS/Include/cmsis_gcc.h **** } 391:Drivers/CMSIS/Include/cmsis_gcc.h **** result <<= s; /* shift when v's highest bits are zero */ 392:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 393:Drivers/CMSIS/Include/cmsis_gcc.h **** return result; 394:Drivers/CMSIS/Include/cmsis_gcc.h **** } 395:Drivers/CMSIS/Include/cmsis_gcc.h **** 396:Drivers/CMSIS/Include/cmsis_gcc.h **** 397:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 398:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Count leading zeros 399:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Counts the number of leading zeros of a data value. 400:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to count the leading zeros 401:Drivers/CMSIS/Include/cmsis_gcc.h **** \return number of leading zeros in value 402:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 403:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) 404:Drivers/CMSIS/Include/cmsis_gcc.h **** { 405:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Even though __builtin_clz produces a CLZ instruction on ARM, formally ARM GAS /tmp/ccwcoXyi.s page 43 406:Drivers/CMSIS/Include/cmsis_gcc.h **** __builtin_clz(0) is undefined behaviour, so handle this case specially. 407:Drivers/CMSIS/Include/cmsis_gcc.h **** This guarantees ARM-compatible results if happening to compile on a non-ARM 408:Drivers/CMSIS/Include/cmsis_gcc.h **** target, and ensures the compiler doesn't decide to activate any 409:Drivers/CMSIS/Include/cmsis_gcc.h **** optimisations using the logic "value was passed to __builtin_clz, so it 410:Drivers/CMSIS/Include/cmsis_gcc.h **** is non-zero". 411:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a 412:Drivers/CMSIS/Include/cmsis_gcc.h **** single CLZ instruction. 413:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 414:Drivers/CMSIS/Include/cmsis_gcc.h **** if (value == 0U) 415:Drivers/CMSIS/Include/cmsis_gcc.h **** { 416:Drivers/CMSIS/Include/cmsis_gcc.h **** return 32U; 417:Drivers/CMSIS/Include/cmsis_gcc.h **** } 418:Drivers/CMSIS/Include/cmsis_gcc.h **** return __builtin_clz(value); 419:Drivers/CMSIS/Include/cmsis_gcc.h **** } 420:Drivers/CMSIS/Include/cmsis_gcc.h **** 421:Drivers/CMSIS/Include/cmsis_gcc.h **** 422:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 423:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 424:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 425:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 426:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 427:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (8 bit) 428:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 8 bit value. 429:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 430:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 431:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 432:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) 433:Drivers/CMSIS/Include/cmsis_gcc.h **** { 434:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 435:Drivers/CMSIS/Include/cmsis_gcc.h **** 436:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 437:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); 438:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 439:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 440:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 441:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 442:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 443:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 444:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 445:Drivers/CMSIS/Include/cmsis_gcc.h **** } 446:Drivers/CMSIS/Include/cmsis_gcc.h **** 447:Drivers/CMSIS/Include/cmsis_gcc.h **** 448:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 449:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (16 bit) 450:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 16 bit values. 451:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 452:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 453:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 454:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) 455:Drivers/CMSIS/Include/cmsis_gcc.h **** { 456:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 457:Drivers/CMSIS/Include/cmsis_gcc.h **** 458:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 459:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); 460:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 461:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 462:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. ARM GAS /tmp/ccwcoXyi.s page 44 463:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 464:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); 465:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 466:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 467:Drivers/CMSIS/Include/cmsis_gcc.h **** } 468:Drivers/CMSIS/Include/cmsis_gcc.h **** 469:Drivers/CMSIS/Include/cmsis_gcc.h **** 470:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 471:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDR Exclusive (32 bit) 472:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive LDR instruction for 32 bit values. 473:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 474:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 475:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 476:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) 477:Drivers/CMSIS/Include/cmsis_gcc.h **** { 478:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 479:Drivers/CMSIS/Include/cmsis_gcc.h **** 480:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); 481:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 482:Drivers/CMSIS/Include/cmsis_gcc.h **** } 483:Drivers/CMSIS/Include/cmsis_gcc.h **** 484:Drivers/CMSIS/Include/cmsis_gcc.h **** 485:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 486:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (8 bit) 487:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 8 bit values. 488:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 489:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 490:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 491:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 492:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 493:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) 494:Drivers/CMSIS/Include/cmsis_gcc.h **** { 495:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 496:Drivers/CMSIS/Include/cmsis_gcc.h **** 497:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 498:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 499:Drivers/CMSIS/Include/cmsis_gcc.h **** } 500:Drivers/CMSIS/Include/cmsis_gcc.h **** 501:Drivers/CMSIS/Include/cmsis_gcc.h **** 502:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 503:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (16 bit) 504:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 16 bit values. 505:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 506:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 507:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 508:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 509:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 510:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) 511:Drivers/CMSIS/Include/cmsis_gcc.h **** { 512:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 513:Drivers/CMSIS/Include/cmsis_gcc.h **** 514:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); 515:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 516:Drivers/CMSIS/Include/cmsis_gcc.h **** } 517:Drivers/CMSIS/Include/cmsis_gcc.h **** 518:Drivers/CMSIS/Include/cmsis_gcc.h **** 519:Drivers/CMSIS/Include/cmsis_gcc.h **** /** ARM GAS /tmp/ccwcoXyi.s page 45 520:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STR Exclusive (32 bit) 521:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a exclusive STR instruction for 32 bit values. 522:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 523:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 524:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 525:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 526:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 527:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) 528:Drivers/CMSIS/Include/cmsis_gcc.h **** { 529:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 530:Drivers/CMSIS/Include/cmsis_gcc.h **** 531:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); 532:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 533:Drivers/CMSIS/Include/cmsis_gcc.h **** } 534:Drivers/CMSIS/Include/cmsis_gcc.h **** 535:Drivers/CMSIS/Include/cmsis_gcc.h **** 536:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 537:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Remove the exclusive lock 538:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Removes the exclusive lock which is created by LDREX. 539:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 540:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __CLREX(void) 541:Drivers/CMSIS/Include/cmsis_gcc.h **** { 542:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("clrex" ::: "memory"); 543:Drivers/CMSIS/Include/cmsis_gcc.h **** } 544:Drivers/CMSIS/Include/cmsis_gcc.h **** 545:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 546:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 547:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 548:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 549:Drivers/CMSIS/Include/cmsis_gcc.h **** 550:Drivers/CMSIS/Include/cmsis_gcc.h **** 551:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 552:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 553:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) 554:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 555:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 556:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 557:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 558:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (1..32) 559:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 560:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 561:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __SSAT(ARG1, ARG2) \ 562:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 563:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 564:Drivers/CMSIS/Include/cmsis_gcc.h **** int32_t __RES, __ARG1 = (ARG1); \ 565:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 566:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 567:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 568:Drivers/CMSIS/Include/cmsis_gcc.h **** 569:Drivers/CMSIS/Include/cmsis_gcc.h **** 570:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 571:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 572:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 573:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG1 Value to be saturated 574:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ARG2 Bit position to saturate to (0..31) 575:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 576:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccwcoXyi.s page 46 577:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __USAT(ARG1, ARG2) \ 578:Drivers/CMSIS/Include/cmsis_gcc.h **** __extension__ \ 579:Drivers/CMSIS/Include/cmsis_gcc.h **** ({ \ 580:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t __RES, __ARG1 = (ARG1); \ 581:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ 582:Drivers/CMSIS/Include/cmsis_gcc.h **** __RES; \ 583:Drivers/CMSIS/Include/cmsis_gcc.h **** }) 584:Drivers/CMSIS/Include/cmsis_gcc.h **** 585:Drivers/CMSIS/Include/cmsis_gcc.h **** 586:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 587:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Rotate Right with Extend (32 bit) 588:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Moves each bit of a bitstring right by one bit. 589:Drivers/CMSIS/Include/cmsis_gcc.h **** The carry input is shifted in at the left end of the bitstring. 590:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to rotate 591:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Rotated value 592:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 593:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) 594:Drivers/CMSIS/Include/cmsis_gcc.h **** { 595:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 596:Drivers/CMSIS/Include/cmsis_gcc.h **** 597:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); 598:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 599:Drivers/CMSIS/Include/cmsis_gcc.h **** } 600:Drivers/CMSIS/Include/cmsis_gcc.h **** 601:Drivers/CMSIS/Include/cmsis_gcc.h **** 602:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 603:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (8 bit) 604:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 8 bit value. 605:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 606:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 607:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 608:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) 609:Drivers/CMSIS/Include/cmsis_gcc.h **** { 610:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 611:Drivers/CMSIS/Include/cmsis_gcc.h **** 612:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 613:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); 614:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 615:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 616:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 617:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 618:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 620:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); /* Add explicit type cast here */ 621:Drivers/CMSIS/Include/cmsis_gcc.h **** } 622:Drivers/CMSIS/Include/cmsis_gcc.h **** 623:Drivers/CMSIS/Include/cmsis_gcc.h **** 624:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 625:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (16 bit) 626:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 16 bit values. 627:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 628:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 629:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 630:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) 631:Drivers/CMSIS/Include/cmsis_gcc.h **** { 632:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 633:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccwcoXyi.s page 47 634:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) 635:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); 636:Drivers/CMSIS/Include/cmsis_gcc.h **** #else 637:Drivers/CMSIS/Include/cmsis_gcc.h **** /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not 638:Drivers/CMSIS/Include/cmsis_gcc.h **** accepted by assembler. So has to use following less efficient pattern. 639:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 640:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); 641:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif 642:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); /* Add explicit type cast here */ 643:Drivers/CMSIS/Include/cmsis_gcc.h **** } 644:Drivers/CMSIS/Include/cmsis_gcc.h **** 645:Drivers/CMSIS/Include/cmsis_gcc.h **** 646:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 647:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief LDRT Unprivileged (32 bit) 648:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged LDRT instruction for 32 bit values. 649:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 650:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 651:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 652:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) 653:Drivers/CMSIS/Include/cmsis_gcc.h **** { 654:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 655:Drivers/CMSIS/Include/cmsis_gcc.h **** 656:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); 657:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 658:Drivers/CMSIS/Include/cmsis_gcc.h **** } 659:Drivers/CMSIS/Include/cmsis_gcc.h **** 660:Drivers/CMSIS/Include/cmsis_gcc.h **** 661:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 662:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (8 bit) 663:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 8 bit values. 664:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 665:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 666:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 667:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) 668:Drivers/CMSIS/Include/cmsis_gcc.h **** { 669:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 670:Drivers/CMSIS/Include/cmsis_gcc.h **** } 671:Drivers/CMSIS/Include/cmsis_gcc.h **** 672:Drivers/CMSIS/Include/cmsis_gcc.h **** 673:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 674:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (16 bit) 675:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 16 bit values. 676:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 677:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 678:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) 680:Drivers/CMSIS/Include/cmsis_gcc.h **** { 681:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); 682:Drivers/CMSIS/Include/cmsis_gcc.h **** } 683:Drivers/CMSIS/Include/cmsis_gcc.h **** 684:Drivers/CMSIS/Include/cmsis_gcc.h **** 685:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 686:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief STRT Unprivileged (32 bit) 687:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a Unprivileged STRT instruction for 32 bit values. 688:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 689:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 690:Drivers/CMSIS/Include/cmsis_gcc.h **** */ ARM GAS /tmp/ccwcoXyi.s page 48 691:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) 692:Drivers/CMSIS/Include/cmsis_gcc.h **** { 693:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); 694:Drivers/CMSIS/Include/cmsis_gcc.h **** } 695:Drivers/CMSIS/Include/cmsis_gcc.h **** 696:Drivers/CMSIS/Include/cmsis_gcc.h **** #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 697:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 698:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 699:Drivers/CMSIS/Include/cmsis_gcc.h **** 700:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 701:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Signed Saturate 702:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates a signed value. 703:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 704:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (1..32) 705:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 706:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 707:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) 708:Drivers/CMSIS/Include/cmsis_gcc.h **** { 709:Drivers/CMSIS/Include/cmsis_gcc.h **** if ((sat >= 1U) && (sat <= 32U)) 710:Drivers/CMSIS/Include/cmsis_gcc.h **** { 711:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); 712:Drivers/CMSIS/Include/cmsis_gcc.h **** const int32_t min = -1 - max ; 713:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > max) 714:Drivers/CMSIS/Include/cmsis_gcc.h **** { 715:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 716:Drivers/CMSIS/Include/cmsis_gcc.h **** } 717:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < min) 718:Drivers/CMSIS/Include/cmsis_gcc.h **** { 719:Drivers/CMSIS/Include/cmsis_gcc.h **** return min; 720:Drivers/CMSIS/Include/cmsis_gcc.h **** } 721:Drivers/CMSIS/Include/cmsis_gcc.h **** } 722:Drivers/CMSIS/Include/cmsis_gcc.h **** return val; 723:Drivers/CMSIS/Include/cmsis_gcc.h **** } 724:Drivers/CMSIS/Include/cmsis_gcc.h **** 725:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 726:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Unsigned Saturate 727:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Saturates an unsigned value. 728:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to be saturated 729:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] sat Bit position to saturate to (0..31) 730:Drivers/CMSIS/Include/cmsis_gcc.h **** \return Saturated value 731:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 732:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) 733:Drivers/CMSIS/Include/cmsis_gcc.h **** { 734:Drivers/CMSIS/Include/cmsis_gcc.h **** if (sat <= 31U) 735:Drivers/CMSIS/Include/cmsis_gcc.h **** { 736:Drivers/CMSIS/Include/cmsis_gcc.h **** const uint32_t max = ((1U << sat) - 1U); 737:Drivers/CMSIS/Include/cmsis_gcc.h **** if (val > (int32_t)max) 738:Drivers/CMSIS/Include/cmsis_gcc.h **** { 739:Drivers/CMSIS/Include/cmsis_gcc.h **** return max; 740:Drivers/CMSIS/Include/cmsis_gcc.h **** } 741:Drivers/CMSIS/Include/cmsis_gcc.h **** else if (val < 0) 742:Drivers/CMSIS/Include/cmsis_gcc.h **** { 743:Drivers/CMSIS/Include/cmsis_gcc.h **** return 0U; 744:Drivers/CMSIS/Include/cmsis_gcc.h **** } 745:Drivers/CMSIS/Include/cmsis_gcc.h **** } 746:Drivers/CMSIS/Include/cmsis_gcc.h **** return (uint32_t)val; 747:Drivers/CMSIS/Include/cmsis_gcc.h **** } ARM GAS /tmp/ccwcoXyi.s page 49 748:Drivers/CMSIS/Include/cmsis_gcc.h **** 749:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ 750:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ 751:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ 752:Drivers/CMSIS/Include/cmsis_gcc.h **** 753:Drivers/CMSIS/Include/cmsis_gcc.h **** 754:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 755:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) 756:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 757:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (8 bit) 758:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB instruction for 8 bit value. 759:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 760:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 761:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 762:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) 763:Drivers/CMSIS/Include/cmsis_gcc.h **** { 764:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 765:Drivers/CMSIS/Include/cmsis_gcc.h **** 766:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 767:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 768:Drivers/CMSIS/Include/cmsis_gcc.h **** } 769:Drivers/CMSIS/Include/cmsis_gcc.h **** 770:Drivers/CMSIS/Include/cmsis_gcc.h **** 771:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 772:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (16 bit) 773:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH instruction for 16 bit values. 774:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 775:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 776:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 777:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) 778:Drivers/CMSIS/Include/cmsis_gcc.h **** { 779:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 780:Drivers/CMSIS/Include/cmsis_gcc.h **** 781:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 782:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 783:Drivers/CMSIS/Include/cmsis_gcc.h **** } 784:Drivers/CMSIS/Include/cmsis_gcc.h **** 785:Drivers/CMSIS/Include/cmsis_gcc.h **** 786:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 787:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire (32 bit) 788:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA instruction for 32 bit values. 789:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 790:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 791:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) 793:Drivers/CMSIS/Include/cmsis_gcc.h **** { 794:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 795:Drivers/CMSIS/Include/cmsis_gcc.h **** 796:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 797:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 798:Drivers/CMSIS/Include/cmsis_gcc.h **** } 799:Drivers/CMSIS/Include/cmsis_gcc.h **** 800:Drivers/CMSIS/Include/cmsis_gcc.h **** 801:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 802:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (8 bit) 803:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB instruction for 8 bit values. 804:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store ARM GAS /tmp/ccwcoXyi.s page 50 805:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 806:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 807:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) 808:Drivers/CMSIS/Include/cmsis_gcc.h **** { 809:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 810:Drivers/CMSIS/Include/cmsis_gcc.h **** } 811:Drivers/CMSIS/Include/cmsis_gcc.h **** 812:Drivers/CMSIS/Include/cmsis_gcc.h **** 813:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 814:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (16 bit) 815:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH instruction for 16 bit values. 816:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 817:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 818:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 819:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) 820:Drivers/CMSIS/Include/cmsis_gcc.h **** { 821:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 822:Drivers/CMSIS/Include/cmsis_gcc.h **** } 823:Drivers/CMSIS/Include/cmsis_gcc.h **** 824:Drivers/CMSIS/Include/cmsis_gcc.h **** 825:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 826:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release (32 bit) 827:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL instruction for 32 bit values. 828:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 829:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 830:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 831:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) 832:Drivers/CMSIS/Include/cmsis_gcc.h **** { 833:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); 834:Drivers/CMSIS/Include/cmsis_gcc.h **** } 835:Drivers/CMSIS/Include/cmsis_gcc.h **** 836:Drivers/CMSIS/Include/cmsis_gcc.h **** 837:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 838:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (8 bit) 839:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAB exclusive instruction for 8 bit value. 840:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 841:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint8_t at (*ptr) 842:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 843:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) 844:Drivers/CMSIS/Include/cmsis_gcc.h **** { 845:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 846:Drivers/CMSIS/Include/cmsis_gcc.h **** 847:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 848:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint8_t) result); 849:Drivers/CMSIS/Include/cmsis_gcc.h **** } 850:Drivers/CMSIS/Include/cmsis_gcc.h **** 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 852:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 853:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (16 bit) 854:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDAH exclusive instruction for 16 bit values. 855:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 856:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint16_t at (*ptr) 857:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 858:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) 859:Drivers/CMSIS/Include/cmsis_gcc.h **** { 860:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 861:Drivers/CMSIS/Include/cmsis_gcc.h **** ARM GAS /tmp/ccwcoXyi.s page 51 862:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 863:Drivers/CMSIS/Include/cmsis_gcc.h **** return ((uint16_t) result); 864:Drivers/CMSIS/Include/cmsis_gcc.h **** } 865:Drivers/CMSIS/Include/cmsis_gcc.h **** 866:Drivers/CMSIS/Include/cmsis_gcc.h **** 867:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 868:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Load-Acquire Exclusive (32 bit) 869:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a LDA exclusive instruction for 32 bit values. 870:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to data 871:Drivers/CMSIS/Include/cmsis_gcc.h **** \return value of type uint32_t at (*ptr) 872:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 873:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) 874:Drivers/CMSIS/Include/cmsis_gcc.h **** { 875:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 876:Drivers/CMSIS/Include/cmsis_gcc.h **** 877:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); 878:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 879:Drivers/CMSIS/Include/cmsis_gcc.h **** } 880:Drivers/CMSIS/Include/cmsis_gcc.h **** 881:Drivers/CMSIS/Include/cmsis_gcc.h **** 882:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 883:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (8 bit) 884:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLB exclusive instruction for 8 bit values. 885:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 886:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 887:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 888:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 889:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 890:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) 891:Drivers/CMSIS/Include/cmsis_gcc.h **** { 892:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 893:Drivers/CMSIS/Include/cmsis_gcc.h **** 894:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 895:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 896:Drivers/CMSIS/Include/cmsis_gcc.h **** } 897:Drivers/CMSIS/Include/cmsis_gcc.h **** 898:Drivers/CMSIS/Include/cmsis_gcc.h **** 899:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 900:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (16 bit) 901:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STLH exclusive instruction for 16 bit values. 902:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 903:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 904:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 905:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 906:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 907:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) 908:Drivers/CMSIS/Include/cmsis_gcc.h **** { 909:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 910:Drivers/CMSIS/Include/cmsis_gcc.h **** 911:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "mem 912:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 913:Drivers/CMSIS/Include/cmsis_gcc.h **** } 914:Drivers/CMSIS/Include/cmsis_gcc.h **** 915:Drivers/CMSIS/Include/cmsis_gcc.h **** 916:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 917:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Store-Release Exclusive (32 bit) 918:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Executes a STL exclusive instruction for 32 bit values. ARM GAS /tmp/ccwcoXyi.s page 52 919:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] value Value to store 920:Drivers/CMSIS/Include/cmsis_gcc.h **** \param [in] ptr Pointer to location 921:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 0 Function succeeded 922:Drivers/CMSIS/Include/cmsis_gcc.h **** \return 1 Function failed 923:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 924:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) 925:Drivers/CMSIS/Include/cmsis_gcc.h **** { 926:Drivers/CMSIS/Include/cmsis_gcc.h **** uint32_t result; 927:Drivers/CMSIS/Include/cmsis_gcc.h **** 928:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memo 929:Drivers/CMSIS/Include/cmsis_gcc.h **** return(result); 930:Drivers/CMSIS/Include/cmsis_gcc.h **** } 931:Drivers/CMSIS/Include/cmsis_gcc.h **** 932:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ 933:Drivers/CMSIS/Include/cmsis_gcc.h **** (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ 934:Drivers/CMSIS/Include/cmsis_gcc.h **** 935:Drivers/CMSIS/Include/cmsis_gcc.h **** /*@}*/ /* end of group CMSIS_Core_InstructionInterface */ 936:Drivers/CMSIS/Include/cmsis_gcc.h **** 937:Drivers/CMSIS/Include/cmsis_gcc.h **** 938:Drivers/CMSIS/Include/cmsis_gcc.h **** /* ########################### Core Function Access ########################### */ 939:Drivers/CMSIS/Include/cmsis_gcc.h **** /** \ingroup CMSIS_Core_FunctionInterface 940:Drivers/CMSIS/Include/cmsis_gcc.h **** \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions 941:Drivers/CMSIS/Include/cmsis_gcc.h **** @{ 942:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 943:Drivers/CMSIS/Include/cmsis_gcc.h **** 944:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 945:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Enable IRQ Interrupts 946:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. 947:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 948:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 949:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __enable_irq(void) 950:Drivers/CMSIS/Include/cmsis_gcc.h **** { 951:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsie i" : : : "memory"); 952:Drivers/CMSIS/Include/cmsis_gcc.h **** } 953:Drivers/CMSIS/Include/cmsis_gcc.h **** 954:Drivers/CMSIS/Include/cmsis_gcc.h **** 955:Drivers/CMSIS/Include/cmsis_gcc.h **** /** 956:Drivers/CMSIS/Include/cmsis_gcc.h **** \brief Disable IRQ Interrupts 957:Drivers/CMSIS/Include/cmsis_gcc.h **** \details Disables IRQ interrupts by setting special-purpose register PRIMASK. 958:Drivers/CMSIS/Include/cmsis_gcc.h **** Can only be executed in Privileged modes. 959:Drivers/CMSIS/Include/cmsis_gcc.h **** */ 960:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_irq(void) 1339 .loc 2 960 27 view .LVU281 1340 .LBB16: 961:Drivers/CMSIS/Include/cmsis_gcc.h **** { 962:Drivers/CMSIS/Include/cmsis_gcc.h **** __ASM volatile ("cpsid i" : : : "memory"); 1341 .loc 2 962 3 view .LVU282 1342 .syntax unified 1343 @ 962 "Drivers/CMSIS/Include/cmsis_gcc.h" 1 1344 0000 72B6 cpsid i 1345 @ 0 "" 2 1346 .thumb 1347 .syntax unified 1348 .L83: 1349 .LBE16: 1350 .LBE15: 425:Core/Src/main.c **** while (1) ARM GAS /tmp/ccwcoXyi.s page 53 1351 .loc 1 425 3 discriminator 1 view .LVU283 426:Core/Src/main.c **** { 427:Core/Src/main.c **** } 1352 .loc 1 427 3 discriminator 1 view .LVU284 425:Core/Src/main.c **** while (1) 1353 .loc 1 425 9 discriminator 1 view .LVU285 1354 0002 FEE7 b .L83 1355 .cfi_endproc 1356 .LFE156: 1358 .section .text.MX_USART2_UART_Init,"ax",%progbits 1359 .align 1 1360 .syntax unified 1361 .thumb 1362 .thumb_func 1363 .fpu fpv4-sp-d16 1365 MX_USART2_UART_Init: 1366 .LFB150: 315:Core/Src/main.c **** huart2.Instance = USART2; 1367 .loc 1 315 1 view -0 1368 .cfi_startproc 1369 @ args = 0, pretend = 0, frame = 0 1370 @ frame_needed = 0, uses_anonymous_args = 0 1371 0000 08B5 push {r3, lr} 1372 .LCFI34: 1373 .cfi_def_cfa_offset 8 1374 .cfi_offset 3, -8 1375 .cfi_offset 14, -4 316:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 1376 .loc 1 316 3 view .LVU287 316:Core/Src/main.c **** huart2.Init.BaudRate = 115200; 1377 .loc 1 316 19 is_stmt 0 view .LVU288 1378 0002 0A48 ldr r0, .L88 1379 0004 0A4B ldr r3, .L88+4 1380 0006 0360 str r3, [r0] 317:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 1381 .loc 1 317 3 is_stmt 1 view .LVU289 317:Core/Src/main.c **** huart2.Init.WordLength = UART_WORDLENGTH_8B; 1382 .loc 1 317 24 is_stmt 0 view .LVU290 1383 0008 4FF4E133 mov r3, #115200 1384 000c 4360 str r3, [r0, #4] 318:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 1385 .loc 1 318 3 is_stmt 1 view .LVU291 318:Core/Src/main.c **** huart2.Init.StopBits = UART_STOPBITS_1; 1386 .loc 1 318 26 is_stmt 0 view .LVU292 1387 000e 0023 movs r3, #0 1388 0010 8360 str r3, [r0, #8] 319:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 1389 .loc 1 319 3 is_stmt 1 view .LVU293 319:Core/Src/main.c **** huart2.Init.Parity = UART_PARITY_NONE; 1390 .loc 1 319 24 is_stmt 0 view .LVU294 1391 0012 C360 str r3, [r0, #12] 320:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 1392 .loc 1 320 3 is_stmt 1 view .LVU295 320:Core/Src/main.c **** huart2.Init.Mode = UART_MODE_TX_RX; 1393 .loc 1 320 22 is_stmt 0 view .LVU296 1394 0014 0361 str r3, [r0, #16] 321:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; ARM GAS /tmp/ccwcoXyi.s page 54 1395 .loc 1 321 3 is_stmt 1 view .LVU297 321:Core/Src/main.c **** huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 1396 .loc 1 321 20 is_stmt 0 view .LVU298 1397 0016 0C22 movs r2, #12 1398 0018 4261 str r2, [r0, #20] 322:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 1399 .loc 1 322 3 is_stmt 1 view .LVU299 322:Core/Src/main.c **** huart2.Init.OverSampling = UART_OVERSAMPLING_16; 1400 .loc 1 322 25 is_stmt 0 view .LVU300 1401 001a 8361 str r3, [r0, #24] 323:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 1402 .loc 1 323 3 is_stmt 1 view .LVU301 323:Core/Src/main.c **** if (HAL_UART_Init(&huart2) != HAL_OK) 1403 .loc 1 323 28 is_stmt 0 view .LVU302 1404 001c C361 str r3, [r0, #28] 324:Core/Src/main.c **** { 1405 .loc 1 324 3 is_stmt 1 view .LVU303 324:Core/Src/main.c **** { 1406 .loc 1 324 7 is_stmt 0 view .LVU304 1407 001e FFF7FEFF bl HAL_UART_Init 1408 .LVL104: 324:Core/Src/main.c **** { 1409 .loc 1 324 6 view .LVU305 1410 0022 00B9 cbnz r0, .L87 329:Core/Src/main.c **** 1411 .loc 1 329 1 view .LVU306 1412 0024 08BD pop {r3, pc} 1413 .L87: 326:Core/Src/main.c **** } 1414 .loc 1 326 5 is_stmt 1 view .LVU307 1415 0026 FFF7FEFF bl Error_Handler 1416 .LVL105: 1417 .L89: 1418 002a 00BF .align 2 1419 .L88: 1420 002c 00000000 .word .LANCHOR1 1421 0030 00440040 .word 1073759232 1422 .cfi_endproc 1423 .LFE150: 1425 .section .text.SystemClock_Config,"ax",%progbits 1426 .align 1 1427 .global SystemClock_Config 1428 .syntax unified 1429 .thumb 1430 .thumb_func 1431 .fpu fpv4-sp-d16 1433 SystemClock_Config: 1434 .LFB149: 268:Core/Src/main.c **** RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 1435 .loc 1 268 1 view -0 1436 .cfi_startproc 1437 @ args = 0, pretend = 0, frame = 80 1438 @ frame_needed = 0, uses_anonymous_args = 0 1439 0000 00B5 push {lr} 1440 .LCFI35: 1441 .cfi_def_cfa_offset 4 1442 .cfi_offset 14, -4 ARM GAS /tmp/ccwcoXyi.s page 55 1443 0002 95B0 sub sp, sp, #84 1444 .LCFI36: 1445 .cfi_def_cfa_offset 88 269:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1446 .loc 1 269 3 view .LVU309 269:Core/Src/main.c **** RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 1447 .loc 1 269 22 is_stmt 0 view .LVU310 1448 0004 3022 movs r2, #48 1449 0006 0021 movs r1, #0 1450 0008 08A8 add r0, sp, #32 1451 000a FFF7FEFF bl memset 1452 .LVL106: 270:Core/Src/main.c **** 1453 .loc 1 270 3 is_stmt 1 view .LVU311 270:Core/Src/main.c **** 1454 .loc 1 270 22 is_stmt 0 view .LVU312 1455 000e 0023 movs r3, #0 1456 0010 0393 str r3, [sp, #12] 1457 0012 0493 str r3, [sp, #16] 1458 0014 0593 str r3, [sp, #20] 1459 0016 0693 str r3, [sp, #24] 1460 0018 0793 str r3, [sp, #28] 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1461 .loc 1 274 3 is_stmt 1 view .LVU313 1462 .LBB17: 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1463 .loc 1 274 3 view .LVU314 1464 001a 0193 str r3, [sp, #4] 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1465 .loc 1 274 3 view .LVU315 1466 001c 1F4A ldr r2, .L96 1467 001e 116C ldr r1, [r2, #64] 1468 0020 41F08051 orr r1, r1, #268435456 1469 0024 1164 str r1, [r2, #64] 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1470 .loc 1 274 3 view .LVU316 1471 0026 126C ldr r2, [r2, #64] 1472 0028 02F08052 and r2, r2, #268435456 1473 002c 0192 str r2, [sp, #4] 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1474 .loc 1 274 3 view .LVU317 1475 002e 019A ldr r2, [sp, #4] 1476 .LBE17: 274:Core/Src/main.c **** __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2); 1477 .loc 1 274 3 view .LVU318 275:Core/Src/main.c **** 1478 .loc 1 275 3 view .LVU319 1479 .LBB18: 275:Core/Src/main.c **** 1480 .loc 1 275 3 view .LVU320 1481 0030 0293 str r3, [sp, #8] 275:Core/Src/main.c **** 1482 .loc 1 275 3 view .LVU321 1483 0032 1B49 ldr r1, .L96+4 1484 0034 0A68 ldr r2, [r1] 1485 0036 22F44042 bic r2, r2, #49152 1486 003a 42F40042 orr r2, r2, #32768 ARM GAS /tmp/ccwcoXyi.s page 56 1487 003e 0A60 str r2, [r1] 275:Core/Src/main.c **** 1488 .loc 1 275 3 view .LVU322 1489 0040 0A68 ldr r2, [r1] 1490 0042 02F44042 and r2, r2, #49152 1491 0046 0292 str r2, [sp, #8] 275:Core/Src/main.c **** 1492 .loc 1 275 3 view .LVU323 1493 0048 029A ldr r2, [sp, #8] 1494 .LBE18: 275:Core/Src/main.c **** 1495 .loc 1 275 3 view .LVU324 280:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1496 .loc 1 280 3 view .LVU325 280:Core/Src/main.c **** RCC_OscInitStruct.HSIState = RCC_HSI_ON; 1497 .loc 1 280 36 is_stmt 0 view .LVU326 1498 004a 0221 movs r1, #2 1499 004c 0891 str r1, [sp, #32] 281:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1500 .loc 1 281 3 is_stmt 1 view .LVU327 281:Core/Src/main.c **** RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 1501 .loc 1 281 30 is_stmt 0 view .LVU328 1502 004e 0122 movs r2, #1 1503 0050 0B92 str r2, [sp, #44] 282:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1504 .loc 1 282 3 is_stmt 1 view .LVU329 282:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; 1505 .loc 1 282 41 is_stmt 0 view .LVU330 1506 0052 1022 movs r2, #16 1507 0054 0C92 str r2, [sp, #48] 283:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 1508 .loc 1 283 3 is_stmt 1 view .LVU331 283:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; 1509 .loc 1 283 34 is_stmt 0 view .LVU332 1510 0056 0E91 str r1, [sp, #56] 284:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; 1511 .loc 1 284 3 is_stmt 1 view .LVU333 284:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLM = 16; 1512 .loc 1 284 35 is_stmt 0 view .LVU334 1513 0058 0F93 str r3, [sp, #60] 285:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 1514 .loc 1 285 3 is_stmt 1 view .LVU335 285:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLN = 336; 1515 .loc 1 285 30 is_stmt 0 view .LVU336 1516 005a 1092 str r2, [sp, #64] 286:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 1517 .loc 1 286 3 is_stmt 1 view .LVU337 286:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; 1518 .loc 1 286 30 is_stmt 0 view .LVU338 1519 005c 4FF4A873 mov r3, #336 1520 0060 1193 str r3, [sp, #68] 287:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 1521 .loc 1 287 3 is_stmt 1 view .LVU339 287:Core/Src/main.c **** RCC_OscInitStruct.PLL.PLLQ = 7; 1522 .loc 1 287 30 is_stmt 0 view .LVU340 1523 0062 0423 movs r3, #4 1524 0064 1293 str r3, [sp, #72] ARM GAS /tmp/ccwcoXyi.s page 57 288:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1525 .loc 1 288 3 is_stmt 1 view .LVU341 288:Core/Src/main.c **** if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 1526 .loc 1 288 30 is_stmt 0 view .LVU342 1527 0066 0723 movs r3, #7 1528 0068 1393 str r3, [sp, #76] 289:Core/Src/main.c **** { 1529 .loc 1 289 3 is_stmt 1 view .LVU343 289:Core/Src/main.c **** { 1530 .loc 1 289 7 is_stmt 0 view .LVU344 1531 006a 08A8 add r0, sp, #32 1532 006c FFF7FEFF bl HAL_RCC_OscConfig 1533 .LVL107: 289:Core/Src/main.c **** { 1534 .loc 1 289 6 view .LVU345 1535 0070 80B9 cbnz r0, .L94 296:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1536 .loc 1 296 3 is_stmt 1 view .LVU346 296:Core/Src/main.c **** |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; 1537 .loc 1 296 31 is_stmt 0 view .LVU347 1538 0072 0F23 movs r3, #15 1539 0074 0393 str r3, [sp, #12] 298:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1540 .loc 1 298 3 is_stmt 1 view .LVU348 298:Core/Src/main.c **** RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 1541 .loc 1 298 34 is_stmt 0 view .LVU349 1542 0076 0221 movs r1, #2 1543 0078 0491 str r1, [sp, #16] 299:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 1544 .loc 1 299 3 is_stmt 1 view .LVU350 299:Core/Src/main.c **** RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; 1545 .loc 1 299 35 is_stmt 0 view .LVU351 1546 007a 0023 movs r3, #0 1547 007c 0593 str r3, [sp, #20] 300:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1548 .loc 1 300 3 is_stmt 1 view .LVU352 300:Core/Src/main.c **** RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 1549 .loc 1 300 36 is_stmt 0 view .LVU353 1550 007e 4FF48052 mov r2, #4096 1551 0082 0692 str r2, [sp, #24] 301:Core/Src/main.c **** 1552 .loc 1 301 3 is_stmt 1 view .LVU354 301:Core/Src/main.c **** 1553 .loc 1 301 36 is_stmt 0 view .LVU355 1554 0084 0793 str r3, [sp, #28] 303:Core/Src/main.c **** { 1555 .loc 1 303 3 is_stmt 1 view .LVU356 303:Core/Src/main.c **** { 1556 .loc 1 303 7 is_stmt 0 view .LVU357 1557 0086 03A8 add r0, sp, #12 1558 0088 FFF7FEFF bl HAL_RCC_ClockConfig 1559 .LVL108: 303:Core/Src/main.c **** { 1560 .loc 1 303 6 view .LVU358 1561 008c 20B9 cbnz r0, .L95 307:Core/Src/main.c **** 1562 .loc 1 307 1 view .LVU359 ARM GAS /tmp/ccwcoXyi.s page 58 1563 008e 15B0 add sp, sp, #84 1564 .LCFI37: 1565 .cfi_remember_state 1566 .cfi_def_cfa_offset 4 1567 @ sp needed 1568 0090 5DF804FB ldr pc, [sp], #4 1569 .L94: 1570 .LCFI38: 1571 .cfi_restore_state 291:Core/Src/main.c **** } 1572 .loc 1 291 5 is_stmt 1 view .LVU360 1573 0094 FFF7FEFF bl Error_Handler 1574 .LVL109: 1575 .L95: 305:Core/Src/main.c **** } 1576 .loc 1 305 5 view .LVU361 1577 0098 FFF7FEFF bl Error_Handler 1578 .LVL110: 1579 .L97: 1580 .align 2 1581 .L96: 1582 009c 00380240 .word 1073887232 1583 00a0 00700040 .word 1073770496 1584 .cfi_endproc 1585 .LFE149: 1587 .section .rodata.main.str1.4,"aMS",%progbits,1 1588 .align 2 1589 .LC6: 1590 0000 30782530 .ascii "0x%02X \015\012\000" 1590 3258200D 1590 0A00 1591 000a 0000 .align 2 1592 .LC7: 1593 000c 3D3D3D3D .ascii "===================================================" 1593 3D3D3D3D 1593 3D3D3D3D 1593 3D3D3D3D 1593 3D3D3D3D 1594 003f 3D3D3D3D .ascii "==================================\015\012\000" 1594 3D3D3D3D 1594 3D3D3D3D 1594 3D3D3D3D 1594 3D3D3D3D 1595 .align 2 1596 .LC8: 1597 0064 205F5F5F .ascii " _____ _____ _____ _____ _____ _____\015\012\000" 1597 5F5F205F 1597 5F5F5F5F 1597 205F5F5F 1597 5F5F205F 1598 008b 00 .align 2 1599 .LC9: 1600 008c 7C202020 .ascii "| __| __| _ | __ | | | ___ ___ ___" 1600 5F5F7C20 1600 20205F5F 1600 7C20205F 1600 20207C20 ARM GAS /tmp/ccwcoXyi.s page 59 1601 00bf 205F5F5F .ascii " ___ ___ ___ _____ _____ ___ ___\015\012\000" 1601 205F5F5F 1601 205F5F5F 1601 205F5F5F 1601 5F5F205F 1602 00e2 0000 .align 2 1603 .LC10: 1604 00e4 7C202020 .ascii "| __| __| __| -| | | | | | | . | _| . " 1604 5F5F7C20 1604 20205F5F 1604 7C202020 1604 5F5F7C20 1605 0117 7C202E20 .ascii "| . | _| .'| | | -_| _|\015\012\000" 1605 7C20205F 1605 7C202E27 1605 7C202020 1605 20207C20 1606 013b 00 .align 2 1607 .LC11: 1608 013c 7C5F5F5F .ascii "|_____|_____|__| |__|__|_____|_|_|_| | _|_| |___" 1608 5F5F7C5F 1608 5F5F5F5F 1608 7C5F5F7C 1608 20207C5F 1609 016f 7C5F2020 .ascii "|_ |_| |__,|_|_|_|_|_|_|___|_|\015\012\000" 1609 7C5F7C20 1609 7C5F5F2C 1609 7C5F7C5F 1609 7C5F7C5F 1610 0191 000000 .align 2 1611 .LC12: 1612 0194 20202020 .ascii " - Ayabusa 2025 |_| " 1612 2D204179 1612 61627573 1612 61203230 1612 32352020 1613 01c7 7C5F5F5F .ascii "|___|\015\012\000" 1613 7C0D0A00 1614 01cf 00 .align 2 1615 .LC13: 1616 01d0 48656C6C .ascii "Hello welcome to the EEPROM programmer! What would " 1616 6F207765 1616 6C636F6D 1616 6520746F 1616 20746865 1617 0203 796F7520 .ascii "you like to do?\015\012\000" 1617 6C696B65 1617 20746F20 1617 646F3F0D 1617 0A00 1618 0215 000000 .align 2 1619 .LC14: 1620 0218 5B315D20 .ascii "[1] Dump Rom as char\015\012\000" 1620 44756D70 1620 20526F6D 1620 20617320 1620 63686172 ARM GAS /tmp/ccwcoXyi.s page 60 1621 022f 00 .align 2 1622 .LC15: 1623 0230 5B325D20 .ascii "[2] Erase chip\015\012\000" 1623 45726173 1623 65206368 1623 69700D0A 1623 00 1624 0241 000000 .align 2 1625 .LC16: 1626 0244 5B335D20 .ascii "[3] Program chip via UART (ASCII mode)\015\012\000" 1626 50726F67 1626 72616D20 1626 63686970 1626 20766961 1627 026d 000000 .align 2 1628 .LC17: 1629 0270 5B345D20 .ascii "[4] Identify device\015\012\000" 1629 4964656E 1629 74696679 1629 20646576 1629 6963650D 1630 0286 0000 .align 2 1631 .LC18: 1632 0288 5B355D20 .ascii "[5] Dump Rom as file (ASCII mode)\015\012\000" 1632 44756D70 1632 20526F6D 1632 20617320 1632 66696C65 1633 .align 2 1634 .LC19: 1635 02ac 44756D70 .ascii "Dumping ROM...\015\012\000" 1635 696E6720 1635 524F4D2E 1635 2E2E0D0A 1635 00 1636 02bd 000000 .align 2 1637 .LC20: 1638 02c0 45726173 .ascii "Erasing Chip...\015\012\000" 1638 696E6720 1638 43686970 1638 2E2E2E0D 1638 0A00 1639 02d2 0000 .align 2 1640 .LC21: 1641 02d4 4C61756E .ascii "Launching programming sequence...\015\012\000" 1641 6368696E 1641 67207072 1641 6F677261 1641 6D6D696E 1642 .align 2 1643 .LC22: 1644 02f8 4964656E .ascii "Identifying device...\015\012\000" 1644 74696679 1644 696E6720 1644 64657669 1644 63652E2E 1645 .align 2 ARM GAS /tmp/ccwcoXyi.s page 61 1646 .LC23: 1647 0310 4D616E75 .ascii "Manufacturer ID = \015\012\000" 1647 66616374 1647 75726572 1647 20494420 1647 3D200D0A 1648 0325 000000 .align 2 1649 .LC24: 1650 0328 44657669 .ascii "Device ID = \015\012\000" 1650 63652049 1650 44203D20 1650 0D0A00 1651 0337 00 .align 2 1652 .LC25: 1653 0338 44756D70 .ascii "Dumping ROM as file, press any key...\015\012\000" 1653 696E6720 1653 524F4D20 1653 61732066 1653 696C652C 1654 .align 2 1655 .LC26: 1656 0360 496E7661 .ascii "Invalid input!\015\012\000" 1656 6C696420 1656 696E7075 1656 74210D0A 1656 00 1657 .section .text.main,"ax",%progbits 1658 .align 1 1659 .global main 1660 .syntax unified 1661 .thumb 1662 .thumb_func 1663 .fpu fpv4-sp-d16 1665 main: 1666 .LFB137: 40:Core/Src/main.c **** /* MCU Configuration--------------------------------------------------------*/ 1667 .loc 1 40 1 view -0 1668 .cfi_startproc 1669 @ args = 0, pretend = 0, frame = 16 1670 @ frame_needed = 0, uses_anonymous_args = 0 1671 0000 70B5 push {r4, r5, r6, lr} 1672 .LCFI39: 1673 .cfi_def_cfa_offset 16 1674 .cfi_offset 4, -16 1675 .cfi_offset 5, -12 1676 .cfi_offset 6, -8 1677 .cfi_offset 14, -4 1678 0002 84B0 sub sp, sp, #16 1679 .LCFI40: 1680 .cfi_def_cfa_offset 32 44:Core/Src/main.c **** 1681 .loc 1 44 3 view .LVU363 1682 0004 FFF7FEFF bl HAL_Init 1683 .LVL111: 47:Core/Src/main.c **** 1684 .loc 1 47 3 view .LVU364 1685 0008 FFF7FEFF bl SystemClock_Config ARM GAS /tmp/ccwcoXyi.s page 62 1686 .LVL112: 50:Core/Src/main.c **** MX_USART2_UART_Init(); 1687 .loc 1 50 3 view .LVU365 1688 000c FFF7FEFF bl MX_GPIO_Init 1689 .LVL113: 51:Core/Src/main.c **** 1690 .loc 1 51 3 view .LVU366 1691 0010 FFF7FEFF bl MX_USART2_UART_Init 1692 .LVL114: 53:Core/Src/main.c **** Address_Pins_Init(); 1693 .loc 1 53 3 view .LVU367 1694 0014 0020 movs r0, #0 1695 0016 FFF7FEFF bl Data_Pins_Init 1696 .LVL115: 54:Core/Src/main.c **** Command_Pins_Init(); 1697 .loc 1 54 3 view .LVU368 1698 001a FFF7FEFF bl Address_Pins_Init 1699 .LVL116: 55:Core/Src/main.c **** 1700 .loc 1 55 3 view .LVU369 1701 001e FFF7FEFF bl Command_Pins_Init 1702 .LVL117: 57:Core/Src/main.c **** Enter_Device_ID(&man_id, &dev_id); 1703 .loc 1 57 3 view .LVU370 58:Core/Src/main.c **** 1704 .loc 1 58 3 view .LVU371 1705 0022 02A9 add r1, sp, #8 1706 0024 03A8 add r0, sp, #12 1707 0026 FFF7FEFF bl Enter_Device_ID 1708 .LVL118: 60:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 1709 .loc 1 60 3 view .LVU372 60:Core/Src/main.c **** char *device = (char*)malloc(13 * sizeof(char)); 1710 .loc 1 60 31 is_stmt 0 view .LVU373 1711 002a 0D20 movs r0, #13 1712 002c FFF7FEFF bl malloc 1713 .LVL119: 1714 0030 0546 mov r5, r0 1715 .LVL120: 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1716 .loc 1 61 3 is_stmt 1 view .LVU374 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1717 .loc 1 61 25 is_stmt 0 view .LVU375 1718 0032 0D20 movs r0, #13 1719 .LVL121: 61:Core/Src/main.c **** sprintf(manufacturer, "0x%02X \r\n", man_id); 1720 .loc 1 61 25 view .LVU376 1721 0034 FFF7FEFF bl malloc 1722 .LVL122: 1723 0038 0446 mov r4, r0 1724 .LVL123: 62:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 1725 .loc 1 62 3 is_stmt 1 view .LVU377 1726 003a 3D4E ldr r6, .L110 1727 003c 039A ldr r2, [sp, #12] 1728 003e 3146 mov r1, r6 1729 0040 2846 mov r0, r5 ARM GAS /tmp/ccwcoXyi.s page 63 1730 .LVL124: 62:Core/Src/main.c **** sprintf(device, "0x%02X \r\n", dev_id); 1731 .loc 1 62 3 is_stmt 0 view .LVU378 1732 0042 FFF7FEFF bl sprintf 1733 .LVL125: 63:Core/Src/main.c **** 1734 .loc 1 63 3 is_stmt 1 view .LVU379 1735 0046 029A ldr r2, [sp, #8] 1736 0048 3146 mov r1, r6 1737 004a 2046 mov r0, r4 1738 004c FFF7FEFF bl sprintf 1739 .LVL126: 65:Core/Src/main.c **** debug_print(" _____ _____ _____ _____ _____ _____\r\n"); 1740 .loc 1 65 3 view .LVU380 1741 0050 384E ldr r6, .L110+4 1742 0052 3046 mov r0, r6 1743 0054 FFF7FEFF bl debug_print 1744 .LVL127: 66:Core/Src/main.c **** debug_print("| __| __| _ | __ | | | ___ ___ ___ ___ ___ ___ _____ _____ ___ ___\ 1745 .loc 1 66 3 view .LVU381 1746 0058 3748 ldr r0, .L110+8 1747 005a FFF7FEFF bl debug_print 1748 .LVL128: 67:Core/Src/main.c **** debug_print("| __| __| __| -| | | | | | | . | _| . | . | _| .'| | | -_| _| 1749 .loc 1 67 3 view .LVU382 1750 005e 3748 ldr r0, .L110+12 1751 0060 FFF7FEFF bl debug_print 1752 .LVL129: 68:Core/Src/main.c **** debug_print("|_____|_____|__| |__|__|_____|_|_|_| | _|_| |___|_ |_| |__,|_|_|_|_|_|_|___|_|\r 1753 .loc 1 68 3 view .LVU383 1754 0064 3648 ldr r0, .L110+16 1755 0066 FFF7FEFF bl debug_print 1756 .LVL130: 69:Core/Src/main.c **** debug_print(" - Ayabusa 2025 |_| |___|\r\n"); 1757 .loc 1 69 3 view .LVU384 1758 006a 3648 ldr r0, .L110+20 1759 006c FFF7FEFF bl debug_print 1760 .LVL131: 70:Core/Src/main.c **** debug_print("==================================================================================== 1761 .loc 1 70 3 view .LVU385 1762 0070 3548 ldr r0, .L110+24 1763 0072 FFF7FEFF bl debug_print 1764 .LVL132: 71:Core/Src/main.c **** 1765 .loc 1 71 3 view .LVU386 1766 0076 3046 mov r0, r6 1767 0078 FFF7FEFF bl debug_print 1768 .LVL133: 1769 .L108: 74:Core/Src/main.c **** { 1770 .loc 1 74 3 view .LVU387 1771 .LBB19: 76:Core/Src/main.c **** debug_print("[1] Dump Rom as char\r\n"); 1772 .loc 1 76 5 view .LVU388 1773 007c 3348 ldr r0, .L110+28 1774 007e FFF7FEFF bl debug_print 1775 .LVL134: ARM GAS /tmp/ccwcoXyi.s page 64 77:Core/Src/main.c **** debug_print("[2] Erase chip\r\n"); 1776 .loc 1 77 5 view .LVU389 1777 0082 3348 ldr r0, .L110+32 1778 0084 FFF7FEFF bl debug_print 1779 .LVL135: 78:Core/Src/main.c **** debug_print("[3] Program chip via UART (ASCII mode)\r\n"); 1780 .loc 1 78 5 view .LVU390 1781 0088 3248 ldr r0, .L110+36 1782 008a FFF7FEFF bl debug_print 1783 .LVL136: 79:Core/Src/main.c **** debug_print("[4] Identify device\r\n"); 1784 .loc 1 79 5 view .LVU391 1785 008e 3248 ldr r0, .L110+40 1786 0090 FFF7FEFF bl debug_print 1787 .LVL137: 80:Core/Src/main.c **** debug_print("[5] Dump Rom as file (ASCII mode)\r\n"); 1788 .loc 1 80 5 view .LVU392 1789 0094 3148 ldr r0, .L110+44 1790 0096 FFF7FEFF bl debug_print 1791 .LVL138: 81:Core/Src/main.c **** uint8_t resp; 1792 .loc 1 81 5 view .LVU393 1793 009a 3148 ldr r0, .L110+48 1794 009c FFF7FEFF bl debug_print 1795 .LVL139: 82:Core/Src/main.c **** HAL_UART_Receive(&huart2, &resp, 1, HAL_MAX_DELAY); 1796 .loc 1 82 5 view .LVU394 83:Core/Src/main.c **** 1797 .loc 1 83 5 view .LVU395 1798 00a0 4FF0FF33 mov r3, #-1 1799 00a4 0122 movs r2, #1 1800 00a6 0DF10601 add r1, sp, #6 1801 00aa 2E48 ldr r0, .L110+52 1802 00ac FFF7FEFF bl HAL_UART_Receive 1803 .LVL140: 85:Core/Src/main.c **** { 1804 .loc 1 85 5 view .LVU396 1805 00b0 9DF80630 ldrb r3, [sp, #6] @ zero_extendqisi2 1806 00b4 313B subs r3, r3, #49 1807 00b6 042B cmp r3, #4 1808 00b8 36D8 bhi .L99 1809 00ba DFE803F0 tbb [pc, r3] 1810 .L101: 1811 00be 03 .byte (.L105-.L101)/2 1812 00bf 0A .byte (.L104-.L101)/2 1813 00c0 10 .byte (.L103-.L101)/2 1814 00c1 16 .byte (.L102-.L101)/2 1815 00c2 26 .byte (.L100-.L101)/2 1816 00c3 00 .p2align 1 1817 .L105: 1818 .LBB20: 88:Core/Src/main.c **** Dump_Flash_UART(1); 1819 .loc 1 88 7 view .LVU397 1820 00c4 2848 ldr r0, .L110+56 1821 00c6 FFF7FEFF bl debug_print 1822 .LVL141: 89:Core/Src/main.c **** break; ARM GAS /tmp/ccwcoXyi.s page 65 1823 .loc 1 89 7 view .LVU398 1824 00ca 0120 movs r0, #1 1825 00cc FFF7FEFF bl Dump_Flash_UART 1826 .LVL142: 90:Core/Src/main.c **** case 0x32: 1827 .loc 1 90 7 view .LVU399 1828 00d0 D4E7 b .L108 1829 .L104: 92:Core/Src/main.c **** Chip_Erase(); 1830 .loc 1 92 7 view .LVU400 1831 00d2 2648 ldr r0, .L110+60 1832 00d4 FFF7FEFF bl debug_print 1833 .LVL143: 93:Core/Src/main.c **** break; 1834 .loc 1 93 7 view .LVU401 1835 00d8 FFF7FEFF bl Chip_Erase 1836 .LVL144: 94:Core/Src/main.c **** case 0x33: 1837 .loc 1 94 7 view .LVU402 1838 00dc CEE7 b .L108 1839 .L103: 96:Core/Src/main.c **** Flash_From_UART(); 1840 .loc 1 96 7 view .LVU403 1841 00de 2448 ldr r0, .L110+64 1842 00e0 FFF7FEFF bl debug_print 1843 .LVL145: 97:Core/Src/main.c **** break; 1844 .loc 1 97 7 view .LVU404 1845 00e4 FFF7FEFF bl Flash_From_UART 1846 .LVL146: 98:Core/Src/main.c **** case 0x34: 1847 .loc 1 98 7 view .LVU405 1848 00e8 C8E7 b .L108 1849 .L102: 100:Core/Src/main.c **** debug_print("Manufacturer ID = \r\n"); 1850 .loc 1 100 7 view .LVU406 1851 00ea 2248 ldr r0, .L110+68 1852 00ec FFF7FEFF bl debug_print 1853 .LVL147: 101:Core/Src/main.c **** debug_print(manufacturer); 1854 .loc 1 101 7 view .LVU407 1855 00f0 2148 ldr r0, .L110+72 1856 00f2 FFF7FEFF bl debug_print 1857 .LVL148: 102:Core/Src/main.c **** debug_print("Device ID = \r\n"); 1858 .loc 1 102 7 view .LVU408 1859 00f6 2846 mov r0, r5 1860 00f8 FFF7FEFF bl debug_print 1861 .LVL149: 103:Core/Src/main.c **** debug_print(device); 1862 .loc 1 103 7 view .LVU409 1863 00fc 1F48 ldr r0, .L110+76 1864 00fe FFF7FEFF bl debug_print 1865 .LVL150: 104:Core/Src/main.c **** break; 1866 .loc 1 104 7 view .LVU410 1867 0102 2046 mov r0, r4 ARM GAS /tmp/ccwcoXyi.s page 66 1868 0104 FFF7FEFF bl debug_print 1869 .LVL151: 105:Core/Src/main.c **** case 0x35: 1870 .loc 1 105 7 view .LVU411 1871 0108 B8E7 b .L108 1872 .L100: 107:Core/Src/main.c **** uint8_t byte; 1873 .loc 1 107 7 view .LVU412 1874 010a 1D48 ldr r0, .L110+80 1875 010c FFF7FEFF bl debug_print 1876 .LVL152: 108:Core/Src/main.c **** HAL_UART_Receive(&huart2, &byte, 1, HAL_MAX_DELAY); 1877 .loc 1 108 7 view .LVU413 109:Core/Src/main.c **** Dump_Flash_UART(0); 1878 .loc 1 109 7 view .LVU414 1879 0110 4FF0FF33 mov r3, #-1 1880 0114 0122 movs r2, #1 1881 0116 0DF10701 add r1, sp, #7 1882 011a 1248 ldr r0, .L110+52 1883 011c FFF7FEFF bl HAL_UART_Receive 1884 .LVL153: 110:Core/Src/main.c **** while(1){} 1885 .loc 1 110 7 view .LVU415 1886 0120 0020 movs r0, #0 1887 0122 FFF7FEFF bl Dump_Flash_UART 1888 .LVL154: 1889 .L107: 111:Core/Src/main.c **** default: 1890 .loc 1 111 7 discriminator 1 view .LVU416 111:Core/Src/main.c **** default: 1891 .loc 1 111 16 discriminator 1 view .LVU417 111:Core/Src/main.c **** default: 1892 .loc 1 111 12 discriminator 1 view .LVU418 1893 0126 FEE7 b .L107 1894 .L99: 113:Core/Src/main.c **** break; 1895 .loc 1 113 7 view .LVU419 1896 0128 1648 ldr r0, .L110+84 1897 012a FFF7FEFF bl debug_print 1898 .LVL155: 114:Core/Src/main.c **** } 1899 .loc 1 114 7 view .LVU420 1900 .LBE20: 1901 .LBE19: 74:Core/Src/main.c **** { 1902 .loc 1 74 9 view .LVU421 75:Core/Src/main.c **** debug_print("Hello welcome to the EEPROM programmer! What would you like to do?\r\n"); 1903 .loc 1 75 3 is_stmt 0 view .LVU422 1904 012e A5E7 b .L108 1905 .L111: 1906 .align 2 1907 .L110: 1908 0130 00000000 .word .LC6 1909 0134 0C000000 .word .LC7 1910 0138 64000000 .word .LC8 1911 013c 8C000000 .word .LC9 1912 0140 E4000000 .word .LC10 ARM GAS /tmp/ccwcoXyi.s page 67 1913 0144 3C010000 .word .LC11 1914 0148 94010000 .word .LC12 1915 014c D0010000 .word .LC13 1916 0150 18020000 .word .LC14 1917 0154 30020000 .word .LC15 1918 0158 44020000 .word .LC16 1919 015c 70020000 .word .LC17 1920 0160 88020000 .word .LC18 1921 0164 00000000 .word .LANCHOR1 1922 0168 AC020000 .word .LC19 1923 016c C0020000 .word .LC20 1924 0170 D4020000 .word .LC21 1925 0174 F8020000 .word .LC22 1926 0178 10030000 .word .LC23 1927 017c 28030000 .word .LC24 1928 0180 38030000 .word .LC25 1929 0184 60030000 .word .LC26 1930 .cfi_endproc 1931 .LFE137: 1933 .global huart2 1934 .section .rodata 1935 .align 2 1936 .set .LANCHOR0,. + 0 1937 .LC0: 1938 0000 01000000 .word 1 1939 0004 02000000 .word 2 1940 0008 04000000 .word 4 1941 000c 08000000 .word 8 1942 0010 10000000 .word 16 1943 0014 20000000 .word 32 1944 0018 40000000 .word 64 1945 001c 80000000 .word 128 1946 0020 00010000 .word 256 1947 0024 00020000 .word 512 1948 0028 00040000 .word 1024 1949 002c 00080000 .word 2048 1950 0030 00100000 .word 4096 1951 0034 00200000 .word 8192 1952 0038 01000000 .word 1 1953 003c 02000000 .word 2 1954 0040 04000000 .word 4 1955 0044 08000000 .word 8 1956 0048 10000000 .word 16 1957 .LC1: 1958 004c 01000000 .word 1 1959 0050 02000000 .word 2 1960 0054 00080000 .word 2048 1961 0058 00100000 .word 4096 1962 005c 10000000 .word 16 1963 0060 20000000 .word 32 1964 0064 40000000 .word 64 1965 0068 80000000 .word 128 1966 .section .bss.huart2,"aw",%nobits 1967 .align 2 1968 .set .LANCHOR1,. + 0 1971 huart2: 1972 0000 00000000 .space 72 ARM GAS /tmp/ccwcoXyi.s page 68 1972 00000000 1972 00000000 1972 00000000 1972 00000000 1973 .text 1974 .Letext0: 1975 .file 3 "/usr/lib/gcc/arm-none-eabi/10.3.1/include/stdint.h" 1976 .file 4 "Drivers/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h" 1977 .file 5 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_def.h" 1978 .file 6 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc_ex.h" 1979 .file 7 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_rcc.h" 1980 .file 8 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_gpio.h" 1981 .file 9 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_dma.h" 1982 .file 10 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal_uart.h" 1983 .file 11 "/usr/include/newlib/string.h" 1984 .file 12 "Drivers/STM32F4xx_HAL_Driver/Inc/stm32f4xx_hal.h" 1985 .file 13 "/usr/include/newlib/stdio.h" 1986 .file 14 "" 1987 .file 15 "/usr/include/newlib/stdlib.h" ARM GAS /tmp/ccwcoXyi.s page 69 DEFINED SYMBOLS *ABS*:0000000000000000 main.c /tmp/ccwcoXyi.s:18 .text.MX_GPIO_Init:0000000000000000 $t /tmp/ccwcoXyi.s:25 .text.MX_GPIO_Init:0000000000000000 MX_GPIO_Init /tmp/ccwcoXyi.s:111 .text.MX_GPIO_Init:000000000000005c $d /tmp/ccwcoXyi.s:116 .text.Write_Address:0000000000000000 $t /tmp/ccwcoXyi.s:123 .text.Write_Address:0000000000000000 Write_Address /tmp/ccwcoXyi.s:236 .text.Write_Address:0000000000000084 $d /tmp/ccwcoXyi.s:243 .text.Write_Command_Pins:0000000000000000 $t /tmp/ccwcoXyi.s:250 .text.Write_Command_Pins:0000000000000000 Write_Command_Pins /tmp/ccwcoXyi.s:305 .text.Write_Command_Pins:000000000000003c $d /tmp/ccwcoXyi.s:310 .text.Data_Pins_Init:0000000000000000 $t /tmp/ccwcoXyi.s:317 .text.Data_Pins_Init:0000000000000000 Data_Pins_Init /tmp/ccwcoXyi.s:385 .text.Data_Pins_Init:0000000000000038 $d /tmp/ccwcoXyi.s:390 .text.Receive_Data:0000000000000000 $t /tmp/ccwcoXyi.s:397 .text.Receive_Data:0000000000000000 Receive_Data /tmp/ccwcoXyi.s:485 .text.Receive_Data:0000000000000048 $d /tmp/ccwcoXyi.s:491 .text.Write_Data:0000000000000000 $t /tmp/ccwcoXyi.s:498 .text.Write_Data:0000000000000000 Write_Data /tmp/ccwcoXyi.s:588 .text.Write_Data:000000000000005c $d /tmp/ccwcoXyi.s:594 .text.Write_Command:0000000000000000 $t /tmp/ccwcoXyi.s:601 .text.Write_Command:0000000000000000 Write_Command /tmp/ccwcoXyi.s:667 .text.Chip_Erase:0000000000000000 $t /tmp/ccwcoXyi.s:674 .text.Chip_Erase:0000000000000000 Chip_Erase /tmp/ccwcoXyi.s:725 .text.Chip_Program_Byte:0000000000000000 $t /tmp/ccwcoXyi.s:732 .text.Chip_Program_Byte:0000000000000000 Chip_Program_Byte /tmp/ccwcoXyi.s:780 .text.Flash_ReadByte:0000000000000000 $t /tmp/ccwcoXyi.s:787 .text.Flash_ReadByte:0000000000000000 Flash_ReadByte /tmp/ccwcoXyi.s:836 .text.Enter_Device_ID:0000000000000000 $t /tmp/ccwcoXyi.s:843 .text.Enter_Device_ID:0000000000000000 Enter_Device_ID /tmp/ccwcoXyi.s:905 .rodata.Dump_Flash_UART.str1.4:0000000000000000 $d /tmp/ccwcoXyi.s:912 .text.Dump_Flash_UART:0000000000000000 $t /tmp/ccwcoXyi.s:919 .text.Dump_Flash_UART:0000000000000000 Dump_Flash_UART /tmp/ccwcoXyi.s:1035 .text.Dump_Flash_UART:000000000000007c $d /tmp/ccwcoXyi.s:1043 .text.Address_Pins_Init:0000000000000000 $t /tmp/ccwcoXyi.s:1050 .text.Address_Pins_Init:0000000000000000 Address_Pins_Init /tmp/ccwcoXyi.s:1124 .text.Address_Pins_Init:0000000000000044 $d /tmp/ccwcoXyi.s:1130 .text.Command_Pins_Init:0000000000000000 $t /tmp/ccwcoXyi.s:1137 .text.Command_Pins_Init:0000000000000000 Command_Pins_Init /tmp/ccwcoXyi.s:1185 .text.Command_Pins_Init:000000000000002c $d /tmp/ccwcoXyi.s:1190 .text.debug_print:0000000000000000 $t /tmp/ccwcoXyi.s:1197 .text.debug_print:0000000000000000 debug_print /tmp/ccwcoXyi.s:1229 .text.debug_print:0000000000000018 $d /tmp/ccwcoXyi.s:1234 .rodata.Flash_From_UART.str1.4:0000000000000000 $d /tmp/ccwcoXyi.s:1241 .text.Flash_From_UART:0000000000000000 $t /tmp/ccwcoXyi.s:1248 .text.Flash_From_UART:0000000000000000 Flash_From_UART /tmp/ccwcoXyi.s:1313 .text.Flash_From_UART:0000000000000038 $d /tmp/ccwcoXyi.s:1320 .text.Error_Handler:0000000000000000 $t /tmp/ccwcoXyi.s:1327 .text.Error_Handler:0000000000000000 Error_Handler /tmp/ccwcoXyi.s:1359 .text.MX_USART2_UART_Init:0000000000000000 $t /tmp/ccwcoXyi.s:1365 .text.MX_USART2_UART_Init:0000000000000000 MX_USART2_UART_Init /tmp/ccwcoXyi.s:1420 .text.MX_USART2_UART_Init:000000000000002c $d /tmp/ccwcoXyi.s:1426 .text.SystemClock_Config:0000000000000000 $t /tmp/ccwcoXyi.s:1433 .text.SystemClock_Config:0000000000000000 SystemClock_Config /tmp/ccwcoXyi.s:1582 .text.SystemClock_Config:000000000000009c $d /tmp/ccwcoXyi.s:1588 .rodata.main.str1.4:0000000000000000 $d /tmp/ccwcoXyi.s:1658 .text.main:0000000000000000 $t ARM GAS /tmp/ccwcoXyi.s page 70 /tmp/ccwcoXyi.s:1665 .text.main:0000000000000000 main /tmp/ccwcoXyi.s:1811 .text.main:00000000000000be $d /tmp/ccwcoXyi.s:1908 .text.main:0000000000000130 $d /tmp/ccwcoXyi.s:1971 .bss.huart2:0000000000000000 huart2 /tmp/ccwcoXyi.s:1935 .rodata:0000000000000000 $d /tmp/ccwcoXyi.s:1967 .bss.huart2:0000000000000000 $d /tmp/ccwcoXyi.s:1816 .text.main:00000000000000c3 $d /tmp/ccwcoXyi.s:1816 .text.main:00000000000000c4 $t UNDEFINED SYMBOLS memcpy HAL_GPIO_WritePin HAL_GPIO_Init HAL_GPIO_ReadPin HAL_Delay sprintf strlen HAL_UART_Transmit HAL_UART_Receive HAL_UART_Init memset HAL_RCC_OscConfig HAL_RCC_ClockConfig HAL_Init malloc