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ayabusa
2024-04-21 14:08:27 +02:00
parent 280af2f4d6
commit be56bce326
65 changed files with 58 additions and 629 deletions
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2
src/Laplace/README.md Normal file
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# Laplace
Laplace is the abstraction layer of Zeta, it is used to control the led, keyboard, screen ...

121
src/Laplace/clock.c Normal file
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#include "clock.h"
/* This should set the speed to 216MHz intead of just 48MHz */
void init_clock(){
// Enable the HSI and wait for it to be ready to use
RCC->CR |= (RCC_CR_HSION);
while (!(RCC->CR & RCC_CR_HSIRDY)) {};
// Enable the HSE and wait for it to be ready to use
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {};
// enable power interface clock
RCC->APB1ENR |= (RCC_APB1ENR_PWREN);
// SSGR stuf, paragraph taken from upsilon
/* To pass electromagnetic compatibility tests, we activate the Spread
* Spectrum clock generation, which adds jitter to the PLL clock in order to
* "lower peak-energy on the central frequency" and its harmonics.
* It must be done before enabling the PLL. */
/* Modper = 250
* Incstep = 25
* SpreadSel = 0
* SSCGEN = 1 */
RCC->SSCGR = 0b10000000000000110010000011111010;
// clear PLL_M, PLL_N ,PLL_Q and PLLSRC in PLLCFGR
RCC->PLLCFGR &= ~(0b00001111010000000111111111111111);
// Set the specified value to PLLCFGR
/* PLL_M = 8 = 0b1000
* PLL_N = 384 = 0b110000000
* PLL_Q = 8 = 0b1000
* PLL_SRC = HSE = 1 */
RCC->PLLCFGR |= 0b00001000010000000110000000001000;
// Now we can enable PLL
RCC->CR |= RCC_CR_PLLON;
// Enable Overdrive (idk what it is) and wait
PWR->CR1 |= PWR_CR1_ODEN;
while (!(PWR->CSR1 & PWR_CSR1_ODRDY)) {};
// Same for ODSWEN
PWR->CR1 |= PWR_CR1_ODSWEN;
while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY)) {};
// Select voltage scale (scale 1 = 0b11)
PWR->CR1 |= 0b00000000000000001100000000000000;
while (!(PWR->CSR1 & PWR_CSR1_VOSRDY)) {};
// Set Latency to 7 wait state (paragraph from Upsilon)
// Enable Prefetching, and ART
/* After reset the Flash runs as fast as the CPU. When we clock the CPU faster
* the flash memory cannot follow and therefore flash memory accesses need to
* wait a little bit.
* The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */
// clear in first place
FLASH->ACR &= ~(FLASH_ACR_LATENCY_Msk | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
// 192MHz is too fast for both APB1 and APB2 so we divide them
// firstly we clear
RCC->CFGR &= ~(0b00000000000000001111110000000000);
/* Then we set
* PPRE1 = 4 = 100
* PPRE2 = 2 = 10 */
RCC->CFGR |= 0b00000000000000001001010000000000;
// We now wait for PLLRDY
while (!(RCC->CR & RCC_CR_PLLRDY)) {};
// We select PLL output as a SYSCLK source
RCC->CFGR |= RCC_CFGR_SW_PLL;
// And wait for it !!!
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {};
// We can now disable HSI
RCC->CR &= ~(RCC_CR_HSION);
// Set normal speed
RCC->CFGR &= ~(RCC_CFGR_HPRE_Msk);
// UNSAFE CODE
// 23999<=>0b0101 1101 1011 1111
SysTick->LOAD &= ~(0b00000000111111111111111111111111);
SysTick->LOAD |= 0b00000000000000000101110110111111;
// set current
SysTick->VAL &= ~(0b00000000111111111111111111111111);
//set some things in CSR
SysTick->CTRL &= ~(0b00000000000000000000000000000111);
SysTick->CTRL |= 0b00000000000000000000000000000011;
}
/* OLD
// ACR means flash Access control register
FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | // 7 wait states
FLASH_ACR_PRFTEN | // prefetch on
FLASH_ACR_ARTEN); // ART on
FLASH->ACR &= ~(0b00000000000000000000101100001111);
// enables HSE and wait for it to be ready
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {};
// clear the specified bit
// (8/4)*108 = 216MHz
RCC->PLLCFGR |= (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz
RCC_PLLCFGR_PLLN_108 | // *108
RCC_PLLCFGR_PLLM_25); // /4
RCC->PLLCFGR = 0b00001000010000100110000000001000; // HSE: 8MHz
// enable the RCC clock and wait for it to be ready
RCC->CR |= (RCC_CR_PLLON);
while (!(RCC->CR & RCC_CR_PLLRDY)) {};
// set it as the system clock source
RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= (RCC_CFGR_SW_PLL);
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {};
*/

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src/Laplace/clock.h Normal file
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/** @file clock.h
*
* @brief Handle clock init and all
*
*/
#ifndef CLOCK_H
#define CLOCK_H
#include "stdint.h"
#include "../device/stm32f730xx.h"
#include "led.h"
/*
RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/
//0b0000/*<-null*/1000/*<-PLLQ*/0/*<-null*/1/*<-PLLPSRC(HSE)*/0000/*<-null*/10/*<-PLLP*/0/*<-null*/110000000/*<-PLLN*/001000/*<-PLLM*/
void init_clock();
#endif

119
src/Laplace/gpio_helper.c Normal file
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#include "gpio_helper.h"
uint8_t GPIOA_state = 0;
uint8_t GPIOB_state = 0;
uint8_t GPIOC_state = 0;
uint8_t GPIOD_state = 0;
uint8_t GPIOE_state = 0;
/* Set a pin High (true) or Low (false) ie:
set_output_pin(GPIO_B, 2, true);
this sets the pin B2 to high */
void set_output_pin(uint8_t gpio_x, uint8_t pin, bool state){
switch (gpio_x)
{
case GPIO_A:
if(state){
GPIOA_state |= (1 << pin);
}else{
GPIOA_state &= ~(1 << pin);
}
GPIOA->ODR = GPIOA_state;
break;
case GPIO_B:
if(state){
GPIOB_state |= (1 << pin);
}else{
GPIOB_state &= ~(1 << pin);
}
GPIOB->ODR = GPIOB_state;
break;
case GPIO_C:
if(state){
GPIOC_state |= (1 << pin);
}else{
GPIOC_state &= ~(1 << pin);
}
GPIOC->ODR = GPIOC_state;
break;
case GPIO_D:
if(state){
GPIOD_state |= (1 << pin);
}else{
GPIOD_state &= ~(1 << pin);
}
GPIOD->ODR = GPIOD_state;
break;
case GPIO_E:
if(state){
GPIOE_state |= (1 << pin);
}else{
GPIOE_state &= ~(1 << pin);
}
GPIOE->ODR = GPIOE_state;
break;
default:
break;
}
}
/* Read the value of an input pin, it returns High (true) or Low (false) ie:
bool state = read_input_pin(GPIO_C, 3);
This stores the state of the pin C3 */
bool read_input_pin(uint8_t gpio_x, uint8_t pin){
// Invert the IDR register since '0' means 'pressed'.
uint8_t idr_val = 0;
switch (gpio_x)
{
case GPIO_A:
idr_val = ~GPIOA->IDR;
break;
case GPIO_B:
idr_val = ~GPIOB->IDR;
break;
case GPIO_C:
idr_val = ~GPIOC->IDR;
break;
case GPIO_D:
idr_val = ~GPIOD->IDR;
break;
case GPIO_E:
idr_val = ~GPIOE->IDR;
break;
default:
break;
}
return idr_val & (1 << pin);
}
/* Enable the specified GPIO */
void enable_gpio_x_rcc(uint8_t gpio_x){
switch (gpio_x)
{
case GPIO_A:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ;
break;
case GPIO_B:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ;
break;
case GPIO_C:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ;
break;
case GPIO_D:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN ;
break;
case GPIO_E:
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOEEN ;
break;
default:
break;
}
}

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src/Laplace/gpio_helper.h Normal file
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/** @file gpio_helper.h
*
* @brief Control all the GPIO
*
*/
#ifndef GPIO_HELPER_H
#define GPIO_HELPER_H
#include "stdbool.h"
#include "../device/stm32f730xx.h"
#define GPIO_A 0
#define GPIO_B 1
#define GPIO_C 2
#define GPIO_D 3
#define GPIO_E 4
/* Set a pin High (true) or Low (false) ie:
set_output_pin(GPIO_B, 2, true);
this sets the pin B2 to high */
void set_output_pin(uint8_t gpio_x, uint8_t pin, bool state);
/* Read the value of an input pin, it returns High (true) or Low (false) ie:
bool state = read_input_pin(GPIO_C, 3);
This stores the state of the pin C3 */
bool read_input_pin(uint8_t gpio_x, uint8_t pin);
/* Enable the specified GPIO */
void enable_gpio_x_rcc(uint8_t gpio_x);
#endif

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src/Laplace/keyboard.c Normal file
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/* The keyboard is a matrix that is laid out as follow:
* (K_B2 and K_B3 are respectively specific to N0100 and N0110
*
* | PC0 | PC1 | PC2 | PC3 | PC4 | PC5 |
* -----+------+------+------+------+------+------+
* PE0 | K_A1 | K_A2 | K_A3 | K_A4 | K_A5 | K_A6 |
* -----+------+------+------+------+------+------+
* PE1 | K_B1 |(K_B2)|(K_B3)| | | |
* -----+------+------+------+------+------+------+
* PE2 | K_C1 | K_C2 | K_C3 | K_C4 | K_C5 | K_C6 |
* -----+------+------+------+------+------+------+
* PE3 | K_D1 | K_D2 | K_D3 | K_D4 | K_D5 | K_D6 |
* -----+------+------+------+------+------+------+
* PE4 | K_E1 | K_E2 | K_E3 | K_E4 | K_E5 | K_E6 |
* -----+------+------+------+------+------+------+
* PE5 | K_F1 | K_F2 | K_F3 | K_F4 | K_F5 | |
* -----+------+------+------+------+------+------+
* PE6 | K_G1 | K_G2 | K_G3 | K_G4 | K_G5 | |
* -----+------+------+------+------+------+------+
* PE7 | K_H1 | K_H2 | K_H3 | K_H4 | K_H5 | |
* -----+------+------+------+------+------+------+
* PE8 | K_I1 | K_I2 | K_I3 | K_I4 | K_I5 | |
* -----+------+------+------+------+------+------|
*
* We decide to drive the rows (PE0-8) and read the columns (PC0-5).
*
* To avoid short-circuits, the pins E0-E8 will not be standard outputs but
* only open-drain. Open drain means the pin is either driven low or left
* floating.
* When a user presses multiple keys, a connection between two rows can happen.
* If we don't use open drain outputs, this situation could trigger a short
* circuit between an output driving high and another driving low.
*
* If the outputs are open-drain, this means that the input must be pulled up.
* So if the input reads "1", this means the key is in fact *not* pressed, and
* if it reads "0" it means that there's a short to an open-drain output. Which
* means the corresponding key is pressed.
*/
#include "keyboard.h"
const uint8_t number_of_rows = 9;
const uint8_t number_of_columns = 6;
const char row_list[9] = {'B', 'A', 'C', 'D', 'E', 'F', 'G', 'H', 'I'};
/* This should be called before accessing any other keyboard related feature
as it sets up all keyboard related peripherals */
void keyboard_init(){
for (int i = 0; i < number_of_rows; i++){
// setup rows (output open drain)
GPIOA->MODER &= ~(0x3 << (i*2));
GPIOA->MODER |= (0x1 << (i*2));
GPIOA->OTYPER |= (1 << i);
}
for (int i = 0; i < number_of_columns; i++){
// setup columns (input pullup)
GPIOC->MODER &= ~(0x3 << (i*2));
GPIOC->PUPDR &= ~(0x3 << (i*2));
GPIOC->PUPDR |= (0x1 << (i*2));
}
}
/* This disable the all the row except for the specified one
It is usefull to test if a specific key is pressed */
void activate_row(uint8_t row_nb){
// set all row to 0 and then reenable selected row
for(int i =0; i < number_of_rows; i++){
set_output_pin(GPIO_A, i, true);
}
set_output_pin(GPIO_A, row_nb, false);
us_wait(100);
}
/* Scans the current state of the keyboard and returns an array of buttons struct
You can find the button struct definition in keyboard.h */
struct button* keyboard_scan(){
static struct button result_button_list[54] = {};
uint8_t i = 0;
for(int r = 0; r < number_of_rows; r++){
activate_row(r);
for(int c = 0; c < number_of_columns; c++){
bool key_state = read_input_pin(GPIO_C, c);
result_button_list[i].row = row_list[r];
result_button_list[i].column = c + 1;
result_button_list[i].state = key_state;
i++;
}
}
return result_button_list;
}
/* Scans the specified key and return true if pressed
It's more performant that scanning the whole keyboard */
bool get_key(char row, uint8_t column){
for(int i = 0; i < number_of_rows; i++){
if(row==row_list[i]){
activate_row(i);
return(read_input_pin(GPIO_C, column));
}
}
return false;
}

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/** @file keyboard.h
*
* @brief All action related to keyboard scan
*
*/
#ifndef KEYBOARD_H
#define KEYBOARD_H
#include "gpio_helper.h"
struct button{
uint8_t column; // ie: 2
char row; // ie: 'A'
bool state; // true is pressed and false released
};
/* This should be called before accessing any other keyboard related feature
as it sets up all keyboard related peripherals */
void keyboard_init();
/* Scans the current state of the keyboard and returns an array of buttons struct
You can find the button struct definition in keyboard.h */
struct button* keyboard_scan();
/* Scans the specified key and return true if pressed
It's more performant that scanning the whole keyboard */
bool get_key(char row, uint8_t column);
#endif

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#include "laplace.h"
/* Initialize all needed peripherals, should be called early in your program */
void laplace_init(){
/* led init */
enable_gpio_x_rcc(GPIO_B);
led_init();
/* keyboard init */
enable_gpio_x_rcc(GPIO_C); //column (in)
enable_gpio_x_rcc(GPIO_A); //row (out)
keyboard_init();
init_clock();
}

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src/Laplace/laplace.h Normal file
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/** @file laplace.h
*
* @brief Global function of Laplace
*
*/
#ifndef LAPLACE_H
#define LAPLACE_H
#include "gpio_helper.h"
#include "led.h"
#include "keyboard.h"
#include "clock.h"
/* Initialize all needed peripherals, should be called early in your program */
void laplace_init();
#endif

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#include "led.h"
// GPIOB for all the leds
uint8_t gpio_b = GPIO_B;
/* This should be called before accessing any other led related feature
as it sets up all led related peripherals */
void led_init(){
// It should be set to push-pull low-speed output.
// setup red led
GPIOB->MODER &= ~(0x3 << (RED_LED_PIN*2));
GPIOB->MODER |= (0x1 << (RED_LED_PIN*2));
GPIOB->OTYPER &= ~(1 << RED_LED_PIN);
// setup green led
GPIOB->MODER &= ~(0x3 << (GREEN_LED_PIN*2));
GPIOB->MODER |= (0x1 << (GREEN_LED_PIN*2));
GPIOB->OTYPER &= ~(1 << GREEN_LED_PIN);
// setup blue led
GPIOB->MODER &= ~(0x3 << (BLUE_LED_PIN*2));
GPIOB->MODER |= (0x1 << (BLUE_LED_PIN*2));
GPIOB->OTYPER &= ~(1 << BLUE_LED_PIN);
}
/* Set the status of the red led
true -> ON
false -> OFF */
void set_led_red(bool state){
set_output_pin(gpio_b, RED_LED_PIN, state);
}
/* Set the status of the green led
true -> ON
false -> OFF */
void set_led_green(bool state){
set_output_pin(gpio_b, GREEN_LED_PIN, state);
}
/* Set the status of the blue led
true -> ON
false -> OFF */
void set_led_blue(bool state){
set_output_pin(gpio_b, BLUE_LED_PIN, state);
}
/* Set the status of all 3 leds at the same time
true -> ON
false -> OFF */
void set_led_all(bool state){
set_output_pin(gpio_b, RED_LED_PIN, state);
set_output_pin(gpio_b, GREEN_LED_PIN, state);
set_output_pin(gpio_b, BLUE_LED_PIN, state);
}

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/** @file led.h
*
* @brief Control the led
*
*/
#ifndef LED_H
#define LED_H
#define RED_LED_PIN (4)
#define GREEN_LED_PIN (5)
#define BLUE_LED_PIN (0)
#include <stdbool.h>
#include "../device/stm32f730xx.h"
#include "gpio_helper.h"
/* This should be called before accessing any other led related feature
as it sets up all led related peripherals */
void led_init();
/* Set the status of the red led
true -> ON
false -> OFF */
void set_led_red(bool state);
/* Set the status of the green led
true -> ON
false -> OFF */
void set_led_green(bool state);
/* Set the status of the blue led
true -> ON
false -> OFF */
void set_led_blue(bool state);
/* Set the status of all 3 leds at the same time
true -> ON
false -> OFF */
void set_led_all(bool state);
#endif

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#include "time.h"
/* Pause the os for x micro seconds */
void us_wait(uint8_t micro_seconds) {
for (volatile uint32_t i=0; i<loops_per_microsecond*micro_seconds; i++) {
__asm volatile("nop");
}
}
/* Pause the os for x milli seconds */
void ms_wait(uint16_t milli_seconds) {
for (volatile uint32_t i=0; i<loops_per_millisecond*milli_seconds; i++) {
__asm volatile("nop");
}
}

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/** @file time.h
*
* @brief Handle timer operation
*
*/
#ifndef TIME_H
#define TIME_H
#define loops_per_microsecond 1
#define loops_per_millisecond 12000
#include "stdint.h"
/* Pause the os for x micro seconds */
void us_wait(uint8_t micro_seconds);
/* Pause the os for x milli seconds */
void ms_wait(uint16_t milli_seconds);
#endif

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/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**************************************************************************//**
* @file core_cmSimd.h
* @brief CMSIS Cortex-M SIMD Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#pragma clang system_header /* treat file as system include file */
#endif
#ifndef __CORE_CMSIMD_H
#define __CORE_CMSIMD_H
#ifdef __cplusplus
extern "C" {
#endif
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
/*------------------ RealView Compiler -----------------*/
#if defined ( __CC_ARM )
#include "cmsis_armcc.h"
/*------------------ ARM Compiler V6 -------------------*/
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include "cmsis_armcc_V6.h"
/*------------------ GNU Compiler ----------------------*/
#elif defined ( __GNUC__ )
#include "cmsis_gcc.h"
/*------------------ ICC Compiler ----------------------*/
#elif defined ( __ICCARM__ )
#include <cmsis_iar.h>
/*------------------ TI CCS Compiler -------------------*/
#elif defined ( __TMS470__ )
#include <cmsis_ccs.h>
/*------------------ TASKING Compiler ------------------*/
#elif defined ( __TASKING__ )
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
/*------------------ COSMIC Compiler -------------------*/
#elif defined ( __CSMC__ )
#include <cmsis_csm.h>
#endif
/*@} end of group CMSIS_SIMD_intrinsics */
#ifdef __cplusplus
}
#endif
#endif /* __CORE_CMSIMD_H */

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/**
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
* - To use or not the peripheral's drivers in application code(i.e.
* code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx
* @{
*/
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F7)
#define STM32F7
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F765xx) && \
!defined (STM32F767xx) && !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && \
!defined (STM32F722xx) && !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && \
!defined (STM32F730xx) && !defined (STM32F750xx)
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
STM32F756NG Devices */
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
/* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
STM32F769NG, STM32F769NI, STM32F768AI Devices */
/* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
/* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
/* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
STM32F722VC, STM32F722RC Devices */
/* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
/* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
/* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
/* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */
/* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
/*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V1.2.8
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F7_CMSIS_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
|(__STM32F7_CMSIS_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F722xx)
#include "stm32f722xx.h"
#elif defined(STM32F723xx)
#include "stm32f723xx.h"
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
#include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
#include "stm32f746xx.h"
#elif defined(STM32F745xx)
#include "stm32f745xx.h"
#elif defined(STM32F765xx)
#include "stm32f765xx.h"
#elif defined(STM32F767xx)
#include "stm32f767xx.h"
#elif defined(STM32F769xx)
#include "stm32f769xx.h"
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
#include "stm32f779xx.h"
#elif defined(STM32F730xx)
#include "stm32f730xx.h"
#elif defined(STM32F750xx)
#include "stm32f750xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
SUCCESS = 0U,
ERROR = !SUCCESS
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macro
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/* Use of CMSIS compiler intrinsics for register exclusive access */
/* Atomic 32-bit register access macro to set one or several bits */
#define ATOMIC_SET_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear one or several bits */
#define ATOMIC_CLEAR_BIT(REG, BIT) \
do { \
uint32_t val; \
do { \
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 32-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
do { \
uint32_t val; \
do { \
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to set one or several bits */
#define ATOMIC_SETH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear one or several bits */
#define ATOMIC_CLEARH_BIT(REG, BIT) \
do { \
uint16_t val; \
do { \
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/* Atomic 16-bit register access macro to clear and set one or several bits */
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
do { \
uint16_t val; \
do { \
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
} while(0)
/**
* @}
*/
#ifdef USE_HAL_DRIVER
#include "stm32f7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F7xx_H */
/**
* @}
*/
/**
* @}
*/

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/**
******************************************************************************
* @file system_stm32f7xx.h
* @author MCD Application Team
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
******************************************************************************
* @attention
*
* Copyright (c) 2016 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f7xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F7XX_H
#define __SYSTEM_STM32F7XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F7xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Variables
* @{
*/
/* The SystemCoreClock variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F7xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F7XX_H */
/**
* @}
*/
/**
* @}
*/

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#include <assert.h>
#include <stdint.h>
#include <stddef.h>
#define byte4 0xFF, 0xFF, 0xFF, 0xFF
#define byte8 byte4, byte4
#define byte16 byte8, byte8
#define byte32 byte16, byte16
#define byte64 byte32, byte32
#define byte128 byte64, byte64
#define byte256 byte128, byte128
#define byte512 byte256, byte256
#define byte1K byte512, byte512
#define byte2K byte1K, byte1K
#define byte4K byte2K, byte2K
#define EXAM_BUFFER_CONTENT byte4K
constexpr static int ExamModeBufferSize = 4*1024;
uint32_t staticStorageArea = {0};
class KernelHeader {
public:
constexpr KernelHeader() :
m_header(Magic),
m_version{"0.0.0"},
m_patchLevel{"zeta"},
m_footer(Magic) { }
const char * version() const {
assert(m_header == Magic);
assert(m_footer == Magic);
return m_version;
}
const char * patchLevel() const {
assert(m_header == Magic);
assert(m_footer == Magic);
return m_patchLevel;
}
private:
constexpr static uint32_t Magic = 0xDEC00DF0;
uint32_t m_header;
const char m_version[8];
const char m_patchLevel[8];
uint32_t m_footer;
};
class UserlandHeader {
public:
constexpr UserlandHeader():
m_header(Magic),
m_expectedEpsilonVersion{"0.0.1"},
m_storageAddressRAM(0x20000AE8),
m_storageSizeRAM(0x0000EA60),
m_externalAppsFlashStart(0xFFFFFFFF),
m_externalAppsFlashEnd(0xFFFFFFFF),
m_externalAppsRAMStart(0xFFFFFFFF),
m_externalAppsRAMEnd(0xFFFFFFFF),
m_footer(Magic),
m_omegaMagicHeader(OmegaMagic),
m_omegaVersion{"0.0.2"},
m_username{"Ayabusa"},
m_omegaMagicFooter(OmegaMagic),
m_upsilonMagicHeader(UpsilonMagic),
m_UpsilonVersion{"0.0.3"},
m_osType(OSType),
m_upsilonMagicFooter(UpsilonMagic) { }
const char * omegaVersion() const {
assert(m_header == Magic);
assert(m_footer == Magic);
assert(m_omegaMagicHeader == OmegaMagic);
assert(m_omegaMagicFooter == OmegaMagic);
return m_omegaVersion;
}
const char * upsilonVersion() const {
assert(m_header == Magic);
assert(m_footer == Magic);
assert(m_omegaMagicHeader == OmegaMagic);
assert(m_omegaMagicFooter == OmegaMagic);
return m_UpsilonVersion;
}
const volatile char * username() const volatile {
assert(m_header == Magic);
assert(m_footer == Magic);
assert(m_omegaMagicHeader == OmegaMagic);
assert(m_omegaMagicFooter == OmegaMagic);
return m_username;
}
const void * storage_address() const {
return &staticStorageArea;
}
private:
constexpr static uint32_t Magic = 0xDEC0EDFE; // FEEDCODE in hex editor
constexpr static uint32_t OmegaMagic = 0xEFBEADDE; // DEADBEEF in hex editor
constexpr static uint32_t UpsilonMagic = 0x55707369; // Upsi (reverse) in hex editor (ASCII)
constexpr static uint32_t OSType = 0x79827178;
uint32_t m_header;
const char m_expectedEpsilonVersion[8];
uint32_t m_storageAddressRAM;
uint32_t m_storageSizeRAM;
/* We store the range addresses of external apps memory because storing the
* size is complicated due to c++11 constexpr. */
uint32_t m_externalAppsFlashStart;
uint32_t m_externalAppsFlashEnd;
uint32_t m_externalAppsRAMStart;
uint32_t m_externalAppsRAMEnd;
uint32_t m_footer;
uint32_t m_omegaMagicHeader;
const char m_omegaVersion[16];
const volatile char m_username[16];
uint32_t m_omegaMagicFooter;
uint32_t m_upsilonMagicHeader;
const char m_UpsilonVersion[16];
uint32_t m_osType;
uint32_t m_upsilonMagicFooter;
};
// kernel header defined in linker
const KernelHeader __attribute__((section(".kernel_header"), used)) k_kernelHeader;
// userland header defined in linker
const UserlandHeader __attribute__((section(".userland_header"), used)) k_userlandHeader;
// Exam mode defined in linker
char ones[ExamModeBufferSize]
__attribute__((section(".exam_mode_buffer")))
__attribute__((used))
= {EXAM_BUFFER_CONTENT};

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/* This is the linker file it required to map out the memory.
* This linker is heavely inspired by epsilon/omega/upsilon and their bootloader_common.ld.
* It is necessary if we want our os to be considered as valid.
* At this time we can only compile this os to slot B, but it might change in the future */
/* numworks stuff */
STACK_SIZE = 32K;
FIRST_FLASH_SECTOR_SIZE = 4K;
SIGNED_PAYLOAD_LENGTH = 8;
USERLAND_OFFSET = 64K;
/* Set minimum size for stack and dynamic memory. */
/* (The linker will generate an error if there is
* less than this much RAM leftover.) */
/* (1KB) */
_Min_Leftover_RAM = 0x400;
MEMORY
{
FLASH ( rx ) : ORIGIN = 0x90400000, LENGTH = 4M /* This is for the B slot */
RAM ( rxw ) : ORIGIN = 0x20000000, LENGTH = 256K
}
SECTIONS
{
/* epsilon stuff */
.signed_payload_prefix ORIGIN(FLASH) : {
FILL(0xFF);
BYTE(0xFF)
. = ORIGIN(FLASH) + SIGNED_PAYLOAD_LENGTH;
} >FLASH
/* Contains some info and is requiered to be considered as a valid slot by the bootloader.
* Located in info_headers.cpp */
.kernel_header : {
KEEP(*(.kernel_header))
} >FLASH
/* Nothing in there for now */
.slot_info : {
*(.slot_info*)
} >RAM
/* The vector table (handle all the interrupts) located in vector_table.cpp */
.isr_vector_table ORIGIN(RAM) + 512 : AT(ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header)) {
/* When booting, the STM32F412 fetches the content of address 0x0, and
* extracts from it various key infos: the initial value of the PC register
* (program counter), the initial value of the stack pointer, and various
* entry points to interrupt service routines. This data is called the ISR
* vector table.
*
* Note that address 0x0 is always an alias. It points to the beginning of
* Flash, SRAM, or integrated bootloader depending on the boot mode chosen.
* (This mode is chosen by setting the BOOTn pins on the chip).
*
* We're generating the ISR vector table in code because it's very
* convenient: using function pointers, we can easily point to the service
* routine for each interrupt. */
_isr_vector_table_start_flash = LOADADDR(.isr_vector_table);
_isr_vector_table_start_ram = .;
KEEP(*(.isr_vector_table))
_isr_vector_table_end_ram = .;
} >RAM
/* this is to prevent the bootloader from booting straight up in our os (we set all to 0) */
.exam_mode_buffer ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header) + SIZEOF(.isr_vector_table) : {
. = ALIGN(4K);
_exam_mode_buffer_start = .;
KEEP(*(.exam_mode_buffer))
/* Note: We don't increment "." here, we set it. */
. = . + FIRST_FLASH_SECTOR_SIZE;
_exam_mode_buffer_end = .;
} >FLASH
/* Contains some more info and is requiered to be considered as a valid slot by the bootloader.
* Located in info_headers.cpp */
.userland_header : {
. = ORIGIN(FLASH) + USERLAND_OFFSET;
KEEP(*(.userland_header));
} > FLASH
.text : {
. = ALIGN(4);
*(.text)
*(.text.*)
} >FLASH
/* The 'rodata' section contains read-only data,
* constants, strings, information that won't change. */
.rodata : {
*(.rodata)
*(.rodata.*)
} >FLASH
/* TODO, understand what is it's purpose */
.init_array : {
. = ALIGN(4);
_init_array_start = .;
KEEP (*(.init_array*))
_init_array_end = .;
} >FLASH
/* The 'data' section is space set aside in RAM for
* things like variables, which can change. */
.data : {
/* The data section is written to Flash but linked as if it were in RAM.
*
* This is required because its initial value matters (so it has to be in
* persistant memory in the first place), but it is a R/W area of memory
* so it will have to live in RAM upon execution (in linker lingo, that
* translates to the data section having a LMA in Flash and a VMA in RAM).
*
* This means we'll have to copy it from Flash to RAM on initialization.
* To do this, we'll need to know the source location of the data section
* (in Flash), the target location (in RAM), and the size of the section.
* That's why we're defining three symbols that we'll use in the initial-
* -ization routine. */
. = ALIGN(4);
_data_section_start_flash = LOADADDR(.data);
_data_section_start_ram = .;
*(.data)
*(.data.*)
_data_section_end_ram = .;
} >RAM AT> FLASH
/* The 'bss' section is similar to the 'data' section,
* but its space is initialized to all 0s at the
* start of the program. */
.bss : {
/* The bss section contains data for all uninitialized variables
* So like the .data section, it will go in RAM, but unlike the data section
* we don't care at all about an initial value.
*
* Before execution, crt0 will erase that section of memory though, so we'll
* need pointers to the beginning and end of this section. */
. = ALIGN(4);
_bss_section_start_ram = .;
*(.bss)
*(.bss.*)
/* The compiler may choose to allocate uninitialized global variables as
* COMMON blocks. This can be disabled with -fno-common if needed. */
*(COMMON)
_bss_section_end_ram = .;
} >RAM
.heap : {
_heap_start = .;
/* Note: We don't increment "." here, we set it. */
. = (ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE);
_heap_end = .;
} >RAM
.stack : {
. = ALIGN(8);
_stack_end = .;
. += (STACK_SIZE - 8);
. = ALIGN(8);
_stack_start = .;
} >RAM
/DISCARD/ : {
/* exidx and extab are needed for unwinding, which we don't use */
*(.ARM.exidx*)
*(.ARM.extab*)
}
}

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#include "main.h"
// this is our main function, I separated it from the c++ code because I don't like this language
void main_entry(){
// init all the peripherals
laplace_init();
// infinite loop
while (1){
/*
struct button * keyboard_state = keyboard_scan();
for(int i =0; i < 54; i++){
if(keyboard_state[i].column == 4 && keyboard_state[i].row == 'H'){
if(keyboard_state[i].state){
set_led_blue(true);
}else{
set_led_blue(false);
}
}
if(keyboard_state[i].column == 3 && keyboard_state[i].row == 'H'){
if(keyboard_state[i].state){
set_led_green(true);
}else{
set_led_green(false);
}
}
}*/
/*
if(get_key('G', 3)){
set_led_red(true);
}else{
set_led_red(false);
}*/
set_led_blue(true);
ms_wait(5000);
set_led_blue(false);
ms_wait(5000);
}
}

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/** @file main.h
*
* @brief The main programm
*
*/
#ifndef MAIN_H
#define MAIN_H
#include "Laplace/laplace.h"
#include "Laplace/led.h"
#include "Laplace/keyboard.h"
#include "Laplace/time.h"
/* our main function */
void main_entry();
#endif

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#include "vector_table.h"
#include <stddef.h>
#include <stdint.h>
#include "device/stm32f730xx.h"
extern "C" {
#include "main.h"
}
//#define LED_PIN (4) // PB0
typedef void (*cxx_constructor)();
extern "C" {
extern char _data_section_start_flash;
extern char _data_section_start_ram;
extern char _data_section_end_ram;
extern char _bss_section_start_ram;
extern char _bss_section_end_ram;
extern cxx_constructor _init_array_start;
extern cxx_constructor _init_array_end;
}
void* memcpy_custom(void* destination, const void* source, size_t num_bytes) {
char* dest_ptr = (char*)destination;
const char* src_ptr = (const char*)source;
// Copy each byte from source to destination
for (size_t i = 0; i < num_bytes; ++i) {
dest_ptr[i] = src_ptr[i];
}
return destination;
}
void* memset_custom(void* ptr, int value, size_t num_bytes) {
unsigned char* p = (unsigned char*)ptr;
unsigned char v = (unsigned char)value;
// Set each byte in the memory block to the specified value
for (size_t i = 0; i < num_bytes; ++i) {
p[i] = v;
}
return ptr;
}
// This the first function when the os boot
void __attribute__((noinline)) start() {
/* Copy data section to RAM
* The data section is R/W but its initialization value matters. It's stored
* in Flash, but linked as if it were in RAM. Now's our opportunity to copy
* it. Note that until then the data section (e.g. global variables) contains
* garbage values and should not be used. */
size_t dataSectionLength = (&_data_section_end_ram - &_data_section_start_ram);
memcpy_custom(&_data_section_start_ram, &_data_section_start_flash, dataSectionLength);
/* Zero-out the bss section in RAM
* Until we do, any uninitialized global variable will be unusable. */
size_t bssSectionLength = (&_bss_section_end_ram - &_bss_section_start_ram);
memset_custom(&_bss_section_start_ram, 0, bssSectionLength);
main_entry();
}

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#include "vector_table.h"
extern const void * _stack_start;
/* Interrupt Service Routines are void->void functions */
typedef void(*ISR)(void);
/* Notice: The Cortex-M4 expects all jumps to be made at an odd address when
* jumping to Thumb code. For example, if you want to execute Thumb code at
* address 0x100, you'll have to jump to 0x101. Luckily, this idiosyncrasy is
* properly handled by the C compiler that will generate proper addresses when
* using function pointers. */
#define INITIALISATION_VECTOR_SIZE 0x71
ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
__attribute__((section(".isr_vector_table")))
__attribute__((used))
= {
(ISR)&_stack_start, // Stack start
start, // Reset service routine,
0, // NMI service routine,
0, // HardFault service routine,
0, // MemManage service routine,
0, // BusFault service routine,
0, // UsageFault service routine,
0, 0, 0, 0, // Reserved
0, // SVCall service routine,
0, // DebugMonitor service routine,
0, // Reserved
0, // PendSV service routine,
0, // SysTick service routine
0, // WWDG service routine
0, // PVD service routine
0, // TampStamp service routine
0, // RtcWakeup service routine
0, // Flash service routine
0, // RCC service routine
0, // EXTI0 service routine
0, // EXTI1 service routine
0, // EXTI2 service routine
0, // EXTI3 service routine
0, // EXTI4 service routine
0, // DMA1Stream0 service routine
0, // DMA1Stream1 service routine
0, // DMA1Stream2 service routine
0, // DMA1Stream3 service routine
0, // DMA1Stream4 service routine
0, // DMA1Stream5 service routine
0, // DMA1Stream6 service routine
0, // ADC1 global interrupt
0, // CAN1 TX interrupt
0, // CAN1 RX0 interrupt
0, // CAN1 RX1 interrupt
0, // CAN1 SCE interrupt
0, // EXTI Line[9:5] interrupts
0, // TIM1 Break interrupt and TIM9 global interrupt
0, // TIM1 update interrupt and TIM10 global interrupt
0, // TIM1 Trigger & Commutation interrupts and TIM11 global interrupt
0, // TIM1 Capture Compare interrupt
0, // TIM2 global interrupt
0, // TIM3 global interrupt
0, // TIM4 global interrupt
0, // I2C1 global event interrupt
0, // I2C1 global error interrupt
0, // I2C2 global event interrupt
0, // I2C2 global error interrupt
0, // SPI1 global interrupt
0, // SPI2 global interrupt
0, // USART1 global interrupt
0, // USART2 global interrupt
0, // USART3 global interrupt
0, // EXTI Line[15:10] interrupts
0, // EXTI Line 17 interrupt RTC Alarms (A and B) through EXTI line interrupt
0, // EXTI Line 18 interrupt / USB On-The-Go FS Wakeup through EXTI line interrupt
0, // TIM8 Break interrupt TIM12 global interrupt
0, // TIM8 Update interrupt TIM13 global interrupt
0, // TIM8 Trigger & Commutation interrupt TIM14 global interrupt
0, // TIM8 Cap/Com interrupt
0, // DMA1 global interrupt Channel 7
0, // FSMC global interrupt
0, // SDIO global interrupt
0, // TIM5 global interrupt
0, // SPI3 global interrupt
0, // ?
0, // ?
0, // TIM6 global interrupt
0, // TIM7 global interrupt
0, // DMA2 Stream0 global interrupt
0, // DMA2 Stream1 global interrupt
0, // DMA2 Stream2 global interrupt
0, // DMA2 Stream3 global interrupt
0, // DMA2 Stream4 global interrupt
0, // SD filter0 global interrupt
0, // SD filter1 global interrupt
0, // CAN2 TX interrupt
0, // BXCAN2 RX0 interrupt
0, // BXCAN2 RX1 interrupt
0, // CAN2 SCE interrupt
0, // USB On The Go FS global interrupt
0, // DMA2 Stream5 global interrupts
0, // DMA2 Stream6 global interrupt
0, // DMA2 Stream7 global interrupt
0, // USART6 global interrupt
0, // I2C3 event interrupt
0, // I2C3 error interrupt
0, // ?
0, // ?
0, // ?
0, // ?
0, // ?
0, // ?
0, // RNG global interrupt
0, // FPU global interrupt
0, // ?
0, // ?
0, // SPI4 global interrupt
0, // SPI5 global interrupt
0, // ?
0, // ?
0, // ?
0, // ?
0, // ?
0, // ?
0, // Quad-SPI global interrupt
0, // ?
0, // ?
0, // I2CFMP1 event interrupt
0 // I2CFMP1 error interrupt
};

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#ifndef VECTOR_TABLE_H
#define VECTOR_TABLE_H
#ifdef __cplusplus
extern "C" {
#endif
void start();
void abort();
void isr_systick();
// Fault handlers
void hard_fault_handler();
void mem_fault_handler();
void usage_fault_handler();
void bus_fault_handler();
#ifdef __cplusplus
}
#endif
#endif