--- /dev/null
+{
+ "configurations": [
+ {
+ "name": "Linux",
+ "includePath": [
+ "${workspaceFolder}/**"
+ ],
+ "defines": [],
+ "compilerPath": "/usr/bin/gcc",
+ "cStandard": "c17",
+ "cppStandard": "gnu++17",
+ "intelliSenseMode": "linux-gcc-x64"
+ }
+ ],
+ "version": 4
+}
\ No newline at end of file
--- /dev/null
+{
+ "files.associations": {
+ "cstdint": "cpp",
+ "cstring": "cpp",
+ "atomic": "cpp",
+ "string": "cpp",
+ "unordered_map": "cpp",
+ "vector": "cpp",
+ "iterator": "cpp",
+ "memory_resource": "cpp",
+ "string_view": "cpp",
+ "functional": "cpp",
+ "istream": "cpp",
+ "new": "cpp",
+ "ostream": "cpp",
+ "stdexcept": "cpp",
+ "streambuf": "cpp",
+ "system_error": "cpp",
+ "tuple": "cpp"
+ }
+}
\ No newline at end of file
+++ /dev/null
-TARGET = main
-
-# Directories
-SRC_DIR = src
-BUILD_DIR = build
-
-# Define the linker script location and chip architecture.
-LD_SCRIPT = $(SRC_DIR)/linker.ld
-MCU_SPEC = cortex-m0
-
-# Toolchain definitions (ARM bare metal defaults)
-TOOLCHAIN = /usr
-CC = $(TOOLCHAIN)/bin/arm-none-eabi-gcc
-AS = $(TOOLCHAIN)/bin/arm-none-eabi-as
-LD = $(TOOLCHAIN)/bin/arm-none-eabi-ld
-OC = $(TOOLCHAIN)/bin/arm-none-eabi-objcopy
-OD = $(TOOLCHAIN)/bin/arm-none-eabi-objdump
-OS = $(TOOLCHAIN)/bin/arm-none-eabi-size
-
-# Assembly directives.
-ASFLAGS += -c
-ASFLAGS += -O0
-ASFLAGS += -mcpu=$(MCU_SPEC)
-ASFLAGS += -mthumb
-ASFLAGS += -Wall
-# (Set error messages to appear on a single line.)
-ASFLAGS += -fmessage-length=0
-
-# C compilation directives
-CFLAGS += -mcpu=$(MCU_SPEC)
-CFLAGS += -mthumb
-CFLAGS += -Wall
-CFLAGS += -g
-# (Set error messages to appear on a single line.)
-CFLAGS += -fmessage-length=0
-# (Set system to ignore semihosted junk)
-CFLAGS += --specs=nosys.specs
-
-# Linker directives.
-LSCRIPT = $(LD_SCRIPT)
-LFLAGS += -mcpu=$(MCU_SPEC)
-LFLAGS += -mthumb
-LFLAGS += -Wall
-LFLAGS += --specs=nosys.specs
-LFLAGS += -nostdlib
-LFLAGS += -lgcc
-LFLAGS += -T$(LSCRIPT)
-
-VECT_TBL = $(SRC_DIR)/vector_table.S
-AS_SRC = $(SRC_DIR)/core.S
-C_SRC = $(SRC_DIR)/main.c
-
-INCLUDE = -I./
-INCLUDE += -I./device
-
-OBJS = $(BUILD_DIR)/$(notdir $(VECT_TBL:.S=.o))
-OBJS += $(BUILD_DIR)/$(notdir $(AS_SRC:.S=.o))
-OBJS += $(BUILD_DIR)/$(notdir $(C_SRC:.c=.o))
-
-.PHONY: all
-all: $(BUILD_DIR)/$(TARGET).bin
-
-$(BUILD_DIR)/%.o: $(SRC_DIR)/%.S
- $(CC) -x assembler-with-cpp $(ASFLAGS) $< -o $@
-
-$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
- $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
-
-$(BUILD_DIR)/$(TARGET).elf: $(OBJS)
- $(CC) $^ $(LFLAGS) -o $@
-
-$(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
- $(OC) -S -O binary $< $@
- $(OS) $<
-
-.PHONY: clean
-clean:
- rm -f $(BUILD_DIR)/*.o
- rm -f $(BUILD_DIR)/$(TARGET).elf
- rm -f $(BUILD_DIR)/$(TARGET).bin
\ No newline at end of file
--- /dev/null
+TARGET = main
+
+# Directories
+SRC_DIR = src
+BUILD_DIR = build
+
+# Define the linker script location and chip architecture.
+LD_SCRIPT = $(SRC_DIR)/linker.ld
+MCU_SPEC = cortex-m0
+
+# Toolchain definitions (ARM bare metal defaults)
+TOOLCHAIN = /usr
+CC = $(TOOLCHAIN)/bin/arm-none-eabi-gcc
+AS = $(TOOLCHAIN)/bin/arm-none-eabi-as
+LD = $(TOOLCHAIN)/bin/arm-none-eabi-ld
+OC = $(TOOLCHAIN)/bin/arm-none-eabi-objcopy
+OD = $(TOOLCHAIN)/bin/arm-none-eabi-objdump
+OS = $(TOOLCHAIN)/bin/arm-none-eabi-size
+
+# Assembly directives.
+ASFLAGS += -c
+ASFLAGS += -O0
+ASFLAGS += -mcpu=$(MCU_SPEC)
+ASFLAGS += -mthumb
+ASFLAGS += -Wall
+# (Set error messages to appear on a single line.)
+ASFLAGS += -fmessage-length=0
+
+# C compilation directives
+CFLAGS += -mcpu=$(MCU_SPEC)
+CFLAGS += -mthumb
+CFLAGS += -Wall
+CFLAGS += -g
+# (Set error messages to appear on a single line.)
+CFLAGS += -fmessage-length=0
+# (Set system to ignore semihosted junk)
+CFLAGS += --specs=nosys.specs
+
+# Linker directives.
+LSCRIPT = $(LD_SCRIPT)
+LFLAGS += -mcpu=$(MCU_SPEC)
+LFLAGS += -mthumb
+LFLAGS += -Wall
+LFLAGS += --specs=nosys.specs
+LFLAGS += -nostdlib
+LFLAGS += -lgcc
+LFLAGS += -T$(LSCRIPT)
+
+VECT_TBL = $(SRC_DIR)/vector_table.S
+AS_SRC = $(SRC_DIR)/core.S
+C_SRC = $(SRC_DIR)/main.c
+
+INCLUDE = -I./
+INCLUDE += -I./device
+
+OBJS = $(BUILD_DIR)/$(notdir $(VECT_TBL:.S=.o))
+OBJS += $(BUILD_DIR)/$(notdir $(AS_SRC:.S=.o))
+OBJS += $(BUILD_DIR)/$(notdir $(C_SRC:.c=.o))
+
+.PHONY: all
+all: $(BUILD_DIR)/$(TARGET).bin
+
+$(BUILD_DIR)/%.o: $(SRC_DIR)/%.S
+ $(CC) -x assembler-with-cpp $(ASFLAGS) $< -o $@
+
+$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
+ $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJS)
+ $(CC) $^ $(LFLAGS) -o $@
+
+$(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
+ $(OC) -S -O binary $< $@
+ $(OS) $<
+
+.PHONY: clean
+clean:
+ rm -f $(BUILD_DIR)/*.o
+ rm -f $(BUILD_DIR)/$(TARGET).elf
+ rm -f $(BUILD_DIR)/$(TARGET).bin
\ No newline at end of file
--- /dev/null
+.syntax unified
+.cpu cortex-m0
+.fpu softvfp
+.thumb
+
+// Global values.
+.global reset_handler
+
+/*
+ * The Reset handler. Called on reset.
+ */
+.type reset_handler, %function
+reset_handler:
+ // Set the stack pointer to the end of the stack.
+ // The '_estack' value is defined in our linker script.
+ LDR r0, =_estack
+ MOV sp, r0
+
+ // Copy data from flash to RAM data init section.
+ // R2 will store our progress along the sidata section.
+ MOVS r0, #0
+ // Load the start/end addresses of the data section,
+ // and the start of the data init section.
+ LDR r1, =_sdata
+ LDR r2, =_edata
+ LDR r3, =_sidata
+ B copy_sidata_loop
+
+ copy_sidata:
+ // Offset the data init section by our copy progress.
+ LDR r4, [r3, r0]
+ // Copy the current word into data, and increment.
+ STR r4, [r1, r0]
+ ADDS r0, r0, #4
+
+ copy_sidata_loop:
+ // Unless we've copied the whole data section, copy the
+ // next word from sidata->data.
+ ADDS r4, r0, r1
+ CMP r4, r2
+ BCC copy_sidata
+
+ // Once we are done copying the data section into RAM,
+ // move on to filling the BSS section with 0s.
+ MOVS r0, #0
+ LDR r1, =_sbss
+ LDR r2, =_ebss
+ B reset_bss_loop
+
+ // Zero out the BSS segment.
+ reset_bss:
+ // Store a 0 and increment by a word.
+ STR r0, [r1]
+ ADDS r1, r1, #4
+
+ reset_bss_loop:
+ // We'll use R1 to count progress here; if we aren't
+ // done, reset the next word and increment.
+ CMP r1, r2
+ BCC reset_bss
+
+ // Branch to the 'main' method.
+ B main
+.size reset_handler, .-reset_handler
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U)\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**
+ * @file core_cm4.h
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version V4.30
+ * @date 20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+ All rights reserved.
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions are met:
+ - Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ - Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+ - Neither the name of ARM nor the names of its contributors may be used
+ to endorse or promote products derived from this software without
+ specific prior written permission.
+ *
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ POSSIBILITY OF SUCH DAMAGE.
+ ---------------------------------------------------------------------------*/
+
+
+#if defined ( __ICCARM__ )
+ #pragma system_include /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
+ CMSIS violates the following MISRA-C:2004 rules:
+
+ \li Required Rule 8.5, object/function definition in header file.<br>
+ Function definitions in header files are used to allow 'inlining'.
+
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+ Unions are used for effective representation of core registers.
+
+ \li Advisory Rule 19.7, Function-like macro defined.<br>
+ Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ * CMSIS definitions
+ ******************************************************************************/
+/**
+ \ingroup Cortex_M4
+ @{
+ */
+
+/* CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+ __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+ #define __STATIC_INLINE static __inline
+
+#elif defined ( __GNUC__ )
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TMS470__ )
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __TASKING__ )
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */
+ #define __STATIC_INLINE static inline
+
+#elif defined ( __CSMC__ )
+ #define __packed
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+ #define __STATIC_INLINE static inline
+
+#else
+ #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+ #if defined __TARGET_FPU_VFP
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+ #if defined __ARM_PCS_VFP
+ #if (__FPU_PRESENT == 1)
+ #define __FPU_USED 1U
+ #else
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __GNUC__ )
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __ICCARM__ )
+ #if defined __ARMVFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TMS470__ )
+ #if defined __TI_VFP_SUPPORT__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __TASKING__ )
+ #if defined __FPU_VFP__
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#elif defined ( __CSMC__ )
+ #if ( __CSMC__ & 0x400U)
+ #if (__FPU_PRESENT == 1U)
+ #define __FPU_USED 1U
+ #else
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+ #define __FPU_USED 0U
+ #endif
+ #else
+ #define __FPU_USED 0U
+ #endif
+
+#endif
+
+#include "core_cmInstr.h" /* Core Instruction Access */
+#include "core_cmFunc.h" /* Core Function Access */
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+ #ifndef __CM4_REV
+ #define __CM4_REV 0x0000U
+ #warning "__CM4_REV not defined in device header file; using default!"
+ #endif
+
+ #ifndef __FPU_PRESENT
+ #define __FPU_PRESENT 0U
+ #warning "__FPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __MPU_PRESENT
+ #define __MPU_PRESENT 0U
+ #warning "__MPU_PRESENT not defined in device header file; using default!"
+ #endif
+
+ #ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4U
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+ #endif
+
+ #ifndef __Vendor_SysTickConfig
+ #define __Vendor_SysTickConfig 0U
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+ #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+ \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+ <strong>IO Type Qualifiers</strong> are used
+ \li to specify the access to peripheral variables.
+ \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+ #define __I volatile /*!< Defines 'read only' permissions */
+#else
+ #define __I volatile const /*!< Defines 'read only' permissions */
+#endif
+#define __O volatile /*!< Defines 'write only' permissions */
+#define __IO volatile /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define __IM volatile const /*! Defines 'read only' structure member permissions */
+#define __OM volatile /*! Defines 'write only' structure member permissions */
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ Core Register contain:
+ - Core Register
+ - Core NVIC Register
+ - Core SCB Register
+ - Core SysTick Register
+ - Core Debug Register
+ - Core MPU Register
+ - Core FPU Register
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_core_register Defines and Type Definitions
+ \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CORE Status and Control Registers
+ \brief Core Register type definitions.
+ @{
+ */
+
+/**
+ \brief Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos 31U /*!< APSR: N Position */
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
+
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
+
+#define APSR_C_Pos 29U /*!< APSR: C Position */
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
+
+#define APSR_V_Pos 28U /*!< APSR: V Position */
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
+
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
+
+
+/**
+ \brief Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
+
+
+/**
+ \brief Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+ struct
+ {
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
+ } b; /*!< Structure used for bit access */
+ uint32_t w; /*!< Type used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
+ \brief Type definitions for the NVIC Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
+ uint32_t RESERVED0[24U];
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24U];
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
+ uint32_t RESERVED2[24U];
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24U];
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
+ uint32_t RESERVED4[56U];
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
+ uint32_t RESERVED5[644U];
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
+} NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCB System Control Block (SCB)
+ \brief Type definitions for the System Control Block Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
+ __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
+ __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
+ __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
+ __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
+ __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
+ __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
+ uint32_t RESERVED0[5U];
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+ \brief Type definitions for the System Control and ID Register not in the SCB
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)
+ \brief Type definitions for the System Timer Registers.
+ @{
+ */
+
+/**
+ \brief Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+ __OM union
+ {
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864U];
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
+ uint32_t RESERVED1[15U];
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
+ uint32_t RESERVED2[15U];
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
+ uint32_t RESERVED3[29U];
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43U];
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
+ uint32_t RESERVED5[6U];
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
+ uint32_t RESERVED1[1U];
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
+ uint32_t RESERVED2[1U];
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)
+ \brief Type definitions for the Trace Port Interface (TPI)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
+ uint32_t RESERVED0[2U];
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
+ uint32_t RESERVED1[55U];
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
+ uint32_t RESERVED2[131U];
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
+ uint32_t RESERVED3[759U];
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
+ uint32_t RESERVED4[1U];
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
+ uint32_t RESERVED5[39U];
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
+ uint32_t RESERVED7[8U];
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)
+ \brief Type definitions for the Memory Protection Unit (MPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)
+ \brief Type definitions for the Floating Point Unit (FPU)
+ @{
+ */
+
+/**
+ \brief Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+ uint32_t RESERVED0[1U];
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
+ \brief Type definitions for the Core Debug Registers
+ @{
+ */
+
+/**
+ \brief Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_bitfield Core register bit field macros
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+ @{
+ */
+
+/**
+ \brief Mask and shift a bit field value for use in a register bit range.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of the bit field.
+ \return Masked and shifted value.
+*/
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
+
+/**
+ \brief Mask and shift a register value to extract a bit filed value.
+ \param[in] field Name of the register bit field.
+ \param[in] value Value of register.
+ \return Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+ \ingroup CMSIS_core_register
+ \defgroup CMSIS_core_base Core Definitions
+ \brief Definitions for base addresses, unions, and structures.
+ @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
+
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ Core Function Interface contains:
+ - Core NVIC Functions
+ - Core SysTick Functions
+ - Core Debug Functions
+ - Core Register Access Functions
+ ******************************************************************************/
+/**
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ########################## NVIC functions #################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+ \brief Functions that manage interrupts and exceptions via the NVIC.
+ @{
+ */
+
+/**
+ \brief Set Priority Grouping
+ \details Sets the priority grouping field using the required unlock sequence.
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+ Only values from 0..7 are used.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+ uint32_t reg_value;
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
+ reg_value = (reg_value |
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+
+/**
+ \brief Get Priority Grouping
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+ \brief Enable External Interrupt
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Disable External Interrupt
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Pending Interrupt
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not pending.
+ \return 1 Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Pending Interrupt
+ \details Sets the pending bit of an external interrupt.
+ \param [in] IRQn Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Clear Pending Interrupt
+ \details Clears the pending bit of an external interrupt.
+ \param [in] IRQn External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+ \brief Get Active Interrupt
+ \details Reads the active register in NVIC and returns the active bit.
+ \param [in] IRQn Interrupt number.
+ \return 0 Interrupt status is not active.
+ \return 1 Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+ \brief Set Interrupt Priority
+ \details Sets the priority of an interrupt.
+ \note The priority cannot be set for every core interrupt.
+ \param [in] IRQn Interrupt number.
+ \param [in] priority Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+ if ((int32_t)(IRQn) < 0)
+ {
+ SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+ else
+ {
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+ }
+}
+
+
+/**
+ \brief Get Interrupt Priority
+ \details Reads the priority of an interrupt.
+ The interrupt number can be positive to specify an external (device specific) interrupt,
+ or negative to specify an internal (core) interrupt.
+ \param [in] IRQn Interrupt number.
+ \return Interrupt Priority.
+ Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if ((int32_t)(IRQn) < 0)
+ {
+ return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+ }
+ else
+ {
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
+ }
+}
+
+
+/**
+ \brief Encode Priority
+ \details Encodes the priority for an interrupt with the given priority group,
+ preemptive priority value, and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+ \param [in] PriorityGroup Used priority group.
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).
+ \param [in] SubPriority Subpriority value (starting from 0).
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ return (
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
+ );
+}
+
+
+/**
+ \brief Decode Priority
+ \details Decodes an interrupt priority value with a given priority group to
+ preemptive priority value and subpriority value.
+ In case of a conflict between priority grouping and available
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+ \param [in] PriorityGroup Used priority group.
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).
+ \param [out] pSubPriority Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
+ uint32_t PreemptPriorityBits;
+ uint32_t SubPriorityBits;
+
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
+}
+
+
+/**
+ \brief System Reset
+ \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+ __DSB(); /* Ensure all outstanding memory accesses included
+ buffered write are completed before reset */
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
+ __DSB(); /* Ensure completion of memory access */
+
+ for(;;) /* wait until reset */
+ {
+ __NOP();
+ }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ################################## SysTick function ############################################ */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+ \brief Functions that configure the System.
+ @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+ \brief System Tick Configuration
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+ Counter is in free running mode to generate periodic interrupts.
+ \param [in] ticks Number of ticks between two interrupts.
+ \return 0 Function succeeded.
+ \return 1 Function failed.
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+ must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ {
+ return (1UL); /* Reload value impossible */
+ }
+
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
+ SysTick_CTRL_TICKINT_Msk |
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
+ return (0UL); /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+ \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_core_DebugFunctions ITM Functions
+ \brief Functions that access the ITM debug interface.
+ @{
+ */
+
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+ \brief ITM Send Character
+ \details Transmits a character via the ITM channel 0, and
+ \li Just returns when no debugger is connected that has booked the output.
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+ \param [in] ch Character to transmit.
+ \returns Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
+ {
+ while (ITM->PORT[0U].u32 == 0UL)
+ {
+ __NOP();
+ }
+ ITM->PORT[0U].u8 = (uint8_t)ch;
+ }
+ return (ch);
+}
+
+
+/**
+ \brief ITM Receive Character
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.
+ \return Received character.
+ \return -1 No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+ int32_t ch = -1; /* no character available */
+
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+ {
+ ch = ITM_RxBuffer;
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
+ }
+
+ return (ch);
+}
+
+
+/**
+ \brief ITM Check Character
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+ \return 0 No character available.
+ \return 1 Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+ {
+ return (0); /* no character available */
+ }
+ else
+ {
+ return (1); /* character available */
+ }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
\ No newline at end of file
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f4xx.h\r
+ * @author MCD Application Team\r
+ * @version V1.2.0RC2 - edited by Keil\r
+ * @date 20-February-2013\r
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. \r
+ * This file contains all the peripheral register's definitions, bits \r
+ * definitions and memory mapping for STM32F4xx devices. \r
+ * \r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The device used in the target application\r
+ * - To use or not the peripheral�s drivers in application code(i.e. \r
+ * code will be based on direct access to peripheral�s registers \r
+ * rather than drivers API), this option is controlled by \r
+ * "#define USE_STDPERIPH_DRIVER"\r
+ * - To change few application-specific parameters such as the HSE \r
+ * crystal frequency\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral�s registers hardware\r
+ * \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+ *\r
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+ * You may not use this file except in compliance with the License.\r
+ * You may obtain a copy of the License at:\r
+ *\r
+ * http://www.st.com/software_license_agreement_liberty_v2\r
+ *\r
+ * Unless required by applicable law or agreed to in writing, software \r
+ * distributed under the License is distributed on an "AS IS" BASIS, \r
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+ * See the License for the specific language governing permissions and\r
+ * limitations under the License.\r
+ *\r
+ ****************************************************************************** \r
+ */ \r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f4xx\r
+ * @{\r
+ */\r
+ \r
+#ifndef __STM32F4xx_H\r
+#define __STM32F4xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+ \r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+ \r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application \r
+ */\r
+\r
+#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X) \r
+ #define STM32F40XX /*!< STM32F40xx/41xx Devices */\r
+ /* #define STM32F427X */ /*!< STM32F427x/437x Devices */\r
+ /* #define STM32F429X */ /*!< STM32F429x/439x Devices */\r
+#endif\r
+\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X)\r
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"\r
+#endif\r
+\r
+#if !defined (USE_STDPERIPH_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will \r
+ be based on direct access to peripherals registers \r
+ */\r
+ /*#define USE_STDPERIPH_DRIVER */\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+ used in your application \r
+ \r
+ Tip: To avoid modifying this file each time you need to use different HSE, you\r
+ can define the HSE value in your toolchain compiler preprocessor.\r
+ */ \r
+\r
+#if !defined (HSE_VALUE) \r
+ #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+ \r
+#endif /* HSE_VALUE */\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+ Timeout value \r
+ */\r
+#if !defined (HSE_STARTUP_TIMEOUT) \r
+ #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0600) /*!< Time out for HSE start up */\r
+#endif /* HSE_STARTUP_TIMEOUT */ \r
+\r
+#if !defined (HSI_VALUE) \r
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */ \r
+\r
+/**\r
+ * @brief STM32F4XX Standard Peripherals Library version number V1.2.0CR2\r
+ */\r
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_RC (0x02) /*!< [7:0] release candidate */ \r
+#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+ |(__STM32F4XX_STDPERIPH_VERSION_RC))\r
+ \r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \r
+ */\r
+#define __CM4_REV 0x0001 /*!< Core revision r0p1 */\r
+#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */\r
+#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1 /*!< FPU present */\r
+\r
+/**\r
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device \r
+ * in @ref Library_configuration_section \r
+ */\r
+typedef enum IRQn\r
+{\r
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+ FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined(STM32F429X)\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+#endif /* STM32F429X */ \r
+\r
+ SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
+ CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
+ CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
+ CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
+ CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */\r
+ HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */\r
+\r
+#if defined(STM32F40XX)\r
+ FPU_IRQn = 81 /*!< FPU global interrupt */\r
+#endif /* STM32F40XX */\r
+\r
+#if defined (STM32F427X) \r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86 /*!< SPI6 global Interrupt */\r
+#endif /* STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
+ LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
+ DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */\r
+#endif /* STM32F429X */ \r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
+#include "system_stm32f4xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */ \r
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
+typedef int32_t s32;\r
+typedef int16_t s16;\r
+typedef int8_t s8;\r
+\r
+typedef const int32_t sc32; /*!< Read Only */\r
+typedef const int16_t sc16; /*!< Read Only */\r
+typedef const int8_t sc8; /*!< Read Only */\r
+\r
+typedef __IO int32_t vs32;\r
+typedef __IO int16_t vs16;\r
+typedef __IO int8_t vs8;\r
+\r
+typedef __I int32_t vsc32; /*!< Read Only */\r
+typedef __I int16_t vsc16; /*!< Read Only */\r
+typedef __I int8_t vsc8; /*!< Read Only */\r
+\r
+typedef uint32_t u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t u8;\r
+\r
+typedef const uint32_t uc32; /*!< Read Only */\r
+typedef const uint16_t uc16; /*!< Read Only */\r
+typedef const uint8_t uc8; /*!< Read Only */\r
+\r
+typedef __IO uint32_t vu32;\r
+typedef __IO uint16_t vu16;\r
+typedef __IO uint8_t vu8;\r
+\r
+typedef __I uint32_t vuc32; /*!< Read Only */\r
+typedef __I uint16_t vuc16; /*!< Read Only */\r
+typedef __I uint8_t vuc8; /*!< Read Only */\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */ \r
+\r
+/** \r
+ * @brief Analog to Digital Converter \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+ * @brief Controller Area Network TxMailBox \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FIFOMailBox \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network FilterRegister \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+ * @brief Controller Area Network \r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+ * @brief CRC calculation unit \r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+ * @brief DCMI\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
+ __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
+ __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
+ __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
+ __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
+ __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+ __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
+ __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
+ __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+#if defined (STM32F429X) \r
+/** \r
+ * @brief DMA2D Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
+ __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
+ __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
+ __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
+ __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
+ __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
+ __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
+ __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
+ __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
+ __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
+ __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
+ __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
+ __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
+ __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
+ __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
+ __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
+ __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
+ __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
+ __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
+ __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
+ uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+ __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
+ __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief Ethernet MAC\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MACCR;\r
+ __IO uint32_t MACFFR;\r
+ __IO uint32_t MACHTHR;\r
+ __IO uint32_t MACHTLR;\r
+ __IO uint32_t MACMIIAR;\r
+ __IO uint32_t MACMIIDR;\r
+ __IO uint32_t MACFCR;\r
+ __IO uint32_t MACVLANTR; /* 8 */\r
+ uint32_t RESERVED0[2];\r
+ __IO uint32_t MACRWUFFR; /* 11 */\r
+ __IO uint32_t MACPMTCSR;\r
+ uint32_t RESERVED1[2];\r
+ __IO uint32_t MACSR; /* 15 */\r
+ __IO uint32_t MACIMR;\r
+ __IO uint32_t MACA0HR;\r
+ __IO uint32_t MACA0LR;\r
+ __IO uint32_t MACA1HR;\r
+ __IO uint32_t MACA1LR;\r
+ __IO uint32_t MACA2HR;\r
+ __IO uint32_t MACA2LR;\r
+ __IO uint32_t MACA3HR;\r
+ __IO uint32_t MACA3LR; /* 24 */\r
+ uint32_t RESERVED2[40];\r
+ __IO uint32_t MMCCR; /* 65 */\r
+ __IO uint32_t MMCRIR;\r
+ __IO uint32_t MMCTIR;\r
+ __IO uint32_t MMCRIMR;\r
+ __IO uint32_t MMCTIMR; /* 69 */\r
+ uint32_t RESERVED3[14];\r
+ __IO uint32_t MMCTGFSCCR; /* 84 */\r
+ __IO uint32_t MMCTGFMSCCR;\r
+ uint32_t RESERVED4[5];\r
+ __IO uint32_t MMCTGFCR;\r
+ uint32_t RESERVED5[10];\r
+ __IO uint32_t MMCRFCECR;\r
+ __IO uint32_t MMCRFAECR;\r
+ uint32_t RESERVED6[10];\r
+ __IO uint32_t MMCRGUFCR;\r
+ uint32_t RESERVED7[334];\r
+ __IO uint32_t PTPTSCR;\r
+ __IO uint32_t PTPSSIR;\r
+ __IO uint32_t PTPTSHR;\r
+ __IO uint32_t PTPTSLR;\r
+ __IO uint32_t PTPTSHUR;\r
+ __IO uint32_t PTPTSLUR;\r
+ __IO uint32_t PTPTSAR;\r
+ __IO uint32_t PTPTTHR;\r
+ __IO uint32_t PTPTTLR;\r
+ __IO uint32_t RESERVED8;\r
+ __IO uint32_t PTPTSSR;\r
+ uint32_t RESERVED9[565];\r
+ __IO uint32_t DMABMR;\r
+ __IO uint32_t DMATPDR;\r
+ __IO uint32_t DMARPDR;\r
+ __IO uint32_t DMARDLAR;\r
+ __IO uint32_t DMATDLAR;\r
+ __IO uint32_t DMASR;\r
+ __IO uint32_t DMAOMR;\r
+ __IO uint32_t DMAIER;\r
+ __IO uint32_t DMAMFBOCR;\r
+ __IO uint32_t DMARSWTR;\r
+ uint32_t RESERVED10[8];\r
+ __IO uint32_t DMACHTDR;\r
+ __IO uint32_t DMACHRDR;\r
+ __IO uint32_t DMACHTBAR;\r
+ __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/** \r
+ * @brief Flexible Static Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FSMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FSMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank2\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
+} FSMC_Bank2_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
+} FSMC_Bank3_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Static Memory Controller Bank4\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r
+} FSMC_Bank4_TypeDef; \r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
+} FMC_Bank1_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank2\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
+ __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
+ __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
+ __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
+ __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
+} FMC_Bank2_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
+ __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
+ __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
+ __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank4\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r
+ __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r
+ __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r
+ __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r
+ __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r
+} FMC_Bank4_TypeDef; \r
+\r
+/** \r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef; \r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */\r
+ __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+ * @brief System configuration controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+ __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */\r
+ uint16_t RESERVED9; /*!< Reserved, 0x26 */\r
+} I2C_TypeDef;\r
+\r
+/** \r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+} IWDG_TypeDef;\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+ * @brief LCD-TFT Display Controller\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
+ __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
+ __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
+ __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
+ __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
+ __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
+ __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
+ uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
+ __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
+ uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
+ __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
+ __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
+ __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
+ __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+ __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
+ __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
+} LTDC_TypeDef; \r
+\r
+/** \r
+ * @brief LCD-TFT Display layer x Controller\r
+ */\r
+ \r
+typedef struct\r
+{ \r
+ __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
+ __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+ __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
+ __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
+ __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
+ __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
+ __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
+ __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
+ uint32_t RESERVED0[2]; /*!< Reserved */\r
+ __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
+ __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
+ __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
+ uint32_t RESERVED1[3]; /*!< Reserved */\r
+ __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
+ __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+/** \r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+\r
+#if defined (STM32F427X) \r
+ uint32_t RESERVED7; /*!< Reserved, 0x88 */\r
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */\r
+#endif /* STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */\r
+#endif /* STM32F429X */\r
+\r
+} RCC_TypeDef;\r
+\r
+/** \r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ uint32_t RESERVED7; /*!< Reserved, 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+} RTC_TypeDef;\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+ * @brief Serial Audio Interface\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */\r
+} SDIO_TypeDef;\r
+\r
+/** \r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+ __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
+ __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ uint16_t RESERVED9; /*!< Reserved, 0x2A */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ uint16_t RESERVED10; /*!< Reserved, 0x32 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ uint16_t RESERVED11; /*!< Reserved, 0x46 */\r
+ __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ uint16_t RESERVED12; /*!< Reserved, 0x4A */\r
+ __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ uint16_t RESERVED13; /*!< Reserved, 0x4E */\r
+ __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ uint16_t RESERVED14; /*!< Reserved, 0x52 */\r
+} TIM_TypeDef;\r
+\r
+/** \r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+ \r
+typedef struct\r
+{\r
+ __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */\r
+ uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
+ __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
+ uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
+ __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
+ uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
+ __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
+ uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
+ __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
+ uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
+ uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
+} USART_TypeDef;\r
+\r
+/** \r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+ * @brief Crypto Processor\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */\r
+ __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */\r
+ __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */\r
+ __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */\r
+ __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */\r
+ __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */\r
+ __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */\r
+ __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */\r
+ __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */\r
+ __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */\r
+ __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */\r
+ __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */\r
+ __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */\r
+ __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */\r
+ __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */\r
+ __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */\r
+ __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */\r
+ __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */\r
+ __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */\r
+ __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */\r
+ __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */\r
+ __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */\r
+ __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */\r
+ __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */\r
+ __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */\r
+ __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */\r
+ __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */\r
+ __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */\r
+ __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */\r
+ __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */\r
+ __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */\r
+ __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */\r
+ __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */\r
+ __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */\r
+} CRYP_TypeDef;\r
+\r
+/** \r
+ * @brief HASH\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */\r
+ __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */\r
+ __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */\r
+ __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */\r
+ __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */\r
+ __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */\r
+ uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */\r
+ __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */\r
+} HASH_TypeDef;\r
+\r
+/** \r
+ * @brief HASH_DIGEST\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ \r
+} HASH_DIGEST_TypeDef;\r
+\r
+/** \r
+ * @brief RNG\r
+ */\r
+ \r
+typedef struct \r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/** \r
+ * @brief USB OTG FS\r
+ */\r
+#pragma anon_unions\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL;\r
+ __IO uint32_t GOTGINT;\r
+ __IO uint32_t GAHBCFG;\r
+ __IO uint32_t GUSBCFG;\r
+ __IO uint32_t GRSTCTL;\r
+ __IO uint32_t GINTSTS;\r
+ __IO uint32_t GINTMSK;\r
+ __IO uint32_t GRXSTSR;\r
+ __IO uint32_t GRXSTSP;\r
+ __IO uint32_t GRXFSIZ;\r
+ union {\r
+ __IO uint32_t HNPTXFSIZ;\r
+ __IO uint32_t DIEPTXF0;\r
+ };\r
+ __IO uint32_t HNPTXSTS;\r
+ __IO uint32_t GI2CCTL;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t GCCFG;\r
+ __IO uint32_t CID;\r
+ uint32_t RESERVED1[48];\r
+ __IO uint32_t HPTXFSIZ;\r
+ __IO uint32_t DIEPTXF1;\r
+ __IO uint32_t DIEPTXF2;\r
+ __IO uint32_t DIEPTXF3;\r
+ __IO uint32_t DIEPTXF4;\r
+ __IO uint32_t DIEPTXF5;\r
+ __IO uint32_t DIEPTXF6;\r
+ __IO uint32_t DIEPTXF7;\r
+ __IO uint32_t DIEPTXF8;\r
+ __IO uint32_t DIEPTXF9;\r
+ __IO uint32_t DIEPTXF10;\r
+ __IO uint32_t DIEPTXF11;\r
+ __IO uint32_t DIEPTXF12;\r
+ __IO uint32_t DIEPTXF13;\r
+ __IO uint32_t DIEPTXF14;\r
+ __IO uint32_t DIEPTXF15;\r
+ uint32_t RESERVED2[176];\r
+ __IO uint32_t HCFG;\r
+ __IO uint32_t HFIR;\r
+ __IO uint32_t HFNUM;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t HPTXSTS;\r
+ __IO uint32_t HAINT;\r
+ __IO uint32_t HAINTMSK;\r
+ uint32_t RESERVED4[9];\r
+ __IO uint32_t HPRT;\r
+ uint32_t RESERVED5[47];\r
+ __IO uint32_t HCCHAR0;\r
+ uint32_t RESERVED6;\r
+ __IO uint32_t HCINT0;\r
+ __IO uint32_t HCINTMSK0;\r
+ __IO uint32_t HCTSIZ0;\r
+ uint32_t RESERVED7[3];\r
+ __IO uint32_t HCCHAR1;\r
+ uint32_t RESERVED8;\r
+ __IO uint32_t HCINT1;\r
+ __IO uint32_t HCINTMSK1;\r
+ __IO uint32_t HCTSIZ1;\r
+ uint32_t RESERVED9[3];\r
+ __IO uint32_t HCCHAR2;\r
+ uint32_t RESERVED10;\r
+ __IO uint32_t HCINT2;\r
+ __IO uint32_t HCINTMSK2;\r
+ __IO uint32_t HCTSIZ2;\r
+ uint32_t RESERVED11[3];\r
+ __IO uint32_t HCCHR3;\r
+ uint32_t RESERVED12;\r
+ __IO uint32_t HCINT3;\r
+ __IO uint32_t HCINTMSK3;\r
+ __IO uint32_t HCTSIZ3;\r
+ uint32_t RESERVED13[3];\r
+ __IO uint32_t HCCHR4;\r
+ uint32_t RESERVED14;\r
+ __IO uint32_t HCINT4;\r
+ __IO uint32_t HCINTMSK4;\r
+ __IO uint32_t HCTSIZ4;\r
+ uint32_t RESERVED15[3];\r
+ __IO uint32_t HCCHR5;\r
+ uint32_t RESERVED16;\r
+ __IO uint32_t HCINT5;\r
+ __IO uint32_t HCINTMSK5;\r
+ __IO uint32_t HCTSIZ5;\r
+ uint32_t RESERVED17[3];\r
+ __IO uint32_t HCCHR6;\r
+ uint32_t RESERVED18;\r
+ __IO uint32_t HCINT6;\r
+ __IO uint32_t HCINTMSK6;\r
+ __IO uint32_t HCTSIZ6;\r
+ uint32_t RESERVED19[3];\r
+ __IO uint32_t HCCHR7;\r
+ uint32_t RESERVED20;\r
+ __IO uint32_t HCINT7;\r
+ __IO uint32_t HCINTMSK7;\r
+ __IO uint32_t HCTSIZ7;\r
+ uint32_t RESERVED21[3];\r
+ __IO uint32_t HCCHR8;\r
+ uint32_t RESERVED22;\r
+ __IO uint32_t HCINT8;\r
+ __IO uint32_t HCINTMSK8;\r
+ __IO uint32_t HCTSIZ8;\r
+ uint32_t RESERVED23[3];\r
+ __IO uint32_t HCCHR9;\r
+ uint32_t RESERVED24;\r
+ __IO uint32_t HCINT9;\r
+ __IO uint32_t HCINTMSK9;\r
+ __IO uint32_t HCTSIZ9;\r
+ uint32_t RESERVED25[3];\r
+ __IO uint32_t HCCHR10;\r
+ uint32_t RESERVED26;\r
+ __IO uint32_t HCINT10;\r
+ __IO uint32_t HCINTMSK10;\r
+ __IO uint32_t HCTSIZ10;\r
+ uint32_t RESERVED27[3];\r
+ __IO uint32_t HCCHR11;\r
+ uint32_t RESERVED28;\r
+ __IO uint32_t HCINT11;\r
+ __IO uint32_t HCINTMSK11;\r
+ __IO uint32_t HCTSIZ11;\r
+ uint32_t RESERVED29[3];\r
+ __IO uint32_t HCCHR12;\r
+ uint32_t RESERVED30;\r
+ __IO uint32_t HCINT12;\r
+ __IO uint32_t HCINTMSK12;\r
+ __IO uint32_t HCTSIZ12;\r
+ uint32_t RESERVED31[3];\r
+ __IO uint32_t HCCHR13;\r
+ uint32_t RESERVED32;\r
+ __IO uint32_t HCINT13;\r
+ __IO uint32_t HCINTMSK13;\r
+ __IO uint32_t HCTSIZ13;\r
+ uint32_t RESERVED33[3];\r
+ __IO uint32_t HCCHR14;\r
+ uint32_t RESERVED34;\r
+ __IO uint32_t HCINT14;\r
+ __IO uint32_t HCINTMSK14;\r
+ __IO uint32_t HCTSIZ14;\r
+ uint32_t RESERVED35[3];\r
+ __IO uint32_t HCCHR15;\r
+ uint32_t RESERVED36;\r
+ __IO uint32_t HCINT15;\r
+ __IO uint32_t HCINTMSK15;\r
+ __IO uint32_t HCTSIZ15;\r
+ uint32_t RESERVED37[3];\r
+ uint32_t RESERVED38[64];\r
+ __IO uint32_t DCFG;\r
+ __IO uint32_t DCTL;\r
+ __IO uint32_t DSTS;\r
+ uint32_t RESERVED39;\r
+ __IO uint32_t DIEPMSK;\r
+ __IO uint32_t DOEPMSK;\r
+ __IO uint32_t DAINT;\r
+ __IO uint32_t DAINTMSK;\r
+ uint32_t RESERVED40[2];\r
+ __IO uint32_t DVBUSDIS;\r
+ __IO uint32_t DVBUSPULSE;\r
+ uint32_t RESERVED41;\r
+ __IO uint32_t DIEPEMPMSK;\r
+ uint32_t RESERVED42[50];\r
+ __IO uint32_t DIEPCTL0;\r
+ uint32_t RESERVED43;\r
+ __IO uint32_t DIEPINT0;\r
+ uint32_t RESERVED44;\r
+ __IO uint32_t DIEPTSIZ0;\r
+ uint32_t RESERVED45;\r
+ __IO uint32_t DTXFSTS0;\r
+ uint32_t RESERVED46;\r
+ __IO uint32_t DIEPCTL1;\r
+ uint32_t RESERVED47;\r
+ __IO uint32_t DIEPINT1;\r
+ uint32_t RESERVED48;\r
+ __IO uint32_t DIEPTSIZ1;\r
+ uint32_t RESERVED49;\r
+ __IO uint32_t DTXFSTS1;\r
+ uint32_t RESERVED50;\r
+ __IO uint32_t DIEPCTL2;\r
+ uint32_t RESERVED51;\r
+ __IO uint32_t DIEPINT2;\r
+ uint32_t RESERVED52;\r
+ __IO uint32_t DIEPTSIZ2;\r
+ uint32_t RESERVED53;\r
+ __IO uint32_t DTXFSTS2;\r
+ uint32_t RESERVED54;\r
+ __IO uint32_t DIEPCTL3;\r
+ uint32_t RESERVED55;\r
+ __IO uint32_t DIEPINT3;\r
+ uint32_t RESERVED56;\r
+ __IO uint32_t DIEPTSIZ3;\r
+ uint32_t RESERVED57;\r
+ __IO uint32_t DTXFSTS3;\r
+ uint32_t RESERVED58;\r
+ __IO uint32_t DIEPCTL4;\r
+ uint32_t RESERVED59;\r
+ __IO uint32_t DIEPINT4;\r
+ uint32_t RESERVED60;\r
+ __IO uint32_t DIEPTSIZ4;\r
+ uint32_t RESERVED61;\r
+ __IO uint32_t DTXFSTS4;\r
+ uint32_t RESERVED62;\r
+ __IO uint32_t DIEPCTL5;\r
+ uint32_t RESERVED63;\r
+ __IO uint32_t DIEPINT5;\r
+ uint32_t RESERVED64;\r
+ __IO uint32_t DIEPTSIZ5;\r
+ uint32_t RESERVED65[3];\r
+ __IO uint32_t DIEPCTL6;\r
+ uint32_t RESERVED66;\r
+ __IO uint32_t DIEPINT6;\r
+ uint32_t RESERVED67;\r
+ __IO uint32_t DIEPTSIZ6;\r
+ uint32_t RESERVED68[3];\r
+ __IO uint32_t DIEPCTL7;\r
+ uint32_t RESERVED69;\r
+ __IO uint32_t DIEPINT7;\r
+ uint32_t RESERVED70;\r
+ __IO uint32_t DIEPTSIZ7;\r
+ uint32_t RESERVED71[3];\r
+ __IO uint32_t DIEPCTL8;\r
+ uint32_t RESERVED72;\r
+ __IO uint32_t DIEPINT8;\r
+ uint32_t RESERVED73;\r
+ __IO uint32_t DIEPTSIZ8;\r
+ uint32_t RESERVED74[3];\r
+ __IO uint32_t DIEPCTL9;\r
+ uint32_t RESERVED75;\r
+ __IO uint32_t DIEPINT9;\r
+ uint32_t RESERVED76;\r
+ __IO uint32_t DIEPTSIZ9;\r
+ uint32_t RESERVED77[3];\r
+ __IO uint32_t DIEPCTL10;\r
+ uint32_t RESERVED78;\r
+ __IO uint32_t DIEPINT10;\r
+ uint32_t RESERVED79;\r
+ __IO uint32_t DIEPTSIZ10;\r
+ uint32_t RESERVED80[3];\r
+ __IO uint32_t DIEPCTL11;\r
+ uint32_t RESERVED81;\r
+ __IO uint32_t DIEPINT11;\r
+ uint32_t RESERVED82;\r
+ __IO uint32_t DIEPTSIZ11;\r
+ uint32_t RESERVED83[3];\r
+ __IO uint32_t DIEPCTL12;\r
+ uint32_t RESERVED84;\r
+ __IO uint32_t DIEPINT12;\r
+ uint32_t RESERVED85;\r
+ __IO uint32_t DIEPTSIZ86;\r
+ uint32_t RESERVED86[3];\r
+ __IO uint32_t DIEPCTL13;\r
+ uint32_t RESERVED87;\r
+ __IO uint32_t DIEPINT13;\r
+ uint32_t RESERVED88;\r
+ __IO uint32_t DIEPTSIZ13;\r
+ uint32_t RESERVED89[3];\r
+ __IO uint32_t DIEPCTL14;\r
+ uint32_t RESERVED90;\r
+ __IO uint32_t DIEPINT14;\r
+ uint32_t RESERVED91;\r
+ __IO uint32_t DIEPTSIZ14;\r
+ uint32_t RESERVED92[3];\r
+ __IO uint32_t DIEPCTL15;\r
+ uint32_t RESERVED93;\r
+ __IO uint32_t DIEPINT15;\r
+ uint32_t RESERVED94;\r
+ __IO uint32_t DIEPTSIZ15;\r
+ uint32_t RESERVED95[3];\r
+ __IO uint32_t DOEPCTL0;\r
+ uint32_t RESERVED96;\r
+ __IO uint32_t DOEPINT0;\r
+ uint32_t RESERVED97;\r
+ __IO uint32_t DOEPTSIZ0;\r
+ uint32_t RESERVED98[3];\r
+ __IO uint32_t DOEPCTL1;\r
+ uint32_t RESERVED99;\r
+ __IO uint32_t DOEPINT1;\r
+ uint32_t RESERVED100;\r
+ __IO uint32_t DOEPTSIZ1;\r
+ uint32_t RESERVED101[3];\r
+ __IO uint32_t DOEPCTL2;\r
+ uint32_t RESERVED102;\r
+ __IO uint32_t DOEPINT2;\r
+ uint32_t RESERVED103;\r
+ __IO uint32_t DOEPTSIZ2;\r
+ uint32_t RESERVED104[3];\r
+ __IO uint32_t DOEPCTL3;\r
+ uint32_t RESERVED105;\r
+ __IO uint32_t DOEPINT3;\r
+ uint32_t RESERVED106;\r
+ __IO uint32_t DOEPTSIZ3;\r
+ uint32_t RESERVED107[3];\r
+ __IO uint32_t DOEPCTL4;\r
+ uint32_t RESERVED108;\r
+ __IO uint32_t DOEPINT4;\r
+ uint32_t RESERVED109;\r
+ __IO uint32_t DOEPTSIZ4;\r
+ uint32_t RESERVED110[3];\r
+ __IO uint32_t DOEPCTL5;\r
+ uint32_t RESERVED111;\r
+ __IO uint32_t DOEPINT5;\r
+ uint32_t RESERVED112;\r
+ __IO uint32_t DOEPTSIZ5;\r
+ uint32_t RESERVED113[3];\r
+ __IO uint32_t DOEPCTL6;\r
+ uint32_t RESERVED114;\r
+ __IO uint32_t DOEPINT6;\r
+ uint32_t RESERVED115;\r
+ __IO uint32_t DOEPTSIZ6;\r
+ uint32_t RESERVED116[3];\r
+ __IO uint32_t DOEPCTL7;\r
+ uint32_t RESERVED117;\r
+ __IO uint32_t DOEPINT7;\r
+ uint32_t RESERVED118;\r
+ __IO uint32_t DOEPTSIZ7;\r
+ uint32_t RESERVED119[3];\r
+ __IO uint32_t DOEPCTL8;\r
+ uint32_t RESERVED120;\r
+ __IO uint32_t DOEPINT8;\r
+ uint32_t RESERVED121;\r
+ __IO uint32_t DOEPTSIZ8;\r
+ uint32_t RESERVED122[3];\r
+ __IO uint32_t DOEPCTL9;\r
+ uint32_t RESERVED123;\r
+ __IO uint32_t DOEPINT9;\r
+ uint32_t RESERVED124;\r
+ __IO uint32_t DOEPTSIZ9;\r
+ uint32_t RESERVED125[3];\r
+ __IO uint32_t DOEPCTL10;\r
+ uint32_t RESERVED126;\r
+ __IO uint32_t DOEPINT10;\r
+ uint32_t RESERVED127;\r
+ __IO uint32_t DOEPTSIZ10;\r
+ uint32_t RESERVED128[3];\r
+ __IO uint32_t DOEPCTL11;\r
+ uint32_t RESERVED129;\r
+ __IO uint32_t DOEPINT11;\r
+ uint32_t RESERVED130;\r
+ __IO uint32_t DOEPTSIZ11;\r
+ uint32_t RESERVED131[3];\r
+ __IO uint32_t DOEPCTL12;\r
+ uint32_t RESERVED132;\r
+ __IO uint32_t DOEPINT12;\r
+ uint32_t RESERVED133;\r
+ __IO uint32_t DOEPTSIZ12;\r
+ uint32_t RESERVED134[3];\r
+ __IO uint32_t DOEPCTL13;\r
+ uint32_t RESERVED135;\r
+ __IO uint32_t DOEPINT13;\r
+ uint32_t RESERVED136;\r
+ __IO uint32_t DOEPTSIZ13;\r
+ uint32_t RESERVED137[3];\r
+ __IO uint32_t DOEPCTL14;\r
+ uint32_t RESERVED138;\r
+ __IO uint32_t DOEPINT14;\r
+ uint32_t RESERVED139;\r
+ __IO uint32_t DOEPTSIZ14;\r
+ uint32_t RESERVED140[3];\r
+ __IO uint32_t DOEPCTL15;\r
+ uint32_t RESERVED141;\r
+ __IO uint32_t DOEPINT15;\r
+ uint32_t RESERVED142;\r
+ __IO uint32_t DOEPTSIZ15;\r
+ uint32_t RESERVED143[3];\r
+ uint32_t RESERVED144[64];\r
+ __IO uint32_t PCGCCTL;\r
+} OTG_FS_TypeDef;\r
+\r
+/** \r
+ * @brief USB OTG HS\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL;\r
+ __IO uint32_t GOTGINT;\r
+ __IO uint32_t GAHBCFG;\r
+ __IO uint32_t GUSBCFG;\r
+ __IO uint32_t GRSTCTL;\r
+ __IO uint32_t GINTSTS;\r
+ __IO uint32_t GINTMSK;\r
+ __IO uint32_t GRXSTSR;\r
+ __IO uint32_t GRXSTSP;\r
+ __IO uint32_t GRXFSIZ;\r
+ union {\r
+ __IO uint32_t GNPTXFSIZ;\r
+ __IO uint32_t TX0FSIZ;\r
+ };\r
+ __IO uint32_t GNPTXSTS;\r
+ __IO uint32_t GI2CCTL;\r
+ uint32_t RESERVED0;\r
+ __IO uint32_t GCCFG;\r
+ __IO uint32_t CID;\r
+ uint32_t RESERVED1[48];\r
+ __IO uint32_t HPTXFSIZ;\r
+ __IO uint32_t DIEPTXF1;\r
+ __IO uint32_t DIEPTXF2;\r
+ __IO uint32_t DIEPTXF3;\r
+ __IO uint32_t DIEPTXF4;\r
+ __IO uint32_t DIEPTXF5;\r
+ __IO uint32_t DIEPTXF6;\r
+ __IO uint32_t DIEPTXF7;\r
+ __IO uint32_t DIEPTXF8;\r
+ __IO uint32_t DIEPTXF9;\r
+ __IO uint32_t DIEPTXF10;\r
+ __IO uint32_t DIEPTXF11;\r
+ __IO uint32_t DIEPTXF12;\r
+ __IO uint32_t DIEPTXF13;\r
+ __IO uint32_t DIEPTXF14;\r
+ __IO uint32_t DIEPTXF15;\r
+ uint32_t RESERVED2[176];\r
+ __IO uint32_t HCFG;\r
+ __IO uint32_t HFIR;\r
+ __IO uint32_t HFNUM;\r
+ uint32_t RESERVED3;\r
+ __IO uint32_t HPTXSTS;\r
+ __IO uint32_t HAINT;\r
+ __IO uint32_t HAINTMSK;\r
+ uint32_t RESERVED4[9];\r
+ __IO uint32_t HPRT;\r
+ uint32_t RESERVED5[47];\r
+ __IO uint32_t HCCHAR0;\r
+ __IO uint32_t HCSPLT0;\r
+ __IO uint32_t HCINT0;\r
+ __IO uint32_t HCINTMSK0;\r
+ __IO uint32_t HCTSIZ0;\r
+ __IO uint32_t HCDMA0;\r
+ uint32_t RESERVED6[2];\r
+ __IO uint32_t HCCHAR1;\r
+ __IO uint32_t HCSPLT1;\r
+ __IO uint32_t HCINT1;\r
+ __IO uint32_t HCINTMSK1;\r
+ __IO uint32_t HCTSIZ1;\r
+ __IO uint32_t HCDMA1;\r
+ uint32_t RESERVED7[2];\r
+ __IO uint32_t HCCHAR2;\r
+ __IO uint32_t HCSPLT2;\r
+ __IO uint32_t HCINT2;\r
+ __IO uint32_t HCINTMSK2;\r
+ __IO uint32_t HCTSIZ2;\r
+ __IO uint32_t HCDMA2;\r
+ uint32_t RESERVED8[2];\r
+ __IO uint32_t HCCHAR3;\r
+ __IO uint32_t HCSPLT3;\r
+ __IO uint32_t HCINT3;\r
+ __IO uint32_t HCINTMSK3;\r
+ __IO uint32_t HCTSIZ3;\r
+ __IO uint32_t HCDMA3;\r
+ uint32_t RESERVED9[2];\r
+ __IO uint32_t HCCHAR4;\r
+ __IO uint32_t HCSPLT4;\r
+ __IO uint32_t HCINT4;\r
+ __IO uint32_t HCINTMSK4;\r
+ __IO uint32_t HCTSIZ4;\r
+ __IO uint32_t HCDMA4;\r
+ uint32_t RESERVED10[2];\r
+ __IO uint32_t HCCHAR5;\r
+ __IO uint32_t HCSPLT5;\r
+ __IO uint32_t HCINT5;\r
+ __IO uint32_t HCINTMSK5;\r
+ __IO uint32_t HCTSIZ5;\r
+ __IO uint32_t HCDMA5;\r
+ uint32_t RESERVED11[2];\r
+ __IO uint32_t HCCHAR6;\r
+ __IO uint32_t HCSPLT6;\r
+ __IO uint32_t HCINT6;\r
+ __IO uint32_t HCINTMSK6;\r
+ __IO uint32_t HCTSIZ6;\r
+ __IO uint32_t HCDMA6;\r
+ uint32_t RESERVED12[2];\r
+ __IO uint32_t HCCHAR7;\r
+ __IO uint32_t HCSPLT7;\r
+ __IO uint32_t HCINT7;\r
+ __IO uint32_t HCINTMSK7;\r
+ __IO uint32_t HCTSIZ7;\r
+ __IO uint32_t HCDMA7;\r
+ uint32_t RESERVED13[2];\r
+ __IO uint32_t HCCHAR8;\r
+ __IO uint32_t HCSPLT8;\r
+ __IO uint32_t HCINT8;\r
+ __IO uint32_t HCINTMSK8;\r
+ __IO uint32_t HCTSIZ8;\r
+ __IO uint32_t HCDMA8;\r
+ uint32_t RESERVED14[2];\r
+ __IO uint32_t HCCHAR9;\r
+ __IO uint32_t HCSPLT9;\r
+ __IO uint32_t HCINT9;\r
+ __IO uint32_t HCINTMSK9;\r
+ __IO uint32_t HCTSIZ9;\r
+ __IO uint32_t HCDMA9;\r
+ uint32_t RESERVED15[2];\r
+ __IO uint32_t HCCHAR10;\r
+ __IO uint32_t HCSPLT10;\r
+ __IO uint32_t HCINT10;\r
+ __IO uint32_t HCINTMSK10;\r
+ __IO uint32_t HCTSIZ10;\r
+ __IO uint32_t HCDMA10;\r
+ uint32_t RESERVED16[2];\r
+ __IO uint32_t HCCHAR11;\r
+ __IO uint32_t HCSPLT11;\r
+ __IO uint32_t HCINT11;\r
+ __IO uint32_t HCINTMSK11;\r
+ __IO uint32_t HCTSIZ11;\r
+ __IO uint32_t HCDMA11;\r
+ uint32_t RESERVED17[2];\r
+ __IO uint32_t HCCHAR12;\r
+ __IO uint32_t HCSPLT12;\r
+ __IO uint32_t HCINT12;\r
+ __IO uint32_t HCINTMSK12;\r
+ __IO uint32_t HCTSIZ12;\r
+ __IO uint32_t HCDMA12;\r
+ uint32_t RESERVED18[2];\r
+ __IO uint32_t HCCHAR13;\r
+ __IO uint32_t HCSPLT13;\r
+ __IO uint32_t HCINT13;\r
+ __IO uint32_t HCINTMSK13;\r
+ __IO uint32_t HCTSIZ13;\r
+ __IO uint32_t HCDMA13;\r
+ uint32_t RESERVED19[2];\r
+ __IO uint32_t HCCHAR14;\r
+ __IO uint32_t HCSPLT14;\r
+ __IO uint32_t HCINT14;\r
+ __IO uint32_t HCINTMSK14;\r
+ __IO uint32_t HCTSIZ14;\r
+ __IO uint32_t HCDMA14;\r
+ uint32_t RESERVED20[2];\r
+ __IO uint32_t HCCHAR15;\r
+ __IO uint32_t HCSPLT15;\r
+ __IO uint32_t HCINT15;\r
+ __IO uint32_t HCINTMSK15;\r
+ __IO uint32_t HCTSIZ15;\r
+ __IO uint32_t HCDMA15;\r
+ uint32_t RESERVED21[2];\r
+ uint32_t RESERVED22[64];\r
+ __IO uint32_t DCFG;\r
+ __IO uint32_t DCTL;\r
+ __IO uint32_t DSTS;\r
+ uint32_t RESERVED23;\r
+ __IO uint32_t DIEPMSK;\r
+ __IO uint32_t DOEPMSK;\r
+ __IO uint32_t DAINT;\r
+ __IO uint32_t DAINTMSK;\r
+ uint32_t RESERVED24[2];\r
+ __IO uint32_t DVBUSDIS;\r
+ __IO uint32_t DVBUSPULSE;\r
+ uint32_t RESERVED25;\r
+ __IO uint32_t DIEPEMPMSK;\r
+ __IO uint32_t EACHHINT;\r
+ __IO uint32_t EACHHINTMSK;\r
+ __IO uint32_t DIEPEACHMSK1;\r
+ uint32_t RESERVED26[15];\r
+ __IO uint32_t DOEPEACHMSK1;\r
+ uint32_t RESERVED27[31];\r
+ __IO uint32_t DIEPCTL0;\r
+ uint32_t RESERVED28;\r
+ __IO uint32_t DIEPINT0;\r
+ uint32_t RESERVED29;\r
+ __IO uint32_t DIEPTSIZ0;\r
+ __IO uint32_t DIEPDMA0;\r
+ __IO uint32_t DTXFSTS0;\r
+ uint32_t RESERVED30;\r
+ __IO uint32_t DIEPCTL1;\r
+ uint32_t RESERVED31;\r
+ __IO uint32_t DIEPINT1;\r
+ uint32_t RESERVED32;\r
+ __IO uint32_t DIEPTSIZ1;\r
+ __IO uint32_t DIEPDMA1;\r
+ __IO uint32_t DTXFSTS1;\r
+ uint32_t RESERVED33;\r
+ __IO uint32_t DIEPCTL2;\r
+ uint32_t RESERVED34;\r
+ __IO uint32_t DIEPINT2;\r
+ uint32_t RESERVED35;\r
+ __IO uint32_t DIEPTSIZ2;\r
+ __IO uint32_t DIEPDMA2;\r
+ __IO uint32_t DTXFSTS2;\r
+ uint32_t RESERVED36;\r
+ __IO uint32_t DIEPCTL3;\r
+ uint32_t RESERVED37;\r
+ __IO uint32_t DIEPINT3;\r
+ uint32_t RESERVED38;\r
+ __IO uint32_t DIEPTSIZ3;\r
+ __IO uint32_t DIEPDMA3;\r
+ __IO uint32_t DTXFSTS3;\r
+ uint32_t RESERVED39;\r
+ __IO uint32_t DIEPCTL4;\r
+ uint32_t RESERVED40;\r
+ __IO uint32_t DIEPINT4;\r
+ uint32_t RESERVED41;\r
+ __IO uint32_t DIEPTSIZ4;\r
+ __IO uint32_t DIEPDMA4;\r
+ __IO uint32_t DTXFSTS4;\r
+ uint32_t RESERVED42;\r
+ __IO uint32_t DIEPCTL5;\r
+ uint32_t RESERVED43;\r
+ __IO uint32_t DIEPINT5;\r
+ uint32_t RESERVED44;\r
+ __IO uint32_t DIEPTSIZ5;\r
+ __IO uint32_t DIEPDMA5;\r
+ __IO uint32_t DTXFSTS5;\r
+ uint32_t RESERVED45;\r
+ __IO uint32_t DIEPCTL6;\r
+ uint32_t RESERVED46;\r
+ __IO uint32_t DIEPINT6;\r
+ uint32_t RESERVED47;\r
+ __IO uint32_t DIEPTSIZ6;\r
+ __IO uint32_t DIEPDMA6;\r
+ __IO uint32_t DTXFSTS6;\r
+ uint32_t RESERVED48;\r
+ __IO uint32_t DIEPCTL7;\r
+ uint32_t RESERVED49;\r
+ __IO uint32_t DIEPINT7;\r
+ uint32_t RESERVED50;\r
+ __IO uint32_t DIEPTSIZ7;\r
+ __IO uint32_t DIEPDMA7;\r
+ __IO uint32_t DTXFSTS7;\r
+ uint32_t RESERVED51;\r
+ __IO uint32_t DIEPCTL8;\r
+ uint32_t RESERVED52;\r
+ __IO uint32_t DIEPINT8;\r
+ uint32_t RESERVED53;\r
+ __IO uint32_t DIEPTSIZ8;\r
+ __IO uint32_t DIEPDMA8;\r
+ __IO uint32_t DTXFSTS8;\r
+ uint32_t RESERVED54;\r
+ __IO uint32_t DIEPCTL9;\r
+ uint32_t RESERVED55;\r
+ __IO uint32_t DIEPINT9;\r
+ uint32_t RESERVED56;\r
+ __IO uint32_t DIEPTSIZ9;\r
+ __IO uint32_t DIEPDMA9;\r
+ __IO uint32_t DTXFSTS9;\r
+ uint32_t RESERVED57;\r
+ __IO uint32_t DIEPCTL10;\r
+ uint32_t RESERVED58;\r
+ __IO uint32_t DIEPINT10;\r
+ uint32_t RESERVED59;\r
+ __IO uint32_t DIEPTSIZ10;\r
+ __IO uint32_t DIEPDMA10;\r
+ __IO uint32_t DTXFSTS10;\r
+ uint32_t RESERVED60;\r
+ __IO uint32_t DIEPCTL11;\r
+ uint32_t RESERVED61;\r
+ __IO uint32_t DIEPINT11;\r
+ uint32_t RESERVED62;\r
+ __IO uint32_t DIEPTSIZ11;\r
+ __IO uint32_t DIEPDMA11;\r
+ __IO uint32_t DTXFSTS11;\r
+ uint32_t RESERVED63;\r
+ __IO uint32_t DIEPCTL12;\r
+ uint32_t RESERVED64;\r
+ __IO uint32_t DIEPINT12;\r
+ uint32_t RESERVED65;\r
+ __IO uint32_t DIEPTSIZ12;\r
+ __IO uint32_t DIEPDMA12;\r
+ __IO uint32_t DTXFSTS12;\r
+ uint32_t RESERVED66;\r
+ __IO uint32_t DIEPCTL13;\r
+ uint32_t RESERVED67;\r
+ __IO uint32_t DIEPINT13;\r
+ uint32_t RESERVED68;\r
+ __IO uint32_t DIEPTSIZ13;\r
+ __IO uint32_t DIEPDMA13;\r
+ __IO uint32_t DTXFSTS13;\r
+ uint32_t RESERVED69;\r
+ __IO uint32_t DIEPCTL14;\r
+ uint32_t RESERVED70;\r
+ __IO uint32_t DIEPINT14;\r
+ uint32_t RESERVED71;\r
+ __IO uint32_t DIEPTSIZ14;\r
+ __IO uint32_t DIEPDMA14;\r
+ __IO uint32_t DTXFSTS14;\r
+ uint32_t RESERVED72;\r
+ __IO uint32_t DIEPCTL15;\r
+ uint32_t RESERVED73;\r
+ __IO uint32_t DIEPINT15;\r
+ uint32_t RESERVED74;\r
+ __IO uint32_t DIEPTSIZ15;\r
+ __IO uint32_t DIEPDMA15;\r
+ __IO uint32_t DTXFSTS15;\r
+ uint32_t RESERVED75;\r
+ __IO uint32_t DOEPCTL0;\r
+ uint32_t RESERVED76;\r
+ __IO uint32_t DOEPINT0;\r
+ uint32_t RESERVED77;\r
+ __IO uint32_t DOEPTSIZ0;\r
+ __IO uint32_t DOEPDMAB0;\r
+ uint32_t RESERVED78[2];\r
+ __IO uint32_t DOEPCTL1;\r
+ uint32_t RESERVED79;\r
+ __IO uint32_t DOEPINT1;\r
+ uint32_t RESERVED80;\r
+ __IO uint32_t DOEPTSIZ1;\r
+ __IO uint32_t DOEPDMAB1;\r
+ uint32_t RESERVED81[2];\r
+ __IO uint32_t DOEPCTL2;\r
+ uint32_t RESERVED82;\r
+ __IO uint32_t DOEPINT2;\r
+ uint32_t RESERVED83;\r
+ __IO uint32_t DOEPTSIZ2;\r
+ __IO uint32_t DOEPDMAB2;\r
+ uint32_t RESERVED84[2];\r
+ __IO uint32_t DOEPCTL3;\r
+ uint32_t RESERVED85;\r
+ __IO uint32_t DOEPINT3;\r
+ uint32_t RESERVED86;\r
+ __IO uint32_t DOEPTSIZ3;\r
+ __IO uint32_t DOEPDMAB3;\r
+ uint32_t RESERVED87[2];\r
+ __IO uint32_t DOEPCTL4;\r
+ uint32_t RESERVED88;\r
+ __IO uint32_t DOEPINT4;\r
+ uint32_t RESERVED89;\r
+ __IO uint32_t DOEPTSIZ4;\r
+ __IO uint32_t DOEPDMAB4;\r
+ uint32_t RESERVED90[2];\r
+ __IO uint32_t DOEPCTL5;\r
+ uint32_t RESERVED91;\r
+ __IO uint32_t DOEPINT5;\r
+ uint32_t RESERVED92;\r
+ __IO uint32_t DOEPTSIZ5;\r
+ __IO uint32_t DOEPDMAB5;\r
+ uint32_t RESERVED93[2];\r
+ __IO uint32_t DOEPCTL6;\r
+ uint32_t RESERVED94;\r
+ __IO uint32_t DOEPINT6;\r
+ uint32_t RESERVED95;\r
+ __IO uint32_t DOEPTSIZ6;\r
+ __IO uint32_t DOEPDMAB6;\r
+ uint32_t RESERVED96[2];\r
+ __IO uint32_t DOEPCTL7;\r
+ uint32_t RESERVED97;\r
+ __IO uint32_t DOEPINT7;\r
+ uint32_t RESERVED98;\r
+ __IO uint32_t DOEPTSIZ7;\r
+ __IO uint32_t DOEPDMAB7;\r
+ uint32_t RESERVED99[2];\r
+ __IO uint32_t DOEPCTL8;\r
+ uint32_t RESERVED100;\r
+ __IO uint32_t DOEPINT8;\r
+ uint32_t RESERVED101;\r
+ __IO uint32_t DOEPTSIZ8;\r
+ __IO uint32_t DOEPDMAB8;\r
+ uint32_t RESERVED102[2];\r
+ __IO uint32_t DOEPCTL9;\r
+ uint32_t RESERVED103;\r
+ __IO uint32_t DOEPINT9;\r
+ uint32_t RESERVED104;\r
+ __IO uint32_t DOEPTSIZ9;\r
+ __IO uint32_t DOEPDMAB9;\r
+ uint32_t RESERVED105[2];\r
+ __IO uint32_t DOEPCTL10;\r
+ uint32_t RESERVED106;\r
+ __IO uint32_t DOEPINT10;\r
+ uint32_t RESERVED107;\r
+ __IO uint32_t DOEPTSIZ10;\r
+ __IO uint32_t DOEPDMAB10;\r
+ uint32_t RESERVED108[2];\r
+ __IO uint32_t DOEPCTL11;\r
+ uint32_t RESERVED109;\r
+ __IO uint32_t DOEPINT11;\r
+ uint32_t RESERVED110;\r
+ __IO uint32_t DOEPTSIZ11;\r
+ __IO uint32_t DOEPDMAB11;\r
+ uint32_t RESERVED111[2];\r
+ __IO uint32_t DOEPCTL12;\r
+ uint32_t RESERVED112;\r
+ __IO uint32_t DOEPINT12;\r
+ uint32_t RESERVED113;\r
+ __IO uint32_t DOEPTSIZ12;\r
+ __IO uint32_t DOEPDMAB12;\r
+ uint32_t RESERVED114[2];\r
+ __IO uint32_t DOEPCTL13;\r
+ uint32_t RESERVED115;\r
+ __IO uint32_t DOEPINT13;\r
+ uint32_t RESERVED116;\r
+ __IO uint32_t DOEPTSIZ13;\r
+ __IO uint32_t DOEPDMAB13;\r
+ uint32_t RESERVED117[2];\r
+ __IO uint32_t DOEPCTL14;\r
+ uint32_t RESERVED118;\r
+ __IO uint32_t DOEPINT14;\r
+ uint32_t RESERVED119;\r
+ __IO uint32_t DOEPTSIZ14;\r
+ __IO uint32_t DOEPDMAB14;\r
+ uint32_t RESERVED120[2];\r
+ __IO uint32_t DOEPCTL15;\r
+ uint32_t RESERVED121;\r
+ __IO uint32_t DOEPINT15;\r
+ uint32_t RESERVED122;\r
+ __IO uint32_t DOEPTSIZ15;\r
+ __IO uint32_t DOEPDMAB15;\r
+ uint32_t RESERVED123[2];\r
+ uint32_t RESERVED143[64];\r
+ __IO uint32_t PCGCCTL;\r
+} OTG_HS_TypeDef;\r
+#pragma no_anon_unions\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */\r
+#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */\r
+#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */\r
+#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */\r
+#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */\r
+#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
+#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */\r
+#endif /* STM32F429X */\r
+\r
+#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */\r
+#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */\r
+#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */\r
+#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */\r
+#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
+#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */\r
+\r
+/* Legacy defines */\r
+#define SRAM_BASE SRAM1_BASE\r
+#define SRAM_BB_BASE SRAM1_BB_BASE\r
+\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
+#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
+#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r
+#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)\r
+#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)\r
+\r
+#if defined (STM32F429X)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)\r
+#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)\r
+#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)\r
+#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) \r
+#endif /* STM32F429X */\r
+\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r
+\r
+#if defined (STM32F429X)\r
+#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)\r
+#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)\r
+#endif /* STM32F429X */\r
+\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r
+#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE (ETH_BASE)\r
+#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
+#define OTG_HS_BASE (AHB1PERIPH_BASE + 0x20000)\r
+#define OTG_HS_DFIFO0_BASE (OTG_HS_BASE + 0x01000)\r
+#define OTG_HS_DFIFO1_BASE (OTG_HS_BASE + 0x02000)\r
+#define OTG_HS_DFIFO2_BASE (OTG_HS_BASE + 0x03000)\r
+#define OTG_HS_DFIFO3_BASE (OTG_HS_BASE + 0x04000)\r
+#define OTG_HS_DFIFO4_BASE (OTG_HS_BASE + 0x05000)\r
+#define OTG_HS_DFIFO5_BASE (OTG_HS_BASE + 0x06000)\r
+#define OTG_HS_DFIFO6_BASE (OTG_HS_BASE + 0x07000)\r
+#define OTG_HS_DFIFO7_BASE (OTG_HS_BASE + 0x08000)\r
+#define OTG_HS_DFIFO8_BASE (OTG_HS_BASE + 0x09000)\r
+#define OTG_HS_DFIFO9_BASE (OTG_HS_BASE + 0x0A000)\r
+#define OTG_HS_DFIFO10_BASE (OTG_HS_BASE + 0x0B000)\r
+#define OTG_HS_DFIFO11_BASE (OTG_HS_BASE + 0x0C000)\r
+#define OTG_HS_DFIFO12_BASE (OTG_HS_BASE + 0x0D000)\r
+#define OTG_HS_DFIFO13_BASE (OTG_HS_BASE + 0x0E000)\r
+#define OTG_HS_DFIFO14_BASE (OTG_HS_BASE + 0x0F000)\r
+#define OTG_HS_DFIFO15_BASE (OTG_HS_BASE + 0x10000)\r
+\r
+#if defined (STM32F429X)\r
+#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)\r
+#endif /* STM32F429X */\r
+\r
+/*!< AHB2 peripherals */\r
+#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x00000)\r
+#define OTG_FS_DFIFO0_BASE (OTG_FS_BASE + 0x01000)\r
+#define OTG_FS_DFIFO1_BASE (OTG_FS_BASE + 0x02000)\r
+#define OTG_FS_DFIFO2_BASE (OTG_FS_BASE + 0x03000)\r
+#define OTG_FS_DFIFO3_BASE (OTG_FS_BASE + 0x04000)\r
+#define OTG_FS_DFIFO4_BASE (OTG_FS_BASE + 0x05000)\r
+#define OTG_FS_DFIFO5_BASE (OTG_FS_BASE + 0x06000)\r
+#define OTG_FS_DFIFO6_BASE (OTG_FS_BASE + 0x07000)\r
+#define OTG_FS_DFIFO7_BASE (OTG_FS_BASE + 0x08000)\r
+#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r
+#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)\r
+#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)\r
+#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/*!< FSMC Bankx registers base address */\r
+#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)\r
+#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)\r
+#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)\r
+#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)\r
+#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)\r
+#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)\r
+#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)\r
+#endif /* STM32F429X */\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE ((uint32_t )0xE0042000)\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */ \r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE)\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE) \r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
+\r
+#if defined (STM32F429X)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+\r
+#if defined (STM32F429X)\r
+#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH ((ETH_TypeDef *) ETH_BASE) \r
+#define OTG_HS ((OTG_HS_TypeDef *) OTG_HS_BASE) \r
+#define OTG_HS_DFIFO0 (((uint32_t *) OTG_HS_DFIFO0_BASE) )\r
+#define OTG_HS_DFIFO1 (((uint32_t *) OTG_HS_DFIFO1_BASE) )\r
+#define OTG_HS_DFIFO2 (((uint32_t *) OTG_HS_DFIFO2_BASE) )\r
+#define OTG_HS_DFIFO3 (((uint32_t *) OTG_HS_DFIFO3_BASE) )\r
+#define OTG_HS_DFIFO4 (((uint32_t *) OTG_HS_DFIFO4_BASE) )\r
+#define OTG_HS_DFIFO5 (((uint32_t *) OTG_HS_DFIFO5_BASE) )\r
+#define OTG_HS_DFIFO6 (((uint32_t *) OTG_HS_DFIFO6_BASE) )\r
+#define OTG_HS_DFIFO7 (((uint32_t *) OTG_HS_DFIFO7_BASE) )\r
+#define OTG_HS_DFIFO8 (((uint32_t *) OTG_HS_DFIFO8_BASE) )\r
+#define OTG_HS_DFIFO9 (((uint32_t *) OTG_HS_DFIFO9_BASE) )\r
+#define OTG_HS_DFIFO10 (((uint32_t *) OTG_HS_DFIFO10_BASE) )\r
+#define OTG_HS_DFIFO11 (((uint32_t *) OTG_HS_DFIFO11_BASE) )\r
+#define OTG_HS_DFIFO12 (((uint32_t *) OTG_HS_DFIFO12_BASE) )\r
+#define OTG_HS_DFIFO13 (((uint32_t *) OTG_HS_DFIFO13_BASE) )\r
+#define OTG_HS_DFIFO14 (((uint32_t *) OTG_HS_DFIFO14_BASE) )\r
+#define OTG_HS_DFIFO15 (((uint32_t *) OTG_HS_DFIFO15_BASE) )\r
+#define OTG_FS ((OTG_FS_TypeDef *) OTG_FS_BASE) \r
+#define OTG_FS_DFIFO0 (((uint32_t *) OTG_FS_DFIFO0_BASE) )\r
+#define OTG_FS_DFIFO1 (((uint32_t *) OTG_FS_DFIFO1_BASE) )\r
+#define OTG_FS_DFIFO2 (((uint32_t *) OTG_FS_DFIFO2_BASE) )\r
+#define OTG_FS_DFIFO3 (((uint32_t *) OTG_FS_DFIFO3_BASE) )\r
+#define OTG_FS_DFIFO4 (((uint32_t *) OTG_FS_DFIFO4_BASE) )\r
+#define OTG_FS_DFIFO5 (((uint32_t *) OTG_FS_DFIFO5_BASE) )\r
+#define OTG_FS_DFIFO6 (((uint32_t *) OTG_FS_DFIFO6_BASE) )\r
+#define OTG_FS_DFIFO7 (((uint32_t *) OTG_FS_DFIFO7_BASE) )\r
+\r
+#if defined (STM32F429X)\r
+#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
+#define CRYP ((CRYP_TypeDef *) CRYP_BASE)\r
+#define HASH ((HASH_TypeDef *) HASH_BASE)\r
+#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
+#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
+#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+ \r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+ \r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */\r
+#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */\r
+ \r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
+#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
+#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
+#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
+#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
+#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
+#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
+#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
+#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
+#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
+#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
+#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
+#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
+#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
+#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
+#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */\r
+#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */\r
+#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
+#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
+#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
+#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
+#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */\r
+\r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */\r
+#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */\r
+#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */\r
+#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+\r
+#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
+#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
+#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/ \r
+#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
+#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
+#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */\r
+#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
+\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Crypto Processor */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for CRYP_CR register ********************/\r
+#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)\r
+\r
+#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)\r
+#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)\r
+#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)\r
+#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)\r
+#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)\r
+\r
+#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)\r
+#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)\r
+#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)\r
+#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)\r
+#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)\r
+#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)\r
+#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)\r
+#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)\r
+\r
+#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)\r
+#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)\r
+#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)\r
+#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) \r
+\r
+/****************** Bits definition for CRYP_SR register *********************/\r
+#define CRYP_SR_IFEM ((uint32_t)0x00000001)\r
+#define CRYP_SR_IFNF ((uint32_t)0x00000002)\r
+#define CRYP_SR_OFNE ((uint32_t)0x00000004)\r
+#define CRYP_SR_OFFU ((uint32_t)0x00000008)\r
+#define CRYP_SR_BUSY ((uint32_t)0x00000010)\r
+/****************** Bits definition for CRYP_DMACR register ******************/\r
+#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)\r
+#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)\r
+/***************** Bits definition for CRYP_IMSCR register ******************/\r
+#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)\r
+#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_RISR register *******************/\r
+#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)\r
+#define CRYP_RISR_INRIS ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_MISR register *******************/\r
+#define CRYP_MISR_INMIS ((uint32_t)0x00000001)\r
+#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
+\r
+#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
+\r
+#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+\r
+#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
+#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
+\r
+#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DCMI */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DCMI_CR register ******************/\r
+#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)\r
+#define DCMI_CR_CM ((uint32_t)0x00000002)\r
+#define DCMI_CR_CROP ((uint32_t)0x00000004)\r
+#define DCMI_CR_JPEG ((uint32_t)0x00000008)\r
+#define DCMI_CR_ESS ((uint32_t)0x00000010)\r
+#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)\r
+#define DCMI_CR_HSPOL ((uint32_t)0x00000040)\r
+#define DCMI_CR_VSPOL ((uint32_t)0x00000080)\r
+#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)\r
+#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)\r
+#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)\r
+#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)\r
+#define DCMI_CR_CRE ((uint32_t)0x00001000)\r
+#define DCMI_CR_ENABLE ((uint32_t)0x00004000)\r
+\r
+/******************** Bits definition for DCMI_SR register ******************/\r
+#define DCMI_SR_HSYNC ((uint32_t)0x00000001)\r
+#define DCMI_SR_VSYNC ((uint32_t)0x00000002)\r
+#define DCMI_SR_FNE ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for DCMI_RISR register ****************/\r
+#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)\r
+#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)\r
+#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)\r
+#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)\r
+#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_IER register *****************/\r
+#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)\r
+#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)\r
+#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)\r
+#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)\r
+#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_MISR register ****************/\r
+#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)\r
+#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)\r
+#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)\r
+#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)\r
+#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)\r
+\r
+/******************** Bits definition for DCMI_ICR register *****************/\r
+#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)\r
+#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)\r
+#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)\r
+#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)\r
+#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/ \r
+#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)\r
+#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)\r
+#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)\r
+#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) \r
+#define DMA_SxCR_MBURST ((uint32_t)0x01800000)\r
+#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)\r
+#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)\r
+#define DMA_SxCR_PBURST ((uint32_t)0x00600000)\r
+#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)\r
+#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)\r
+#define DMA_SxCR_ACK ((uint32_t)0x00100000)\r
+#define DMA_SxCR_CT ((uint32_t)0x00080000) \r
+#define DMA_SxCR_DBM ((uint32_t)0x00040000)\r
+#define DMA_SxCR_PL ((uint32_t)0x00030000)\r
+#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)\r
+#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)\r
+#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)\r
+#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)\r
+#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)\r
+#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)\r
+#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)\r
+#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)\r
+#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)\r
+#define DMA_SxCR_MINC ((uint32_t)0x00000400)\r
+#define DMA_SxCR_PINC ((uint32_t)0x00000200)\r
+#define DMA_SxCR_CIRC ((uint32_t)0x00000100)\r
+#define DMA_SxCR_DIR ((uint32_t)0x000000C0)\r
+#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)\r
+#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)\r
+#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)\r
+#define DMA_SxCR_TCIE ((uint32_t)0x00000010)\r
+#define DMA_SxCR_HTIE ((uint32_t)0x00000008)\r
+#define DMA_SxCR_TEIE ((uint32_t)0x00000004)\r
+#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)\r
+#define DMA_SxCR_EN ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT ((uint32_t)0x0000FFFF)\r
+#define DMA_SxNDT_0 ((uint32_t)0x00000001)\r
+#define DMA_SxNDT_1 ((uint32_t)0x00000002)\r
+#define DMA_SxNDT_2 ((uint32_t)0x00000004)\r
+#define DMA_SxNDT_3 ((uint32_t)0x00000008)\r
+#define DMA_SxNDT_4 ((uint32_t)0x00000010)\r
+#define DMA_SxNDT_5 ((uint32_t)0x00000020)\r
+#define DMA_SxNDT_6 ((uint32_t)0x00000040)\r
+#define DMA_SxNDT_7 ((uint32_t)0x00000080)\r
+#define DMA_SxNDT_8 ((uint32_t)0x00000100)\r
+#define DMA_SxNDT_9 ((uint32_t)0x00000200)\r
+#define DMA_SxNDT_10 ((uint32_t)0x00000400)\r
+#define DMA_SxNDT_11 ((uint32_t)0x00000800)\r
+#define DMA_SxNDT_12 ((uint32_t)0x00001000)\r
+#define DMA_SxNDT_13 ((uint32_t)0x00002000)\r
+#define DMA_SxNDT_14 ((uint32_t)0x00004000)\r
+#define DMA_SxNDT_15 ((uint32_t)0x00008000)\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/ \r
+#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)\r
+#define DMA_SxFCR_FS ((uint32_t)0x00000038)\r
+#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)\r
+#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)\r
+#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)\r
+#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)\r
+#define DMA_SxFCR_FTH ((uint32_t)0x00000003)\r
+#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)\r
+#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/ \r
+#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/ \r
+#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/ \r
+#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)\r
+#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)\r
+#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)\r
+#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)\r
+#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)\r
+#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)\r
+#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)\r
+#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)\r
+#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)\r
+#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)\r
+#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)\r
+#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)\r
+#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)\r
+#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)\r
+#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)\r
+#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)\r
+#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)\r
+#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)\r
+#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)\r
+#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/ \r
+#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)\r
+#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)\r
+#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)\r
+#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)\r
+#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)\r
+#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)\r
+#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)\r
+#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)\r
+#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)\r
+#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)\r
+#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)\r
+#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)\r
+#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)\r
+#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)\r
+#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)\r
+#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)\r
+#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)\r
+#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)\r
+#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)\r
+#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/* */\r
+/* AHB Master DMA2D Controller (DMA2D) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for DMA2D_CR register ******************/\r
+\r
+#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */\r
+#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */\r
+\r
+/******************** Bit definition for DMA2D_ISR register *****************/\r
+\r
+#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_IFSR register ****************/\r
+\r
+#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/******************** Bit definition for DMA2D_FGMAR register ***************/\r
+\r
+#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_FGOR register ****************/\r
+\r
+#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_BGMAR register ***************/\r
+\r
+#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGOR register ****************/\r
+\r
+#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
+\r
+#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */\r
+#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_FGCOLR register **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ \r
+\r
+/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
+\r
+#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
+#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
+#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */\r
+#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
+\r
+/******************** Bit definition for DMA2D_BGCOLR register **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */\r
+\r
+/******************** Bit definition for DMA2D_FGCMAR register **************/\r
+\r
+#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_BGCMAR register **************/\r
+\r
+#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OPFCCR register **************/\r
+\r
+#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */\r
+\r
+/******************** Bit definition for DMA2D_OCOLR register ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */\r
+#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */\r
+\r
+/******************** Bit definition for DMA2D_OMAR register ****************/\r
+\r
+#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
+\r
+/******************** Bit definition for DMA2D_OOR register *****************/\r
+\r
+#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
+\r
+/******************** Bit definition for DMA2D_NLR register *****************/\r
+\r
+#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */\r
+#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */\r
+\r
+/******************** Bit definition for DMA2D_LWR register *****************/\r
+\r
+#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */\r
+\r
+/******************** Bit definition for DMA2D_AMTCR register ***************/\r
+\r
+#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */\r
+#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */\r
+\r
+\r
+\r
+/******************** Bit definition for DMA2D_FGCLUT register **************/\r
+ \r
+/******************** Bit definition for DMA2D_BGCLUT register **************/\r
+#endif /* STM32F429X */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)\r
+#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)\r
+#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)\r
+#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)\r
+#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)\r
+#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)\r
+#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)\r
+#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)\r
+#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)\r
+#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)\r
+#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)\r
+#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)\r
+#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)\r
+#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)\r
+#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)\r
+#endif /* STM32F429X */\r
+\r
+#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)\r
+#define FLASH_ACR_ICEN ((uint32_t)0x00000200)\r
+#define FLASH_ACR_DCEN ((uint32_t)0x00000400)\r
+#define FLASH_ACR_ICRST ((uint32_t)0x00000800)\r
+#define FLASH_ACR_DCRST ((uint32_t)0x00001000)\r
+#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)\r
+#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP ((uint32_t)0x00000001)\r
+#define FLASH_SR_SOP ((uint32_t)0x00000002)\r
+#define FLASH_SR_WRPERR ((uint32_t)0x00000010)\r
+#define FLASH_SR_PGAERR ((uint32_t)0x00000020)\r
+#define FLASH_SR_PGPERR ((uint32_t)0x00000040)\r
+#define FLASH_SR_PGSERR ((uint32_t)0x00000080)\r
+#define FLASH_SR_BSY ((uint32_t)0x00010000)\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG ((uint32_t)0x00000001)\r
+#define FLASH_CR_SER ((uint32_t)0x00000002)\r
+#define FLASH_CR_MER ((uint32_t)0x00000004)\r
+#define FLASH_CR_MER1 FLASH_CR_MER\r
+#define FLASH_CR_SNB ((uint32_t)0x000000F8)\r
+#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)\r
+#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)\r
+#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)\r
+#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)\r
+#define FLASH_CR_SNB_4 ((uint32_t)0x00000040)\r
+#define FLASH_CR_PSIZE ((uint32_t)0x00000300)\r
+#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)\r
+#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)\r
+#define FLASH_CR_MER2 ((uint32_t)0x00008000)\r
+#define FLASH_CR_STRT ((uint32_t)0x00010000)\r
+#define FLASH_CR_EOPIE ((uint32_t)0x01000000)\r
+#define FLASH_CR_LOCK ((uint32_t)0x80000000)\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)\r
+#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)\r
+#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
+#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
+#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)\r
+#endif /* STM32F429X */\r
+\r
+#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
+#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
+#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
+#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)\r
+#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)\r
+#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)\r
+#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)\r
+#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)\r
+#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)\r
+#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)\r
+#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)\r
+#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)\r
+#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)\r
+#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)\r
+#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)\r
+#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000) \r
+#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) \r
+#endif /* STM32F429X */\r
+ \r
+/****************** Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)\r
+#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)\r
+#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)\r
+#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)\r
+#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Static Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FSMC_BCR1 register *******************/\r
+#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR2 register *******************/\r
+#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR3 register *******************/\r
+#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BCR4 register *******************/\r
+#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FSMC_BTR1 register ******************/\r
+#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR2 register *******************/\r
+#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FSMC_BTR3 register *******************/\r
+#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BTR4 register *******************/\r
+#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR1 register ******************/\r
+#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR2 register ******************/\r
+#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
+#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR3 register ******************/\r
+#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_BWTR4 register ******************/\r
+#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FSMC_PCR2 register *******************/\r
+#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR3 register *******************/\r
+#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FSMC_PCR4 register *******************/\r
+#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FSMC_SR2 register *******************/\r
+#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR3 register *******************/\r
+#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FSMC_SR4 register *******************/\r
+#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FSMC_PMEM2 register ******************/\r
+#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM3 register ******************/\r
+#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PMEM4 register ******************/\r
+#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT2 register ******************/\r
+#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT3 register ******************/\r
+#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PATT4 register ******************/\r
+#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_PIO4 register *******************/\r
+#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FSMC_ECCR2 register ******************/\r
+#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FSMC_ECCR3 register ******************/\r
+#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
+\r
+#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
+#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
+#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+\r
+#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
+#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_PCR2 register *******************/\r
+#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_PCR3 register *******************/\r
+#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_PCR4 register *******************/\r
+#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
+#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
+\r
+#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
+\r
+#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
+#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
+#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
+#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
+#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
+\r
+#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
+#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
+#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for FMC_SR2 register *******************/\r
+#define FMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FMC_SR3 register *******************/\r
+#define FMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/******************* Bit definition for FMC_SR4 register *******************/\r
+#define FMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
+#define FMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
+#define FMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
+#define FMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM2 register ******************/\r
+#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PMEM3 register ******************/\r
+#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PMEM4 register ******************/\r
+#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT2 register ******************/\r
+#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT3 register ******************/\r
+#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PATT4 register ******************/\r
+#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_PIO4 register *******************/\r
+#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
+\r
+#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
+#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
+#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
+#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
+#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
+\r
+#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
+#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
+#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
+#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
+#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
+\r
+/****************** Bit definition for FMC_ECCR2 register ******************/\r
+#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_ECCR3 register ******************/\r
+#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
+\r
+#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */\r
+\r
+#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
+\r
+#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
+#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+ \r
+#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
+#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
+\r
+#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
+#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
+#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */\r
+ \r
+#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */\r
+\r
+#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */\r
+\r
+#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
+\r
+#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */\r
+\r
+#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */\r
+\r
+#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */\r
+\r
+#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
+#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
+\r
+#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */\r
+\r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
+\r
+#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
+\r
+#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
+\r
+#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
+\r
+#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
+\r
+#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
+\r
+#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
+\r
+#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
+\r
+#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
+\r
+#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
+\r
+#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0\r
+#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1\r
+#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2\r
+#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3\r
+#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4\r
+#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5\r
+#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6\r
+#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7\r
+#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8\r
+#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9\r
+#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10\r
+#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11\r
+#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12\r
+#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13\r
+#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14\r
+#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0\r
+#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1\r
+#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2\r
+#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3\r
+#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4\r
+#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5\r
+#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6\r
+#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7\r
+#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8\r
+#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9\r
+#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10\r
+#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11\r
+#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12\r
+#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13\r
+#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14\r
+#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* HASH */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for HASH_CR register ********************/\r
+#define HASH_CR_INIT ((uint32_t)0x00000004)\r
+#define HASH_CR_DMAE ((uint32_t)0x00000008)\r
+#define HASH_CR_DATATYPE ((uint32_t)0x00000030)\r
+#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)\r
+#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)\r
+#define HASH_CR_MODE ((uint32_t)0x00000040)\r
+#define HASH_CR_ALGO ((uint32_t)0x00040080)\r
+#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)\r
+#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)\r
+#define HASH_CR_NBW ((uint32_t)0x00000F00)\r
+#define HASH_CR_NBW_0 ((uint32_t)0x00000100)\r
+#define HASH_CR_NBW_1 ((uint32_t)0x00000200)\r
+#define HASH_CR_NBW_2 ((uint32_t)0x00000400)\r
+#define HASH_CR_NBW_3 ((uint32_t)0x00000800)\r
+#define HASH_CR_DINNE ((uint32_t)0x00001000)\r
+#define HASH_CR_MDMAT ((uint32_t)0x00002000)\r
+#define HASH_CR_LKEY ((uint32_t)0x00010000)\r
+\r
+/****************** Bits definition for HASH_STR register *******************/\r
+#define HASH_STR_NBW ((uint32_t)0x0000001F)\r
+#define HASH_STR_NBW_0 ((uint32_t)0x00000001)\r
+#define HASH_STR_NBW_1 ((uint32_t)0x00000002)\r
+#define HASH_STR_NBW_2 ((uint32_t)0x00000004)\r
+#define HASH_STR_NBW_3 ((uint32_t)0x00000008)\r
+#define HASH_STR_NBW_4 ((uint32_t)0x00000010)\r
+#define HASH_STR_DCAL ((uint32_t)0x00000100)\r
+\r
+/****************** Bits definition for HASH_IMR register *******************/\r
+#define HASH_IMR_DINIM ((uint32_t)0x00000001)\r
+#define HASH_IMR_DCIM ((uint32_t)0x00000002)\r
+\r
+/****************** Bits definition for HASH_SR register ********************/\r
+#define HASH_SR_DINIS ((uint32_t)0x00000001)\r
+#define HASH_SR_DCIS ((uint32_t)0x00000002)\r
+#define HASH_SR_DMAS ((uint32_t)0x00000004)\r
+#define HASH_SR_BUSY ((uint32_t)0x00000008)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register ********************/\r
+#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */\r
+#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */\r
+#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */\r
+#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */\r
+#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */\r
+#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */\r
+#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */\r
+#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */\r
+#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */\r
+#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */\r
+#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */\r
+#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */\r
+#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */\r
+#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */\r
+\r
+/******************* Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */\r
+#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+\r
+#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */\r
+#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */\r
+#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */\r
+#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */\r
+#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */\r
+\r
+/******************* Bit definition for I2C_OAR1 register *******************/\r
+#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */\r
+#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */\r
+\r
+#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */\r
+#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */\r
+\r
+#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */\r
+\r
+/******************* Bit definition for I2C_OAR2 register *******************/\r
+#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */\r
+#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */\r
+\r
+/******************** Bit definition for I2C_DR register ********************/\r
+#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */\r
+\r
+/******************* Bit definition for I2C_SR1 register ********************/\r
+#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */\r
+#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */\r
+#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */\r
+#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */\r
+#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */\r
+#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */\r
+#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */\r
+#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */\r
+#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */\r
+#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */\r
+#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */\r
+#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */\r
+#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */\r
+#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */\r
+\r
+/******************* Bit definition for I2C_SR2 register ********************/\r
+#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */\r
+#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */\r
+#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */\r
+#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */\r
+#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */\r
+#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */\r
+#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */\r
+#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */\r
+\r
+/******************* Bit definition for I2C_CCR register ********************/\r
+#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */\r
+#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */\r
+\r
+/****************** Bit definition for I2C_TRISE register *******************/\r
+#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/****************** Bit definition for I2C_FLTR register *******************/\r
+#define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */\r
+#define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */\r
+#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/* */\r
+/* LCD-TFT Display Controller (LTDC) */\r
+/* */\r
+/******************************************************************************/\r
+\r
+/******************** Bit definition for LTDC_SSCR register *****************/\r
+\r
+#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */\r
+\r
+/******************** Bit definition for LTDC_BPCR register *****************/\r
+\r
+#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */\r
+\r
+/******************** Bit definition for LTDC_AWCR register *****************/\r
+\r
+#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */\r
+\r
+/******************** Bit definition for LTDC_TWCR register *****************/\r
+\r
+#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */\r
+\r
+/******************** Bit definition for LTDC_GCR register ******************/\r
+\r
+#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */\r
+#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */\r
+\r
+/******************** Bit definition for LTDC_SRCR register *****************/\r
+\r
+#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */\r
+\r
+/******************** Bit definition for LTDC_BCCR register *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */\r
+\r
+/******************** Bit definition for LTDC_IER register ******************/\r
+\r
+#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */\r
+\r
+/******************** Bit definition for LTDC_ISR register ******************/\r
+\r
+#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_ICR register ******************/\r
+\r
+#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */\r
+\r
+/******************** Bit definition for LTDC_LIPCR register ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */\r
+\r
+/******************** Bit definition for LTDC_CPSR register *****************/\r
+\r
+#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */\r
+\r
+/******************** Bit definition for LTDC_CDSR register *****************/\r
+\r
+#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */\r
+\r
+/******************** Bit definition for LTDC_LxCR register *****************/\r
+\r
+#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */\r
+\r
+/******************** Bit definition for LTDC_LxWHPCR register **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxWVPCR register **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */\r
+\r
+/******************** Bit definition for LTDC_LxCKCR register ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */\r
+\r
+/******************** Bit definition for LTDC_LxPFCR register ***************/\r
+\r
+#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */\r
+\r
+/******************** Bit definition for LTDC_LxCACR register ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */\r
+\r
+/******************** Bit definition for LTDC_LxDCCR register ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */\r
+ \r
+/******************** Bit definition for LTDC_LxBFCR register ***************/\r
+\r
+#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */\r
+\r
+/******************** Bit definition for LTDC_LxCFBAR register **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLR register **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */\r
+\r
+/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */\r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR register ********************/\r
+#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */\r
+#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */\r
+#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */\r
+#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */\r
+#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */\r
+\r
+#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
+#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
+#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */\r
+#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */\r
+#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */\r
+#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */\r
+#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */\r
+#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */\r
+#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */\r
+#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */\r
+\r
+#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */\r
+#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */\r
+\r
+#if defined (STM32F429X)\r
+#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */\r
+#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */\r
+#endif /* STM32F429X */\r
+\r
+#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ \r
+\r
+#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
+#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
+\r
+#if defined (STM32F429X)\r
+#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */\r
+#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */\r
+#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */\r
+#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
+#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
+#endif /* STM32F429X */\r
+\r
+/* Legacy define */\r
+#define PWR_CR_PMODE PWR_CR_VOS\r
+\r
+/******************* Bit definition for PWR_CSR register ********************/\r
+#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */\r
+#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */\r
+#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */\r
+#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */\r
+#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */\r
+#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */\r
+#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */\r
+\r
+#if defined (STM32F429X)\r
+#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */\r
+#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */\r
+#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */\r
+#endif /* STM32F429X */\r
+/* Legacy define */\r
+#define PWR_CSR_REGRDY PWR_CSR_VOSRDY\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION ((uint32_t)0x00000001)\r
+#define RCC_CR_HSIRDY ((uint32_t)0x00000002)\r
+\r
+#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)\r
+#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */\r
+#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */\r
+#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */\r
+#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */\r
+#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */\r
+\r
+#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)\r
+#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */\r
+#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */\r
+#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */\r
+#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */\r
+#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */\r
+#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */\r
+#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */\r
+#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */\r
+\r
+#define RCC_CR_HSEON ((uint32_t)0x00010000)\r
+#define RCC_CR_HSERDY ((uint32_t)0x00020000)\r
+#define RCC_CR_HSEBYP ((uint32_t)0x00040000)\r
+#define RCC_CR_CSSON ((uint32_t)0x00080000)\r
+#define RCC_CR_PLLON ((uint32_t)0x01000000)\r
+#define RCC_CR_PLLRDY ((uint32_t)0x02000000)\r
+#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)\r
+#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_CR_PLLSAION ((uint32_t)0x10000000)\r
+#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)\r
+#endif /* STM32F429X */\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)\r
+#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)\r
+#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)\r
+#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)\r
+#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)\r
+#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)\r
+#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)\r
+\r
+#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)\r
+#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)\r
+#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)\r
+#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)\r
+#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)\r
+#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)\r
+#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)\r
+#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)\r
+#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)\r
+\r
+#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)\r
+#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)\r
+#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)\r
+\r
+#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)\r
+#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)\r
+\r
+#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)\r
+#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)\r
+#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)\r
+#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
+#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
+#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
+\r
+#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
+#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
+#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
+#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
+#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
+#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)\r
+#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)\r
+#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)\r
+#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)\r
+#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)\r
+#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)\r
+#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)\r
+#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)\r
+\r
+#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)\r
+\r
+#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)\r
+#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)\r
+#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)\r
+#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)\r
+\r
+#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)\r
+#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)\r
+#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)\r
+#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)\r
+\r
+#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)\r
+#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)\r
+#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)\r
+#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)\r
+#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)\r
+#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)\r
+#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)\r
+#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_CIR_CSSF ((uint32_t)0x00000080)\r
+#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)\r
+#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)\r
+#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)\r
+#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)\r
+#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)\r
+#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)\r
+#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)\r
+#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)\r
+#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)\r
+#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)\r
+#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_CIR_CSSC ((uint32_t)0x00800000)\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)\r
+#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)\r
+#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)\r
+#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)\r
+#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)\r
+#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)\r
+#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)\r
+#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)\r
+#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)\r
+#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)\r
+#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)\r
+#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)\r
+#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)\r
+#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)\r
+ /* maintained for legacy purpose */\r
+ #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST\r
+#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)\r
+#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)\r
+#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)\r
+#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)\r
+#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)\r
+#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)\r
+#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)\r
+#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)\r
+#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)\r
+#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)\r
+#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)\r
+#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)\r
+#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)\r
+#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)\r
+#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)\r
+#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)\r
+#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)\r
+#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)\r
+#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)\r
+#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)\r
+#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)\r
+#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)\r
+#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)\r
+#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)\r
+#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)\r
+#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)\r
+#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)\r
+#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)\r
+#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)\r
+#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)\r
+#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)\r
+#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)\r
+#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)\r
+#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)\r
+#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)\r
+#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)\r
+#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)\r
+#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)\r
+#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)\r
+#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/* Old SPI1RST bit definition, maintained for legacy purpose */\r
+#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)\r
+#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)\r
+#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)\r
+#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)\r
+#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)\r
+#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)\r
+#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)\r
+#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)\r
+#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)\r
+#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)\r
+#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)\r
+#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)\r
+#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)\r
+#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)\r
+#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)\r
+#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)\r
+#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)\r
+#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)\r
+#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)\r
+#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)\r
+#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)\r
+#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)\r
+#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)\r
+#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)\r
+#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)\r
+#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)\r
+#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)\r
+#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)\r
+#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)\r
+#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)\r
+#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)\r
+#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)\r
+#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)\r
+#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)\r
+#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)\r
+#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)\r
+#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)\r
+#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)\r
+#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)\r
+#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)\r
+#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)\r
+#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)\r
+#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)\r
+#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)\r
+#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)\r
+#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)\r
+#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)\r
+#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)\r
+#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)\r
+#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)\r
+#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)\r
+#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)\r
+#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)\r
+#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)\r
+#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)\r
+#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)\r
+#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)\r
+#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)\r
+#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)\r
+#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)\r
+#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)\r
+#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)\r
+#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)\r
+#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)\r
+#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)\r
+#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)\r
+#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)\r
+#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)\r
+#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)\r
+#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)\r
+#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)\r
+#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)\r
+#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)\r
+#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)\r
+#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)\r
+#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)\r
+#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)\r
+#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)\r
+#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)\r
+#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)\r
+#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)\r
+#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)\r
+#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)\r
+#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)\r
+#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)\r
+#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)\r
+#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)\r
+#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)\r
+#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)\r
+#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)\r
+#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)\r
+#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON ((uint32_t)0x00000001)\r
+#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)\r
+#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)\r
+\r
+#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)\r
+#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)\r
+#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)\r
+\r
+#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)\r
+#define RCC_BDCR_BDRST ((uint32_t)0x00010000)\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION ((uint32_t)0x00000001)\r
+#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)\r
+#define RCC_CSR_RMVF ((uint32_t)0x01000000)\r
+#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)\r
+#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)\r
+#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)\r
+#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)\r
+#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)\r
+#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)\r
+#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)\r
+#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)\r
+#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)\r
+#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
+\r
+#if defined (STM32F429X)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
+#endif /* STM32F429X */\r
+\r
+#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)\r
+\r
+#if defined (STM32F429X)\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
+#define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
+#define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)\r
+\r
+/******************** Bit definition for RCC_DCKCFGR register ***************/\r
+#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)\r
+#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)\r
+#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)\r
+#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)\r
+#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)\r
+#endif /* STM32F429X */\r
+#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN ((uint32_t)0x00000004)\r
+#define RNG_CR_IE ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY ((uint32_t)0x00000001)\r
+#define RNG_SR_CECS ((uint32_t)0x00000002)\r
+#define RNG_SR_SECS ((uint32_t)0x00000004)\r
+#define RNG_SR_CEIS ((uint32_t)0x00000020)\r
+#define RNG_SR_SEIS ((uint32_t)0x00000040)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM ((uint32_t)0x00400000)\r
+#define RTC_TR_HT ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TR_ST ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
+#define RTC_DR_YU ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_DR_MT ((uint32_t)0x00001000)\r
+#define RTC_DR_MU ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_DR_DT ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_DR_DU ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_COE ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
+#define RTC_CR_POL ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CALIBR register ***************/\r
+#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
+\r
+/******************** Bits definition for RTC_TAFCR register ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)\r
+#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)\r
+#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)\r
+#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)\r
+#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
+#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
+#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)\r
+#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
+#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
+#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)\r
+#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
+#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
+#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
+#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)\r
+#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
+#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
+#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
+#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
+#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
+\r
+#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
+#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
+\r
+#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */\r
+#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
+#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
+#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
+#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+\r
+#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
+#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
+#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
+#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
+#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
+#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
+\r
+#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
+#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
+#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
+#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
+\r
+#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
+#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
+#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
+\r
+#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
+#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
+#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
+#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
+#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
+ \r
+#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
+#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
+\r
+#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
+#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
+#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
+#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
+\r
+#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */\r
+#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
+#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
+#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register ******************/\r
+#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) \r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDIO_POWER register ******************/\r
+#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */\r
+\r
+/****************** Bit definition for SDIO_CLKCR register ******************/\r
+#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */\r
+#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */\r
+#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */\r
+#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */\r
+\r
+#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */\r
+#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */\r
+\r
+#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */\r
+#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDIO_ARG register *******************/\r
+#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
+\r
+/******************* Bit definition for SDIO_CMD register *******************/\r
+#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */\r
+\r
+#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
+#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
+\r
+#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
+#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */\r
+#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */\r
+#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */\r
+#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */\r
+\r
+/***************** Bit definition for SDIO_RESPCMD register *****************/\r
+#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */\r
+\r
+/****************** Bit definition for SDIO_RESP0 register ******************/\r
+#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP1 register ******************/\r
+#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP2 register ******************/\r
+#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP3 register ******************/\r
+#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_RESP4 register ******************/\r
+#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
+\r
+/****************** Bit definition for SDIO_DTIMER register *****************/\r
+#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDIO_DLEN register *******************/\r
+#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
+\r
+/****************** Bit definition for SDIO_DCTRL register ******************/\r
+#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */\r
+#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */\r
+#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */\r
+#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */\r
+\r
+#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */\r
+#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */\r
+#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */\r
+#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDIO_DCOUNT register *****************/\r
+#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
+\r
+/****************** Bit definition for SDIO_STA register ********************/\r
+#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
+#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
+#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
+#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
+#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
+#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
+#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
+#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
+#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */\r
+#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
+#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
+#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
+#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
+#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
+#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
+#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
+#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
+#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
+#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
+#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */\r
+#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */\r
+\r
+/******************* Bit definition for SDIO_ICR register *******************/\r
+#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
+#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
+#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
+#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
+#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
+#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
+#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
+#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
+#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
+#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */\r
+#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
+#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */\r
+#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */\r
+\r
+/****************** Bit definition for SDIO_MASK register *******************/\r
+#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
+#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
+#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
+#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
+#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
+#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
+#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */\r
+#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
+#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
+#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
+#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
+#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */\r
+#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */\r
+\r
+/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
+#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDIO_FIFO register *******************/\r
+#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */\r
+#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */\r
+#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */\r
+\r
+#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */\r
+#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */\r
+#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */\r
+\r
+#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */\r
+#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */\r
+#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */\r
+#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */\r
+#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */\r
+#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */\r
+#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */\r
+#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */\r
+#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */\r
+#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */\r
+#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */\r
+#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */\r
+#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */\r
+#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */\r
+#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
+\r
+#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
+\r
+#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
+#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)\r
+#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)\r
+#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)\r
+\r
+#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */\r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\r
+#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */\r
+/** \r
+ * @brief EXTI0 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) /*!<PK[0] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI1 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) /*!<PK[1] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI2 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) /*!<PK[2] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI3 configuration \r
+ */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) /*!<PK[3] pin */\r
+#endif /* STM32F429X */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */\r
+/** \r
+ * @brief EXTI4 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) /*!<PK[4] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI5 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) /*!<PK[5] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI6 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) /*!<PK[6] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI7 configuration \r
+ */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) /*!<PK[7] pin */\r
+#endif /* STM32F429X */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */\r
+ \r
+/** \r
+ * @brief EXTI8 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) /*!<PJ[8] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI9 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) /*!<PJ[9] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI10 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) /*!<PJ[10] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI11 configuration \r
+ */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) /*!<PJ[11] pin */\r
+#endif /* STM32F429X */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */\r
+/** \r
+ * @brief EXTI12 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) /*!<PJ[12] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI13 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) /*!<PJ[13] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI14 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) /*!<PJ[14] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+ * @brief EXTI15 configuration \r
+ */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) /*!<PJ[15] pin */\r
+#endif /* STM32F429X */\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
+#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */\r
+#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
+#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
+#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
+#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
+#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
+\r
+#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
+#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
+\r
+#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+\r
+#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
+#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
+#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
+#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
+#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+\r
+#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
+\r
+#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
+#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+\r
+#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
+#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
+#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+\r
+#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
+#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
+#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
+#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
+#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR register *********************/\r
+#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for USART_SR register *******************/\r
+#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */\r
+#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */\r
+#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */\r
+#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */\r
+#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */\r
+#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */\r
+#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */\r
+#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */\r
+#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */\r
+#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */\r
+\r
+/******************* Bit definition for USART_DR register *******************/\r
+#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */\r
+#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */\r
+#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */\r
+#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */\r
+#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */\r
+#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */\r
+#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */\r
+#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */\r
+#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
+#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
+#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
+#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
+#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */\r
+#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */\r
+#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */\r
+#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */\r
+#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */\r
+\r
+#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
+#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
+\r
+#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */\r
+#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */\r
+#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */\r
+#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */\r
+#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */\r
+#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */\r
+#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */\r
+#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */\r
+#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
+#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
+#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
+\r
+#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */\r
+#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */\r
+#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */\r
+#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */\r
+#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */\r
+#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */\r
+#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */\r
+\r
+#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */\r
+#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */\r
+#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */\r
+#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */\r
+#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */\r
+#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */\r
+#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */\r
+\r
+#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */\r
+#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */\r
+\r
+#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)\r
+#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)\r
+#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)\r
+#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)\r
+\r
+#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)\r
+#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */\r
+#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)\r
+#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)\r
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */\r
+#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)\r
+#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)\r
+#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)\r
+#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Ethernet MAC Registers bits definitions */\r
+/* */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
+#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
+#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
+ #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
+ #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
+ #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
+ #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
+ #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
+ #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
+ #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
+#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
+#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
+#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
+#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
+#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
+#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+ a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+ #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
+ #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
+ #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
+ #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
+#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
+#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
+#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
+ #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
+ #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+ #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
+#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
+#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
+ #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+ #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+ #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+ #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+ #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
+#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
+#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
+ \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
+#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
+ #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
+ #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
+ #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
+ #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
+#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+ Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+ Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+ Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+ Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+ Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+ RSVD - Filter1 Command - RSVD - Filter0 Command\r
+ Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+ Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+ Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
+#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
+#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+ #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
+#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
+#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
+ #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
+ #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
+ #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
+ #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
+ #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/* Ethernet MMC Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */\r
+#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
+#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/* Ethernet PTP Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/* Ethernet DMA Registers bits definition */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
+#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
+#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
+ #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+ #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+ #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
+ #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+ #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+ #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+ #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+ #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+ #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
+#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
+ #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
+#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
+ #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+ #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+ #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
+ #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+ #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+ #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+ #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+ #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+ #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
+#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
+#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
+ /* combination with EBS[2:0] for GetFlagStatus function */\r
+ #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
+ #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
+ #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
+ #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
+ #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
+ #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
+ #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
+ #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
+ #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
+ #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
+ #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
+ #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
+ #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
+ #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
+ #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
+#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
+#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
+#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
+#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
+#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
+#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
+#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
+ #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+ #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+ #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+ #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+ #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+ #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
+ #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+ #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+ #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+ #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
+#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
+\r
+/**\r
+ *\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+ #include "stm32f4xx_conf.h"\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F4xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
--- /dev/null
+/**
+ ******************************************************************************
+ * @file system_stm32f4xx.h
+ * @author MCD Application Team
+ * @version V1.6.1
+ * @date 21-October-2015
+ * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
+ *
+ * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+ * You may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at:
+ *
+ * http://www.st.com/software_license_agreement_liberty_v2
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32f4xx_system
+ * @{
+ */
+
+/**
+ * @brief Define to prevent recursive inclusion
+ */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** @addtogroup STM32F4xx_System_Includes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+ * @{
+ */
+
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+ * @{
+ */
+
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null
+/* Label for the program's entry point */
+ENTRY(reset_handler)
+
+/* the end of the stack */
+_estack = 0x20018000;
+
+/* Set minimum size for stack and dynamic memory. */
+/* (The linker will generate an error if there is
+ * less than this much RAM leftover.) */
+/* (1KB) */
+_Min_Leftover_RAM = 0x400;
+
+
+MEMORY
+{
+ FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+SECTIONS
+{
+ /* The vector table goes at the start of flash. */
+ .vector_table :
+ {
+ . = ALIGN(4);
+ KEEP (*(.vector_table))
+ . = ALIGN(4);
+ } >FLASH
+ /* The 'text' section contains the main program code. */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text*)
+ . = ALIGN(4);
+ } >FLASH
+ /* The 'rodata' section contains read-only data,
+ * constants, strings, information that won't change. */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata)
+ *(.rodata*)
+ . = ALIGN(4);
+ } >FLASH
+ /* The 'data' section is space set aside in RAM for
+ * things like variables, which can change. */
+ _sidata = .;
+ .data : AT(_sidata)
+ {
+ . = ALIGN(4);
+ /* Mark start/end locations for the 'data' section. */
+ _sdata = .;
+ *(.data)
+ *(.data*)
+ _edata = .;
+ . = ALIGN(4);
+ } >RAM
+ /* The 'bss' section is similar to the 'data' section,
+ * but its space is initialized to all 0s at the
+ * start of the program. */
+ .bss :
+ {
+ . = ALIGN(4);
+ /* Also mark the start/end of the BSS section. */
+ _sbss = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = .;
+ } >RAM
+ /* Space set aside for the application's heap/stack. */
+ .dynamic_allocations :
+ {
+ . = ALIGN(4);
+ _ssystem_ram = .;
+ . = . + _Min_Leftover_RAM;
+ . = ALIGN(4);
+ _esystem_ram = .;
+ } >RAM
+}
--- /dev/null
+#include "main.h"
+
+/**
+ * Main program.
+ */
+int main(void) {
+ // Enable the GPIOa and GPIOC peripheral in RCC.
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ;
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ;
+
+ // Initialize the GPIOC pins.
+ // C15 should be set to 'input' mode with pull-up.
+ GPIOC->MODER &= ~(0x3 << (BUTTON_PIN*2));
+ GPIOC->PUPDR &= ~(0x3 << (BUTTON_PIN*2));
+ GPIOC->PUPDR |= (0x1 << (BUTTON_PIN*2));
+
+ // A5 is connected to an LED on the 'Nucleo' board.
+ // It should be set to push-pull low-speed output.
+ GPIOA->MODER &= ~(0x3 << (LED_PIN*2));
+ GPIOA->MODER |= (0x1 << (LED_PIN*2));
+ GPIOA->OTYPER &= ~(1 << LED_PIN);
+
+ // Main loop
+ while (1){
+ // Invert the IDR register since '0' means 'pressed'.
+ uint32_t idr_val = ~GPIOC->IDR;
+ if (idr_val & (1 << BUTTON_PIN)) {
+ GPIOA->ODR = (1 << LED_PIN);
+ }
+ else {
+ GPIOA->ODR = (0 << LED_PIN);
+ }
+ }
+}
\ No newline at end of file
--- /dev/null
+#ifndef _VVC_MAIN_H
+#define _VVC_MAIN_H
+#include <stdint.h>
+#include "device/stm32f4xx.h"
+// Define GPIOB pin mappings for our LED and button.
+#define BUTTON_PIN (13) //C13
+#define LED_PIN (5) //A5
+#endif
\ No newline at end of file
--- /dev/null
+// These instructions define attributes of our chip and
+// the assembly language we'll use:
+.syntax unified
+.cpu cortex-m4
+.fpu softvfp
+.thumb
+
+// Global memory locations.
+.global vtable
+.global Default_Handler
+
+/*
+ * The actual vector table.
+ */
+.type vtable, %object
+.section .vector_table,"a",%progbits
+vtable:
+ .word _estack
+ .word reset_handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word 0 /* Reserved */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word 0 /* Reserved */
+ .word SDIO_IRQHandler /* SDIO */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word FPU_IRQHandler /* FPU */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SPI4_IRQHandler /* SPI4 */
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak SDIO_IRQHandler
+ .thumb_set SDIO_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+.size vtable, .-vtable
+
+/*
+ * A 'Default' interrupt handler. This is where interrupts
+ * which are not otherwise configured will go.
+ * It is an infinite loop, because...well, we weren't
+ * expecting the interrupt, so what can we do?
+ */
+.section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+ default_interrupt_loop:
+ B default_interrupt_loop
+.size Default_Handler, .-Default_Handler
--- /dev/null
+ENTRY(Reset_Handler)
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+SECTIONS
+{
+ .text :
+ {
+ *(.text)
+ *(.text.*)
+ } > FLASH
+
+ .data :
+ {
+ *(.data)
+ *(.data.*)
+ } > RAM AT > FLASH
+
+ .bss :
+ {
+ *(.bss)
+ *(.bss.*)
+ } > RAM
+}
\ No newline at end of file
--- /dev/null
+// Minimal main.c file
+int main() {
+ // Your code here
+ return 0;
+}
\ No newline at end of file
--- /dev/null
+/**
+ ******************************************************************************
+ * @file startup_stm32f730xx.s
+ * @author MCD Application Team
+ * @brief STM32F730xx Devices vector table for GCC based toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M7 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * Copyright (c) 2016 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software is licensed under terms that can be found in the LICENSE file
+ * in the root directory of this software component.
+ * If no LICENSE file comes with this software, it is provided AS-IS.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m7
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ ldr r0, =_sdata
+ ldr r1, =_edata
+ ldr r2, =_sidata
+ movs r3, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r4, [r2, r3]
+ str r4, [r0, r3]
+ adds r3, r3, #4
+
+LoopCopyDataInit:
+ adds r4, r0, r3
+ cmp r4, r1
+ bcc CopyDataInit
+
+/* Zero fill the bss segment. */
+ ldr r2, =_sbss
+ ldr r4, =_ebss
+ movs r3, #0
+ b LoopFillZerobss
+
+FillZerobss:
+ str r3, [r2]
+ adds r2, r2, #4
+
+LoopFillZerobss:
+ cmp r2, r4
+ bcc FillZerobss
+
+/* Call the clock system intitialization function.*/
+ bl SystemInit
+/* Call static constructors */
+ bl __libc_init_array
+/* Call the application's entry point.*/
+ bl main
+ bx lr
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ * @param None
+ * @retval None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M7. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+*******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .word _estack
+ .word Reset_Handler
+
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+
+ /* External Interrupts */
+ .word WWDG_IRQHandler /* Window WatchDog */
+ .word PVD_IRQHandler /* PVD through EXTI Line detection */
+ .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
+ .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
+ .word FLASH_IRQHandler /* FLASH */
+ .word RCC_IRQHandler /* RCC */
+ .word EXTI0_IRQHandler /* EXTI Line0 */
+ .word EXTI1_IRQHandler /* EXTI Line1 */
+ .word EXTI2_IRQHandler /* EXTI Line2 */
+ .word EXTI3_IRQHandler /* EXTI Line3 */
+ .word EXTI4_IRQHandler /* EXTI Line4 */
+ .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
+ .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
+ .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
+ .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
+ .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
+ .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
+ .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
+ .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
+ .word CAN1_TX_IRQHandler /* CAN1 TX */
+ .word CAN1_RX0_IRQHandler /* CAN1 RX0 */
+ .word CAN1_RX1_IRQHandler /* CAN1 RX1 */
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */
+ .word EXTI9_5_IRQHandler /* External Line[9:5]s */
+ .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
+ .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
+ .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
+ .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
+ .word TIM2_IRQHandler /* TIM2 */
+ .word TIM3_IRQHandler /* TIM3 */
+ .word TIM4_IRQHandler /* TIM4 */
+ .word I2C1_EV_IRQHandler /* I2C1 Event */
+ .word I2C1_ER_IRQHandler /* I2C1 Error */
+ .word I2C2_EV_IRQHandler /* I2C2 Event */
+ .word I2C2_ER_IRQHandler /* I2C2 Error */
+ .word SPI1_IRQHandler /* SPI1 */
+ .word SPI2_IRQHandler /* SPI2 */
+ .word USART1_IRQHandler /* USART1 */
+ .word USART2_IRQHandler /* USART2 */
+ .word USART3_IRQHandler /* USART3 */
+ .word EXTI15_10_IRQHandler /* External Line[15:10]s */
+ .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
+ .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
+ .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
+ .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
+ .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
+ .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
+ .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
+ .word FMC_IRQHandler /* FMC */
+ .word SDMMC1_IRQHandler /* SDMMC1 */
+ .word TIM5_IRQHandler /* TIM5 */
+ .word SPI3_IRQHandler /* SPI3 */
+ .word UART4_IRQHandler /* UART4 */
+ .word UART5_IRQHandler /* UART5 */
+ .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
+ .word TIM7_IRQHandler /* TIM7 */
+ .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
+ .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
+ .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
+ .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
+ .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word OTG_FS_IRQHandler /* USB OTG FS */
+ .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
+ .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
+ .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
+ .word USART6_IRQHandler /* USART6 */
+ .word I2C3_EV_IRQHandler /* I2C3 event */
+ .word I2C3_ER_IRQHandler /* I2C3 error */
+ .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
+ .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
+ .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
+ .word OTG_HS_IRQHandler /* USB OTG HS */
+ .word 0 /* Reserved */
+ .word AES_IRQHandler /* AES */
+ .word RNG_IRQHandler /* RNG */
+ .word FPU_IRQHandler /* FPU */
+ .word UART7_IRQHandler /* UART7 */
+ .word UART8_IRQHandler /* UART8 */
+ .word SPI4_IRQHandler /* SPI4 */
+ .word SPI5_IRQHandler /* SPI5 */
+ .word 0 /* Reserved */
+ .word SAI1_IRQHandler /* SAI1 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SAI2_IRQHandler /* SAI2 */
+ .word QUADSPI_IRQHandler /* QUADSPI */
+ .word LPTIM1_IRQHandler /* LPTIM1 */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word 0 /* Reserved */
+ .word SDMMC2_IRQHandler /* SDMMC2 */
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_IRQHandler
+ .thumb_set PVD_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream0_IRQHandler
+ .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream1_IRQHandler
+ .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream2_IRQHandler
+ .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream3_IRQHandler
+ .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream4_IRQHandler
+ .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream5_IRQHandler
+ .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream6_IRQHandler
+ .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+
+ .weak ADC_IRQHandler
+ .thumb_set ADC_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM9_IRQHandler
+ .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM10_IRQHandler
+ .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM11_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak OTG_FS_WKUP_IRQHandler
+ .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_TIM12_IRQHandler
+ .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_TIM13_IRQHandler
+ .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_TIM14_IRQHandler
+ .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak DMA1_Stream7_IRQHandler
+ .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream0_IRQHandler
+ .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream1_IRQHandler
+ .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream2_IRQHandler
+ .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream3_IRQHandler
+ .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream4_IRQHandler
+ .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream5_IRQHandler
+ .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream6_IRQHandler
+ .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+
+ .weak DMA2_Stream7_IRQHandler
+ .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+
+ .weak USART6_IRQHandler
+ .thumb_set USART6_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_OUT_IRQHandler
+ .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+
+ .weak OTG_HS_EP1_IN_IRQHandler
+ .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+
+ .weak OTG_HS_WKUP_IRQHandler
+ .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+
+ .weak OTG_HS_IRQHandler
+ .thumb_set OTG_HS_IRQHandler,Default_Handler
+
+ .weak AES_IRQHandler
+ .thumb_set AES_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+
+ .weak UART7_IRQHandler
+ .thumb_set UART7_IRQHandler,Default_Handler
+
+ .weak UART8_IRQHandler
+ .thumb_set UART8_IRQHandler,Default_Handler
+
+ .weak SPI4_IRQHandler
+ .thumb_set SPI4_IRQHandler,Default_Handler
+
+ .weak SPI5_IRQHandler
+ .thumb_set SPI5_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak SDMMC2_IRQHandler
+ .thumb_set SDMMC2_IRQHandler,Default_Handler
+
+
\ No newline at end of file
--- /dev/null
+TARGET = main
+
+# Directories
+SRC_DIR = src
+BUILD_DIR = build
+
+# Define the linker script location and chip architecture.
+LD_SCRIPT = $(SRC_DIR)/linker.ld
+MCU_SPEC = cortex-m7
+
+# Toolchain definitions (ARM bare metal defaults)
+TOOLCHAIN = /usr
+CP = $(TOOLCHAIN)/bin/arm-none-eabi-g++
+CC = $(TOOLCHAIN)/bin/arm-none-eabi-gcc
+AS = $(TOOLCHAIN)/bin/arm-none-eabi-as
+LD = $(TOOLCHAIN)/bin/arm-none-eabi-ld
+OC = $(TOOLCHAIN)/bin/arm-none-eabi-objcopy
+OD = $(TOOLCHAIN)/bin/arm-none-eabi-objdump
+OS = $(TOOLCHAIN)/bin/arm-none-eabi-size
+
+# Assembly directives.
+ASFLAGS += -c
+ASFLAGS += -O0
+ASFLAGS += -mcpu=$(MCU_SPEC)
+ASFLAGS += -march=armv7e-m
+ASFLAGS += -mfpu=fpv5-sp-d16
+ASFLAGS += -mfloat-abi=softfp
+ASFLAGS += -mthumb
+ASFLAGS += -Wall
+# (Set error messages to appear on a single line.)
+ASFLAGS += -fmessage-length=0
+
+# C compilation directives
+CFLAGS += -mcpu=$(MCU_SPEC)
+CFLAGS += -march=armv7e-m
+CFLAGS += -mfpu=fpv5-sp-d16
+CFLAGS += -mfloat-abi=softfp
+CFLAGS += -mthumb
+CFLAGS += -Wall
+CFLAGS += -g
+# (Set error messages to appear on a single line.)
+CFLAGS += -fmessage-length=0
+# (Set system to ignore semihosted junk)
+CFLAGS += --specs=nosys.specs
+
+# Linker directives.
+LSCRIPT = $(LD_SCRIPT)
+LFLAGS += -mcpu=$(MCU_SPEC)
+LFLAGS += -mthumb
+LFLAGS += -Wall
+LFLAGS += --specs=nosys.specs
+LFLAGS += -nostdlib
+LFLAGS += -lgcc
+LFLAGS += -T$(LSCRIPT)
+
+# AS_SRC = $(SRC_DIR)/core.S
+#C_SRC = $(SRC_DIR)/main.c
+CPP_SRC := $(wildcard $(SRC_DIR)/*.cpp)
+
+INCLUDE = -I./
+INCLUDE += -I./device
+
+#OBJS = $(BUILD_DIR)/$(notdir $(AS_SRC:.S=.o))
+#OBJS += $(BUILD_DIR)/$(notdir $(C_SRC:.c=.o))
+OBJS += $(patsubst $(SRC_DIR)/%.cpp, $(BUILD_DIR)/%.o, $(CPP_SRC))
+
+.PHONY: all
+all: $(BUILD_DIR)/$(TARGET).bin
+
+#$(BUILD_DIR)/%.o: $(SRC_DIR)/%.S
+# $(CC) -x assembler-with-cpp $(ASFLAGS) $< -o $@
+
+$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
+ $(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
+
+$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp
+ $(CP) -c $(CFLAGS) $(INCLUDE) $< -o $@
+
+$(BUILD_DIR)/$(TARGET).elf: $(OBJS)
+ $(CC) $^ $(LFLAGS) -o $@
+
+$(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
+ $(OC) -S -O binary $< $@
+ $(OS) $<
+
+.PHONY: clean
+clean:
+ rm -f $(BUILD_DIR)/*.o
+ rm -f $(BUILD_DIR)/$(TARGET).elf
+ rm -f $(BUILD_DIR)/$(TARGET).bin
\ No newline at end of file
--- /dev/null
+/*
+ * Test program to boot an STM32 chip with the absolute
+ * minimum required code for teaching about the chips.
+ *
+ * Copyright William Ransohoff, Vivonomicon, LLC, 2017
+ *
+ * Open source under the MIT License
+ */
+
+.syntax unified
+.cpu cortex-m7
+.fpu softvfp
+.thumb
+
+// Global values.
+.global vtable
+.global reset_handler
+
+/*
+ * The vector table.
+ * Most entries are ommitted for simplicity.
+ */
+
+/*
+ * The Reset handler. Called on reset.
+ */
+.type reset_handler, %function
+reset_handler:
+ // Set the stack pointer to the end of the stack.
+ // The '_estack' value is defined in our linker script.
+ LDR r0, =_estack
+ MOV sp, r0
+
+ // Copy data from flash to RAM data init section.
+ // R2 will store our progress along the sidata section.
+ MOVS r0, #0
+ // Load the start/end addresses of the data section,
+ // and the start of the data init section.
+ LDR r1, =_sdata
+ LDR r2, =_edata
+ LDR r3, =_sidata
+ B copy_sidata_loop
+
+ copy_sidata:
+ // Offset the data init section by our copy progress.
+ LDR r4, [r3, r0]
+ // Copy the current word into data, and increment.
+ STR r4, [r1, r0]
+ ADDS r0, r0, #4
+
+ copy_sidata_loop:
+ // Unless we've copied the whole data section, copy the
+ // next word from sidata->data.
+ ADDS r4, r0, r1
+ CMP r4, r2
+ BCC copy_sidata
+
+ // Once we are done copying the data section into RAM,
+ // move on to filling the BSS section with 0s.
+ MOVS r0, #0
+ LDR r1, =_sbss
+ LDR r2, =_ebss
+ B reset_bss_loop
+
+ // Zero out the BSS segment.
+ reset_bss:
+ // Store a 0 and increment by a word.
+ STR r0, [r1]
+ ADDS r1, r1, #4
+
+ reset_bss_loop:
+ // We'll use R1 to count progress here; if we aren't
+ // done, reset the next word and increment.
+ CMP r1, r2
+ BCC reset_bss
+
+ // Branch to the 'main' method.
+ B main
+.size reset_handler, .-reset_handler
\ No newline at end of file
--- /dev/null
+/**************************************************************************//**\r
+ * @file cmsis_gcc.h\r
+ * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Enable IRQ Interrupts\r
+ \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+ __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable IRQ Interrupts\r
+ \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+ __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Control Register\r
+ \details Returns the content of the Control Register.\r
+ \return Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Control Register\r
+ \details Writes the given value to the Control Register.\r
+ \param [in] control Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+ __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get IPSR Register\r
+ \details Returns the content of the IPSR Register.\r
+ \return IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get APSR Register\r
+ \details Returns the content of the APSR Register.\r
+ \return APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get xPSR Register\r
+ \details Returns the content of the xPSR Register.\r
+\r
+ \return xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Process Stack Pointer\r
+ \details Returns the current value of the Process Stack Pointer (PSP).\r
+ \return PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Process Stack Pointer\r
+ \details Assigns the given value to the Process Stack Pointer (PSP).\r
+ \param [in] topOfProcStack Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Main Stack Pointer\r
+ \details Returns the current value of the Main Stack Pointer (MSP).\r
+ \return MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+ register uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Main Stack Pointer\r
+ \details Assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+ \param [in] topOfMainStack Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Mask\r
+ \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+ \return Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Priority Mask\r
+ \details Assigns the given value to the Priority Mask Register.\r
+ \param [in] priMask Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U)\r
+\r
+/**\r
+ \brief Enable FIQ\r
+ \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable FIQ\r
+ \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+ Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+ __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Base Priority\r
+ \details Returns the current value of the Base Priority register.\r
+ \return Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority\r
+ \details Assigns the given value to the Base Priority register.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Base Priority with condition\r
+ \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+ or the new value increases the BASEPRI priority level.\r
+ \param [in] basePri Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+ __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Fault Mask\r
+ \details Returns the current value of the Fault Mask register.\r
+ \return Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Fault Mask\r
+ \details Assigns the given value to the Fault Mask register.\r
+ \param [in] faultMask Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) */\r
+\r
+\r
+#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+ \brief Get FPSCR\r
+ \details Returns the current value of the Floating Point Status/Control register.\r
+ \return Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ uint32_t result;\r
+\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+ __ASM volatile ("");\r
+ return(result);\r
+#else\r
+ return(0);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Set FPSCR\r
+ \details Assigns the given value to the Floating Point Status/Control register.\r
+ \param [in] fpscr Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+ /* Empty asm statement works as a scheduling barrier */\r
+ __ASM volatile ("");\r
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+ __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+ \brief No Operation\r
+ \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+ __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Interrupt\r
+ \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+ __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+ \brief Wait For Event\r
+ \details Wait For Event is a hint instruction that permits the processor to enter\r
+ a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+ __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+ \brief Send Event\r
+ \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+ __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+ \brief Instruction Synchronization Barrier\r
+ \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+ so that all instructions following the ISB are fetched from cache or memory,\r
+ after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+ __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Synchronization Barrier\r
+ \details Acts as a special kind of Data Memory Barrier.\r
+ It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+ __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Data Memory Barrier\r
+ \details Ensures the apparent order of the explicit memory operations before\r
+ and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+ __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (32 bit)\r
+ \details Reverses the byte order in integer value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+ return __builtin_bswap32(value);\r
+#else\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order (16 bit)\r
+ \details Reverses the byte order in two unsigned short values.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Reverse byte order in signed short value\r
+ \details Reverses the byte order in a signed short value with sign extension to integer.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ return (short)__builtin_bswap16(value);\r
+#else\r
+ int32_t result;\r
+\r
+ __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Rotate Right in unsigned value (32 bit)\r
+ \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+ \param [in] value Value to rotate\r
+ \param [in] value Number of Bits to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+ return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+ \brief Breakpoint\r
+ \details Causes the processor to enter Debug state.\r
+ Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+ \param [in] value is ignored by the processor.\r
+ If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+ \brief Reverse bit order of value\r
+ \details Reverses the bit order of the given value.\r
+ \param [in] value Value to reverse\r
+ \return Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+ int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+ result = value; /* r will be reversed bits of v; first get LSB of v */\r
+ for (value >>= 1U; value; value >>= 1U)\r
+ {\r
+ result <<= 1U;\r
+ result |= value & 1U;\r
+ s--;\r
+ }\r
+ result <<= s; /* shift when v's highest bits are zero */\r
+#endif\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Count leading zeros\r
+ \details Counts the number of leading zeros of a data value.\r
+ \param [in] value Value to count the leading zeros\r
+ \return number of leading zeros in value\r
+ */\r
+#define __CLZ __builtin_clz\r
+\r
+\r
+#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+ \brief LDR Exclusive (8 bit)\r
+ \details Executes a exclusive LDR instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (16 bit)\r
+ \details Executes a exclusive LDR instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDR Exclusive (32 bit)\r
+ \details Executes a exclusive LDR instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (8 bit)\r
+ \details Executes a exclusive STR instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (16 bit)\r
+ \details Executes a exclusive STR instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STR Exclusive (32 bit)\r
+ \details Executes a exclusive STR instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ \return 0 Function succeeded\r
+ \return 1 Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief Remove the exclusive lock\r
+ \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+ __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+ \brief Signed Saturate\r
+ \details Saturates a signed value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (1..32)\r
+ \return Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Unsigned Saturate\r
+ \details Saturates an unsigned value.\r
+ \param [in] value Value to be saturated\r
+ \param [in] sat Bit position to saturate to (0..31)\r
+ \return Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+\r
+/**\r
+ \brief Rotate Right with Extend (32 bit)\r
+ \details Moves each bit of a bitstring right by one bit.\r
+ The carry input is shifted in at the left end of the bitstring.\r
+ \param [in] value Value to rotate\r
+ \return Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint8_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+ __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+ /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+ accepted by assembler. So has to use following less efficient pattern.\r
+ */\r
+ __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+ return ((uint16_t) result); /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+ \brief LDRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+ \param [in] ptr Pointer to data\r
+ \return value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+ return(result);\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (8 bit)\r
+ \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+{\r
+ __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (16 bit)\r
+ \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+{\r
+ __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+ \brief STRT Unprivileged (32 bit)\r
+ \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+ \param [in] value Value to store\r
+ \param [in] ptr Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+{\r
+ __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({ \\r
+ int32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1); \\r
+ __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+ union llreg_u{\r
+ uint32_t w32[2];\r
+ uint64_t w64;\r
+ } llr;\r
+ llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__ /* Little endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else /* Big endian */\r
+ __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+ return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
+{\r
+ uint32_t result;\r
+\r
+ __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+ return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({ \\r
+ uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+ if (ARG3 == 0) \\r
+ __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
+ else \\r
+ __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
+ __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cm7.h\r
+ * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CM7_H_GENERIC\r
+#define __CORE_CM7_H_GENERIC\r
+\r
+#include <stdint.h>\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/**\r
+ \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions\r
+ CMSIS violates the following MISRA-C:2004 rules:\r
+\r
+ \li Required Rule 8.5, object/function definition in header file.<br>\r
+ Function definitions in header files are used to allow 'inlining'.\r
+\r
+ \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>\r
+ Unions are used for effective representation of core registers.\r
+\r
+ \li Advisory Rule 19.7, Function-like macro defined.<br>\r
+ Function-like macros are used to allow more efficient code.\r
+ */\r
+\r
+\r
+/*******************************************************************************\r
+ * CMSIS definitions\r
+ ******************************************************************************/\r
+/**\r
+ \ingroup Cortex_M7\r
+ @{\r
+ */\r
+\r
+/* CMSIS CM7 definitions */\r
+#define __CM7_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */\r
+#define __CM7_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */\r
+#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \\r
+ __CM7_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */\r
+\r
+#define __CORTEX_M (0x07U) /*!< Cortex-M Core */\r
+\r
+\r
+#if defined ( __CC_ARM )\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */\r
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */\r
+ #define __STATIC_INLINE static __inline\r
+\r
+#elif defined ( __GNUC__ )\r
+ #define __ASM __asm /*!< asm keyword for GNU Compiler */\r
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */\r
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TMS470__ )\r
+ #define __ASM __asm /*!< asm keyword for TI CCS Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __TASKING__ )\r
+ #define __ASM __asm /*!< asm keyword for TASKING Compiler */\r
+ #define __INLINE inline /*!< inline keyword for TASKING Compiler */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#elif defined ( __CSMC__ )\r
+ #define __packed\r
+ #define __ASM _asm /*!< asm keyword for COSMIC Compiler */\r
+ #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */\r
+ #define __STATIC_INLINE static inline\r
+\r
+#else\r
+ #error Unknown compiler\r
+#endif\r
+\r
+/** __FPU_USED indicates whether an FPU is used or not.\r
+ For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.\r
+*/\r
+#if defined ( __CC_ARM )\r
+ #if defined __TARGET_FPU_VFP\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #if defined __ARM_PCS_VFP\r
+ #if (__FPU_PRESENT == 1)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __GNUC__ )\r
+ #if defined (__VFP_FP__) && !defined(__SOFTFP__)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __ICCARM__ )\r
+ #if defined __ARMVFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TMS470__ )\r
+ #if defined __TI_VFP_SUPPORT__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __TASKING__ )\r
+ #if defined __FPU_VFP__\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#elif defined ( __CSMC__ )\r
+ #if ( __CSMC__ & 0x400U)\r
+ #if (__FPU_PRESENT == 1U)\r
+ #define __FPU_USED 1U\r
+ #else\r
+ #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"\r
+ #define __FPU_USED 0U\r
+ #endif\r
+ #else\r
+ #define __FPU_USED 0U\r
+ #endif\r
+\r
+#endif\r
+\r
+#include "core_cmInstr.h" /* Core Instruction Access */\r
+#include "core_cmFunc.h" /* Core Function Access */\r
+#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_GENERIC */\r
+\r
+#ifndef __CMSIS_GENERIC\r
+\r
+#ifndef __CORE_CM7_H_DEPENDANT\r
+#define __CORE_CM7_H_DEPENDANT\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+/* check device defines and use defaults */\r
+#if defined __CHECK_DEVICE_DEFINES\r
+ #ifndef __CM7_REV\r
+ #define __CM7_REV 0x0000U\r
+ #warning "__CM7_REV not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __FPU_PRESENT\r
+ #define __FPU_PRESENT 0U\r
+ #warning "__FPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __MPU_PRESENT\r
+ #define __MPU_PRESENT 0U\r
+ #warning "__MPU_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __ICACHE_PRESENT\r
+ #define __ICACHE_PRESENT 0U\r
+ #warning "__ICACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DCACHE_PRESENT\r
+ #define __DCACHE_PRESENT 0U\r
+ #warning "__DCACHE_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __DTCM_PRESENT\r
+ #define __DTCM_PRESENT 0U\r
+ #warning "__DTCM_PRESENT not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __NVIC_PRIO_BITS\r
+ #define __NVIC_PRIO_BITS 3U\r
+ #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"\r
+ #endif\r
+\r
+ #ifndef __Vendor_SysTickConfig\r
+ #define __Vendor_SysTickConfig 0U\r
+ #warning "__Vendor_SysTickConfig not defined in device header file; using default!"\r
+ #endif\r
+#endif\r
+\r
+/* IO definitions (access restrictions to peripheral registers) */\r
+/**\r
+ \defgroup CMSIS_glob_defs CMSIS Global Defines\r
+\r
+ <strong>IO Type Qualifiers</strong> are used\r
+ \li to specify the access to peripheral variables.\r
+ \li for automatic generation of peripheral register debug information.\r
+*/\r
+#ifdef __cplusplus\r
+ #define __I volatile /*!< Defines 'read only' permissions */\r
+#else\r
+ #define __I volatile const /*!< Defines 'read only' permissions */\r
+#endif\r
+#define __O volatile /*!< Defines 'write only' permissions */\r
+#define __IO volatile /*!< Defines 'read / write' permissions */\r
+\r
+/* following defines should be used for structure members */\r
+#define __IM volatile const /*! Defines 'read only' structure member permissions */\r
+#define __OM volatile /*! Defines 'write only' structure member permissions */\r
+#define __IOM volatile /*! Defines 'read / write' structure member permissions */\r
+\r
+/*@} end of group Cortex_M7 */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Register Abstraction\r
+ Core Register contain:\r
+ - Core Register\r
+ - Core NVIC Register\r
+ - Core SCB Register\r
+ - Core SysTick Register\r
+ - Core Debug Register\r
+ - Core MPU Register\r
+ - Core FPU Register\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_core_register Defines and Type Definitions\r
+ \brief Type definitions and defines for Cortex-M processor based devices.\r
+*/\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CORE Status and Control Registers\r
+ \brief Core Register type definitions.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Union type to access the Application Program Status Register (APSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} APSR_Type;\r
+\r
+/* APSR Register Definitions */\r
+#define APSR_N_Pos 31U /*!< APSR: N Position */\r
+#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */\r
+\r
+#define APSR_Z_Pos 30U /*!< APSR: Z Position */\r
+#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */\r
+\r
+#define APSR_C_Pos 29U /*!< APSR: C Position */\r
+#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */\r
+\r
+#define APSR_V_Pos 28U /*!< APSR: V Position */\r
+#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */\r
+\r
+#define APSR_Q_Pos 27U /*!< APSR: Q Position */\r
+#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */\r
+\r
+#define APSR_GE_Pos 16U /*!< APSR: GE Position */\r
+#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Interrupt Program Status Register (IPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} IPSR_Type;\r
+\r
+/* IPSR Register Definitions */\r
+#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */\r
+#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Special-Purpose Program Status Registers (xPSR).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */\r
+ uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */\r
+ uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */\r
+ uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */\r
+ uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */\r
+ uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */\r
+ uint32_t Q:1; /*!< bit: 27 Saturation condition flag */\r
+ uint32_t V:1; /*!< bit: 28 Overflow condition code flag */\r
+ uint32_t C:1; /*!< bit: 29 Carry condition code flag */\r
+ uint32_t Z:1; /*!< bit: 30 Zero condition code flag */\r
+ uint32_t N:1; /*!< bit: 31 Negative condition code flag */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} xPSR_Type;\r
+\r
+/* xPSR Register Definitions */\r
+#define xPSR_N_Pos 31U /*!< xPSR: N Position */\r
+#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */\r
+\r
+#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */\r
+#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */\r
+\r
+#define xPSR_C_Pos 29U /*!< xPSR: C Position */\r
+#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */\r
+\r
+#define xPSR_V_Pos 28U /*!< xPSR: V Position */\r
+#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */\r
+\r
+#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */\r
+#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */\r
+\r
+#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */\r
+#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */\r
+\r
+#define xPSR_T_Pos 24U /*!< xPSR: T Position */\r
+#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */\r
+\r
+#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */\r
+#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */\r
+\r
+#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */\r
+#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */\r
+\r
+\r
+/**\r
+ \brief Union type to access the Control Registers (CONTROL).\r
+ */\r
+typedef union\r
+{\r
+ struct\r
+ {\r
+ uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */\r
+ uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */\r
+ uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */\r
+ uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */\r
+ } b; /*!< Structure used for bit access */\r
+ uint32_t w; /*!< Type used for word access */\r
+} CONTROL_Type;\r
+\r
+/* CONTROL Register Definitions */\r
+#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */\r
+#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */\r
+\r
+#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */\r
+#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */\r
+\r
+#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */\r
+#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */\r
+\r
+/*@} end of group CMSIS_CORE */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)\r
+ \brief Type definitions for the NVIC Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */\r
+ uint32_t RESERVED0[24U];\r
+ __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */\r
+ uint32_t RSERVED1[24U];\r
+ __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */\r
+ uint32_t RESERVED2[24U];\r
+ __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */\r
+ uint32_t RESERVED3[24U];\r
+ __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */\r
+ uint32_t RESERVED4[56U];\r
+ __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */\r
+ uint32_t RESERVED5[644U];\r
+ __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */\r
+} NVIC_Type;\r
+\r
+/* Software Triggered Interrupt Register Definitions */\r
+#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */\r
+#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */\r
+\r
+/*@} end of group CMSIS_NVIC */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCB System Control Block (SCB)\r
+ \brief Type definitions for the System Control Block Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control Block (SCB).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */\r
+ __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */\r
+ __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */\r
+ __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */\r
+ __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */\r
+ __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */\r
+ __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */\r
+ __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */\r
+ __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */\r
+ __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */\r
+ __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */\r
+ __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */\r
+ __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */\r
+ __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */\r
+ __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */\r
+ __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */\r
+ __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */\r
+ __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */\r
+ __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */\r
+ __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */\r
+ __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */\r
+ __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */\r
+ __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */\r
+ uint32_t RESERVED3[93U];\r
+ __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */\r
+ uint32_t RESERVED4[15U];\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 1 */\r
+ uint32_t RESERVED5[1U];\r
+ __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */\r
+ uint32_t RESERVED6[1U];\r
+ __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */\r
+ __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */\r
+ __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */\r
+ __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */\r
+ __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */\r
+ __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */\r
+ __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */\r
+ __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */\r
+ uint32_t RESERVED7[6U];\r
+ __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */\r
+ __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */\r
+ __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */\r
+ __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */\r
+ __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */\r
+ uint32_t RESERVED8[1U];\r
+ __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */\r
+} SCB_Type;\r
+\r
+/* SCB CPUID Register Definitions */\r
+#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */\r
+#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */\r
+\r
+#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */\r
+#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */\r
+\r
+#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */\r
+#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */\r
+\r
+#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */\r
+#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */\r
+\r
+#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */\r
+#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */\r
+\r
+/* SCB Interrupt Control State Register Definitions */\r
+#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */\r
+#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */\r
+#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */\r
+\r
+#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */\r
+#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */\r
+\r
+#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */\r
+#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */\r
+\r
+#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */\r
+#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */\r
+\r
+#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */\r
+#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */\r
+\r
+#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */\r
+#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */\r
+\r
+#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */\r
+#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */\r
+\r
+#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */\r
+#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */\r
+\r
+#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */\r
+#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */\r
+\r
+/* SCB Vector Table Offset Register Definitions */\r
+#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */\r
+#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */\r
+\r
+/* SCB Application Interrupt and Reset Control Register Definitions */\r
+#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */\r
+#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */\r
+\r
+#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */\r
+#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */\r
+\r
+#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */\r
+#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */\r
+\r
+#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */\r
+#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */\r
+\r
+#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */\r
+#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */\r
+\r
+#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */\r
+#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */\r
+\r
+#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */\r
+#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */\r
+\r
+/* SCB System Control Register Definitions */\r
+#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */\r
+#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */\r
+\r
+#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */\r
+#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */\r
+\r
+#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */\r
+#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */\r
+\r
+/* SCB Configuration Control Register Definitions */\r
+#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */\r
+#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */\r
+\r
+#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */\r
+#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */\r
+\r
+#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */\r
+#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */\r
+\r
+#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */\r
+#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */\r
+\r
+#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */\r
+#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */\r
+\r
+#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */\r
+#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */\r
+\r
+#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */\r
+#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */\r
+\r
+#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */\r
+#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */\r
+\r
+#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */\r
+#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */\r
+\r
+/* SCB System Handler Control and State Register Definitions */\r
+#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */\r
+#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */\r
+#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */\r
+#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */\r
+\r
+#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */\r
+#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */\r
+#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */\r
+#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */\r
+#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */\r
+\r
+#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */\r
+#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */\r
+\r
+#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */\r
+#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */\r
+\r
+#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */\r
+#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */\r
+\r
+#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */\r
+#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */\r
+\r
+#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */\r
+#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */\r
+#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */\r
+\r
+#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */\r
+#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */\r
+\r
+/* SCB Configurable Fault Status Register Definitions */\r
+#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */\r
+#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */\r
+#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */\r
+\r
+#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */\r
+#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */\r
+\r
+/* SCB Hard Fault Status Register Definitions */\r
+#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */\r
+#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */\r
+\r
+#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */\r
+#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */\r
+\r
+#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */\r
+#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */\r
+\r
+/* SCB Debug Fault Status Register Definitions */\r
+#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */\r
+#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */\r
+\r
+#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */\r
+#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */\r
+\r
+#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */\r
+#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */\r
+\r
+#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */\r
+#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */\r
+\r
+#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */\r
+#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */\r
+\r
+/* SCB Cache Level ID Register Definitions */\r
+#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */\r
+#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */\r
+\r
+#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */\r
+#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */\r
+\r
+/* SCB Cache Type Register Definitions */\r
+#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */\r
+#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */\r
+\r
+#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */\r
+#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */\r
+\r
+#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */\r
+#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */\r
+\r
+#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */\r
+#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */\r
+\r
+#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */\r
+#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */\r
+\r
+/* SCB Cache Size ID Register Definitions */\r
+#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */\r
+#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */\r
+\r
+#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */\r
+#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */\r
+\r
+#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */\r
+#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */\r
+\r
+#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */\r
+#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */\r
+\r
+#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */\r
+#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */\r
+\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */\r
+#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */\r
+\r
+#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */\r
+#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */\r
+\r
+/* SCB Cache Size Selection Register Definitions */\r
+#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */\r
+#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */\r
+\r
+#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */\r
+#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */\r
+\r
+/* SCB Software Triggered Interrupt Register Definitions */\r
+#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */\r
+#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */\r
+\r
+/* SCB D-Cache Invalidate by Set-way Register Definitions */\r
+#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */\r
+#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */\r
+\r
+#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */\r
+#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */\r
+\r
+/* SCB D-Cache Clean by Set-way Register Definitions */\r
+#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */\r
+#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */\r
+\r
+#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */\r
+#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */\r
+\r
+/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */\r
+#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */\r
+#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */\r
+\r
+#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */\r
+#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */\r
+\r
+/* Instruction Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */\r
+#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */\r
+\r
+#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */\r
+#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */\r
+\r
+#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */\r
+#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */\r
+\r
+#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */\r
+#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */\r
+\r
+/* Data Tightly-Coupled Memory Control Register Definitions */\r
+#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */\r
+#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */\r
+\r
+#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */\r
+#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */\r
+\r
+#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */\r
+#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */\r
+\r
+#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */\r
+#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */\r
+\r
+/* AHBP Control Register Definitions */\r
+#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */\r
+#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */\r
+\r
+#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */\r
+#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */\r
+\r
+/* L1 Cache Control Register Definitions */\r
+#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */\r
+#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */\r
+\r
+#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */\r
+#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */\r
+\r
+#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */\r
+#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */\r
+\r
+/* AHBS Control Register Definitions */\r
+#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */\r
+#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */\r
+\r
+#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */\r
+#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */\r
+\r
+#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/\r
+#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */\r
+\r
+/* Auxiliary Bus Fault Status Register Definitions */\r
+#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/\r
+#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */\r
+\r
+#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/\r
+#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */\r
+\r
+#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/\r
+#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */\r
+\r
+#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/\r
+#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */\r
+\r
+#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/\r
+#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */\r
+\r
+#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/\r
+#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */\r
+\r
+/*@} end of group CMSIS_SCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)\r
+ \brief Type definitions for the System Control and ID Register not in the SCB\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Control and ID Register not in the SCB.\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */\r
+ __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */\r
+} SCnSCB_Type;\r
+\r
+/* Interrupt Controller Type Register Definitions */\r
+#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */\r
+#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */\r
+\r
+/* Auxiliary Control Register Definitions */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */\r
+#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */\r
+\r
+#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */\r
+#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */\r
+\r
+#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */\r
+#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */\r
+\r
+#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */\r
+#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */\r
+\r
+#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */\r
+#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */\r
+\r
+/*@} end of group CMSIS_SCnotSCB */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_SysTick System Tick Timer (SysTick)\r
+ \brief Type definitions for the System Timer Registers.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the System Timer (SysTick).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */\r
+ __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */\r
+ __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */\r
+ __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */\r
+} SysTick_Type;\r
+\r
+/* SysTick Control / Status Register Definitions */\r
+#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */\r
+#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */\r
+\r
+#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */\r
+#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */\r
+\r
+#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */\r
+#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */\r
+\r
+#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */\r
+#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */\r
+\r
+/* SysTick Reload Register Definitions */\r
+#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */\r
+#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */\r
+\r
+/* SysTick Current Register Definitions */\r
+#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */\r
+#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */\r
+\r
+/* SysTick Calibration Register Definitions */\r
+#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */\r
+#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */\r
+\r
+#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */\r
+#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */\r
+\r
+#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */\r
+#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */\r
+\r
+/*@} end of group CMSIS_SysTick */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)\r
+ \brief Type definitions for the Instrumentation Trace Macrocell (ITM)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).\r
+ */\r
+typedef struct\r
+{\r
+ __OM union\r
+ {\r
+ __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */\r
+ __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */\r
+ __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */\r
+ } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */\r
+ uint32_t RESERVED0[864U];\r
+ __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */\r
+ uint32_t RESERVED1[15U];\r
+ __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */\r
+ uint32_t RESERVED2[15U];\r
+ __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */\r
+ uint32_t RESERVED3[29U];\r
+ __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */\r
+ __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */\r
+ __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */\r
+ uint32_t RESERVED4[43U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */\r
+ uint32_t RESERVED5[6U];\r
+ __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */\r
+ __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */\r
+ __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */\r
+ __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */\r
+ __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */\r
+ __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */\r
+ __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */\r
+ __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */\r
+ __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */\r
+ __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */\r
+ __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */\r
+ __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */\r
+} ITM_Type;\r
+\r
+/* ITM Trace Privilege Register Definitions */\r
+#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */\r
+#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */\r
+\r
+/* ITM Trace Control Register Definitions */\r
+#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */\r
+#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */\r
+\r
+#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */\r
+#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */\r
+\r
+#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */\r
+#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */\r
+\r
+#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */\r
+#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */\r
+\r
+#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */\r
+#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */\r
+\r
+#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */\r
+#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */\r
+\r
+#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */\r
+#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */\r
+\r
+#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */\r
+#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */\r
+\r
+#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */\r
+#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */\r
+\r
+/* ITM Integration Write Register Definitions */\r
+#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */\r
+#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */\r
+\r
+/* ITM Integration Read Register Definitions */\r
+#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */\r
+#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */\r
+\r
+/* ITM Integration Mode Control Register Definitions */\r
+#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */\r
+#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */\r
+\r
+/* ITM Lock Status Register Definitions */\r
+#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */\r
+#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */\r
+\r
+#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */\r
+#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */\r
+\r
+#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */\r
+#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_ITM */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)\r
+ \brief Type definitions for the Data Watchpoint and Trace (DWT)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Data Watchpoint and Trace Register (DWT).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */\r
+ __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */\r
+ __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */\r
+ __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */\r
+ __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */\r
+ __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */\r
+ __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */\r
+ __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */\r
+ __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */\r
+ __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */\r
+ __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */\r
+ __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */\r
+ __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */\r
+ uint32_t RESERVED1[1U];\r
+ __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */\r
+ __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */\r
+ __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */\r
+ uint32_t RESERVED2[1U];\r
+ __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */\r
+ __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */\r
+ __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */\r
+ uint32_t RESERVED3[981U];\r
+ __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */\r
+ __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */\r
+} DWT_Type;\r
+\r
+/* DWT Control Register Definitions */\r
+#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */\r
+#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */\r
+\r
+#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */\r
+#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */\r
+\r
+#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */\r
+#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */\r
+\r
+#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */\r
+#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */\r
+\r
+#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */\r
+#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */\r
+\r
+#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */\r
+#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */\r
+\r
+#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */\r
+#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */\r
+\r
+#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */\r
+#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */\r
+\r
+#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */\r
+#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */\r
+#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */\r
+\r
+#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */\r
+#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */\r
+\r
+#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */\r
+#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */\r
+\r
+#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */\r
+#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */\r
+\r
+#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */\r
+#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */\r
+\r
+#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */\r
+#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */\r
+\r
+#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */\r
+#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */\r
+\r
+#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */\r
+#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */\r
+\r
+#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */\r
+#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */\r
+\r
+/* DWT CPI Count Register Definitions */\r
+#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */\r
+#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */\r
+\r
+/* DWT Exception Overhead Count Register Definitions */\r
+#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */\r
+#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */\r
+\r
+/* DWT Sleep Count Register Definitions */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */\r
+#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */\r
+\r
+/* DWT LSU Count Register Definitions */\r
+#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */\r
+#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */\r
+\r
+/* DWT Folded-instruction Count Register Definitions */\r
+#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */\r
+#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */\r
+\r
+/* DWT Comparator Mask Register Definitions */\r
+#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */\r
+#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */\r
+\r
+/* DWT Comparator Function Register Definitions */\r
+#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */\r
+#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */\r
+#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */\r
+#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */\r
+\r
+#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */\r
+#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */\r
+\r
+#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */\r
+#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */\r
+\r
+#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */\r
+#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */\r
+\r
+#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */\r
+#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */\r
+\r
+#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */\r
+#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */\r
+\r
+#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */\r
+#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_DWT */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_TPI Trace Port Interface (TPI)\r
+ \brief Type definitions for the Trace Port Interface (TPI)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Trace Port Interface Register (TPI).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */\r
+ __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */\r
+ uint32_t RESERVED0[2U];\r
+ __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */\r
+ uint32_t RESERVED1[55U];\r
+ __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */\r
+ uint32_t RESERVED2[131U];\r
+ __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */\r
+ __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */\r
+ __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */\r
+ uint32_t RESERVED3[759U];\r
+ __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */\r
+ __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */\r
+ __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */\r
+ uint32_t RESERVED4[1U];\r
+ __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */\r
+ __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */\r
+ __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */\r
+ uint32_t RESERVED5[39U];\r
+ __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */\r
+ __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */\r
+ uint32_t RESERVED7[8U];\r
+ __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */\r
+ __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */\r
+} TPI_Type;\r
+\r
+/* TPI Asynchronous Clock Prescaler Register Definitions */\r
+#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */\r
+#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */\r
+\r
+/* TPI Selected Pin Protocol Register Definitions */\r
+#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */\r
+#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */\r
+\r
+/* TPI Formatter and Flush Status Register Definitions */\r
+#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */\r
+#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */\r
+\r
+#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */\r
+#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */\r
+\r
+#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */\r
+#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */\r
+\r
+#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */\r
+#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */\r
+\r
+/* TPI Formatter and Flush Control Register Definitions */\r
+#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */\r
+#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */\r
+\r
+#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */\r
+#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */\r
+\r
+/* TPI TRIGGER Register Definitions */\r
+#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */\r
+#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */\r
+\r
+/* TPI Integration ETM Data Register Definitions (FIFO0) */\r
+#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */\r
+#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */\r
+#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */\r
+#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */\r
+#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */\r
+#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */\r
+\r
+#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */\r
+#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */\r
+\r
+#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */\r
+#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */\r
+\r
+/* TPI ITATBCTR2 Register Definitions */\r
+#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */\r
+#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */\r
+\r
+/* TPI Integration ITM Data Register Definitions (FIFO1) */\r
+#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */\r
+#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */\r
+#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */\r
+#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */\r
+\r
+#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */\r
+#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */\r
+\r
+#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */\r
+#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */\r
+\r
+#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */\r
+#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */\r
+\r
+#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */\r
+#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */\r
+\r
+/* TPI ITATBCTR0 Register Definitions */\r
+#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */\r
+#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */\r
+\r
+/* TPI Integration Mode Control Register Definitions */\r
+#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */\r
+#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */\r
+\r
+/* TPI DEVID Register Definitions */\r
+#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */\r
+#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */\r
+\r
+#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */\r
+#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */\r
+\r
+#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */\r
+#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */\r
+\r
+#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */\r
+#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */\r
+\r
+#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */\r
+#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */\r
+\r
+#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */\r
+#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */\r
+\r
+/* TPI DEVTYPE Register Definitions */\r
+#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */\r
+#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */\r
+\r
+#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */\r
+#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */\r
+\r
+/*@}*/ /* end of group CMSIS_TPI */\r
+\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_MPU Memory Protection Unit (MPU)\r
+ \brief Type definitions for the Memory Protection Unit (MPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Memory Protection Unit (MPU).\r
+ */\r
+typedef struct\r
+{\r
+ __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */\r
+ __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */\r
+ __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */\r
+ __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */\r
+ __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */\r
+ __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */\r
+ __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */\r
+ __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */\r
+ __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */\r
+} MPU_Type;\r
+\r
+/* MPU Type Register Definitions */\r
+#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */\r
+#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */\r
+\r
+#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */\r
+#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */\r
+\r
+#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */\r
+#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */\r
+\r
+/* MPU Control Register Definitions */\r
+#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */\r
+#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */\r
+\r
+#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */\r
+#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */\r
+\r
+#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */\r
+#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */\r
+\r
+/* MPU Region Number Register Definitions */\r
+#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */\r
+#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */\r
+\r
+/* MPU Region Base Address Register Definitions */\r
+#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */\r
+#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */\r
+\r
+#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */\r
+#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */\r
+\r
+#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */\r
+#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */\r
+\r
+/* MPU Region Attribute and Size Register Definitions */\r
+#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */\r
+#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */\r
+\r
+#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */\r
+#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */\r
+\r
+#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */\r
+#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */\r
+\r
+#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */\r
+#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */\r
+\r
+#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */\r
+#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */\r
+\r
+#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */\r
+#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */\r
+\r
+#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */\r
+#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */\r
+\r
+#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */\r
+#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */\r
+\r
+#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */\r
+#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */\r
+\r
+#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */\r
+#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */\r
+\r
+/*@} end of group CMSIS_MPU */\r
+#endif\r
+\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_FPU Floating Point Unit (FPU)\r
+ \brief Type definitions for the Floating Point Unit (FPU)\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Floating Point Unit (FPU).\r
+ */\r
+typedef struct\r
+{\r
+ uint32_t RESERVED0[1U];\r
+ __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */\r
+ __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */\r
+ __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */\r
+ __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */\r
+ __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */\r
+ __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */\r
+} FPU_Type;\r
+\r
+/* Floating-Point Context Control Register Definitions */\r
+#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */\r
+#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */\r
+\r
+#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */\r
+#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */\r
+\r
+#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */\r
+#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */\r
+\r
+#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */\r
+#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */\r
+#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */\r
+\r
+#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */\r
+#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */\r
+\r
+#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */\r
+#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */\r
+\r
+#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */\r
+#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */\r
+\r
+#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */\r
+#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */\r
+\r
+/* Floating-Point Context Address Register Definitions */\r
+#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */\r
+#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */\r
+\r
+/* Floating-Point Default Status Control Register Definitions */\r
+#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */\r
+#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */\r
+\r
+#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */\r
+#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */\r
+\r
+#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */\r
+#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */\r
+\r
+#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */\r
+#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */\r
+\r
+/* Media and FP Feature Register 0 Definitions */\r
+#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */\r
+#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */\r
+\r
+#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */\r
+#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */\r
+\r
+#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */\r
+#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */\r
+\r
+#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */\r
+#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */\r
+\r
+#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */\r
+#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */\r
+\r
+#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */\r
+#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */\r
+\r
+#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */\r
+#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */\r
+\r
+#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */\r
+#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */\r
+\r
+/* Media and FP Feature Register 1 Definitions */\r
+#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */\r
+#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */\r
+\r
+#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */\r
+#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */\r
+\r
+#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */\r
+#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */\r
+\r
+#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */\r
+#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */\r
+\r
+/* Media and FP Feature Register 2 Definitions */\r
+\r
+/*@} end of group CMSIS_FPU */\r
+#endif\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)\r
+ \brief Type definitions for the Core Debug Registers\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Structure type to access the Core Debug Register (CoreDebug).\r
+ */\r
+typedef struct\r
+{\r
+ __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */\r
+ __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */\r
+ __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */\r
+ __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */\r
+} CoreDebug_Type;\r
+\r
+/* Debug Halting Control and Status Register Definitions */\r
+#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */\r
+#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */\r
+#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */\r
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */\r
+\r
+#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */\r
+#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */\r
+#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */\r
+\r
+#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */\r
+#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */\r
+#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */\r
+\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */\r
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */\r
+\r
+#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */\r
+#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */\r
+\r
+#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */\r
+#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */\r
+\r
+#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */\r
+#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */\r
+\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */\r
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */\r
+\r
+/* Debug Core Register Selector Register Definitions */\r
+#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */\r
+#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */\r
+\r
+#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */\r
+#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */\r
+\r
+/* Debug Exception and Monitor Control Register Definitions */\r
+#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */\r
+#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */\r
+#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */\r
+#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */\r
+#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */\r
+\r
+#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */\r
+#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */\r
+#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */\r
+#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */\r
+#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */\r
+#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */\r
+#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */\r
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */\r
+#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */\r
+\r
+#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */\r
+#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */\r
+\r
+/*@} end of group CMSIS_CoreDebug */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_bitfield Core register bit field macros\r
+ \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Mask and shift a bit field value for use in a register bit range.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of the bit field.\r
+ \return Masked and shifted value.\r
+*/\r
+#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)\r
+\r
+/**\r
+ \brief Mask and shift a register value to extract a bit filed value.\r
+ \param[in] field Name of the register bit field.\r
+ \param[in] value Value of register.\r
+ \return Masked and shifted bit field value.\r
+*/\r
+#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)\r
+\r
+/*@} end of group CMSIS_core_bitfield */\r
+\r
+\r
+/**\r
+ \ingroup CMSIS_core_register\r
+ \defgroup CMSIS_core_base Core Definitions\r
+ \brief Definitions for base addresses, unions, and structures.\r
+ @{\r
+ */\r
+\r
+/* Memory mapping of Cortex-M4 Hardware */\r
+#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */\r
+#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */\r
+#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */\r
+#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */\r
+#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */\r
+#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */\r
+#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */\r
+#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */\r
+\r
+#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */\r
+#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */\r
+#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */\r
+#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */\r
+#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */\r
+#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */\r
+#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */\r
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */\r
+\r
+#if (__MPU_PRESENT == 1U)\r
+ #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */\r
+ #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */\r
+#endif\r
+\r
+#if (__FPU_PRESENT == 1U)\r
+ #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */\r
+ #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */\r
+#endif\r
+\r
+/*@} */\r
+\r
+\r
+\r
+/*******************************************************************************\r
+ * Hardware Abstraction Layer\r
+ Core Function Interface contains:\r
+ - Core NVIC Functions\r
+ - Core SysTick Functions\r
+ - Core Debug Functions\r
+ - Core Register Access Functions\r
+ ******************************************************************************/\r
+/**\r
+ \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference\r
+*/\r
+\r
+\r
+\r
+/* ########################## NVIC functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_NVICFunctions NVIC Functions\r
+ \brief Functions that manage interrupts and exceptions via the NVIC.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief Set Priority Grouping\r
+ \details Sets the priority grouping field using the required unlock sequence.\r
+ The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.\r
+ Only values from 0..7 are used.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Priority grouping field.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)\r
+{\r
+ uint32_t reg_value;\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+\r
+ reg_value = SCB->AIRCR; /* read old register configuration */\r
+ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */\r
+ reg_value = (reg_value |\r
+ ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */\r
+ SCB->AIRCR = reg_value;\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Priority Grouping\r
+ \details Reads the priority grouping field from the NVIC Interrupt Controller.\r
+ \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)\r
+{\r
+ return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable External Interrupt\r
+ \details Enables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable External Interrupt\r
+ \details Disables a device-specific interrupt in the NVIC interrupt controller.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Pending Interrupt\r
+ \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not pending.\r
+ \return 1 Interrupt status is pending.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Pending Interrupt\r
+ \details Sets the pending bit of an external interrupt.\r
+ \param [in] IRQn Interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Clear Pending Interrupt\r
+ \details Clears the pending bit of an external interrupt.\r
+ \param [in] IRQn External interrupt number. Value cannot be negative.\r
+ */\r
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)\r
+{\r
+ NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Active Interrupt\r
+ \details Reads the active register in NVIC and returns the active bit.\r
+ \param [in] IRQn Interrupt number.\r
+ \return 0 Interrupt status is not active.\r
+ \return 1 Interrupt status is active.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)\r
+{\r
+ return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));\r
+}\r
+\r
+\r
+/**\r
+ \brief Set Interrupt Priority\r
+ \details Sets the priority of an interrupt.\r
+ \note The priority cannot be set for every core interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \param [in] priority Priority to set.\r
+ */\r
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)\r
+{\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+ else\r
+ {\r
+ NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Get Interrupt Priority\r
+ \details Reads the priority of an interrupt.\r
+ The interrupt number can be positive to specify an external (device specific) interrupt,\r
+ or negative to specify an internal (core) interrupt.\r
+ \param [in] IRQn Interrupt number.\r
+ \return Interrupt Priority.\r
+ Value is aligned automatically to the implemented priority bits of the microcontroller.\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)\r
+{\r
+\r
+ if ((int32_t)(IRQn) < 0)\r
+ {\r
+ return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+ else\r
+ {\r
+ return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ \brief Encode Priority\r
+ \details Encodes the priority for an interrupt with the given priority group,\r
+ preemptive priority value, and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [in] PreemptPriority Preemptive priority value (starting from 0).\r
+ \param [in] SubPriority Subpriority value (starting from 0).\r
+ \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().\r
+ */\r
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ return (\r
+ ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |\r
+ ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))\r
+ );\r
+}\r
+\r
+\r
+/**\r
+ \brief Decode Priority\r
+ \details Decodes an interrupt priority value with a given priority group to\r
+ preemptive priority value and subpriority value.\r
+ In case of a conflict between priority grouping and available\r
+ priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.\r
+ \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().\r
+ \param [in] PriorityGroup Used priority group.\r
+ \param [out] pPreemptPriority Preemptive priority value (starting from 0).\r
+ \param [out] pSubPriority Subpriority value (starting from 0).\r
+ */\r
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)\r
+{\r
+ uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */\r
+ uint32_t PreemptPriorityBits;\r
+ uint32_t SubPriorityBits;\r
+\r
+ PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);\r
+ SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));\r
+\r
+ *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);\r
+ *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);\r
+}\r
+\r
+\r
+/**\r
+ \brief System Reset\r
+ \details Initiates a system reset request to reset the MCU.\r
+ */\r
+__STATIC_INLINE void NVIC_SystemReset(void)\r
+{\r
+ __DSB(); /* Ensure all outstanding memory accesses included\r
+ buffered write are completed before reset */\r
+ SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |\r
+ (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |\r
+ SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */\r
+ __DSB(); /* Ensure completion of memory access */\r
+\r
+ for(;;) /* wait until reset */\r
+ {\r
+ __NOP();\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_Core_NVICFunctions */\r
+\r
+\r
+/* ########################## FPU functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_FpuFunctions FPU Functions\r
+ \brief Function that provides FPU type.\r
+ @{\r
+ */\r
+\r
+/**\r
+ \brief get FPU type\r
+ \details returns the FPU type\r
+ \returns\r
+ - \b 0: No FPU\r
+ - \b 1: Single precision FPU\r
+ - \b 2: Double + Single precision FPU\r
+ */\r
+__STATIC_INLINE uint32_t SCB_GetFPUType(void)\r
+{\r
+ uint32_t mvfr0;\r
+\r
+ mvfr0 = SCB->MVFR0;\r
+ if ((mvfr0 & 0x00000FF0UL) == 0x220UL)\r
+ {\r
+ return 2UL; /* Double + Single precision FPU */\r
+ }\r
+ else if ((mvfr0 & 0x00000FF0UL) == 0x020UL)\r
+ {\r
+ return 1UL; /* Single precision FPU */\r
+ }\r
+ else\r
+ {\r
+ return 0UL; /* No FPU */\r
+ }\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_FpuFunctions */\r
+\r
+\r
+\r
+/* ########################## Cache functions #################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_CacheFunctions Cache Functions\r
+ \brief Functions that configure Instruction and Data cache.\r
+ @{\r
+ */\r
+\r
+/* Cache Size ID Register Macros */\r
+#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)\r
+#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )\r
+\r
+\r
+/**\r
+ \brief Enable I-Cache\r
+ \details Turns on I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable I-Cache\r
+ \details Turns off I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */\r
+ SCB->ICIALLU = 0UL; /* invalidate I-Cache */\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate I-Cache\r
+ \details Invalidates I-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateICache (void)\r
+{\r
+ #if (__ICACHE_PRESENT == 1U)\r
+ __DSB();\r
+ __ISB();\r
+ SCB->ICIALLU = 0UL;\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Enable D-Cache\r
+ \details Turns on D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_EnableDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+ __DSB();\r
+\r
+ SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Disable D-Cache\r
+ \details Turns off D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_DisableDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Invalidate D-Cache\r
+ \details Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_InvalidateDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |\r
+ ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean D-Cache\r
+ \details Cleans D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |\r
+ ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief Clean & Invalidate D-Cache\r
+ \details Cleans and Invalidates D-Cache\r
+ */\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache (void)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ uint32_t ccsidr;\r
+ uint32_t sets;\r
+ uint32_t ways;\r
+\r
+ SCB->CSSELR = (0U << 1U) | 0U; /* Level 1 data cache */\r
+ __DSB();\r
+\r
+ ccsidr = SCB->CCSIDR;\r
+\r
+ /* clean & invalidate D-Cache */\r
+ sets = (uint32_t)(CCSIDR_SETS(ccsidr));\r
+ do {\r
+ ways = (uint32_t)(CCSIDR_WAYS(ccsidr));\r
+ do {\r
+ SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |\r
+ ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );\r
+ #if defined ( __CC_ARM )\r
+ __schedule_barrier();\r
+ #endif\r
+ } while (ways--);\r
+ } while(sets--);\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Invalidate by address\r
+ \details Invalidates D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_InvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t)addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean by address\r
+ \details Cleans D-Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/**\r
+ \brief D-Cache Clean and Invalidate by address\r
+ \details Cleans and invalidates D_Cache for the given address\r
+ \param[in] addr address (aligned to 32-byte boundary)\r
+ \param[in] dsize size of memory block (in number of bytes)\r
+*/\r
+__STATIC_INLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)\r
+{\r
+ #if (__DCACHE_PRESENT == 1U)\r
+ int32_t op_size = dsize;\r
+ uint32_t op_addr = (uint32_t) addr;\r
+ int32_t linesize = 32U; /* in Cortex-M7 size of cache line is fixed to 8 words (32 bytes) */\r
+\r
+ __DSB();\r
+\r
+ while (op_size > 0) {\r
+ SCB->DCCIMVAC = op_addr;\r
+ op_addr += linesize;\r
+ op_size -= linesize;\r
+ }\r
+\r
+ __DSB();\r
+ __ISB();\r
+ #endif\r
+}\r
+\r
+\r
+/*@} end of CMSIS_Core_CacheFunctions */\r
+\r
+\r
+\r
+/* ################################## SysTick function ############################################ */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_SysTickFunctions SysTick Functions\r
+ \brief Functions that configure the System.\r
+ @{\r
+ */\r
+\r
+#if (__Vendor_SysTickConfig == 0U)\r
+\r
+/**\r
+ \brief System Tick Configuration\r
+ \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.\r
+ Counter is in free running mode to generate periodic interrupts.\r
+ \param [in] ticks Number of ticks between two interrupts.\r
+ \return 0 Function succeeded.\r
+ \return 1 Function failed.\r
+ \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the\r
+ function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>\r
+ must contain a vendor-specific implementation of this function.\r
+ */\r
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)\r
+{\r
+ if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)\r
+ {\r
+ return (1UL); /* Reload value impossible */\r
+ }\r
+\r
+ SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */\r
+ NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */\r
+ SysTick->VAL = 0UL; /* Load the SysTick Counter Value */\r
+ SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |\r
+ SysTick_CTRL_TICKINT_Msk |\r
+ SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */\r
+ return (0UL); /* Function successful */\r
+}\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_SysTickFunctions */\r
+\r
+\r
+\r
+/* ##################################### Debug In/Output function ########################################### */\r
+/**\r
+ \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_core_DebugFunctions ITM Functions\r
+ \brief Functions that access the ITM debug interface.\r
+ @{\r
+ */\r
+\r
+extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */\r
+#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */\r
+\r
+\r
+/**\r
+ \brief ITM Send Character\r
+ \details Transmits a character via the ITM channel 0, and\r
+ \li Just returns when no debugger is connected that has booked the output.\r
+ \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.\r
+ \param [in] ch Character to transmit.\r
+ \returns Character to transmit.\r
+ */\r
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)\r
+{\r
+ if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */\r
+ ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */\r
+ {\r
+ while (ITM->PORT[0U].u32 == 0UL)\r
+ {\r
+ __NOP();\r
+ }\r
+ ITM->PORT[0U].u8 = (uint8_t)ch;\r
+ }\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Receive Character\r
+ \details Inputs a character via the external variable \ref ITM_RxBuffer.\r
+ \return Received character.\r
+ \return -1 No character pending.\r
+ */\r
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)\r
+{\r
+ int32_t ch = -1; /* no character available */\r
+\r
+ if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)\r
+ {\r
+ ch = ITM_RxBuffer;\r
+ ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */\r
+ }\r
+\r
+ return (ch);\r
+}\r
+\r
+\r
+/**\r
+ \brief ITM Check Character\r
+ \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.\r
+ \return 0 No character available.\r
+ \return 1 Character available.\r
+ */\r
+__STATIC_INLINE int32_t ITM_CheckChar (void)\r
+{\r
+\r
+ if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)\r
+ {\r
+ return (0); /* no character available */\r
+ }\r
+ else\r
+ {\r
+ return (1); /* character available */\r
+ }\r
+}\r
+\r
+/*@} end of CMSIS_core_DebugFunctions */\r
+\r
+\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CM7_H_DEPENDANT */\r
+\r
+#endif /* __CMSIS_GENERIC */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmFunc.h\r
+ * @brief CMSIS Cortex-M Core Function Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ########################### Core Function Access ########################### */\r
+/** \ingroup CMSIS_Core_FunctionInterface\r
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmInstr.h\r
+ * @brief CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ########################## Core Instruction Access ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+ Access to dedicated instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r
--- /dev/null
+/**************************************************************************//**\r
+ * @file core_cmSimd.h\r
+ * @brief CMSIS Cortex-M SIMD Header File\r
+ * @version V4.30\r
+ * @date 20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+ All rights reserved.\r
+ Redistribution and use in source and binary forms, with or without\r
+ modification, are permitted provided that the following conditions are met:\r
+ - Redistributions of source code must retain the above copyright\r
+ notice, this list of conditions and the following disclaimer.\r
+ - Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+ - Neither the name of ARM nor the names of its contributors may be used\r
+ to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+ *\r
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+ ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+ POSSIBILITY OF SUCH DAMAGE.\r
+ ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if defined ( __ICCARM__ )\r
+ #pragma system_include /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #pragma clang system_header /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ################### Compiler specific Intrinsics ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+ Access to dedicated SIMD instructions\r
+ @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if defined ( __CC_ARM )\r
+ #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+ #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+ #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+ #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+ #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+ /*\r
+ * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+ * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+ * Including the CMSIS ones.\r
+ */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+ #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f730xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.\r
+ *\r
+ * This file contains:\r
+ * - Data structures and the address mapping for all peripherals\r
+ * - Peripheral's registers declarations and bits definition\r
+ * - Macros to access peripheral's registers hardware\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.\r
+ *\r
+ * This software is licensed under terms that can be found in the LICENSE file\r
+ * in the root directory of this software component.\r
+ * If no LICENSE file comes with this software, it is provided AS-IS.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS_Device\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f730xx\r
+ * @{\r
+ */\r
+\r
+#ifndef __STM32F730xx_H\r
+#define __STM32F730xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32F7xx Interrupt Number Definition, according to the selected device\r
+ * in @ref Library_configuration_section\r
+ */\r
+typedef enum\r
+{\r
+/****** Cortex-M7 Processor Exceptions Numbers ****************************************************************/\r
+ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M7 Memory Management Interrupt */\r
+ BusFault_IRQn = -11, /*!< 5 Cortex-M7 Bus Fault Interrupt */\r
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M7 Usage Fault Interrupt */\r
+ SVCall_IRQn = -5, /*!< 11 Cortex-M7 SV Call Interrupt */\r
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M7 Debug Monitor Interrupt */\r
+ PendSV_IRQn = -2, /*!< 14 Cortex-M7 Pend SV Interrupt */\r
+ SysTick_IRQn = -1, /*!< 15 Cortex-M7 System Tick Interrupt */\r
+/****** STM32 specific Interrupt Numbers **********************************************************************/\r
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
+ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
+ RCC_IRQn = 5, /*!< RCC global Interrupt */\r
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
+ DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
+ DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
+ DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
+ DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
+ DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
+ DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
+ DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
+ ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
+ TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
+ TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
+ TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
+ TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
+ TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */\r
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
+ OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */\r
+ TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
+ TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
+ TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+ TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
+ DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
+ FMC_IRQn = 48, /*!< FMC global Interrupt */\r
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */\r
+ TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
+ UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
+ UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
+ DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
+ DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
+ DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
+ DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
+ DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
+ ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
+ ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
+ OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
+ DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
+ DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
+ DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
+ USART6_IRQn = 71, /*!< USART6 global interrupt */\r
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
+ OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
+ OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
+ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
+ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
+ AES_IRQn = 79, /*!< AES global interrupt */\r
+ RNG_IRQn = 80, /*!< RNG global interrupt */\r
+ FPU_IRQn = 81, /*!< FPU global interrupt */\r
+ UART7_IRQn = 82, /*!< UART7 global interrupt */\r
+ UART8_IRQn = 83, /*!< UART8 global interrupt */\r
+ SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
+ SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
+ SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
+ SAI2_IRQn = 91, /*!< SAI2 global Interrupt */\r
+ QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */\r
+ LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */\r
+ SDMMC2_IRQn = 103, /*!< SDMMC2 global Interrupt */\r
+} IRQn_Type;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M7 Processor and Core Peripherals\r
+ */\r
+#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */\r
+#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */\r
+#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */\r
+#define __FPU_PRESENT 1U /*!< FPU present */\r
+#define __ICACHE_PRESENT 1U /*!< CM7 instruction cache present */\r
+#define __DCACHE_PRESENT 1U /*!< CM7 data cache present */\r
+#include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */\r
+\r
+\r
+#include "system_stm32f7xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief Analog to Digital Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
+ __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
+ __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
+ __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
+ __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+ __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+ __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+ __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+ __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
+ __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
+ __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
+ __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
+ __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
+ __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
+ __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
+ __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
+ __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
+ __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
+ __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
+ __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
+ __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
+ AND triple modes, Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Controller Area Network TxMailBox\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network FIFOMailBox\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network FilterRegister\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/**\r
+ * @brief Controller Area Network\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */\r
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
+} CAN_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief CRC calculation unit\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */\r
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */\r
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */\r
+} CRC_TypeDef;\r
+\r
+/**\r
+ * @brief Digital to Analog Converter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Debug MCU\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+ __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief DMA Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< DMA stream x configuration register */\r
+ __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
+ __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
+ __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
+ __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
+ __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
+ __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
+ __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
+ __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief External Interrupt/Event Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
+ __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
+ __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
+ __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+ __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
+ __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/**\r
+ * @brief FLASH Registers\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
+ __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
+ __IO uint32_t OPTCR1; /*!< FLASH option control register 1 , Address offset: 0x18 */\r
+ __IO uint32_t OPTCR2; /*!< FLASH option control register 2 , Address offset: 0x1C */\r
+} FLASH_TypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief Flexible Memory Controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */\r
+} FMC_Bank1_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank1E\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank3\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */\r
+ __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */\r
+ __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */\r
+ __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
+ __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/**\r
+ * @brief Flexible Memory Controller Bank5_6\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
+ __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
+ __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
+ __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
+ __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
+} FMC_Bank5_6_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief General Purpose I/O\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */\r
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/**\r
+ * @brief System configuration controller\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
+ __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+ uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */\r
+ __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
+} SYSCFG_TypeDef;\r
+\r
+/**\r
+ * @brief Inter-integrated Circuit Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */\r
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */\r
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */\r
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */\r
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */\r
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */\r
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */\r
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */\r
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */\r
+} I2C_TypeDef;\r
+\r
+/**\r
+ * @brief Independent WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */\r
+} IWDG_TypeDef;\r
+\r
+\r
+\r
+/**\r
+ * @brief Power Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CSR1; /*!< PWR power control/status register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */\r
+ __IO uint32_t CSR2; /*!< PWR power control/status register 2, Address offset: 0x0C */\r
+} PWR_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Reset and Clock Control\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
+ __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
+ __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
+ uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
+ __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
+ uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
+ uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
+ __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
+ uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
+ __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+ __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+ __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+ uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
+ __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+ __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+ uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
+ __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
+ uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
+ __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
+ __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
+ __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
+ __IO uint32_t DCKCFGR1; /*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C */\r
+ __IO uint32_t DCKCFGR2; /*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 */\r
+\r
+} RCC_TypeDef;\r
+\r
+/**\r
+ * @brief Real-Time Clock\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
+ uint32_t reserved; /*!< Reserved */\r
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */\r
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */\r
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */\r
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */\r
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */\r
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */\r
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */\r
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */\r
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */\r
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */\r
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */\r
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */\r
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */\r
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */\r
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */\r
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */\r
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */\r
+} RTC_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Serial Audio Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief SD host Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */\r
+ __IO uint32_t CLKCR; /*!< SDMMClock control register, Address offset: 0x04 */\r
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */\r
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */\r
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */\r
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */\r
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */\r
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */\r
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */\r
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */\r
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */\r
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */\r
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */\r
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */\r
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */\r
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */\r
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */\r
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */\r
+} SDMMC_TypeDef;\r
+\r
+/**\r
+ * @brief Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< SPI status register, Address offset: 0x08 */\r
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */\r
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+ __IO uint32_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
+ __IO uint32_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
+ __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
+ __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
+} SPI_TypeDef;\r
+\r
+/**\r
+ * @brief QUAD Serial Peripheral Interface\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */\r
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */\r
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */\r
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */\r
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */\r
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */\r
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */\r
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */\r
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */\r
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */\r
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */\r
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */\r
+} QUADSPI_TypeDef;\r
+\r
+/**\r
+ * @brief TIM\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */\r
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
+ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */\r
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */\r
+ __IO uint32_t CCR5; /*!< TIM capture/compare mode register5, Address offset: 0x58 */\r
+ __IO uint32_t CCR6; /*!< TIM capture/compare mode register6, Address offset: 0x5C */\r
+\r
+} TIM_TypeDef;\r
+\r
+/**\r
+ * @brief LPTIMIMER\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */\r
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */\r
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */\r
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */\r
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */\r
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */\r
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */\r
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */\r
+} LPTIM_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */\r
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */\r
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */\r
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */\r
+ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */\r
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */\r
+ __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */\r
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */\r
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */\r
+ __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */\r
+ __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */\r
+} USART_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief Window WATCHDOG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+\r
+/**\r
+ * @brief AES hardware accelerator\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */\r
+ __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */\r
+ __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */\r
+ __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */\r
+ __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */\r
+ __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */\r
+ __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */\r
+ __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */\r
+ __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */\r
+ __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */\r
+ __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */\r
+ __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */\r
+ __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */\r
+ __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */\r
+ __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */\r
+ __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */\r
+ __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */\r
+ __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */\r
+ __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */\r
+ __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */\r
+ __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */\r
+ __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */\r
+ __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x6C */\r
+} AES_TypeDef;\r
+/**\r
+ * @brief RNG\r
+ */\r
+\r
+typedef struct\r
+{\r
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @brief USB_OTG_Core_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */\r
+ __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */\r
+ __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */\r
+ __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */\r
+ __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */\r
+ __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */\r
+ __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */\r
+ __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */\r
+ __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */\r
+ __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */\r
+ __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */\r
+ __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */\r
+ uint32_t Reserved30[2]; /*!< Reserved 030h */\r
+ __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */\r
+ __IO uint32_t CID; /*!< User ID Register 03Ch */\r
+ uint32_t Reserved5[3]; /*!< Reserved 040h-048h */\r
+ __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */\r
+ uint32_t Reserved6; /*!< Reserved 050h */\r
+ __IO uint32_t GLPMCFG; /*!< LPM Register 054h */\r
+ uint32_t Reserved7; /*!< Reserved 058h */\r
+ __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */\r
+ uint32_t Reserved43[40]; /*!< Reserved 60h-0FFh */\r
+ __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */\r
+ __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO 104h-13Ch */\r
+} USB_OTG_GlobalTypeDef;\r
+\r
+/**\r
+ * @brief USB_HS_PHY_Registers\r
+ */\r
+typedef struct\r
+{\r
+\r
+__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */\r
+__IO uint32_t Reserved04; /*!< Reserved 004h */\r
+__IO uint32_t Reserved08; /*!< Reserved 008h */\r
+__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */\r
+__IO uint32_t Reserved10; /*!< Reserved 010h */\r
+__IO uint32_t Reserved14; /*!< Reserved 014h */\r
+__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */\r
+} USB_HS_PHYC_GlobalTypeDef;\r
+\r
+/**\r
+ * @brief USB_OTG_device_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DCFG; /*!< dev Configuration Register 800h */\r
+ __IO uint32_t DCTL; /*!< dev Control Register 804h */\r
+ __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */\r
+ uint32_t Reserved0C; /*!< Reserved 80Ch */\r
+ __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */\r
+ __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */\r
+ __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */\r
+ __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */\r
+ uint32_t Reserved20; /*!< Reserved 820h */\r
+ uint32_t Reserved9; /*!< Reserved 824h */\r
+ __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */\r
+ __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */\r
+ __IO uint32_t DTHRCTL; /*!< dev threshold 830h */\r
+ __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */\r
+ __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */\r
+ __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */\r
+ uint32_t Reserved40; /*!< dedicated EP mask 840h */\r
+ __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */\r
+ uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */\r
+ __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */\r
+} USB_OTG_DeviceTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_IN_Endpoint-Specific_Register\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */\r
+ __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */\r
+ uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */\r
+} USB_OTG_INEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_OUT_Endpoint-Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */\r
+ uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */\r
+ __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */\r
+ uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */\r
+ __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */\r
+ __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */\r
+ uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */\r
+} USB_OTG_OUTEndpointTypeDef;\r
+\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Mode_Register_Structures\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCFG; /*!< Host Configuration Register 400h */\r
+ __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */\r
+ __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */\r
+ uint32_t Reserved40C; /*!< Reserved 40Ch */\r
+ __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */\r
+ __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */\r
+ __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */\r
+} USB_OTG_HostTypeDef;\r
+\r
+/**\r
+ * @brief USB_OTG_Host_Channel_Specific_Registers\r
+ */\r
+typedef struct\r
+{\r
+ __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */\r
+ __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */\r
+ __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */\r
+ __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */\r
+ __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */\r
+ __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */\r
+ uint32_t Reserved[2]; /*!< Reserved */\r
+} USB_OTG_HostChannelTypeDef;\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+\r
+\r
+/** @addtogroup Peripheral_memory_map\r
+ * @{\r
+ */\r
+#define RAMITCM_BASE 0x00000000UL /*!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM */\r
+#define FLASHITCM_BASE 0x00200000UL /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over ITCM */\r
+#define FLASHAXI_BASE 0x08000000UL /*!< Base address of : (up to 64 KB) embedded FLASH memory accessible over AXI */\r
+#define RAMDTCM_BASE 0x20000000UL /*!< Base address of : 64KB system data RAM accessible over DTCM */\r
+#define PERIPH_BASE 0x40000000UL /*!< Base address of : AHB/ABP Peripherals */\r
+#define BKPSRAM_BASE 0x40024000UL /*!< Base address of : Backup SRAM(4 KB) */\r
+#define QSPI_BASE 0x90000000UL /*!< Base address of : QSPI memories accessible over AXI */\r
+#define FMC_R_BASE 0xA0000000UL /*!< Base address of : FMC Control registers */\r
+#define QSPI_R_BASE 0xA0001000UL /*!< Base address of : QSPI Control registers */\r
+#define SRAM1_BASE 0x20010000UL /*!< Base address of : 176KB RAM1 accessible over AXI/AHB */\r
+#define SRAM2_BASE 0x2003C000UL /*!< Base address of : 16KB RAM2 accessible over AXI/AHB */\r
+#define FLASH_END 0x0800FFFFUL /*!< FLASH end address */\r
+#define FLASH_OTP_BASE 0x1FF07800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area */\r
+#define FLASH_OTP_END 0x1FF07A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area */\r
+\r
+/* Legacy define */\r
+#define FLASH_BASE FLASHAXI_BASE\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE PERIPH_BASE\r
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)\r
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)\r
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000UL)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)\r
+#define TIM3_BASE (APB1PERIPH_BASE + 0x0400UL)\r
+#define TIM4_BASE (APB1PERIPH_BASE + 0x0800UL)\r
+#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00UL)\r
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)\r
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)\r
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800UL)\r
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00UL)\r
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000UL)\r
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400UL)\r
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)\r
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)\r
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)\r
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)\r
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)\r
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)\r
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)\r
+#define UART4_BASE (APB1PERIPH_BASE + 0x4C00UL)\r
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000UL)\r
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)\r
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)\r
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)\r
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)\r
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)\r
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)\r
+#define UART7_BASE (APB1PERIPH_BASE + 0x7800UL)\r
+#define UART8_BASE (APB1PERIPH_BASE + 0x7C00UL)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE (APB2PERIPH_BASE + 0x0000UL)\r
+#define TIM8_BASE (APB2PERIPH_BASE + 0x0400UL)\r
+#define USART1_BASE (APB2PERIPH_BASE + 0x1000UL)\r
+#define USART6_BASE (APB2PERIPH_BASE + 0x1400UL)\r
+#define SDMMC2_BASE (APB2PERIPH_BASE + 0x1C00UL)\r
+#define ADC1_BASE (APB2PERIPH_BASE + 0x2000UL)\r
+#define ADC2_BASE (APB2PERIPH_BASE + 0x2100UL)\r
+#define ADC3_BASE (APB2PERIPH_BASE + 0x2200UL)\r
+#define ADC_BASE (APB2PERIPH_BASE + 0x2300UL)\r
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00UL)\r
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)\r
+#define SPI4_BASE (APB2PERIPH_BASE + 0x3400UL)\r
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800UL)\r
+#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00UL)\r
+#define TIM9_BASE (APB2PERIPH_BASE + 0x4000UL)\r
+#define TIM10_BASE (APB2PERIPH_BASE + 0x4400UL)\r
+#define TIM11_BASE (APB2PERIPH_BASE + 0x4800UL)\r
+#define SPI5_BASE (APB2PERIPH_BASE + 0x5000UL)\r
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5800UL)\r
+#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00UL)\r
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)\r
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)\r
+#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)\r
+#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000UL)\r
+#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400UL)\r
+#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800UL)\r
+#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00UL)\r
+#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000UL)\r
+#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400UL)\r
+#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800UL)\r
+#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00UL)\r
+#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000UL)\r
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)\r
+#define RCC_BASE (AHB1PERIPH_BASE + 0x3800UL)\r
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00UL)\r
+#define UID_BASE 0x1FF07A10UL /*!< Unique device ID register base address */\r
+#define FLASHSIZE_BASE 0x1FF07A22UL /*!< FLASH Size register base address */\r
+#define PACKAGE_BASE 0x1FF07BF0UL /*!< Package size register base address */\r
+/* Legacy define */\r
+#define PACKAGESIZE_BASE PACKAGE_BASE\r
+\r
+#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000UL)\r
+#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)\r
+#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)\r
+#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)\r
+#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)\r
+#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)\r
+#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)\r
+#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)\r
+#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)\r
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400UL)\r
+#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)\r
+#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)\r
+#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)\r
+#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)\r
+#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)\r
+#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)\r
+#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)\r
+#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)\r
+/*!< AHB2 peripherals */\r
+#define AES_BASE (AHB2PERIPH_BASE + 0x60000UL)\r
+#define RNG_BASE (AHB2PERIPH_BASE + 0x60800UL)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)\r
+#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)\r
+#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)\r
+#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE 0xE0042000UL\r
+\r
+/*!< USB registers base address */\r
+#define USB_OTG_HS_PERIPH_BASE 0x40040000UL\r
+#define USB_OTG_FS_PERIPH_BASE 0x50000000UL\r
+#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00UL\r
+\r
+#define USB_OTG_GLOBAL_BASE 0x0000UL\r
+#define USB_OTG_DEVICE_BASE 0x0800UL\r
+#define USB_OTG_IN_ENDPOINT_BASE 0x0900UL\r
+#define USB_OTG_OUT_ENDPOINT_BASE 0x0B00UL\r
+#define USB_OTG_EP_REG_SIZE 0x0020UL\r
+#define USB_OTG_HOST_BASE 0x0400UL\r
+#define USB_OTG_HOST_PORT_BASE 0x0440UL\r
+#define USB_OTG_HOST_CHANNEL_BASE 0x0500UL\r
+#define USB_OTG_HOST_CHANNEL_SIZE 0x0020UL\r
+#define USB_OTG_PCGCCTL_BASE 0x0E00UL\r
+#define USB_OTG_FIFO_BASE 0x1000UL\r
+#define USB_OTG_FIFO_SIZE 0x1000UL\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Peripheral_declaration\r
+ * @{\r
+ */\r
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)\r
+#define RTC ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
+#define USART2 ((USART_TypeDef *) USART2_BASE)\r
+#define USART3 ((USART_TypeDef *) USART3_BASE)\r
+#define UART4 ((USART_TypeDef *) UART4_BASE)\r
+#define UART5 ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
+#define PWR ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC1 ((DAC_TypeDef *) DAC_BASE)\r
+#define DAC ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */\r
+#define UART7 ((USART_TypeDef *) UART7_BASE)\r
+#define UART8 ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1 ((USART_TypeDef *) USART1_BASE)\r
+#define USART6 ((USART_TypeDef *) USART6_BASE)\r
+#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
+#define ADC123_COMMON ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)\r
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)\r
+#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI2 ((SAI_TypeDef *) SAI2_BASE)\r
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)\r
+#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)\r
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
+#define CRC ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define AES ((AES_TypeDef *) AES_BASE)\r
+#define RNG ((RNG_TypeDef *) RNG_BASE)\r
+#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)\r
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)\r
+#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)\r
+#define USB_HS_PHYC ((USB_HS_PHYC_GlobalTypeDef *) USB_HS_PHYC_CONTROLLER_BASE)\r
+#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_constants\r
+ * @{\r
+ */\r
+\r
+ /** @addtogroup Hardware_Constant_Definition\r
+ * @{\r
+ */\r
+#define LSI_STARTUP_TIME 40U /*!< LSI Maximum startup time in us */\r
+\r
+ /**\r
+ * @}\r
+ */\r
+\r
+ /** @addtogroup Peripheral_Registers_Bits_Definition\r
+ * @{\r
+ */\r
+\r
+/******************************************************************************/\r
+/* Peripheral Registers_Bits_Definition */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Analog to Digital Converter */\r
+/* */\r
+/******************************************************************************/\r
+#define VREFINT_CAL_ADDR_CMSIS ((uint16_t*) (0x1FF07A2A)) /*!<Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+#define TEMPSENSOR_CAL1_ADDR_CMSIS ((uint16_t*) (0x1FF07A2C)) /*!<Internal temperature sensor, address of parameter TS_CAL1: On STM32F7, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+#define TEMPSENSOR_CAL2_ADDR_CMSIS ((uint16_t*) (0x1FF07A2E)) /*!<Internal temperature sensor, address of parameter TS_CAL2: On STM32F7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */\r
+\r
+/******************** Bit definition for ADC_SR register ********************/\r
+#define ADC_SR_AWD_Pos (0U)\r
+#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */\r
+#define ADC_SR_AWD ADC_SR_AWD_Msk /*!<Analog watchdog flag */\r
+#define ADC_SR_EOC_Pos (1U)\r
+#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000002 */\r
+#define ADC_SR_EOC ADC_SR_EOC_Msk /*!<End of conversion */\r
+#define ADC_SR_JEOC_Pos (2U)\r
+#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */\r
+#define ADC_SR_JEOC ADC_SR_JEOC_Msk /*!<Injected channel end of conversion */\r
+#define ADC_SR_JSTRT_Pos (3U)\r
+#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */\r
+#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!<Injected channel Start flag */\r
+#define ADC_SR_STRT_Pos (4U)\r
+#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */\r
+#define ADC_SR_STRT ADC_SR_STRT_Msk /*!<Regular channel Start flag */\r
+#define ADC_SR_OVR_Pos (5U)\r
+#define ADC_SR_OVR_Msk (0x1UL << ADC_SR_OVR_Pos) /*!< 0x00000020 */\r
+#define ADC_SR_OVR ADC_SR_OVR_Msk /*!<Overrun flag */\r
+\r
+/******************* Bit definition for ADC_CR1 register ********************/\r
+#define ADC_CR1_AWDCH_Pos (0U)\r
+#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */\r
+#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */\r
+#define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */\r
+#define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */\r
+#define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */\r
+#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */\r
+#define ADC_CR1_EOCIE_Pos (5U)\r
+#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */\r
+#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk /*!<Interrupt enable for EOC */\r
+#define ADC_CR1_AWDIE_Pos (6U)\r
+#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */\r
+#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!<AAnalog Watchdog interrupt enable */\r
+#define ADC_CR1_JEOCIE_Pos (7U)\r
+#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */\r
+#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!<Interrupt enable for injected channels */\r
+#define ADC_CR1_SCAN_Pos (8U)\r
+#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */\r
+#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!<Scan mode */\r
+#define ADC_CR1_AWDSGL_Pos (9U)\r
+#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */\r
+#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!<Enable the watchdog on a single channel in scan mode */\r
+#define ADC_CR1_JAUTO_Pos (10U)\r
+#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */\r
+#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!<Automatic injected group conversion */\r
+#define ADC_CR1_DISCEN_Pos (11U)\r
+#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!<Discontinuous mode on regular channels */\r
+#define ADC_CR1_JDISCEN_Pos (12U)\r
+#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */\r
+#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!<Discontinuous mode on injected channels */\r
+#define ADC_CR1_DISCNUM_Pos (13U)\r
+#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */\r
+#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */\r
+#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */\r
+#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */\r
+#define ADC_CR1_JAWDEN_Pos (22U)\r
+#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */\r
+#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!<Analog watchdog enable on injected channels */\r
+#define ADC_CR1_AWDEN_Pos (23U)\r
+#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */\r
+#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!<Analog watchdog enable on regular channels */\r
+#define ADC_CR1_RES_Pos (24U)\r
+#define ADC_CR1_RES_Msk (0x3UL << ADC_CR1_RES_Pos) /*!< 0x03000000 */\r
+#define ADC_CR1_RES ADC_CR1_RES_Msk /*!<RES[2:0] bits (Resolution) */\r
+#define ADC_CR1_RES_0 (0x1UL << ADC_CR1_RES_Pos) /*!< 0x01000000 */\r
+#define ADC_CR1_RES_1 (0x2UL << ADC_CR1_RES_Pos) /*!< 0x02000000 */\r
+#define ADC_CR1_OVRIE_Pos (26U)\r
+#define ADC_CR1_OVRIE_Msk (0x1UL << ADC_CR1_OVRIE_Pos) /*!< 0x04000000 */\r
+#define ADC_CR1_OVRIE ADC_CR1_OVRIE_Msk /*!<overrun interrupt enable */\r
+\r
+/******************* Bit definition for ADC_CR2 register ********************/\r
+#define ADC_CR2_ADON_Pos (0U)\r
+#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */\r
+#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!<A/D Converter ON / OFF */\r
+#define ADC_CR2_CONT_Pos (1U)\r
+#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */\r
+#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!<Continuous Conversion */\r
+#define ADC_CR2_DMA_Pos (8U)\r
+#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */\r
+#define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!<Direct Memory access mode */\r
+#define ADC_CR2_DDS_Pos (9U)\r
+#define ADC_CR2_DDS_Msk (0x1UL << ADC_CR2_DDS_Pos) /*!< 0x00000200 */\r
+#define ADC_CR2_DDS ADC_CR2_DDS_Msk /*!<DMA disable selection (Single ADC) */\r
+#define ADC_CR2_EOCS_Pos (10U)\r
+#define ADC_CR2_EOCS_Msk (0x1UL << ADC_CR2_EOCS_Pos) /*!< 0x00000400 */\r
+#define ADC_CR2_EOCS ADC_CR2_EOCS_Msk /*!<End of conversion selection */\r
+#define ADC_CR2_ALIGN_Pos (11U)\r
+#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */\r
+#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!<Data Alignment */\r
+#define ADC_CR2_JEXTSEL_Pos (16U)\r
+#define ADC_CR2_JEXTSEL_Msk (0xFUL << ADC_CR2_JEXTSEL_Pos) /*!< 0x000F0000 */\r
+#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00010000 */\r
+#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00020000 */\r
+#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00040000 */\r
+#define ADC_CR2_JEXTSEL_3 (0x8UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00080000 */\r
+#define ADC_CR2_JEXTEN_Pos (20U)\r
+#define ADC_CR2_JEXTEN_Msk (0x3UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00300000 */\r
+#define ADC_CR2_JEXTEN ADC_CR2_JEXTEN_Msk /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define ADC_CR2_JEXTEN_0 (0x1UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00100000 */\r
+#define ADC_CR2_JEXTEN_1 (0x2UL << ADC_CR2_JEXTEN_Pos) /*!< 0x00200000 */\r
+#define ADC_CR2_JSWSTART_Pos (22U)\r
+#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00400000 */\r
+#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!<Start Conversion of injected channels */\r
+#define ADC_CR2_EXTSEL_Pos (24U)\r
+#define ADC_CR2_EXTSEL_Msk (0xFUL << ADC_CR2_EXTSEL_Pos) /*!< 0x0F000000 */\r
+#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x01000000 */\r
+#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x02000000 */\r
+#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x04000000 */\r
+#define ADC_CR2_EXTSEL_3 (0x8UL << ADC_CR2_EXTSEL_Pos) /*!< 0x08000000 */\r
+#define ADC_CR2_EXTEN_Pos (28U)\r
+#define ADC_CR2_EXTEN_Msk (0x3UL << ADC_CR2_EXTEN_Pos) /*!< 0x30000000 */\r
+#define ADC_CR2_EXTEN ADC_CR2_EXTEN_Msk /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define ADC_CR2_EXTEN_0 (0x1UL << ADC_CR2_EXTEN_Pos) /*!< 0x10000000 */\r
+#define ADC_CR2_EXTEN_1 (0x2UL << ADC_CR2_EXTEN_Pos) /*!< 0x20000000 */\r
+#define ADC_CR2_SWSTART_Pos (30U)\r
+#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x40000000 */\r
+#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!<Start Conversion of regular channels */\r
+\r
+/****************** Bit definition for ADC_SMPR1 register *******************/\r
+#define ADC_SMPR1_SMP10_Pos (0U)\r
+#define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */\r
+#define ADC_SMPR1_SMP11_Pos (3U)\r
+#define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */\r
+#define ADC_SMPR1_SMP12_Pos (6U)\r
+#define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */\r
+#define ADC_SMPR1_SMP13_Pos (9U)\r
+#define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */\r
+#define ADC_SMPR1_SMP14_Pos (12U)\r
+#define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */\r
+#define ADC_SMPR1_SMP15_Pos (15U)\r
+#define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */\r
+#define ADC_SMPR1_SMP16_Pos (18U)\r
+#define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */\r
+#define ADC_SMPR1_SMP17_Pos (21U)\r
+#define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */\r
+#define ADC_SMPR1_SMP18_Pos (24U)\r
+#define ADC_SMPR1_SMP18_Msk (0x7UL << ADC_SMPR1_SMP18_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR1_SMP18 ADC_SMPR1_SMP18_Msk /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define ADC_SMPR1_SMP18_0 (0x1UL << ADC_SMPR1_SMP18_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR1_SMP18_1 (0x2UL << ADC_SMPR1_SMP18_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR1_SMP18_2 (0x4UL << ADC_SMPR1_SMP18_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for ADC_SMPR2 register *******************/\r
+#define ADC_SMPR2_SMP0_Pos (0U)\r
+#define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */\r
+#define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */\r
+#define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */\r
+#define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */\r
+#define ADC_SMPR2_SMP1_Pos (3U)\r
+#define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */\r
+#define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */\r
+#define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */\r
+#define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */\r
+#define ADC_SMPR2_SMP2_Pos (6U)\r
+#define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */\r
+#define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */\r
+#define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */\r
+#define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */\r
+#define ADC_SMPR2_SMP3_Pos (9U)\r
+#define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */\r
+#define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */\r
+#define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */\r
+#define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */\r
+#define ADC_SMPR2_SMP4_Pos (12U)\r
+#define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */\r
+#define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */\r
+#define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */\r
+#define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */\r
+#define ADC_SMPR2_SMP5_Pos (15U)\r
+#define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */\r
+#define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */\r
+#define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */\r
+#define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */\r
+#define ADC_SMPR2_SMP6_Pos (18U)\r
+#define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */\r
+#define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */\r
+#define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */\r
+#define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */\r
+#define ADC_SMPR2_SMP7_Pos (21U)\r
+#define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */\r
+#define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */\r
+#define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */\r
+#define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */\r
+#define ADC_SMPR2_SMP8_Pos (24U)\r
+#define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */\r
+#define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */\r
+#define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */\r
+#define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */\r
+#define ADC_SMPR2_SMP9_Pos (27U)\r
+#define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */\r
+#define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */\r
+#define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */\r
+#define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for ADC_JOFR1 register *******************/\r
+#define ADC_JOFR1_JOFFSET1_Pos (0U)\r
+#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!<Data offset for injected channel 1 */\r
+\r
+/****************** Bit definition for ADC_JOFR2 register *******************/\r
+#define ADC_JOFR2_JOFFSET2_Pos (0U)\r
+#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!<Data offset for injected channel 2 */\r
+\r
+/****************** Bit definition for ADC_JOFR3 register *******************/\r
+#define ADC_JOFR3_JOFFSET3_Pos (0U)\r
+#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!<Data offset for injected channel 3 */\r
+\r
+/****************** Bit definition for ADC_JOFR4 register *******************/\r
+#define ADC_JOFR4_JOFFSET4_Pos (0U)\r
+#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */\r
+#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!<Data offset for injected channel 4 */\r
+\r
+/******************* Bit definition for ADC_HTR register ********************/\r
+#define ADC_HTR_HT_Pos (0U)\r
+#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */\r
+#define ADC_HTR_HT ADC_HTR_HT_Msk /*!<Analog watchdog high threshold */\r
+\r
+/******************* Bit definition for ADC_LTR register ********************/\r
+#define ADC_LTR_LT_Pos (0U)\r
+#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */\r
+#define ADC_LTR_LT ADC_LTR_LT_Msk /*!<Analog watchdog low threshold */\r
+\r
+/******************* Bit definition for ADC_SQR1 register *******************/\r
+#define ADC_SQR1_SQ13_Pos (0U)\r
+#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR1_SQ14_Pos (5U)\r
+#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR1_SQ15_Pos (10U)\r
+#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR1_SQ16_Pos (15U)\r
+#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR1_L_Pos (20U)\r
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */\r
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */\r
+\r
+/******************* Bit definition for ADC_SQR2 register *******************/\r
+#define ADC_SQR2_SQ7_Pos (0U)\r
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR2_SQ8_Pos (5U)\r
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR2_SQ9_Pos (10U)\r
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR2_SQ10_Pos (15U)\r
+#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR2_SQ11_Pos (20U)\r
+#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR2_SQ12_Pos (25U)\r
+#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_SQR3 register *******************/\r
+#define ADC_SQR3_SQ1_Pos (0U)\r
+#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */\r
+#define ADC_SQR3_SQ2_Pos (5U)\r
+#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */\r
+#define ADC_SQR3_SQ3_Pos (10U)\r
+#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */\r
+#define ADC_SQR3_SQ4_Pos (15U)\r
+#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */\r
+#define ADC_SQR3_SQ5_Pos (20U)\r
+#define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */\r
+#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */\r
+#define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */\r
+#define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */\r
+#define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */\r
+#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */\r
+#define ADC_SQR3_SQ6_Pos (25U)\r
+#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */\r
+#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */\r
+#define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */\r
+#define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */\r
+#define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */\r
+#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for ADC_JSQR register *******************/\r
+#define ADC_JSQR_JSQ1_Pos (0U)\r
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */\r
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */\r
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */\r
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */\r
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */\r
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */\r
+#define ADC_JSQR_JSQ2_Pos (5U)\r
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */\r
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */\r
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */\r
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */\r
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */\r
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */\r
+#define ADC_JSQR_JSQ3_Pos (10U)\r
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */\r
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */\r
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */\r
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */\r
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */\r
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */\r
+#define ADC_JSQR_JSQ4_Pos (15U)\r
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */\r
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */\r
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */\r
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */\r
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */\r
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */\r
+#define ADC_JSQR_JL_Pos (20U)\r
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */\r
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */\r
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */\r
+\r
+/******************* Bit definition for ADC_JDR1 register *******************/\r
+#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR2 register *******************/\r
+#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR3 register *******************/\r
+#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************* Bit definition for ADC_JDR4 register *******************/\r
+#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /*!<Injected data */\r
+\r
+/******************** Bit definition for ADC_DR register ********************/\r
+#define ADC_DR_DATA_Pos (0U)\r
+#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */\r
+#define ADC_DR_DATA ADC_DR_DATA_Msk /*!<Regular data */\r
+#define ADC_DR_ADC2DATA_Pos (16U)\r
+#define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */\r
+#define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!<ADC2 data */\r
+\r
+/******************* Bit definition for ADC_CSR register ********************/\r
+#define ADC_CSR_AWD1_Pos (0U)\r
+#define ADC_CSR_AWD1_Msk (0x1UL << ADC_CSR_AWD1_Pos) /*!< 0x00000001 */\r
+#define ADC_CSR_AWD1 ADC_CSR_AWD1_Msk /*!<ADC1 Analog watchdog flag */\r
+#define ADC_CSR_EOC1_Pos (1U)\r
+#define ADC_CSR_EOC1_Msk (0x1UL << ADC_CSR_EOC1_Pos) /*!< 0x00000002 */\r
+#define ADC_CSR_EOC1 ADC_CSR_EOC1_Msk /*!<ADC1 End of conversion */\r
+#define ADC_CSR_JEOC1_Pos (2U)\r
+#define ADC_CSR_JEOC1_Msk (0x1UL << ADC_CSR_JEOC1_Pos) /*!< 0x00000004 */\r
+#define ADC_CSR_JEOC1 ADC_CSR_JEOC1_Msk /*!<ADC1 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT1_Pos (3U)\r
+#define ADC_CSR_JSTRT1_Msk (0x1UL << ADC_CSR_JSTRT1_Pos) /*!< 0x00000008 */\r
+#define ADC_CSR_JSTRT1 ADC_CSR_JSTRT1_Msk /*!<ADC1 Injected channel Start flag */\r
+#define ADC_CSR_STRT1_Pos (4U)\r
+#define ADC_CSR_STRT1_Msk (0x1UL << ADC_CSR_STRT1_Pos) /*!< 0x00000010 */\r
+#define ADC_CSR_STRT1 ADC_CSR_STRT1_Msk /*!<ADC1 Regular channel Start flag */\r
+#define ADC_CSR_OVR1_Pos (5U)\r
+#define ADC_CSR_OVR1_Msk (0x1UL << ADC_CSR_OVR1_Pos) /*!< 0x00000020 */\r
+#define ADC_CSR_OVR1 ADC_CSR_OVR1_Msk /*!<ADC1 Overrun flag */\r
+#define ADC_CSR_AWD2_Pos (8U)\r
+#define ADC_CSR_AWD2_Msk (0x1UL << ADC_CSR_AWD2_Pos) /*!< 0x00000100 */\r
+#define ADC_CSR_AWD2 ADC_CSR_AWD2_Msk /*!<ADC2 Analog watchdog flag */\r
+#define ADC_CSR_EOC2_Pos (9U)\r
+#define ADC_CSR_EOC2_Msk (0x1UL << ADC_CSR_EOC2_Pos) /*!< 0x00000200 */\r
+#define ADC_CSR_EOC2 ADC_CSR_EOC2_Msk /*!<ADC2 End of conversion */\r
+#define ADC_CSR_JEOC2_Pos (10U)\r
+#define ADC_CSR_JEOC2_Msk (0x1UL << ADC_CSR_JEOC2_Pos) /*!< 0x00000400 */\r
+#define ADC_CSR_JEOC2 ADC_CSR_JEOC2_Msk /*!<ADC2 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT2_Pos (11U)\r
+#define ADC_CSR_JSTRT2_Msk (0x1UL << ADC_CSR_JSTRT2_Pos) /*!< 0x00000800 */\r
+#define ADC_CSR_JSTRT2 ADC_CSR_JSTRT2_Msk /*!<ADC2 Injected channel Start flag */\r
+#define ADC_CSR_STRT2_Pos (12U)\r
+#define ADC_CSR_STRT2_Msk (0x1UL << ADC_CSR_STRT2_Pos) /*!< 0x00001000 */\r
+#define ADC_CSR_STRT2 ADC_CSR_STRT2_Msk /*!<ADC2 Regular channel Start flag */\r
+#define ADC_CSR_OVR2_Pos (13U)\r
+#define ADC_CSR_OVR2_Msk (0x1UL << ADC_CSR_OVR2_Pos) /*!< 0x00002000 */\r
+#define ADC_CSR_OVR2 ADC_CSR_OVR2_Msk /*!<ADC2 Overrun flag */\r
+#define ADC_CSR_AWD3_Pos (16U)\r
+#define ADC_CSR_AWD3_Msk (0x1UL << ADC_CSR_AWD3_Pos) /*!< 0x00010000 */\r
+#define ADC_CSR_AWD3 ADC_CSR_AWD3_Msk /*!<ADC3 Analog watchdog flag */\r
+#define ADC_CSR_EOC3_Pos (17U)\r
+#define ADC_CSR_EOC3_Msk (0x1UL << ADC_CSR_EOC3_Pos) /*!< 0x00020000 */\r
+#define ADC_CSR_EOC3 ADC_CSR_EOC3_Msk /*!<ADC3 End of conversion */\r
+#define ADC_CSR_JEOC3_Pos (18U)\r
+#define ADC_CSR_JEOC3_Msk (0x1UL << ADC_CSR_JEOC3_Pos) /*!< 0x00040000 */\r
+#define ADC_CSR_JEOC3 ADC_CSR_JEOC3_Msk /*!<ADC3 Injected channel end of conversion */\r
+#define ADC_CSR_JSTRT3_Pos (19U)\r
+#define ADC_CSR_JSTRT3_Msk (0x1UL << ADC_CSR_JSTRT3_Pos) /*!< 0x00080000 */\r
+#define ADC_CSR_JSTRT3 ADC_CSR_JSTRT3_Msk /*!<ADC3 Injected channel Start flag */\r
+#define ADC_CSR_STRT3_Pos (20U)\r
+#define ADC_CSR_STRT3_Msk (0x1UL << ADC_CSR_STRT3_Pos) /*!< 0x00100000 */\r
+#define ADC_CSR_STRT3 ADC_CSR_STRT3_Msk /*!<ADC3 Regular channel Start flag */\r
+#define ADC_CSR_OVR3_Pos (21U)\r
+#define ADC_CSR_OVR3_Msk (0x1UL << ADC_CSR_OVR3_Pos) /*!< 0x00200000 */\r
+#define ADC_CSR_OVR3 ADC_CSR_OVR3_Msk /*!<ADC3 Overrun flag */\r
+\r
+/* Legacy defines */\r
+#define ADC_CSR_DOVR1 ADC_CSR_OVR1\r
+#define ADC_CSR_DOVR2 ADC_CSR_OVR2\r
+#define ADC_CSR_DOVR3 ADC_CSR_OVR3\r
+\r
+\r
+/******************* Bit definition for ADC_CCR register ********************/\r
+#define ADC_CCR_MULTI_Pos (0U)\r
+#define ADC_CCR_MULTI_Msk (0x1FUL << ADC_CCR_MULTI_Pos) /*!< 0x0000001F */\r
+#define ADC_CCR_MULTI ADC_CCR_MULTI_Msk /*!<MULTI[4:0] bits (Multi-ADC mode selection) */\r
+#define ADC_CCR_MULTI_0 (0x01UL << ADC_CCR_MULTI_Pos) /*!< 0x00000001 */\r
+#define ADC_CCR_MULTI_1 (0x02UL << ADC_CCR_MULTI_Pos) /*!< 0x00000002 */\r
+#define ADC_CCR_MULTI_2 (0x04UL << ADC_CCR_MULTI_Pos) /*!< 0x00000004 */\r
+#define ADC_CCR_MULTI_3 (0x08UL << ADC_CCR_MULTI_Pos) /*!< 0x00000008 */\r
+#define ADC_CCR_MULTI_4 (0x10UL << ADC_CCR_MULTI_Pos) /*!< 0x00000010 */\r
+#define ADC_CCR_DELAY_Pos (8U)\r
+#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */\r
+#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */\r
+#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */\r
+#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */\r
+#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */\r
+#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */\r
+#define ADC_CCR_DDS_Pos (13U)\r
+#define ADC_CCR_DDS_Msk (0x1UL << ADC_CCR_DDS_Pos) /*!< 0x00002000 */\r
+#define ADC_CCR_DDS ADC_CCR_DDS_Msk /*!<DMA disable selection (Multi-ADC mode) */\r
+#define ADC_CCR_DMA_Pos (14U)\r
+#define ADC_CCR_DMA_Msk (0x3UL << ADC_CCR_DMA_Pos) /*!< 0x0000C000 */\r
+#define ADC_CCR_DMA ADC_CCR_DMA_Msk /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */\r
+#define ADC_CCR_DMA_0 (0x1UL << ADC_CCR_DMA_Pos) /*!< 0x00004000 */\r
+#define ADC_CCR_DMA_1 (0x2UL << ADC_CCR_DMA_Pos) /*!< 0x00008000 */\r
+#define ADC_CCR_ADCPRE_Pos (16U)\r
+#define ADC_CCR_ADCPRE_Msk (0x3UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00030000 */\r
+#define ADC_CCR_ADCPRE ADC_CCR_ADCPRE_Msk /*!<ADCPRE[1:0] bits (ADC prescaler) */\r
+#define ADC_CCR_ADCPRE_0 (0x1UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00010000 */\r
+#define ADC_CCR_ADCPRE_1 (0x2UL << ADC_CCR_ADCPRE_Pos) /*!< 0x00020000 */\r
+#define ADC_CCR_VBATE_Pos (22U)\r
+#define ADC_CCR_VBATE_Msk (0x1UL << ADC_CCR_VBATE_Pos) /*!< 0x00400000 */\r
+#define ADC_CCR_VBATE ADC_CCR_VBATE_Msk /*!<VBAT Enable */\r
+#define ADC_CCR_TSVREFE_Pos (23U)\r
+#define ADC_CCR_TSVREFE_Msk (0x1UL << ADC_CCR_TSVREFE_Pos) /*!< 0x00800000 */\r
+#define ADC_CCR_TSVREFE ADC_CCR_TSVREFE_Msk /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/******************* Bit definition for ADC_CDR register ********************/\r
+#define ADC_CDR_DATA1_Pos (0U)\r
+#define ADC_CDR_DATA1_Msk (0xFFFFUL << ADC_CDR_DATA1_Pos) /*!< 0x0000FFFF */\r
+#define ADC_CDR_DATA1 ADC_CDR_DATA1_Msk /*!<1st data of a pair of regular conversions */\r
+#define ADC_CDR_DATA2_Pos (16U)\r
+#define ADC_CDR_DATA2_Msk (0xFFFFUL << ADC_CDR_DATA2_Pos) /*!< 0xFFFF0000 */\r
+#define ADC_CDR_DATA2 ADC_CDR_DATA2_Msk /*!<2nd data of a pair of regular conversions */\r
+\r
+/* Legacy defines */\r
+#define ADC_CDR_RDATA_MST ADC_CDR_DATA1\r
+#define ADC_CDR_RDATA_SLV ADC_CDR_DATA2\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Controller Area Network */\r
+/* */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/******************* Bit definition for CAN_MCR register ********************/\r
+#define CAN_MCR_INRQ_Pos (0U)\r
+#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */\r
+#define CAN_MCR_SLEEP_Pos (1U)\r
+#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */\r
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */\r
+#define CAN_MCR_TXFP_Pos (2U)\r
+#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */\r
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */\r
+#define CAN_MCR_RFLM_Pos (3U)\r
+#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */\r
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */\r
+#define CAN_MCR_NART_Pos (4U)\r
+#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */\r
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */\r
+#define CAN_MCR_AWUM_Pos (5U)\r
+#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */\r
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */\r
+#define CAN_MCR_ABOM_Pos (6U)\r
+#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */\r
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */\r
+#define CAN_MCR_TTCM_Pos (7U)\r
+#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */\r
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */\r
+#define CAN_MCR_RESET_Pos (15U)\r
+#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */\r
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */\r
+\r
+/******************* Bit definition for CAN_MSR register ********************/\r
+#define CAN_MSR_INAK_Pos (0U)\r
+#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */\r
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */\r
+#define CAN_MSR_SLAK_Pos (1U)\r
+#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */\r
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */\r
+#define CAN_MSR_ERRI_Pos (2U)\r
+#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */\r
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */\r
+#define CAN_MSR_WKUI_Pos (3U)\r
+#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */\r
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */\r
+#define CAN_MSR_SLAKI_Pos (4U)\r
+#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */\r
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */\r
+#define CAN_MSR_TXM_Pos (8U)\r
+#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */\r
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */\r
+#define CAN_MSR_RXM_Pos (9U)\r
+#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */\r
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */\r
+#define CAN_MSR_SAMP_Pos (10U)\r
+#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */\r
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */\r
+#define CAN_MSR_RX_Pos (11U)\r
+#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */\r
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */\r
+\r
+/******************* Bit definition for CAN_TSR register ********************/\r
+#define CAN_TSR_RQCP0_Pos (0U)\r
+#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */\r
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */\r
+#define CAN_TSR_TXOK0_Pos (1U)\r
+#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */\r
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */\r
+#define CAN_TSR_ALST0_Pos (2U)\r
+#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */\r
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */\r
+#define CAN_TSR_TERR0_Pos (3U)\r
+#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */\r
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */\r
+#define CAN_TSR_ABRQ0_Pos (7U)\r
+#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */\r
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */\r
+#define CAN_TSR_RQCP1_Pos (8U)\r
+#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */\r
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */\r
+#define CAN_TSR_TXOK1_Pos (9U)\r
+#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */\r
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */\r
+#define CAN_TSR_ALST1_Pos (10U)\r
+#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */\r
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */\r
+#define CAN_TSR_TERR1_Pos (11U)\r
+#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */\r
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */\r
+#define CAN_TSR_ABRQ1_Pos (15U)\r
+#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */\r
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */\r
+#define CAN_TSR_RQCP2_Pos (16U)\r
+#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */\r
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */\r
+#define CAN_TSR_TXOK2_Pos (17U)\r
+#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */\r
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */\r
+#define CAN_TSR_ALST2_Pos (18U)\r
+#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */\r
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */\r
+#define CAN_TSR_TERR2_Pos (19U)\r
+#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */\r
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */\r
+#define CAN_TSR_ABRQ2_Pos (23U)\r
+#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */\r
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */\r
+#define CAN_TSR_CODE_Pos (24U)\r
+#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */\r
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */\r
+\r
+#define CAN_TSR_TME_Pos (26U)\r
+#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */\r
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */\r
+#define CAN_TSR_TME0_Pos (26U)\r
+#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */\r
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */\r
+#define CAN_TSR_TME1_Pos (27U)\r
+#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */\r
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */\r
+#define CAN_TSR_TME2_Pos (28U)\r
+#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */\r
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define CAN_TSR_LOW_Pos (29U)\r
+#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */\r
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */\r
+#define CAN_TSR_LOW0_Pos (29U)\r
+#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */\r
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define CAN_TSR_LOW1_Pos (30U)\r
+#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */\r
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define CAN_TSR_LOW2_Pos (31U)\r
+#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */\r
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/******************* Bit definition for CAN_RF0R register *******************/\r
+#define CAN_RF0R_FMP0_Pos (0U)\r
+#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */\r
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */\r
+#define CAN_RF0R_FULL0_Pos (3U)\r
+#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */\r
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */\r
+#define CAN_RF0R_FOVR0_Pos (4U)\r
+#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */\r
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */\r
+#define CAN_RF0R_RFOM0_Pos (5U)\r
+#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */\r
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/******************* Bit definition for CAN_RF1R register *******************/\r
+#define CAN_RF1R_FMP1_Pos (0U)\r
+#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */\r
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */\r
+#define CAN_RF1R_FULL1_Pos (3U)\r
+#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */\r
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */\r
+#define CAN_RF1R_FOVR1_Pos (4U)\r
+#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */\r
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */\r
+#define CAN_RF1R_RFOM1_Pos (5U)\r
+#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */\r
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/******************** Bit definition for CAN_IER register *******************/\r
+#define CAN_IER_TMEIE_Pos (0U)\r
+#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */\r
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define CAN_IER_FMPIE0_Pos (1U)\r
+#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */\r
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE0_Pos (2U)\r
+#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */\r
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE0_Pos (3U)\r
+#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */\r
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_FMPIE1_Pos (4U)\r
+#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */\r
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */\r
+#define CAN_IER_FFIE1_Pos (5U)\r
+#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */\r
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */\r
+#define CAN_IER_FOVIE1_Pos (6U)\r
+#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */\r
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */\r
+#define CAN_IER_EWGIE_Pos (8U)\r
+#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */\r
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */\r
+#define CAN_IER_EPVIE_Pos (9U)\r
+#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */\r
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */\r
+#define CAN_IER_BOFIE_Pos (10U)\r
+#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */\r
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */\r
+#define CAN_IER_LECIE_Pos (11U)\r
+#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */\r
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */\r
+#define CAN_IER_ERRIE_Pos (15U)\r
+#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */\r
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */\r
+#define CAN_IER_WKUIE_Pos (16U)\r
+#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */\r
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */\r
+#define CAN_IER_SLKIE_Pos (17U)\r
+#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */\r
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */\r
+\r
+/******************** Bit definition for CAN_ESR register *******************/\r
+#define CAN_ESR_EWGF_Pos (0U)\r
+#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */\r
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */\r
+#define CAN_ESR_EPVF_Pos (1U)\r
+#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */\r
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */\r
+#define CAN_ESR_BOFF_Pos (2U)\r
+#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */\r
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */\r
+\r
+#define CAN_ESR_LEC_Pos (4U)\r
+#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */\r
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */\r
+#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */\r
+#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */\r
+#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */\r
+\r
+#define CAN_ESR_TEC_Pos (16U)\r
+#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */\r
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define CAN_ESR_REC_Pos (24U)\r
+#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */\r
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */\r
+\r
+/******************* Bit definition for CAN_BTR register ********************/\r
+#define CAN_BTR_BRP_Pos (0U)\r
+#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */\r
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */\r
+#define CAN_BTR_TS1_Pos (16U)\r
+#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */\r
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */\r
+#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */\r
+#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */\r
+#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */\r
+#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */\r
+#define CAN_BTR_TS2_Pos (20U)\r
+#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */\r
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */\r
+#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */\r
+#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */\r
+#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */\r
+#define CAN_BTR_SJW_Pos (24U)\r
+#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */\r
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */\r
+#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */\r
+#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */\r
+#define CAN_BTR_LBKM_Pos (30U)\r
+#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */\r
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */\r
+#define CAN_BTR_SILM_Pos (31U)\r
+#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */\r
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/****************** Bit definition for CAN_TI0R register ********************/\r
+#define CAN_TI0R_TXRQ_Pos (0U)\r
+#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI0R_RTR_Pos (1U)\r
+#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI0R_IDE_Pos (2U)\r
+#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI0R_EXID_Pos (3U)\r
+#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_TI0R_STID_Pos (21U)\r
+#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/****************** Bit definition for CAN_TDT0R register *******************/\r
+#define CAN_TDT0R_DLC_Pos (0U)\r
+#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT0R_TGT_Pos (8U)\r
+#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT0R_TIME_Pos (16U)\r
+#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/****************** Bit definition for CAN_TDL0R register *******************/\r
+#define CAN_TDL0R_DATA0_Pos (0U)\r
+#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL0R_DATA1_Pos (8U)\r
+#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL0R_DATA2_Pos (16U)\r
+#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL0R_DATA3_Pos (24U)\r
+#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/****************** Bit definition for CAN_TDH0R register *******************/\r
+#define CAN_TDH0R_DATA4_Pos (0U)\r
+#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH0R_DATA5_Pos (8U)\r
+#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH0R_DATA6_Pos (16U)\r
+#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH0R_DATA7_Pos (24U)\r
+#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI1R register *******************/\r
+#define CAN_TI1R_TXRQ_Pos (0U)\r
+#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI1R_RTR_Pos (1U)\r
+#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI1R_IDE_Pos (2U)\r
+#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI1R_EXID_Pos (3U)\r
+#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_TI1R_STID_Pos (21U)\r
+#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT1R register ******************/\r
+#define CAN_TDT1R_DLC_Pos (0U)\r
+#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT1R_TGT_Pos (8U)\r
+#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT1R_TIME_Pos (16U)\r
+#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL1R register ******************/\r
+#define CAN_TDL1R_DATA0_Pos (0U)\r
+#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL1R_DATA1_Pos (8U)\r
+#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL1R_DATA2_Pos (16U)\r
+#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL1R_DATA3_Pos (24U)\r
+#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH1R register ******************/\r
+#define CAN_TDH1R_DATA4_Pos (0U)\r
+#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH1R_DATA5_Pos (8U)\r
+#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH1R_DATA6_Pos (16U)\r
+#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH1R_DATA7_Pos (24U)\r
+#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_TI2R register *******************/\r
+#define CAN_TI2R_TXRQ_Pos (0U)\r
+#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */\r
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */\r
+#define CAN_TI2R_RTR_Pos (1U)\r
+#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_TI2R_IDE_Pos (2U)\r
+#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_TI2R_EXID_Pos (3U)\r
+#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */\r
+#define CAN_TI2R_STID_Pos (21U)\r
+#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_TDT2R register ******************/\r
+#define CAN_TDT2R_DLC_Pos (0U)\r
+#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_TDT2R_TGT_Pos (8U)\r
+#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */\r
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */\r
+#define CAN_TDT2R_TIME_Pos (16U)\r
+#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_TDL2R register ******************/\r
+#define CAN_TDL2R_DATA0_Pos (0U)\r
+#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_TDL2R_DATA1_Pos (8U)\r
+#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_TDL2R_DATA2_Pos (16U)\r
+#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_TDL2R_DATA3_Pos (24U)\r
+#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_TDH2R register ******************/\r
+#define CAN_TDH2R_DATA4_Pos (0U)\r
+#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_TDH2R_DATA5_Pos (8U)\r
+#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_TDH2R_DATA6_Pos (16U)\r
+#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_TDH2R_DATA7_Pos (24U)\r
+#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI0R register *******************/\r
+#define CAN_RI0R_RTR_Pos (1U)\r
+#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_RI0R_IDE_Pos (2U)\r
+#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_RI0R_EXID_Pos (3U)\r
+#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */\r
+#define CAN_RI0R_STID_Pos (21U)\r
+#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT0R register ******************/\r
+#define CAN_RDT0R_DLC_Pos (0U)\r
+#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_RDT0R_FMI_Pos (8U)\r
+#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */\r
+#define CAN_RDT0R_TIME_Pos (16U)\r
+#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL0R register ******************/\r
+#define CAN_RDL0R_DATA0_Pos (0U)\r
+#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_RDL0R_DATA1_Pos (8U)\r
+#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_RDL0R_DATA2_Pos (16U)\r
+#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_RDL0R_DATA3_Pos (24U)\r
+#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH0R register ******************/\r
+#define CAN_RDH0R_DATA4_Pos (0U)\r
+#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_RDH0R_DATA5_Pos (8U)\r
+#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_RDH0R_DATA6_Pos (16U)\r
+#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_RDH0R_DATA7_Pos (24U)\r
+#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/******************* Bit definition for CAN_RI1R register *******************/\r
+#define CAN_RI1R_RTR_Pos (1U)\r
+#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */\r
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */\r
+#define CAN_RI1R_IDE_Pos (2U)\r
+#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */\r
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */\r
+#define CAN_RI1R_EXID_Pos (3U)\r
+#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */\r
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */\r
+#define CAN_RI1R_STID_Pos (21U)\r
+#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */\r
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************* Bit definition for CAN_RDT1R register ******************/\r
+#define CAN_RDT1R_DLC_Pos (0U)\r
+#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */\r
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */\r
+#define CAN_RDT1R_FMI_Pos (8U)\r
+#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */\r
+#define CAN_RDT1R_TIME_Pos (16U)\r
+#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */\r
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */\r
+\r
+/******************* Bit definition for CAN_RDL1R register ******************/\r
+#define CAN_RDL1R_DATA0_Pos (0U)\r
+#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */\r
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */\r
+#define CAN_RDL1R_DATA1_Pos (8U)\r
+#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */\r
+#define CAN_RDL1R_DATA2_Pos (16U)\r
+#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */\r
+#define CAN_RDL1R_DATA3_Pos (24U)\r
+#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */\r
+\r
+/******************* Bit definition for CAN_RDH1R register ******************/\r
+#define CAN_RDH1R_DATA4_Pos (0U)\r
+#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */\r
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */\r
+#define CAN_RDH1R_DATA5_Pos (8U)\r
+#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */\r
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */\r
+#define CAN_RDH1R_DATA6_Pos (16U)\r
+#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */\r
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */\r
+#define CAN_RDH1R_DATA7_Pos (24U)\r
+#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */\r
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/******************* Bit definition for CAN_FMR register ********************/\r
+#define CAN_FMR_FINIT ((uint8_t)0x01U) /*!<Filter Init Mode */\r
+\r
+/******************* Bit definition for CAN_FM1R register *******************/\r
+#define CAN_FM1R_FBM_Pos (0U)\r
+#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */\r
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */\r
+#define CAN_FM1R_FBM0_Pos (0U)\r
+#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */\r
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */\r
+#define CAN_FM1R_FBM1_Pos (1U)\r
+#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */\r
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */\r
+#define CAN_FM1R_FBM2_Pos (2U)\r
+#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */\r
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */\r
+#define CAN_FM1R_FBM3_Pos (3U)\r
+#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */\r
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */\r
+#define CAN_FM1R_FBM4_Pos (4U)\r
+#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */\r
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */\r
+#define CAN_FM1R_FBM5_Pos (5U)\r
+#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */\r
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */\r
+#define CAN_FM1R_FBM6_Pos (6U)\r
+#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */\r
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */\r
+#define CAN_FM1R_FBM7_Pos (7U)\r
+#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */\r
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */\r
+#define CAN_FM1R_FBM8_Pos (8U)\r
+#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */\r
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */\r
+#define CAN_FM1R_FBM9_Pos (9U)\r
+#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */\r
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */\r
+#define CAN_FM1R_FBM10_Pos (10U)\r
+#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */\r
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */\r
+#define CAN_FM1R_FBM11_Pos (11U)\r
+#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */\r
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */\r
+#define CAN_FM1R_FBM12_Pos (12U)\r
+#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */\r
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */\r
+#define CAN_FM1R_FBM13_Pos (13U)\r
+#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */\r
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */\r
+\r
+/******************* Bit definition for CAN_FS1R register *******************/\r
+#define CAN_FS1R_FSC_Pos (0U)\r
+#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */\r
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */\r
+#define CAN_FS1R_FSC0_Pos (0U)\r
+#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */\r
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */\r
+#define CAN_FS1R_FSC1_Pos (1U)\r
+#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */\r
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */\r
+#define CAN_FS1R_FSC2_Pos (2U)\r
+#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */\r
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */\r
+#define CAN_FS1R_FSC3_Pos (3U)\r
+#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */\r
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */\r
+#define CAN_FS1R_FSC4_Pos (4U)\r
+#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */\r
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */\r
+#define CAN_FS1R_FSC5_Pos (5U)\r
+#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */\r
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */\r
+#define CAN_FS1R_FSC6_Pos (6U)\r
+#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */\r
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */\r
+#define CAN_FS1R_FSC7_Pos (7U)\r
+#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */\r
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */\r
+#define CAN_FS1R_FSC8_Pos (8U)\r
+#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */\r
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */\r
+#define CAN_FS1R_FSC9_Pos (9U)\r
+#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */\r
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */\r
+#define CAN_FS1R_FSC10_Pos (10U)\r
+#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */\r
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */\r
+#define CAN_FS1R_FSC11_Pos (11U)\r
+#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */\r
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */\r
+#define CAN_FS1R_FSC12_Pos (12U)\r
+#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */\r
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */\r
+#define CAN_FS1R_FSC13_Pos (13U)\r
+#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */\r
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */\r
+\r
+/****************** Bit definition for CAN_FFA1R register *******************/\r
+#define CAN_FFA1R_FFA_Pos (0U)\r
+#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */\r
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */\r
+#define CAN_FFA1R_FFA0_Pos (0U)\r
+#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */\r
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */\r
+#define CAN_FFA1R_FFA1_Pos (1U)\r
+#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */\r
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */\r
+#define CAN_FFA1R_FFA2_Pos (2U)\r
+#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */\r
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */\r
+#define CAN_FFA1R_FFA3_Pos (3U)\r
+#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */\r
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */\r
+#define CAN_FFA1R_FFA4_Pos (4U)\r
+#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */\r
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */\r
+#define CAN_FFA1R_FFA5_Pos (5U)\r
+#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */\r
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */\r
+#define CAN_FFA1R_FFA6_Pos (6U)\r
+#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */\r
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */\r
+#define CAN_FFA1R_FFA7_Pos (7U)\r
+#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */\r
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */\r
+#define CAN_FFA1R_FFA8_Pos (8U)\r
+#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */\r
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */\r
+#define CAN_FFA1R_FFA9_Pos (9U)\r
+#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */\r
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */\r
+#define CAN_FFA1R_FFA10_Pos (10U)\r
+#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */\r
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */\r
+#define CAN_FFA1R_FFA11_Pos (11U)\r
+#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */\r
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */\r
+#define CAN_FFA1R_FFA12_Pos (12U)\r
+#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */\r
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */\r
+#define CAN_FFA1R_FFA13_Pos (13U)\r
+#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */\r
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/******************* Bit definition for CAN_FA1R register *******************/\r
+#define CAN_FA1R_FACT_Pos (0U)\r
+#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */\r
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */\r
+#define CAN_FA1R_FACT0_Pos (0U)\r
+#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */\r
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */\r
+#define CAN_FA1R_FACT1_Pos (1U)\r
+#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */\r
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */\r
+#define CAN_FA1R_FACT2_Pos (2U)\r
+#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */\r
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */\r
+#define CAN_FA1R_FACT3_Pos (3U)\r
+#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */\r
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */\r
+#define CAN_FA1R_FACT4_Pos (4U)\r
+#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */\r
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */\r
+#define CAN_FA1R_FACT5_Pos (5U)\r
+#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */\r
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */\r
+#define CAN_FA1R_FACT6_Pos (6U)\r
+#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */\r
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */\r
+#define CAN_FA1R_FACT7_Pos (7U)\r
+#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */\r
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */\r
+#define CAN_FA1R_FACT8_Pos (8U)\r
+#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */\r
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */\r
+#define CAN_FA1R_FACT9_Pos (9U)\r
+#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */\r
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */\r
+#define CAN_FA1R_FACT10_Pos (10U)\r
+#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */\r
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */\r
+#define CAN_FA1R_FACT11_Pos (11U)\r
+#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */\r
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */\r
+#define CAN_FA1R_FACT12_Pos (12U)\r
+#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */\r
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */\r
+#define CAN_FA1R_FACT13_Pos (13U)\r
+#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */\r
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */\r
+\r
+/******************* Bit definition for CAN_F0R1 register *******************/\r
+#define CAN_F0R1_FB0_Pos (0U)\r
+#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F0R1_FB1_Pos (1U)\r
+#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F0R1_FB2_Pos (2U)\r
+#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F0R1_FB3_Pos (3U)\r
+#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F0R1_FB4_Pos (4U)\r
+#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F0R1_FB5_Pos (5U)\r
+#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F0R1_FB6_Pos (6U)\r
+#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F0R1_FB7_Pos (7U)\r
+#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F0R1_FB8_Pos (8U)\r
+#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F0R1_FB9_Pos (9U)\r
+#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F0R1_FB10_Pos (10U)\r
+#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F0R1_FB11_Pos (11U)\r
+#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F0R1_FB12_Pos (12U)\r
+#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F0R1_FB13_Pos (13U)\r
+#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F0R1_FB14_Pos (14U)\r
+#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F0R1_FB15_Pos (15U)\r
+#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F0R1_FB16_Pos (16U)\r
+#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F0R1_FB17_Pos (17U)\r
+#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F0R1_FB18_Pos (18U)\r
+#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F0R1_FB19_Pos (19U)\r
+#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F0R1_FB20_Pos (20U)\r
+#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F0R1_FB21_Pos (21U)\r
+#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F0R1_FB22_Pos (22U)\r
+#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F0R1_FB23_Pos (23U)\r
+#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F0R1_FB24_Pos (24U)\r
+#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F0R1_FB25_Pos (25U)\r
+#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F0R1_FB26_Pos (26U)\r
+#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F0R1_FB27_Pos (27U)\r
+#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F0R1_FB28_Pos (28U)\r
+#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F0R1_FB29_Pos (29U)\r
+#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F0R1_FB30_Pos (30U)\r
+#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F0R1_FB31_Pos (31U)\r
+#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R1 register *******************/\r
+#define CAN_F1R1_FB0_Pos (0U)\r
+#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F1R1_FB1_Pos (1U)\r
+#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F1R1_FB2_Pos (2U)\r
+#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F1R1_FB3_Pos (3U)\r
+#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F1R1_FB4_Pos (4U)\r
+#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F1R1_FB5_Pos (5U)\r
+#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F1R1_FB6_Pos (6U)\r
+#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F1R1_FB7_Pos (7U)\r
+#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F1R1_FB8_Pos (8U)\r
+#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F1R1_FB9_Pos (9U)\r
+#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F1R1_FB10_Pos (10U)\r
+#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F1R1_FB11_Pos (11U)\r
+#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F1R1_FB12_Pos (12U)\r
+#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F1R1_FB13_Pos (13U)\r
+#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F1R1_FB14_Pos (14U)\r
+#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F1R1_FB15_Pos (15U)\r
+#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F1R1_FB16_Pos (16U)\r
+#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F1R1_FB17_Pos (17U)\r
+#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F1R1_FB18_Pos (18U)\r
+#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F1R1_FB19_Pos (19U)\r
+#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F1R1_FB20_Pos (20U)\r
+#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F1R1_FB21_Pos (21U)\r
+#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F1R1_FB22_Pos (22U)\r
+#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F1R1_FB23_Pos (23U)\r
+#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F1R1_FB24_Pos (24U)\r
+#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F1R1_FB25_Pos (25U)\r
+#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F1R1_FB26_Pos (26U)\r
+#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F1R1_FB27_Pos (27U)\r
+#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F1R1_FB28_Pos (28U)\r
+#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F1R1_FB29_Pos (29U)\r
+#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F1R1_FB30_Pos (30U)\r
+#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F1R1_FB31_Pos (31U)\r
+#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R1 register *******************/\r
+#define CAN_F2R1_FB0_Pos (0U)\r
+#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F2R1_FB1_Pos (1U)\r
+#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F2R1_FB2_Pos (2U)\r
+#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F2R1_FB3_Pos (3U)\r
+#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F2R1_FB4_Pos (4U)\r
+#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F2R1_FB5_Pos (5U)\r
+#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F2R1_FB6_Pos (6U)\r
+#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F2R1_FB7_Pos (7U)\r
+#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F2R1_FB8_Pos (8U)\r
+#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F2R1_FB9_Pos (9U)\r
+#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F2R1_FB10_Pos (10U)\r
+#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F2R1_FB11_Pos (11U)\r
+#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F2R1_FB12_Pos (12U)\r
+#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F2R1_FB13_Pos (13U)\r
+#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F2R1_FB14_Pos (14U)\r
+#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F2R1_FB15_Pos (15U)\r
+#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F2R1_FB16_Pos (16U)\r
+#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F2R1_FB17_Pos (17U)\r
+#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F2R1_FB18_Pos (18U)\r
+#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F2R1_FB19_Pos (19U)\r
+#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F2R1_FB20_Pos (20U)\r
+#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F2R1_FB21_Pos (21U)\r
+#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F2R1_FB22_Pos (22U)\r
+#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F2R1_FB23_Pos (23U)\r
+#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F2R1_FB24_Pos (24U)\r
+#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F2R1_FB25_Pos (25U)\r
+#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F2R1_FB26_Pos (26U)\r
+#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F2R1_FB27_Pos (27U)\r
+#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F2R1_FB28_Pos (28U)\r
+#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F2R1_FB29_Pos (29U)\r
+#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F2R1_FB30_Pos (30U)\r
+#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F2R1_FB31_Pos (31U)\r
+#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R1 register *******************/\r
+#define CAN_F3R1_FB0_Pos (0U)\r
+#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F3R1_FB1_Pos (1U)\r
+#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F3R1_FB2_Pos (2U)\r
+#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F3R1_FB3_Pos (3U)\r
+#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F3R1_FB4_Pos (4U)\r
+#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F3R1_FB5_Pos (5U)\r
+#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F3R1_FB6_Pos (6U)\r
+#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F3R1_FB7_Pos (7U)\r
+#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F3R1_FB8_Pos (8U)\r
+#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F3R1_FB9_Pos (9U)\r
+#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F3R1_FB10_Pos (10U)\r
+#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F3R1_FB11_Pos (11U)\r
+#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F3R1_FB12_Pos (12U)\r
+#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F3R1_FB13_Pos (13U)\r
+#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F3R1_FB14_Pos (14U)\r
+#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F3R1_FB15_Pos (15U)\r
+#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F3R1_FB16_Pos (16U)\r
+#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F3R1_FB17_Pos (17U)\r
+#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F3R1_FB18_Pos (18U)\r
+#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F3R1_FB19_Pos (19U)\r
+#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F3R1_FB20_Pos (20U)\r
+#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F3R1_FB21_Pos (21U)\r
+#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F3R1_FB22_Pos (22U)\r
+#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F3R1_FB23_Pos (23U)\r
+#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F3R1_FB24_Pos (24U)\r
+#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F3R1_FB25_Pos (25U)\r
+#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F3R1_FB26_Pos (26U)\r
+#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F3R1_FB27_Pos (27U)\r
+#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F3R1_FB28_Pos (28U)\r
+#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F3R1_FB29_Pos (29U)\r
+#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F3R1_FB30_Pos (30U)\r
+#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F3R1_FB31_Pos (31U)\r
+#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R1 register *******************/\r
+#define CAN_F4R1_FB0_Pos (0U)\r
+#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F4R1_FB1_Pos (1U)\r
+#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F4R1_FB2_Pos (2U)\r
+#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F4R1_FB3_Pos (3U)\r
+#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F4R1_FB4_Pos (4U)\r
+#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F4R1_FB5_Pos (5U)\r
+#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F4R1_FB6_Pos (6U)\r
+#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F4R1_FB7_Pos (7U)\r
+#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F4R1_FB8_Pos (8U)\r
+#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F4R1_FB9_Pos (9U)\r
+#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F4R1_FB10_Pos (10U)\r
+#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F4R1_FB11_Pos (11U)\r
+#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F4R1_FB12_Pos (12U)\r
+#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F4R1_FB13_Pos (13U)\r
+#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F4R1_FB14_Pos (14U)\r
+#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F4R1_FB15_Pos (15U)\r
+#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F4R1_FB16_Pos (16U)\r
+#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F4R1_FB17_Pos (17U)\r
+#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F4R1_FB18_Pos (18U)\r
+#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F4R1_FB19_Pos (19U)\r
+#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F4R1_FB20_Pos (20U)\r
+#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F4R1_FB21_Pos (21U)\r
+#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F4R1_FB22_Pos (22U)\r
+#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F4R1_FB23_Pos (23U)\r
+#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F4R1_FB24_Pos (24U)\r
+#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F4R1_FB25_Pos (25U)\r
+#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F4R1_FB26_Pos (26U)\r
+#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F4R1_FB27_Pos (27U)\r
+#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F4R1_FB28_Pos (28U)\r
+#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F4R1_FB29_Pos (29U)\r
+#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F4R1_FB30_Pos (30U)\r
+#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F4R1_FB31_Pos (31U)\r
+#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R1 register *******************/\r
+#define CAN_F5R1_FB0_Pos (0U)\r
+#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F5R1_FB1_Pos (1U)\r
+#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F5R1_FB2_Pos (2U)\r
+#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F5R1_FB3_Pos (3U)\r
+#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F5R1_FB4_Pos (4U)\r
+#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F5R1_FB5_Pos (5U)\r
+#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F5R1_FB6_Pos (6U)\r
+#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F5R1_FB7_Pos (7U)\r
+#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F5R1_FB8_Pos (8U)\r
+#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F5R1_FB9_Pos (9U)\r
+#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F5R1_FB10_Pos (10U)\r
+#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F5R1_FB11_Pos (11U)\r
+#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F5R1_FB12_Pos (12U)\r
+#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F5R1_FB13_Pos (13U)\r
+#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F5R1_FB14_Pos (14U)\r
+#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F5R1_FB15_Pos (15U)\r
+#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F5R1_FB16_Pos (16U)\r
+#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F5R1_FB17_Pos (17U)\r
+#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F5R1_FB18_Pos (18U)\r
+#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F5R1_FB19_Pos (19U)\r
+#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F5R1_FB20_Pos (20U)\r
+#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F5R1_FB21_Pos (21U)\r
+#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F5R1_FB22_Pos (22U)\r
+#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F5R1_FB23_Pos (23U)\r
+#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F5R1_FB24_Pos (24U)\r
+#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F5R1_FB25_Pos (25U)\r
+#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F5R1_FB26_Pos (26U)\r
+#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F5R1_FB27_Pos (27U)\r
+#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F5R1_FB28_Pos (28U)\r
+#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F5R1_FB29_Pos (29U)\r
+#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F5R1_FB30_Pos (30U)\r
+#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F5R1_FB31_Pos (31U)\r
+#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R1 register *******************/\r
+#define CAN_F6R1_FB0_Pos (0U)\r
+#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F6R1_FB1_Pos (1U)\r
+#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F6R1_FB2_Pos (2U)\r
+#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F6R1_FB3_Pos (3U)\r
+#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F6R1_FB4_Pos (4U)\r
+#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F6R1_FB5_Pos (5U)\r
+#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F6R1_FB6_Pos (6U)\r
+#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F6R1_FB7_Pos (7U)\r
+#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F6R1_FB8_Pos (8U)\r
+#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F6R1_FB9_Pos (9U)\r
+#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F6R1_FB10_Pos (10U)\r
+#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F6R1_FB11_Pos (11U)\r
+#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F6R1_FB12_Pos (12U)\r
+#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F6R1_FB13_Pos (13U)\r
+#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F6R1_FB14_Pos (14U)\r
+#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F6R1_FB15_Pos (15U)\r
+#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F6R1_FB16_Pos (16U)\r
+#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F6R1_FB17_Pos (17U)\r
+#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F6R1_FB18_Pos (18U)\r
+#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F6R1_FB19_Pos (19U)\r
+#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F6R1_FB20_Pos (20U)\r
+#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F6R1_FB21_Pos (21U)\r
+#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F6R1_FB22_Pos (22U)\r
+#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F6R1_FB23_Pos (23U)\r
+#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F6R1_FB24_Pos (24U)\r
+#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F6R1_FB25_Pos (25U)\r
+#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F6R1_FB26_Pos (26U)\r
+#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F6R1_FB27_Pos (27U)\r
+#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F6R1_FB28_Pos (28U)\r
+#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F6R1_FB29_Pos (29U)\r
+#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F6R1_FB30_Pos (30U)\r
+#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F6R1_FB31_Pos (31U)\r
+#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R1 register *******************/\r
+#define CAN_F7R1_FB0_Pos (0U)\r
+#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F7R1_FB1_Pos (1U)\r
+#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F7R1_FB2_Pos (2U)\r
+#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F7R1_FB3_Pos (3U)\r
+#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F7R1_FB4_Pos (4U)\r
+#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F7R1_FB5_Pos (5U)\r
+#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F7R1_FB6_Pos (6U)\r
+#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F7R1_FB7_Pos (7U)\r
+#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F7R1_FB8_Pos (8U)\r
+#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F7R1_FB9_Pos (9U)\r
+#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F7R1_FB10_Pos (10U)\r
+#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F7R1_FB11_Pos (11U)\r
+#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F7R1_FB12_Pos (12U)\r
+#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F7R1_FB13_Pos (13U)\r
+#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F7R1_FB14_Pos (14U)\r
+#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F7R1_FB15_Pos (15U)\r
+#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F7R1_FB16_Pos (16U)\r
+#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F7R1_FB17_Pos (17U)\r
+#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F7R1_FB18_Pos (18U)\r
+#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F7R1_FB19_Pos (19U)\r
+#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F7R1_FB20_Pos (20U)\r
+#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F7R1_FB21_Pos (21U)\r
+#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F7R1_FB22_Pos (22U)\r
+#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F7R1_FB23_Pos (23U)\r
+#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F7R1_FB24_Pos (24U)\r
+#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F7R1_FB25_Pos (25U)\r
+#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F7R1_FB26_Pos (26U)\r
+#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F7R1_FB27_Pos (27U)\r
+#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F7R1_FB28_Pos (28U)\r
+#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F7R1_FB29_Pos (29U)\r
+#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F7R1_FB30_Pos (30U)\r
+#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F7R1_FB31_Pos (31U)\r
+#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R1 register *******************/\r
+#define CAN_F8R1_FB0_Pos (0U)\r
+#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F8R1_FB1_Pos (1U)\r
+#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F8R1_FB2_Pos (2U)\r
+#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F8R1_FB3_Pos (3U)\r
+#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F8R1_FB4_Pos (4U)\r
+#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F8R1_FB5_Pos (5U)\r
+#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F8R1_FB6_Pos (6U)\r
+#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F8R1_FB7_Pos (7U)\r
+#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F8R1_FB8_Pos (8U)\r
+#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F8R1_FB9_Pos (9U)\r
+#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F8R1_FB10_Pos (10U)\r
+#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F8R1_FB11_Pos (11U)\r
+#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F8R1_FB12_Pos (12U)\r
+#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F8R1_FB13_Pos (13U)\r
+#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F8R1_FB14_Pos (14U)\r
+#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F8R1_FB15_Pos (15U)\r
+#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F8R1_FB16_Pos (16U)\r
+#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F8R1_FB17_Pos (17U)\r
+#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F8R1_FB18_Pos (18U)\r
+#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F8R1_FB19_Pos (19U)\r
+#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F8R1_FB20_Pos (20U)\r
+#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F8R1_FB21_Pos (21U)\r
+#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F8R1_FB22_Pos (22U)\r
+#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F8R1_FB23_Pos (23U)\r
+#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F8R1_FB24_Pos (24U)\r
+#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F8R1_FB25_Pos (25U)\r
+#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F8R1_FB26_Pos (26U)\r
+#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F8R1_FB27_Pos (27U)\r
+#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F8R1_FB28_Pos (28U)\r
+#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F8R1_FB29_Pos (29U)\r
+#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F8R1_FB30_Pos (30U)\r
+#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F8R1_FB31_Pos (31U)\r
+#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R1 register *******************/\r
+#define CAN_F9R1_FB0_Pos (0U)\r
+#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F9R1_FB1_Pos (1U)\r
+#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F9R1_FB2_Pos (2U)\r
+#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F9R1_FB3_Pos (3U)\r
+#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F9R1_FB4_Pos (4U)\r
+#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F9R1_FB5_Pos (5U)\r
+#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F9R1_FB6_Pos (6U)\r
+#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F9R1_FB7_Pos (7U)\r
+#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F9R1_FB8_Pos (8U)\r
+#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F9R1_FB9_Pos (9U)\r
+#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F9R1_FB10_Pos (10U)\r
+#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F9R1_FB11_Pos (11U)\r
+#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F9R1_FB12_Pos (12U)\r
+#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F9R1_FB13_Pos (13U)\r
+#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F9R1_FB14_Pos (14U)\r
+#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F9R1_FB15_Pos (15U)\r
+#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F9R1_FB16_Pos (16U)\r
+#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F9R1_FB17_Pos (17U)\r
+#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F9R1_FB18_Pos (18U)\r
+#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F9R1_FB19_Pos (19U)\r
+#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F9R1_FB20_Pos (20U)\r
+#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F9R1_FB21_Pos (21U)\r
+#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F9R1_FB22_Pos (22U)\r
+#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F9R1_FB23_Pos (23U)\r
+#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F9R1_FB24_Pos (24U)\r
+#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F9R1_FB25_Pos (25U)\r
+#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F9R1_FB26_Pos (26U)\r
+#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F9R1_FB27_Pos (27U)\r
+#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F9R1_FB28_Pos (28U)\r
+#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F9R1_FB29_Pos (29U)\r
+#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F9R1_FB30_Pos (30U)\r
+#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F9R1_FB31_Pos (31U)\r
+#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R1 register ******************/\r
+#define CAN_F10R1_FB0_Pos (0U)\r
+#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F10R1_FB1_Pos (1U)\r
+#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F10R1_FB2_Pos (2U)\r
+#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F10R1_FB3_Pos (3U)\r
+#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F10R1_FB4_Pos (4U)\r
+#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F10R1_FB5_Pos (5U)\r
+#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F10R1_FB6_Pos (6U)\r
+#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F10R1_FB7_Pos (7U)\r
+#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F10R1_FB8_Pos (8U)\r
+#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F10R1_FB9_Pos (9U)\r
+#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F10R1_FB10_Pos (10U)\r
+#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F10R1_FB11_Pos (11U)\r
+#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F10R1_FB12_Pos (12U)\r
+#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F10R1_FB13_Pos (13U)\r
+#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F10R1_FB14_Pos (14U)\r
+#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F10R1_FB15_Pos (15U)\r
+#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F10R1_FB16_Pos (16U)\r
+#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F10R1_FB17_Pos (17U)\r
+#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F10R1_FB18_Pos (18U)\r
+#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F10R1_FB19_Pos (19U)\r
+#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F10R1_FB20_Pos (20U)\r
+#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F10R1_FB21_Pos (21U)\r
+#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F10R1_FB22_Pos (22U)\r
+#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F10R1_FB23_Pos (23U)\r
+#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F10R1_FB24_Pos (24U)\r
+#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F10R1_FB25_Pos (25U)\r
+#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F10R1_FB26_Pos (26U)\r
+#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F10R1_FB27_Pos (27U)\r
+#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F10R1_FB28_Pos (28U)\r
+#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F10R1_FB29_Pos (29U)\r
+#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F10R1_FB30_Pos (30U)\r
+#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F10R1_FB31_Pos (31U)\r
+#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R1 register ******************/\r
+#define CAN_F11R1_FB0_Pos (0U)\r
+#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F11R1_FB1_Pos (1U)\r
+#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F11R1_FB2_Pos (2U)\r
+#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F11R1_FB3_Pos (3U)\r
+#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F11R1_FB4_Pos (4U)\r
+#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F11R1_FB5_Pos (5U)\r
+#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F11R1_FB6_Pos (6U)\r
+#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F11R1_FB7_Pos (7U)\r
+#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F11R1_FB8_Pos (8U)\r
+#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F11R1_FB9_Pos (9U)\r
+#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F11R1_FB10_Pos (10U)\r
+#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F11R1_FB11_Pos (11U)\r
+#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F11R1_FB12_Pos (12U)\r
+#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F11R1_FB13_Pos (13U)\r
+#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F11R1_FB14_Pos (14U)\r
+#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F11R1_FB15_Pos (15U)\r
+#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F11R1_FB16_Pos (16U)\r
+#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F11R1_FB17_Pos (17U)\r
+#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F11R1_FB18_Pos (18U)\r
+#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F11R1_FB19_Pos (19U)\r
+#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F11R1_FB20_Pos (20U)\r
+#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F11R1_FB21_Pos (21U)\r
+#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F11R1_FB22_Pos (22U)\r
+#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F11R1_FB23_Pos (23U)\r
+#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F11R1_FB24_Pos (24U)\r
+#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F11R1_FB25_Pos (25U)\r
+#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F11R1_FB26_Pos (26U)\r
+#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F11R1_FB27_Pos (27U)\r
+#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F11R1_FB28_Pos (28U)\r
+#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F11R1_FB29_Pos (29U)\r
+#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F11R1_FB30_Pos (30U)\r
+#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F11R1_FB31_Pos (31U)\r
+#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R1 register ******************/\r
+#define CAN_F12R1_FB0_Pos (0U)\r
+#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F12R1_FB1_Pos (1U)\r
+#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F12R1_FB2_Pos (2U)\r
+#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F12R1_FB3_Pos (3U)\r
+#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F12R1_FB4_Pos (4U)\r
+#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F12R1_FB5_Pos (5U)\r
+#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F12R1_FB6_Pos (6U)\r
+#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F12R1_FB7_Pos (7U)\r
+#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F12R1_FB8_Pos (8U)\r
+#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F12R1_FB9_Pos (9U)\r
+#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F12R1_FB10_Pos (10U)\r
+#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F12R1_FB11_Pos (11U)\r
+#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F12R1_FB12_Pos (12U)\r
+#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F12R1_FB13_Pos (13U)\r
+#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F12R1_FB14_Pos (14U)\r
+#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F12R1_FB15_Pos (15U)\r
+#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F12R1_FB16_Pos (16U)\r
+#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F12R1_FB17_Pos (17U)\r
+#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F12R1_FB18_Pos (18U)\r
+#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F12R1_FB19_Pos (19U)\r
+#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F12R1_FB20_Pos (20U)\r
+#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F12R1_FB21_Pos (21U)\r
+#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F12R1_FB22_Pos (22U)\r
+#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F12R1_FB23_Pos (23U)\r
+#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F12R1_FB24_Pos (24U)\r
+#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F12R1_FB25_Pos (25U)\r
+#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F12R1_FB26_Pos (26U)\r
+#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F12R1_FB27_Pos (27U)\r
+#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F12R1_FB28_Pos (28U)\r
+#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F12R1_FB29_Pos (29U)\r
+#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F12R1_FB30_Pos (30U)\r
+#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F12R1_FB31_Pos (31U)\r
+#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R1 register ******************/\r
+#define CAN_F13R1_FB0_Pos (0U)\r
+#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F13R1_FB1_Pos (1U)\r
+#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F13R1_FB2_Pos (2U)\r
+#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F13R1_FB3_Pos (3U)\r
+#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F13R1_FB4_Pos (4U)\r
+#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F13R1_FB5_Pos (5U)\r
+#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F13R1_FB6_Pos (6U)\r
+#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F13R1_FB7_Pos (7U)\r
+#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F13R1_FB8_Pos (8U)\r
+#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F13R1_FB9_Pos (9U)\r
+#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F13R1_FB10_Pos (10U)\r
+#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F13R1_FB11_Pos (11U)\r
+#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F13R1_FB12_Pos (12U)\r
+#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F13R1_FB13_Pos (13U)\r
+#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F13R1_FB14_Pos (14U)\r
+#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F13R1_FB15_Pos (15U)\r
+#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F13R1_FB16_Pos (16U)\r
+#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F13R1_FB17_Pos (17U)\r
+#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F13R1_FB18_Pos (18U)\r
+#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F13R1_FB19_Pos (19U)\r
+#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F13R1_FB20_Pos (20U)\r
+#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F13R1_FB21_Pos (21U)\r
+#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F13R1_FB22_Pos (22U)\r
+#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F13R1_FB23_Pos (23U)\r
+#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F13R1_FB24_Pos (24U)\r
+#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F13R1_FB25_Pos (25U)\r
+#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F13R1_FB26_Pos (26U)\r
+#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F13R1_FB27_Pos (27U)\r
+#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F13R1_FB28_Pos (28U)\r
+#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F13R1_FB29_Pos (29U)\r
+#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F13R1_FB30_Pos (30U)\r
+#define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F13R1_FB31_Pos (31U)\r
+#define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F0R2 register *******************/\r
+#define CAN_F0R2_FB0_Pos (0U)\r
+#define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F0R2_FB1_Pos (1U)\r
+#define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F0R2_FB2_Pos (2U)\r
+#define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F0R2_FB3_Pos (3U)\r
+#define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F0R2_FB4_Pos (4U)\r
+#define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F0R2_FB5_Pos (5U)\r
+#define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F0R2_FB6_Pos (6U)\r
+#define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F0R2_FB7_Pos (7U)\r
+#define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F0R2_FB8_Pos (8U)\r
+#define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F0R2_FB9_Pos (9U)\r
+#define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F0R2_FB10_Pos (10U)\r
+#define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F0R2_FB11_Pos (11U)\r
+#define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F0R2_FB12_Pos (12U)\r
+#define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F0R2_FB13_Pos (13U)\r
+#define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F0R2_FB14_Pos (14U)\r
+#define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F0R2_FB15_Pos (15U)\r
+#define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F0R2_FB16_Pos (16U)\r
+#define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F0R2_FB17_Pos (17U)\r
+#define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F0R2_FB18_Pos (18U)\r
+#define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F0R2_FB19_Pos (19U)\r
+#define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F0R2_FB20_Pos (20U)\r
+#define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F0R2_FB21_Pos (21U)\r
+#define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F0R2_FB22_Pos (22U)\r
+#define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F0R2_FB23_Pos (23U)\r
+#define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F0R2_FB24_Pos (24U)\r
+#define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F0R2_FB25_Pos (25U)\r
+#define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F0R2_FB26_Pos (26U)\r
+#define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F0R2_FB27_Pos (27U)\r
+#define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F0R2_FB28_Pos (28U)\r
+#define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F0R2_FB29_Pos (29U)\r
+#define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F0R2_FB30_Pos (30U)\r
+#define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F0R2_FB31_Pos (31U)\r
+#define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F1R2 register *******************/\r
+#define CAN_F1R2_FB0_Pos (0U)\r
+#define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F1R2_FB1_Pos (1U)\r
+#define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F1R2_FB2_Pos (2U)\r
+#define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F1R2_FB3_Pos (3U)\r
+#define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F1R2_FB4_Pos (4U)\r
+#define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F1R2_FB5_Pos (5U)\r
+#define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F1R2_FB6_Pos (6U)\r
+#define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F1R2_FB7_Pos (7U)\r
+#define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F1R2_FB8_Pos (8U)\r
+#define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F1R2_FB9_Pos (9U)\r
+#define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F1R2_FB10_Pos (10U)\r
+#define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F1R2_FB11_Pos (11U)\r
+#define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F1R2_FB12_Pos (12U)\r
+#define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F1R2_FB13_Pos (13U)\r
+#define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F1R2_FB14_Pos (14U)\r
+#define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F1R2_FB15_Pos (15U)\r
+#define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F1R2_FB16_Pos (16U)\r
+#define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F1R2_FB17_Pos (17U)\r
+#define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F1R2_FB18_Pos (18U)\r
+#define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F1R2_FB19_Pos (19U)\r
+#define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F1R2_FB20_Pos (20U)\r
+#define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F1R2_FB21_Pos (21U)\r
+#define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F1R2_FB22_Pos (22U)\r
+#define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F1R2_FB23_Pos (23U)\r
+#define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F1R2_FB24_Pos (24U)\r
+#define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F1R2_FB25_Pos (25U)\r
+#define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F1R2_FB26_Pos (26U)\r
+#define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F1R2_FB27_Pos (27U)\r
+#define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F1R2_FB28_Pos (28U)\r
+#define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F1R2_FB29_Pos (29U)\r
+#define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F1R2_FB30_Pos (30U)\r
+#define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F1R2_FB31_Pos (31U)\r
+#define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F2R2 register *******************/\r
+#define CAN_F2R2_FB0_Pos (0U)\r
+#define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F2R2_FB1_Pos (1U)\r
+#define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F2R2_FB2_Pos (2U)\r
+#define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F2R2_FB3_Pos (3U)\r
+#define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F2R2_FB4_Pos (4U)\r
+#define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F2R2_FB5_Pos (5U)\r
+#define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F2R2_FB6_Pos (6U)\r
+#define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F2R2_FB7_Pos (7U)\r
+#define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F2R2_FB8_Pos (8U)\r
+#define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F2R2_FB9_Pos (9U)\r
+#define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F2R2_FB10_Pos (10U)\r
+#define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F2R2_FB11_Pos (11U)\r
+#define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F2R2_FB12_Pos (12U)\r
+#define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F2R2_FB13_Pos (13U)\r
+#define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F2R2_FB14_Pos (14U)\r
+#define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F2R2_FB15_Pos (15U)\r
+#define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F2R2_FB16_Pos (16U)\r
+#define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F2R2_FB17_Pos (17U)\r
+#define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F2R2_FB18_Pos (18U)\r
+#define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F2R2_FB19_Pos (19U)\r
+#define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F2R2_FB20_Pos (20U)\r
+#define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F2R2_FB21_Pos (21U)\r
+#define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F2R2_FB22_Pos (22U)\r
+#define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F2R2_FB23_Pos (23U)\r
+#define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F2R2_FB24_Pos (24U)\r
+#define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F2R2_FB25_Pos (25U)\r
+#define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F2R2_FB26_Pos (26U)\r
+#define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F2R2_FB27_Pos (27U)\r
+#define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F2R2_FB28_Pos (28U)\r
+#define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F2R2_FB29_Pos (29U)\r
+#define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F2R2_FB30_Pos (30U)\r
+#define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F2R2_FB31_Pos (31U)\r
+#define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F3R2 register *******************/\r
+#define CAN_F3R2_FB0_Pos (0U)\r
+#define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F3R2_FB1_Pos (1U)\r
+#define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F3R2_FB2_Pos (2U)\r
+#define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F3R2_FB3_Pos (3U)\r
+#define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F3R2_FB4_Pos (4U)\r
+#define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F3R2_FB5_Pos (5U)\r
+#define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F3R2_FB6_Pos (6U)\r
+#define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F3R2_FB7_Pos (7U)\r
+#define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F3R2_FB8_Pos (8U)\r
+#define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F3R2_FB9_Pos (9U)\r
+#define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F3R2_FB10_Pos (10U)\r
+#define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F3R2_FB11_Pos (11U)\r
+#define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F3R2_FB12_Pos (12U)\r
+#define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F3R2_FB13_Pos (13U)\r
+#define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F3R2_FB14_Pos (14U)\r
+#define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F3R2_FB15_Pos (15U)\r
+#define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F3R2_FB16_Pos (16U)\r
+#define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F3R2_FB17_Pos (17U)\r
+#define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F3R2_FB18_Pos (18U)\r
+#define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F3R2_FB19_Pos (19U)\r
+#define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F3R2_FB20_Pos (20U)\r
+#define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F3R2_FB21_Pos (21U)\r
+#define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F3R2_FB22_Pos (22U)\r
+#define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F3R2_FB23_Pos (23U)\r
+#define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F3R2_FB24_Pos (24U)\r
+#define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F3R2_FB25_Pos (25U)\r
+#define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F3R2_FB26_Pos (26U)\r
+#define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F3R2_FB27_Pos (27U)\r
+#define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F3R2_FB28_Pos (28U)\r
+#define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F3R2_FB29_Pos (29U)\r
+#define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F3R2_FB30_Pos (30U)\r
+#define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F3R2_FB31_Pos (31U)\r
+#define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F4R2 register *******************/\r
+#define CAN_F4R2_FB0_Pos (0U)\r
+#define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F4R2_FB1_Pos (1U)\r
+#define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F4R2_FB2_Pos (2U)\r
+#define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F4R2_FB3_Pos (3U)\r
+#define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F4R2_FB4_Pos (4U)\r
+#define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F4R2_FB5_Pos (5U)\r
+#define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F4R2_FB6_Pos (6U)\r
+#define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F4R2_FB7_Pos (7U)\r
+#define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F4R2_FB8_Pos (8U)\r
+#define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F4R2_FB9_Pos (9U)\r
+#define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F4R2_FB10_Pos (10U)\r
+#define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F4R2_FB11_Pos (11U)\r
+#define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F4R2_FB12_Pos (12U)\r
+#define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F4R2_FB13_Pos (13U)\r
+#define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F4R2_FB14_Pos (14U)\r
+#define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F4R2_FB15_Pos (15U)\r
+#define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F4R2_FB16_Pos (16U)\r
+#define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F4R2_FB17_Pos (17U)\r
+#define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F4R2_FB18_Pos (18U)\r
+#define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F4R2_FB19_Pos (19U)\r
+#define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F4R2_FB20_Pos (20U)\r
+#define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F4R2_FB21_Pos (21U)\r
+#define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F4R2_FB22_Pos (22U)\r
+#define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F4R2_FB23_Pos (23U)\r
+#define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F4R2_FB24_Pos (24U)\r
+#define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F4R2_FB25_Pos (25U)\r
+#define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F4R2_FB26_Pos (26U)\r
+#define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F4R2_FB27_Pos (27U)\r
+#define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F4R2_FB28_Pos (28U)\r
+#define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F4R2_FB29_Pos (29U)\r
+#define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F4R2_FB30_Pos (30U)\r
+#define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F4R2_FB31_Pos (31U)\r
+#define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F5R2 register *******************/\r
+#define CAN_F5R2_FB0_Pos (0U)\r
+#define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F5R2_FB1_Pos (1U)\r
+#define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F5R2_FB2_Pos (2U)\r
+#define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F5R2_FB3_Pos (3U)\r
+#define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F5R2_FB4_Pos (4U)\r
+#define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F5R2_FB5_Pos (5U)\r
+#define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F5R2_FB6_Pos (6U)\r
+#define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F5R2_FB7_Pos (7U)\r
+#define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F5R2_FB8_Pos (8U)\r
+#define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F5R2_FB9_Pos (9U)\r
+#define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F5R2_FB10_Pos (10U)\r
+#define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F5R2_FB11_Pos (11U)\r
+#define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F5R2_FB12_Pos (12U)\r
+#define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F5R2_FB13_Pos (13U)\r
+#define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F5R2_FB14_Pos (14U)\r
+#define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F5R2_FB15_Pos (15U)\r
+#define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F5R2_FB16_Pos (16U)\r
+#define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F5R2_FB17_Pos (17U)\r
+#define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F5R2_FB18_Pos (18U)\r
+#define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F5R2_FB19_Pos (19U)\r
+#define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F5R2_FB20_Pos (20U)\r
+#define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F5R2_FB21_Pos (21U)\r
+#define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F5R2_FB22_Pos (22U)\r
+#define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F5R2_FB23_Pos (23U)\r
+#define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F5R2_FB24_Pos (24U)\r
+#define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F5R2_FB25_Pos (25U)\r
+#define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F5R2_FB26_Pos (26U)\r
+#define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F5R2_FB27_Pos (27U)\r
+#define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F5R2_FB28_Pos (28U)\r
+#define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F5R2_FB29_Pos (29U)\r
+#define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F5R2_FB30_Pos (30U)\r
+#define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F5R2_FB31_Pos (31U)\r
+#define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F6R2 register *******************/\r
+#define CAN_F6R2_FB0_Pos (0U)\r
+#define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F6R2_FB1_Pos (1U)\r
+#define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F6R2_FB2_Pos (2U)\r
+#define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F6R2_FB3_Pos (3U)\r
+#define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F6R2_FB4_Pos (4U)\r
+#define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F6R2_FB5_Pos (5U)\r
+#define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F6R2_FB6_Pos (6U)\r
+#define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F6R2_FB7_Pos (7U)\r
+#define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F6R2_FB8_Pos (8U)\r
+#define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F6R2_FB9_Pos (9U)\r
+#define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F6R2_FB10_Pos (10U)\r
+#define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F6R2_FB11_Pos (11U)\r
+#define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F6R2_FB12_Pos (12U)\r
+#define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F6R2_FB13_Pos (13U)\r
+#define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F6R2_FB14_Pos (14U)\r
+#define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F6R2_FB15_Pos (15U)\r
+#define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F6R2_FB16_Pos (16U)\r
+#define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F6R2_FB17_Pos (17U)\r
+#define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F6R2_FB18_Pos (18U)\r
+#define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F6R2_FB19_Pos (19U)\r
+#define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F6R2_FB20_Pos (20U)\r
+#define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F6R2_FB21_Pos (21U)\r
+#define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F6R2_FB22_Pos (22U)\r
+#define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F6R2_FB23_Pos (23U)\r
+#define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F6R2_FB24_Pos (24U)\r
+#define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F6R2_FB25_Pos (25U)\r
+#define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F6R2_FB26_Pos (26U)\r
+#define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F6R2_FB27_Pos (27U)\r
+#define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F6R2_FB28_Pos (28U)\r
+#define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F6R2_FB29_Pos (29U)\r
+#define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F6R2_FB30_Pos (30U)\r
+#define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F6R2_FB31_Pos (31U)\r
+#define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F7R2 register *******************/\r
+#define CAN_F7R2_FB0_Pos (0U)\r
+#define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F7R2_FB1_Pos (1U)\r
+#define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F7R2_FB2_Pos (2U)\r
+#define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F7R2_FB3_Pos (3U)\r
+#define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F7R2_FB4_Pos (4U)\r
+#define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F7R2_FB5_Pos (5U)\r
+#define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F7R2_FB6_Pos (6U)\r
+#define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F7R2_FB7_Pos (7U)\r
+#define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F7R2_FB8_Pos (8U)\r
+#define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F7R2_FB9_Pos (9U)\r
+#define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F7R2_FB10_Pos (10U)\r
+#define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F7R2_FB11_Pos (11U)\r
+#define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F7R2_FB12_Pos (12U)\r
+#define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F7R2_FB13_Pos (13U)\r
+#define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F7R2_FB14_Pos (14U)\r
+#define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F7R2_FB15_Pos (15U)\r
+#define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F7R2_FB16_Pos (16U)\r
+#define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F7R2_FB17_Pos (17U)\r
+#define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F7R2_FB18_Pos (18U)\r
+#define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F7R2_FB19_Pos (19U)\r
+#define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F7R2_FB20_Pos (20U)\r
+#define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F7R2_FB21_Pos (21U)\r
+#define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F7R2_FB22_Pos (22U)\r
+#define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F7R2_FB23_Pos (23U)\r
+#define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F7R2_FB24_Pos (24U)\r
+#define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F7R2_FB25_Pos (25U)\r
+#define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F7R2_FB26_Pos (26U)\r
+#define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F7R2_FB27_Pos (27U)\r
+#define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F7R2_FB28_Pos (28U)\r
+#define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F7R2_FB29_Pos (29U)\r
+#define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F7R2_FB30_Pos (30U)\r
+#define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F7R2_FB31_Pos (31U)\r
+#define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F8R2 register *******************/\r
+#define CAN_F8R2_FB0_Pos (0U)\r
+#define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F8R2_FB1_Pos (1U)\r
+#define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F8R2_FB2_Pos (2U)\r
+#define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F8R2_FB3_Pos (3U)\r
+#define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F8R2_FB4_Pos (4U)\r
+#define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F8R2_FB5_Pos (5U)\r
+#define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F8R2_FB6_Pos (6U)\r
+#define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F8R2_FB7_Pos (7U)\r
+#define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F8R2_FB8_Pos (8U)\r
+#define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F8R2_FB9_Pos (9U)\r
+#define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F8R2_FB10_Pos (10U)\r
+#define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F8R2_FB11_Pos (11U)\r
+#define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F8R2_FB12_Pos (12U)\r
+#define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F8R2_FB13_Pos (13U)\r
+#define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F8R2_FB14_Pos (14U)\r
+#define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F8R2_FB15_Pos (15U)\r
+#define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F8R2_FB16_Pos (16U)\r
+#define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F8R2_FB17_Pos (17U)\r
+#define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F8R2_FB18_Pos (18U)\r
+#define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F8R2_FB19_Pos (19U)\r
+#define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F8R2_FB20_Pos (20U)\r
+#define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F8R2_FB21_Pos (21U)\r
+#define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F8R2_FB22_Pos (22U)\r
+#define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F8R2_FB23_Pos (23U)\r
+#define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F8R2_FB24_Pos (24U)\r
+#define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F8R2_FB25_Pos (25U)\r
+#define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F8R2_FB26_Pos (26U)\r
+#define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F8R2_FB27_Pos (27U)\r
+#define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F8R2_FB28_Pos (28U)\r
+#define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F8R2_FB29_Pos (29U)\r
+#define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F8R2_FB30_Pos (30U)\r
+#define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F8R2_FB31_Pos (31U)\r
+#define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F9R2 register *******************/\r
+#define CAN_F9R2_FB0_Pos (0U)\r
+#define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F9R2_FB1_Pos (1U)\r
+#define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F9R2_FB2_Pos (2U)\r
+#define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F9R2_FB3_Pos (3U)\r
+#define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F9R2_FB4_Pos (4U)\r
+#define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F9R2_FB5_Pos (5U)\r
+#define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F9R2_FB6_Pos (6U)\r
+#define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F9R2_FB7_Pos (7U)\r
+#define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F9R2_FB8_Pos (8U)\r
+#define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F9R2_FB9_Pos (9U)\r
+#define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F9R2_FB10_Pos (10U)\r
+#define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F9R2_FB11_Pos (11U)\r
+#define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F9R2_FB12_Pos (12U)\r
+#define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F9R2_FB13_Pos (13U)\r
+#define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F9R2_FB14_Pos (14U)\r
+#define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F9R2_FB15_Pos (15U)\r
+#define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F9R2_FB16_Pos (16U)\r
+#define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F9R2_FB17_Pos (17U)\r
+#define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F9R2_FB18_Pos (18U)\r
+#define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F9R2_FB19_Pos (19U)\r
+#define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F9R2_FB20_Pos (20U)\r
+#define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F9R2_FB21_Pos (21U)\r
+#define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F9R2_FB22_Pos (22U)\r
+#define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F9R2_FB23_Pos (23U)\r
+#define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F9R2_FB24_Pos (24U)\r
+#define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F9R2_FB25_Pos (25U)\r
+#define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F9R2_FB26_Pos (26U)\r
+#define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F9R2_FB27_Pos (27U)\r
+#define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F9R2_FB28_Pos (28U)\r
+#define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F9R2_FB29_Pos (29U)\r
+#define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F9R2_FB30_Pos (30U)\r
+#define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F9R2_FB31_Pos (31U)\r
+#define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F10R2 register ******************/\r
+#define CAN_F10R2_FB0_Pos (0U)\r
+#define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F10R2_FB1_Pos (1U)\r
+#define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F10R2_FB2_Pos (2U)\r
+#define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F10R2_FB3_Pos (3U)\r
+#define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F10R2_FB4_Pos (4U)\r
+#define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F10R2_FB5_Pos (5U)\r
+#define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F10R2_FB6_Pos (6U)\r
+#define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F10R2_FB7_Pos (7U)\r
+#define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F10R2_FB8_Pos (8U)\r
+#define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F10R2_FB9_Pos (9U)\r
+#define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F10R2_FB10_Pos (10U)\r
+#define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F10R2_FB11_Pos (11U)\r
+#define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F10R2_FB12_Pos (12U)\r
+#define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F10R2_FB13_Pos (13U)\r
+#define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F10R2_FB14_Pos (14U)\r
+#define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F10R2_FB15_Pos (15U)\r
+#define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F10R2_FB16_Pos (16U)\r
+#define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F10R2_FB17_Pos (17U)\r
+#define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F10R2_FB18_Pos (18U)\r
+#define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F10R2_FB19_Pos (19U)\r
+#define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F10R2_FB20_Pos (20U)\r
+#define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F10R2_FB21_Pos (21U)\r
+#define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F10R2_FB22_Pos (22U)\r
+#define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F10R2_FB23_Pos (23U)\r
+#define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F10R2_FB24_Pos (24U)\r
+#define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F10R2_FB25_Pos (25U)\r
+#define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F10R2_FB26_Pos (26U)\r
+#define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F10R2_FB27_Pos (27U)\r
+#define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F10R2_FB28_Pos (28U)\r
+#define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F10R2_FB29_Pos (29U)\r
+#define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F10R2_FB30_Pos (30U)\r
+#define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F10R2_FB31_Pos (31U)\r
+#define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F11R2 register ******************/\r
+#define CAN_F11R2_FB0_Pos (0U)\r
+#define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F11R2_FB1_Pos (1U)\r
+#define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F11R2_FB2_Pos (2U)\r
+#define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F11R2_FB3_Pos (3U)\r
+#define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F11R2_FB4_Pos (4U)\r
+#define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F11R2_FB5_Pos (5U)\r
+#define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F11R2_FB6_Pos (6U)\r
+#define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F11R2_FB7_Pos (7U)\r
+#define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F11R2_FB8_Pos (8U)\r
+#define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F11R2_FB9_Pos (9U)\r
+#define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F11R2_FB10_Pos (10U)\r
+#define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F11R2_FB11_Pos (11U)\r
+#define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F11R2_FB12_Pos (12U)\r
+#define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F11R2_FB13_Pos (13U)\r
+#define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F11R2_FB14_Pos (14U)\r
+#define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F11R2_FB15_Pos (15U)\r
+#define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F11R2_FB16_Pos (16U)\r
+#define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F11R2_FB17_Pos (17U)\r
+#define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F11R2_FB18_Pos (18U)\r
+#define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F11R2_FB19_Pos (19U)\r
+#define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F11R2_FB20_Pos (20U)\r
+#define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F11R2_FB21_Pos (21U)\r
+#define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F11R2_FB22_Pos (22U)\r
+#define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F11R2_FB23_Pos (23U)\r
+#define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F11R2_FB24_Pos (24U)\r
+#define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F11R2_FB25_Pos (25U)\r
+#define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F11R2_FB26_Pos (26U)\r
+#define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F11R2_FB27_Pos (27U)\r
+#define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F11R2_FB28_Pos (28U)\r
+#define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F11R2_FB29_Pos (29U)\r
+#define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F11R2_FB30_Pos (30U)\r
+#define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F11R2_FB31_Pos (31U)\r
+#define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F12R2 register ******************/\r
+#define CAN_F12R2_FB0_Pos (0U)\r
+#define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F12R2_FB1_Pos (1U)\r
+#define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F12R2_FB2_Pos (2U)\r
+#define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F12R2_FB3_Pos (3U)\r
+#define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F12R2_FB4_Pos (4U)\r
+#define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F12R2_FB5_Pos (5U)\r
+#define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F12R2_FB6_Pos (6U)\r
+#define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F12R2_FB7_Pos (7U)\r
+#define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F12R2_FB8_Pos (8U)\r
+#define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F12R2_FB9_Pos (9U)\r
+#define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F12R2_FB10_Pos (10U)\r
+#define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F12R2_FB11_Pos (11U)\r
+#define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F12R2_FB12_Pos (12U)\r
+#define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F12R2_FB13_Pos (13U)\r
+#define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F12R2_FB14_Pos (14U)\r
+#define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F12R2_FB15_Pos (15U)\r
+#define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F12R2_FB16_Pos (16U)\r
+#define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F12R2_FB17_Pos (17U)\r
+#define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F12R2_FB18_Pos (18U)\r
+#define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F12R2_FB19_Pos (19U)\r
+#define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F12R2_FB20_Pos (20U)\r
+#define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F12R2_FB21_Pos (21U)\r
+#define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F12R2_FB22_Pos (22U)\r
+#define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F12R2_FB23_Pos (23U)\r
+#define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F12R2_FB24_Pos (24U)\r
+#define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F12R2_FB25_Pos (25U)\r
+#define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F12R2_FB26_Pos (26U)\r
+#define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F12R2_FB27_Pos (27U)\r
+#define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F12R2_FB28_Pos (28U)\r
+#define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F12R2_FB29_Pos (29U)\r
+#define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F12R2_FB30_Pos (30U)\r
+#define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F12R2_FB31_Pos (31U)\r
+#define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+/******************* Bit definition for CAN_F13R2 register ******************/\r
+#define CAN_F13R2_FB0_Pos (0U)\r
+#define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */\r
+#define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!<Filter bit 0 */\r
+#define CAN_F13R2_FB1_Pos (1U)\r
+#define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */\r
+#define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!<Filter bit 1 */\r
+#define CAN_F13R2_FB2_Pos (2U)\r
+#define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */\r
+#define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!<Filter bit 2 */\r
+#define CAN_F13R2_FB3_Pos (3U)\r
+#define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */\r
+#define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!<Filter bit 3 */\r
+#define CAN_F13R2_FB4_Pos (4U)\r
+#define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */\r
+#define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!<Filter bit 4 */\r
+#define CAN_F13R2_FB5_Pos (5U)\r
+#define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */\r
+#define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!<Filter bit 5 */\r
+#define CAN_F13R2_FB6_Pos (6U)\r
+#define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */\r
+#define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!<Filter bit 6 */\r
+#define CAN_F13R2_FB7_Pos (7U)\r
+#define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */\r
+#define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!<Filter bit 7 */\r
+#define CAN_F13R2_FB8_Pos (8U)\r
+#define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */\r
+#define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!<Filter bit 8 */\r
+#define CAN_F13R2_FB9_Pos (9U)\r
+#define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */\r
+#define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!<Filter bit 9 */\r
+#define CAN_F13R2_FB10_Pos (10U)\r
+#define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */\r
+#define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!<Filter bit 10 */\r
+#define CAN_F13R2_FB11_Pos (11U)\r
+#define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */\r
+#define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!<Filter bit 11 */\r
+#define CAN_F13R2_FB12_Pos (12U)\r
+#define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */\r
+#define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!<Filter bit 12 */\r
+#define CAN_F13R2_FB13_Pos (13U)\r
+#define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */\r
+#define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!<Filter bit 13 */\r
+#define CAN_F13R2_FB14_Pos (14U)\r
+#define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */\r
+#define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!<Filter bit 14 */\r
+#define CAN_F13R2_FB15_Pos (15U)\r
+#define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */\r
+#define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!<Filter bit 15 */\r
+#define CAN_F13R2_FB16_Pos (16U)\r
+#define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */\r
+#define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!<Filter bit 16 */\r
+#define CAN_F13R2_FB17_Pos (17U)\r
+#define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */\r
+#define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!<Filter bit 17 */\r
+#define CAN_F13R2_FB18_Pos (18U)\r
+#define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */\r
+#define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!<Filter bit 18 */\r
+#define CAN_F13R2_FB19_Pos (19U)\r
+#define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */\r
+#define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!<Filter bit 19 */\r
+#define CAN_F13R2_FB20_Pos (20U)\r
+#define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */\r
+#define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!<Filter bit 20 */\r
+#define CAN_F13R2_FB21_Pos (21U)\r
+#define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */\r
+#define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!<Filter bit 21 */\r
+#define CAN_F13R2_FB22_Pos (22U)\r
+#define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */\r
+#define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!<Filter bit 22 */\r
+#define CAN_F13R2_FB23_Pos (23U)\r
+#define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */\r
+#define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!<Filter bit 23 */\r
+#define CAN_F13R2_FB24_Pos (24U)\r
+#define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */\r
+#define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!<Filter bit 24 */\r
+#define CAN_F13R2_FB25_Pos (25U)\r
+#define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */\r
+#define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!<Filter bit 25 */\r
+#define CAN_F13R2_FB26_Pos (26U)\r
+#define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */\r
+#define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!<Filter bit 26 */\r
+#define CAN_F13R2_FB27_Pos (27U)\r
+#define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */\r
+#define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!<Filter bit 27 */\r
+#define CAN_F13R2_FB28_Pos (28U)\r
+#define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */\r
+#define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!<Filter bit 28 */\r
+#define CAN_F13R2_FB29_Pos (29U)\r
+#define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */\r
+#define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!<Filter bit 29 */\r
+#define CAN_F13R2_FB30_Pos (30U)\r
+#define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */\r
+#define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!<Filter bit 30 */\r
+#define CAN_F13R2_FB31_Pos (31U)\r
+#define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */\r
+#define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!<Filter bit 31 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* CRC calculation unit */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for CRC_DR register *********************/\r
+#define CRC_DR_DR_Pos (0U)\r
+#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */\r
+\r
+/******************* Bit definition for CRC_IDR register ********************/\r
+#define CRC_IDR_IDR_Pos (0U)\r
+#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */\r
+#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */\r
+\r
+/******************** Bit definition for CRC_CR register ********************/\r
+#define CRC_CR_RESET_Pos (0U)\r
+#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */\r
+#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */\r
+#define CRC_CR_POLYSIZE_Pos (3U)\r
+#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */\r
+#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */\r
+#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */\r
+#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */\r
+#define CRC_CR_REV_IN_Pos (5U)\r
+#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */\r
+#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */\r
+#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */\r
+#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */\r
+#define CRC_CR_REV_OUT_Pos (7U)\r
+#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */\r
+#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */\r
+\r
+/******************* Bit definition for CRC_INIT register *******************/\r
+#define CRC_INIT_INIT_Pos (0U)\r
+#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */\r
+\r
+/******************* Bit definition for CRC_POL register ********************/\r
+#define CRC_POL_POL_Pos (0U)\r
+#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */\r
+#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Advanced Encryption Standard (AES) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for AES_CR register *********************/\r
+#define AES_CR_EN_Pos (0U)\r
+#define AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) /*!< 0x00000001 */\r
+#define AES_CR_EN AES_CR_EN_Msk /*!< AES Enable */\r
+#define AES_CR_DATATYPE_Pos (1U)\r
+#define AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) /*!< 0x00000006 */\r
+#define AES_CR_DATATYPE AES_CR_DATATYPE_Msk /*!< Data type selection */\r
+#define AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) /*!< 0x00000002 */\r
+#define AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) /*!< 0x00000004 */\r
+\r
+#define AES_CR_MODE_Pos (3U)\r
+#define AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) /*!< 0x00000018 */\r
+#define AES_CR_MODE AES_CR_MODE_Msk /*!< AES Mode Of Operation */\r
+#define AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) /*!< 0x00000008 */\r
+#define AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) /*!< 0x00000010 */\r
+\r
+#define AES_CR_CHMOD_Pos (5U)\r
+#define AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) /*!< 0x00010060 */\r
+#define AES_CR_CHMOD AES_CR_CHMOD_Msk /*!< AES Chaining Mode */\r
+#define AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) /*!< 0x00000020 */\r
+#define AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) /*!< 0x00000040 */\r
+#define AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) /*!< 0x00010000 */\r
+\r
+#define AES_CR_CCFC_Pos (7U)\r
+#define AES_CR_CCFC_Msk (0x1UL << AES_CR_CCFC_Pos) /*!< 0x00000080 */\r
+#define AES_CR_CCFC AES_CR_CCFC_Msk /*!< Computation Complete Flag Clear */\r
+#define AES_CR_ERRC_Pos (8U)\r
+#define AES_CR_ERRC_Msk (0x1UL << AES_CR_ERRC_Pos) /*!< 0x00000100 */\r
+#define AES_CR_ERRC AES_CR_ERRC_Msk /*!< Error Clear */\r
+#define AES_CR_CCFIE_Pos (9U)\r
+#define AES_CR_CCFIE_Msk (0x1UL << AES_CR_CCFIE_Pos) /*!< 0x00000200 */\r
+#define AES_CR_CCFIE AES_CR_CCFIE_Msk /*!< Computation Complete Flag Interrupt Enable */\r
+#define AES_CR_ERRIE_Pos (10U)\r
+#define AES_CR_ERRIE_Msk (0x1UL << AES_CR_ERRIE_Pos) /*!< 0x00000400 */\r
+#define AES_CR_ERRIE AES_CR_ERRIE_Msk /*!< Error Interrupt Enable */\r
+#define AES_CR_DMAINEN_Pos (11U)\r
+#define AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) /*!< 0x00000800 */\r
+#define AES_CR_DMAINEN AES_CR_DMAINEN_Msk /*!< Enable data input phase DMA management */\r
+#define AES_CR_DMAOUTEN_Pos (12U)\r
+#define AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) /*!< 0x00001000 */\r
+#define AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk /*!< Enable data output phase DMA management */\r
+\r
+#define AES_CR_GCMPH_Pos (13U)\r
+#define AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) /*!< 0x00006000 */\r
+#define AES_CR_GCMPH AES_CR_GCMPH_Msk /*!< GCM Phase */\r
+#define AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) /*!< 0x00002000 */\r
+#define AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) /*!< 0x00004000 */\r
+\r
+#define AES_CR_KEYSIZE_Pos (18U)\r
+#define AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) /*!< 0x00040000 */\r
+#define AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk /*!< Key size selection */\r
+\r
+/******************* Bit definition for AES_SR register *********************/\r
+#define AES_SR_CCF_Pos (0U)\r
+#define AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) /*!< 0x00000001 */\r
+#define AES_SR_CCF AES_SR_CCF_Msk /*!< Computation Complete Flag */\r
+#define AES_SR_RDERR_Pos (1U)\r
+#define AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) /*!< 0x00000002 */\r
+#define AES_SR_RDERR AES_SR_RDERR_Msk /*!< Read Error Flag */\r
+#define AES_SR_WRERR_Pos (2U)\r
+#define AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) /*!< 0x00000004 */\r
+#define AES_SR_WRERR AES_SR_WRERR_Msk /*!< Write Error Flag */\r
+#define AES_SR_BUSY_Pos (3U)\r
+#define AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) /*!< 0x00000008 */\r
+#define AES_SR_BUSY AES_SR_BUSY_Msk /*!< Busy Flag */\r
+\r
+/******************* Bit definition for AES_DINR register *******************/\r
+#define AES_DINR_Pos (0U)\r
+#define AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_DINR AES_DINR_Msk /*!< AES Data Input Register */\r
+\r
+/******************* Bit definition for AES_DOUTR register ******************/\r
+#define AES_DOUTR_Pos (0U)\r
+#define AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_DOUTR AES_DOUTR_Msk /*!< AES Data Output Register */\r
+\r
+/******************* Bit definition for AES_KEYR0 register ******************/\r
+#define AES_KEYR0_Pos (0U)\r
+#define AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR0 AES_KEYR0_Msk /*!< AES Key Register 0 */\r
+\r
+/******************* Bit definition for AES_KEYR1 register ******************/\r
+#define AES_KEYR1_Pos (0U)\r
+#define AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR1 AES_KEYR1_Msk /*!< AES Key Register 1 */\r
+\r
+/******************* Bit definition for AES_KEYR2 register ******************/\r
+#define AES_KEYR2_Pos (0U)\r
+#define AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR2 AES_KEYR2_Msk /*!< AES Key Register 2 */\r
+\r
+/******************* Bit definition for AES_KEYR3 register ******************/\r
+#define AES_KEYR3_Pos (0U)\r
+#define AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR3 AES_KEYR3_Msk /*!< AES Key Register 3 */\r
+\r
+/******************* Bit definition for AES_KEYR4 register ******************/\r
+#define AES_KEYR4_Pos (0U)\r
+#define AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR4 AES_KEYR4_Msk /*!< AES Key Register 4 */\r
+\r
+/******************* Bit definition for AES_KEYR5 register ******************/\r
+#define AES_KEYR5_Pos (0U)\r
+#define AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR5 AES_KEYR5_Msk /*!< AES Key Register 5 */\r
+\r
+/******************* Bit definition for AES_KEYR6 register ******************/\r
+#define AES_KEYR6_Pos (0U)\r
+#define AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR6 AES_KEYR6_Msk /*!< AES Key Register 6 */\r
+\r
+/******************* Bit definition for AES_KEYR7 register ******************/\r
+#define AES_KEYR7_Pos (0U)\r
+#define AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_KEYR7 AES_KEYR7_Msk /*!< AES Key Register 7 */\r
+\r
+/******************* Bit definition for AES_IVR0 register ******************/\r
+#define AES_IVR0_Pos (0U)\r
+#define AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_IVR0 AES_IVR0_Msk /*!< AES Initialization Vector Register 0 */\r
+\r
+/******************* Bit definition for AES_IVR1 register ******************/\r
+#define AES_IVR1_Pos (0U)\r
+#define AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_IVR1 AES_IVR1_Msk /*!< AES Initialization Vector Register 1 */\r
+\r
+/******************* Bit definition for AES_IVR2 register ******************/\r
+#define AES_IVR2_Pos (0U)\r
+#define AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_IVR2 AES_IVR2_Msk /*!< AES Initialization Vector Register 2 */\r
+\r
+/******************* Bit definition for AES_IVR3 register ******************/\r
+#define AES_IVR3_Pos (0U)\r
+#define AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_IVR3 AES_IVR3_Msk /*!< AES Initialization Vector Register 3 */\r
+\r
+/******************* Bit definition for AES_SUSP0R register ******************/\r
+#define AES_SUSP0R_Pos (0U)\r
+#define AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP0R AES_SUSP0R_Msk /*!< AES Suspend registers 0 */\r
+\r
+/******************* Bit definition for AES_SUSP1R register ******************/\r
+#define AES_SUSP1R_Pos (0U)\r
+#define AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP1R AES_SUSP1R_Msk /*!< AES Suspend registers 1 */\r
+\r
+/******************* Bit definition for AES_SUSP2R register ******************/\r
+#define AES_SUSP2R_Pos (0U)\r
+#define AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP2R AES_SUSP2R_Msk /*!< AES Suspend registers 2 */\r
+\r
+/******************* Bit definition for AES_SUSP3R register ******************/\r
+#define AES_SUSP3R_Pos (0U)\r
+#define AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP3R AES_SUSP3R_Msk /*!< AES Suspend registers 3 */\r
+\r
+/******************* Bit definition for AES_SUSP4R register ******************/\r
+#define AES_SUSP4R_Pos (0U)\r
+#define AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP4R AES_SUSP4R_Msk /*!< AES Suspend registers 4 */\r
+\r
+/******************* Bit definition for AES_SUSP5R register ******************/\r
+#define AES_SUSP5R_Pos (0U)\r
+#define AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP5R AES_SUSP5R_Msk /*!< AES Suspend registers 5 */\r
+\r
+/******************* Bit definition for AES_SUSP6R register ******************/\r
+#define AES_SUSP6R_Pos (0U)\r
+#define AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP6R AES_SUSP6R_Msk /*!< AES Suspend registers 6 */\r
+\r
+/******************* Bit definition for AES_SUSP7R register ******************/\r
+#define AES_SUSP7R_Pos (0U)\r
+#define AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) /*!< 0xFFFFFFFF */\r
+#define AES_SUSP7R AES_SUSP7R_Msk /*!< AES Suspend registers 7 */\r
+/******************************************************************************/\r
+/* */\r
+/* Digital to Analog Converter */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DAC_CR register ********************/\r
+#define DAC_CR_EN1_Pos (0U)\r
+#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */\r
+#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */\r
+#define DAC_CR_BOFF1_Pos (1U)\r
+#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */\r
+#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!<DAC channel1 output buffer disable */\r
+#define DAC_CR_TEN1_Pos (2U)\r
+#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */\r
+#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */\r
+#define DAC_CR_TSEL1_Pos (3U)\r
+#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */\r
+#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */\r
+#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */\r
+#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */\r
+#define DAC_CR_WAVE1_Pos (6U)\r
+#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */\r
+#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) */\r
+#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */\r
+#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */\r
+#define DAC_CR_MAMP1_Pos (8U)\r
+#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */\r
+#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */\r
+#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */\r
+#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */\r
+#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */\r
+#define DAC_CR_DMAEN1_Pos (12U)\r
+#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */\r
+#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */\r
+#define DAC_CR_DMAUDRIE1_Pos (13U)\r
+#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */\r
+#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel1 DMA underrun interrupt enable */\r
+#define DAC_CR_EN2_Pos (16U)\r
+#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */\r
+#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */\r
+#define DAC_CR_BOFF2_Pos (17U)\r
+#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */\r
+#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!<DAC channel2 output buffer disable */\r
+#define DAC_CR_TEN2_Pos (18U)\r
+#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */\r
+#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */\r
+#define DAC_CR_TSEL2_Pos (19U)\r
+#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */\r
+#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */\r
+#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */\r
+#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */\r
+#define DAC_CR_WAVE2_Pos (22U)\r
+#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */\r
+#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */\r
+#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */\r
+#define DAC_CR_MAMP2_Pos (24U)\r
+#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */\r
+#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */\r
+#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */\r
+#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */\r
+#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */\r
+#define DAC_CR_DMAEN2_Pos (28U)\r
+#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */\r
+#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enable */\r
+#define DAC_CR_DMAUDRIE2_Pos (29U)\r
+#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */\r
+#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable */\r
+\r
+/***************** Bit definition for DAC_SWTRIGR register ******************/\r
+#define DAC_SWTRIGR_SWTRIG1_Pos (0U)\r
+#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */\r
+#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */\r
+#define DAC_SWTRIGR_SWTRIG2_Pos (1U)\r
+#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */\r
+#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */\r
+\r
+/***************** Bit definition for DAC_DHR12R1 register ******************/\r
+#define DAC_DHR12R1_DACC1DHR_Pos (0U)\r
+#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L1 register ******************/\r
+#define DAC_DHR12L1_DACC1DHR_Pos (4U)\r
+#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R1 register ******************/\r
+#define DAC_DHR8R1_DACC1DHR_Pos (0U)\r
+#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12R2 register ******************/\r
+#define DAC_DHR12R2_DACC2DHR_Pos (0U)\r
+#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12L2 register ******************/\r
+#define DAC_DHR12L2_DACC2DHR_Pos (4U)\r
+#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8R2 register ******************/\r
+#define DAC_DHR8R2_DACC2DHR_Pos (0U)\r
+#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12RD register ******************/\r
+#define DAC_DHR12RD_DACC1DHR_Pos (0U)\r
+#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */\r
+#define DAC_DHR12RD_DACC2DHR_Pos (16U)\r
+#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */\r
+#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/***************** Bit definition for DAC_DHR12LD register ******************/\r
+#define DAC_DHR12LD_DACC1DHR_Pos (4U)\r
+#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */\r
+#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */\r
+#define DAC_DHR12LD_DACC2DHR_Pos (20U)\r
+#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */\r
+#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/****************** Bit definition for DAC_DHR8RD register ******************/\r
+#define DAC_DHR8RD_DACC1DHR_Pos (0U)\r
+#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */\r
+#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */\r
+#define DAC_DHR8RD_DACC2DHR_Pos (8U)\r
+#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */\r
+#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/******************* Bit definition for DAC_DOR1 register *******************/\r
+#define DAC_DOR1_DACC1DOR_Pos (0U)\r
+#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */\r
+\r
+/******************* Bit definition for DAC_DOR2 register *******************/\r
+#define DAC_DOR2_DACC2DOR_Pos (0U)\r
+#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */\r
+#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */\r
+\r
+/******************** Bit definition for DAC_SR register ********************/\r
+#define DAC_SR_DMAUDR1_Pos (13U)\r
+#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */\r
+#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */\r
+#define DAC_SR_DMAUDR2_Pos (29U)\r
+#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */\r
+#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Debug MCU */\r
+/* */\r
+/******************************************************************************/\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DMA Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for DMA_SxCR register *****************/\r
+#define DMA_SxCR_CHSEL_Pos (25U)\r
+#define DMA_SxCR_CHSEL_Msk (0xFUL << DMA_SxCR_CHSEL_Pos) /*!< 0x1E000000 */\r
+#define DMA_SxCR_CHSEL DMA_SxCR_CHSEL_Msk\r
+#define DMA_SxCR_CHSEL_0 (0x1UL << DMA_SxCR_CHSEL_Pos) /*!< 0x02000000 */\r
+#define DMA_SxCR_CHSEL_1 (0x2UL << DMA_SxCR_CHSEL_Pos) /*!< 0x04000000 */\r
+#define DMA_SxCR_CHSEL_2 (0x4UL << DMA_SxCR_CHSEL_Pos) /*!< 0x08000000 */\r
+#define DMA_SxCR_CHSEL_3 (0x8UL << DMA_SxCR_CHSEL_Pos) /*!< 0x10000000 */\r
+#define DMA_SxCR_MBURST_Pos (23U)\r
+#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */\r
+#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk\r
+#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */\r
+#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */\r
+#define DMA_SxCR_PBURST_Pos (21U)\r
+#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */\r
+#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk\r
+#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */\r
+#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */\r
+#define DMA_SxCR_CT_Pos (19U)\r
+#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */\r
+#define DMA_SxCR_CT DMA_SxCR_CT_Msk\r
+#define DMA_SxCR_DBM_Pos (18U)\r
+#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */\r
+#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk\r
+#define DMA_SxCR_PL_Pos (16U)\r
+#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */\r
+#define DMA_SxCR_PL DMA_SxCR_PL_Msk\r
+#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */\r
+#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */\r
+#define DMA_SxCR_PINCOS_Pos (15U)\r
+#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */\r
+#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk\r
+#define DMA_SxCR_MSIZE_Pos (13U)\r
+#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */\r
+#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk\r
+#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */\r
+#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */\r
+#define DMA_SxCR_PSIZE_Pos (11U)\r
+#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */\r
+#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk\r
+#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */\r
+#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */\r
+#define DMA_SxCR_MINC_Pos (10U)\r
+#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */\r
+#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk\r
+#define DMA_SxCR_PINC_Pos (9U)\r
+#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */\r
+#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk\r
+#define DMA_SxCR_CIRC_Pos (8U)\r
+#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */\r
+#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk\r
+#define DMA_SxCR_DIR_Pos (6U)\r
+#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */\r
+#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk\r
+#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */\r
+#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */\r
+#define DMA_SxCR_PFCTRL_Pos (5U)\r
+#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */\r
+#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk\r
+#define DMA_SxCR_TCIE_Pos (4U)\r
+#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */\r
+#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk\r
+#define DMA_SxCR_HTIE_Pos (3U)\r
+#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */\r
+#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk\r
+#define DMA_SxCR_TEIE_Pos (2U)\r
+#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */\r
+#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk\r
+#define DMA_SxCR_DMEIE_Pos (1U)\r
+#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */\r
+#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk\r
+#define DMA_SxCR_EN_Pos (0U)\r
+#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */\r
+#define DMA_SxCR_EN DMA_SxCR_EN_Msk\r
+\r
+/******************** Bits definition for DMA_SxCNDTR register **************/\r
+#define DMA_SxNDT_Pos (0U)\r
+#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */\r
+#define DMA_SxNDT DMA_SxNDT_Msk\r
+#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */\r
+#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */\r
+#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */\r
+#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */\r
+#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */\r
+#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */\r
+#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */\r
+#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */\r
+#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */\r
+#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */\r
+#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */\r
+#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */\r
+#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */\r
+#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */\r
+#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */\r
+#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */\r
+\r
+/******************** Bits definition for DMA_SxFCR register ****************/\r
+#define DMA_SxFCR_FEIE_Pos (7U)\r
+#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */\r
+#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk\r
+#define DMA_SxFCR_FS_Pos (3U)\r
+#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */\r
+#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk\r
+#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */\r
+#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */\r
+#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */\r
+#define DMA_SxFCR_DMDIS_Pos (2U)\r
+#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */\r
+#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk\r
+#define DMA_SxFCR_FTH_Pos (0U)\r
+#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */\r
+#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk\r
+#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */\r
+#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */\r
+\r
+/******************** Bits definition for DMA_LISR register *****************/\r
+#define DMA_LISR_TCIF3_Pos (27U)\r
+#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk\r
+#define DMA_LISR_HTIF3_Pos (26U)\r
+#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk\r
+#define DMA_LISR_TEIF3_Pos (25U)\r
+#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk\r
+#define DMA_LISR_DMEIF3_Pos (24U)\r
+#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk\r
+#define DMA_LISR_FEIF3_Pos (22U)\r
+#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk\r
+#define DMA_LISR_TCIF2_Pos (21U)\r
+#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk\r
+#define DMA_LISR_HTIF2_Pos (20U)\r
+#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk\r
+#define DMA_LISR_TEIF2_Pos (19U)\r
+#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk\r
+#define DMA_LISR_DMEIF2_Pos (18U)\r
+#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk\r
+#define DMA_LISR_FEIF2_Pos (16U)\r
+#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk\r
+#define DMA_LISR_TCIF1_Pos (11U)\r
+#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk\r
+#define DMA_LISR_HTIF1_Pos (10U)\r
+#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk\r
+#define DMA_LISR_TEIF1_Pos (9U)\r
+#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk\r
+#define DMA_LISR_DMEIF1_Pos (8U)\r
+#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk\r
+#define DMA_LISR_FEIF1_Pos (6U)\r
+#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk\r
+#define DMA_LISR_TCIF0_Pos (5U)\r
+#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk\r
+#define DMA_LISR_HTIF0_Pos (4U)\r
+#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk\r
+#define DMA_LISR_TEIF0_Pos (3U)\r
+#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk\r
+#define DMA_LISR_DMEIF0_Pos (2U)\r
+#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk\r
+#define DMA_LISR_FEIF0_Pos (0U)\r
+#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk\r
+\r
+/******************** Bits definition for DMA_HISR register *****************/\r
+#define DMA_HISR_TCIF7_Pos (27U)\r
+#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk\r
+#define DMA_HISR_HTIF7_Pos (26U)\r
+#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk\r
+#define DMA_HISR_TEIF7_Pos (25U)\r
+#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk\r
+#define DMA_HISR_DMEIF7_Pos (24U)\r
+#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk\r
+#define DMA_HISR_FEIF7_Pos (22U)\r
+#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk\r
+#define DMA_HISR_TCIF6_Pos (21U)\r
+#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk\r
+#define DMA_HISR_HTIF6_Pos (20U)\r
+#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk\r
+#define DMA_HISR_TEIF6_Pos (19U)\r
+#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk\r
+#define DMA_HISR_DMEIF6_Pos (18U)\r
+#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk\r
+#define DMA_HISR_FEIF6_Pos (16U)\r
+#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk\r
+#define DMA_HISR_TCIF5_Pos (11U)\r
+#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk\r
+#define DMA_HISR_HTIF5_Pos (10U)\r
+#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk\r
+#define DMA_HISR_TEIF5_Pos (9U)\r
+#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk\r
+#define DMA_HISR_DMEIF5_Pos (8U)\r
+#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk\r
+#define DMA_HISR_FEIF5_Pos (6U)\r
+#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk\r
+#define DMA_HISR_TCIF4_Pos (5U)\r
+#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk\r
+#define DMA_HISR_HTIF4_Pos (4U)\r
+#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk\r
+#define DMA_HISR_TEIF4_Pos (3U)\r
+#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk\r
+#define DMA_HISR_DMEIF4_Pos (2U)\r
+#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk\r
+#define DMA_HISR_FEIF4_Pos (0U)\r
+#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk\r
+\r
+/******************** Bits definition for DMA_LIFCR register ****************/\r
+#define DMA_LIFCR_CTCIF3_Pos (27U)\r
+#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */\r
+#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk\r
+#define DMA_LIFCR_CHTIF3_Pos (26U)\r
+#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */\r
+#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk\r
+#define DMA_LIFCR_CTEIF3_Pos (25U)\r
+#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */\r
+#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk\r
+#define DMA_LIFCR_CDMEIF3_Pos (24U)\r
+#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */\r
+#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk\r
+#define DMA_LIFCR_CFEIF3_Pos (22U)\r
+#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */\r
+#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk\r
+#define DMA_LIFCR_CTCIF2_Pos (21U)\r
+#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */\r
+#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk\r
+#define DMA_LIFCR_CHTIF2_Pos (20U)\r
+#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */\r
+#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk\r
+#define DMA_LIFCR_CTEIF2_Pos (19U)\r
+#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */\r
+#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk\r
+#define DMA_LIFCR_CDMEIF2_Pos (18U)\r
+#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */\r
+#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk\r
+#define DMA_LIFCR_CFEIF2_Pos (16U)\r
+#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */\r
+#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk\r
+#define DMA_LIFCR_CTCIF1_Pos (11U)\r
+#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */\r
+#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk\r
+#define DMA_LIFCR_CHTIF1_Pos (10U)\r
+#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */\r
+#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk\r
+#define DMA_LIFCR_CTEIF1_Pos (9U)\r
+#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */\r
+#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk\r
+#define DMA_LIFCR_CDMEIF1_Pos (8U)\r
+#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */\r
+#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk\r
+#define DMA_LIFCR_CFEIF1_Pos (6U)\r
+#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */\r
+#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk\r
+#define DMA_LIFCR_CTCIF0_Pos (5U)\r
+#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */\r
+#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk\r
+#define DMA_LIFCR_CHTIF0_Pos (4U)\r
+#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */\r
+#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk\r
+#define DMA_LIFCR_CTEIF0_Pos (3U)\r
+#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */\r
+#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk\r
+#define DMA_LIFCR_CDMEIF0_Pos (2U)\r
+#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */\r
+#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk\r
+#define DMA_LIFCR_CFEIF0_Pos (0U)\r
+#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */\r
+#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk\r
+\r
+/******************** Bits definition for DMA_HIFCR register ****************/\r
+#define DMA_HIFCR_CTCIF7_Pos (27U)\r
+#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */\r
+#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk\r
+#define DMA_HIFCR_CHTIF7_Pos (26U)\r
+#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */\r
+#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk\r
+#define DMA_HIFCR_CTEIF7_Pos (25U)\r
+#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */\r
+#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk\r
+#define DMA_HIFCR_CDMEIF7_Pos (24U)\r
+#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */\r
+#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk\r
+#define DMA_HIFCR_CFEIF7_Pos (22U)\r
+#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */\r
+#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk\r
+#define DMA_HIFCR_CTCIF6_Pos (21U)\r
+#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */\r
+#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk\r
+#define DMA_HIFCR_CHTIF6_Pos (20U)\r
+#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */\r
+#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk\r
+#define DMA_HIFCR_CTEIF6_Pos (19U)\r
+#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */\r
+#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk\r
+#define DMA_HIFCR_CDMEIF6_Pos (18U)\r
+#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */\r
+#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk\r
+#define DMA_HIFCR_CFEIF6_Pos (16U)\r
+#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */\r
+#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk\r
+#define DMA_HIFCR_CTCIF5_Pos (11U)\r
+#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */\r
+#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk\r
+#define DMA_HIFCR_CHTIF5_Pos (10U)\r
+#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */\r
+#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk\r
+#define DMA_HIFCR_CTEIF5_Pos (9U)\r
+#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */\r
+#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk\r
+#define DMA_HIFCR_CDMEIF5_Pos (8U)\r
+#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */\r
+#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk\r
+#define DMA_HIFCR_CFEIF5_Pos (6U)\r
+#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */\r
+#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk\r
+#define DMA_HIFCR_CTCIF4_Pos (5U)\r
+#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */\r
+#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk\r
+#define DMA_HIFCR_CHTIF4_Pos (4U)\r
+#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */\r
+#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk\r
+#define DMA_HIFCR_CTEIF4_Pos (3U)\r
+#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */\r
+#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk\r
+#define DMA_HIFCR_CDMEIF4_Pos (2U)\r
+#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */\r
+#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk\r
+#define DMA_HIFCR_CFEIF4_Pos (0U)\r
+#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */\r
+#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk\r
+\r
+/****************** Bit definition for DMA_SxPAR register ********************/\r
+#define DMA_SxPAR_PA_Pos (0U)\r
+#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */\r
+\r
+/****************** Bit definition for DMA_SxM0AR register ********************/\r
+#define DMA_SxM0AR_M0A_Pos (0U)\r
+#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory Address */\r
+\r
+/****************** Bit definition for DMA_SxM1AR register ********************/\r
+#define DMA_SxM1AR_M1A_Pos (0U)\r
+#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */\r
+#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory Address */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* External Interrupt/Event Controller */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for EXTI_IMR register *******************/\r
+#define EXTI_IMR_MR0_Pos (0U)\r
+#define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */\r
+#define EXTI_IMR_MR1_Pos (1U)\r
+#define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */\r
+#define EXTI_IMR_MR2_Pos (2U)\r
+#define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */\r
+#define EXTI_IMR_MR3_Pos (3U)\r
+#define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */\r
+#define EXTI_IMR_MR4_Pos (4U)\r
+#define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */\r
+#define EXTI_IMR_MR5_Pos (5U)\r
+#define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */\r
+#define EXTI_IMR_MR6_Pos (6U)\r
+#define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */\r
+#define EXTI_IMR_MR7_Pos (7U)\r
+#define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */\r
+#define EXTI_IMR_MR8_Pos (8U)\r
+#define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */\r
+#define EXTI_IMR_MR9_Pos (9U)\r
+#define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */\r
+#define EXTI_IMR_MR10_Pos (10U)\r
+#define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */\r
+#define EXTI_IMR_MR11_Pos (11U)\r
+#define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */\r
+#define EXTI_IMR_MR12_Pos (12U)\r
+#define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */\r
+#define EXTI_IMR_MR13_Pos (13U)\r
+#define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */\r
+#define EXTI_IMR_MR14_Pos (14U)\r
+#define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */\r
+#define EXTI_IMR_MR15_Pos (15U)\r
+#define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */\r
+#define EXTI_IMR_MR16_Pos (16U)\r
+#define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */\r
+#define EXTI_IMR_MR17_Pos (17U)\r
+#define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */\r
+#define EXTI_IMR_MR18_Pos (18U)\r
+#define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */\r
+#define EXTI_IMR_MR19_Pos (19U)\r
+#define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */\r
+#define EXTI_IMR_MR20_Pos (20U)\r
+#define EXTI_IMR_MR20_Msk (0x1UL << EXTI_IMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_IMR_MR20 EXTI_IMR_MR20_Msk /*!< Interrupt Mask on line 20 */\r
+#define EXTI_IMR_MR21_Pos (21U)\r
+#define EXTI_IMR_MR21_Msk (0x1UL << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */\r
+#define EXTI_IMR_MR22_Pos (22U)\r
+#define EXTI_IMR_MR22_Msk (0x1UL << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */\r
+#define EXTI_IMR_MR23_Pos (23U)\r
+#define EXTI_IMR_MR23_Msk (0x1UL << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_IMR_IM0 EXTI_IMR_MR0\r
+#define EXTI_IMR_IM1 EXTI_IMR_MR1\r
+#define EXTI_IMR_IM2 EXTI_IMR_MR2\r
+#define EXTI_IMR_IM3 EXTI_IMR_MR3\r
+#define EXTI_IMR_IM4 EXTI_IMR_MR4\r
+#define EXTI_IMR_IM5 EXTI_IMR_MR5\r
+#define EXTI_IMR_IM6 EXTI_IMR_MR6\r
+#define EXTI_IMR_IM7 EXTI_IMR_MR7\r
+#define EXTI_IMR_IM8 EXTI_IMR_MR8\r
+#define EXTI_IMR_IM9 EXTI_IMR_MR9\r
+#define EXTI_IMR_IM10 EXTI_IMR_MR10\r
+#define EXTI_IMR_IM11 EXTI_IMR_MR11\r
+#define EXTI_IMR_IM12 EXTI_IMR_MR12\r
+#define EXTI_IMR_IM13 EXTI_IMR_MR13\r
+#define EXTI_IMR_IM14 EXTI_IMR_MR14\r
+#define EXTI_IMR_IM15 EXTI_IMR_MR15\r
+#define EXTI_IMR_IM16 EXTI_IMR_MR16\r
+#define EXTI_IMR_IM17 EXTI_IMR_MR17\r
+#define EXTI_IMR_IM18 EXTI_IMR_MR18\r
+#define EXTI_IMR_IM19 EXTI_IMR_MR19\r
+#define EXTI_IMR_IM20 EXTI_IMR_MR20\r
+#define EXTI_IMR_IM21 EXTI_IMR_MR21\r
+#define EXTI_IMR_IM22 EXTI_IMR_MR22\r
+#define EXTI_IMR_IM23 EXTI_IMR_MR23\r
+\r
+#define EXTI_IMR_IM_Pos (0U)\r
+#define EXTI_IMR_IM_Msk (0xFFFFFFUL << EXTI_IMR_IM_Pos) /*!< 0x00FFFFFF */\r
+#define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */\r
+\r
+/******************* Bit definition for EXTI_EMR register *******************/\r
+#define EXTI_EMR_MR0_Pos (0U)\r
+#define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */\r
+#define EXTI_EMR_MR1_Pos (1U)\r
+#define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */\r
+#define EXTI_EMR_MR2_Pos (2U)\r
+#define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */\r
+#define EXTI_EMR_MR3_Pos (3U)\r
+#define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */\r
+#define EXTI_EMR_MR4_Pos (4U)\r
+#define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */\r
+#define EXTI_EMR_MR5_Pos (5U)\r
+#define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */\r
+#define EXTI_EMR_MR6_Pos (6U)\r
+#define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */\r
+#define EXTI_EMR_MR7_Pos (7U)\r
+#define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */\r
+#define EXTI_EMR_MR8_Pos (8U)\r
+#define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */\r
+#define EXTI_EMR_MR9_Pos (9U)\r
+#define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */\r
+#define EXTI_EMR_MR10_Pos (10U)\r
+#define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */\r
+#define EXTI_EMR_MR11_Pos (11U)\r
+#define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */\r
+#define EXTI_EMR_MR12_Pos (12U)\r
+#define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */\r
+#define EXTI_EMR_MR13_Pos (13U)\r
+#define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */\r
+#define EXTI_EMR_MR14_Pos (14U)\r
+#define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */\r
+#define EXTI_EMR_MR15_Pos (15U)\r
+#define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */\r
+#define EXTI_EMR_MR16_Pos (16U)\r
+#define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */\r
+#define EXTI_EMR_MR17_Pos (17U)\r
+#define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */\r
+#define EXTI_EMR_MR18_Pos (18U)\r
+#define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */\r
+#define EXTI_EMR_MR19_Pos (19U)\r
+#define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */\r
+#define EXTI_EMR_MR20_Pos (20U)\r
+#define EXTI_EMR_MR20_Msk (0x1UL << EXTI_EMR_MR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_EMR_MR20 EXTI_EMR_MR20_Msk /*!< Event Mask on line 20 */\r
+#define EXTI_EMR_MR21_Pos (21U)\r
+#define EXTI_EMR_MR21_Msk (0x1UL << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */\r
+#define EXTI_EMR_MR22_Pos (22U)\r
+#define EXTI_EMR_MR22_Msk (0x1UL << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */\r
+#define EXTI_EMR_MR23_Pos (23U)\r
+#define EXTI_EMR_MR23_Msk (0x1UL << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */\r
+\r
+/* Reference Defines */\r
+#define EXTI_EMR_EM0 EXTI_EMR_MR0\r
+#define EXTI_EMR_EM1 EXTI_EMR_MR1\r
+#define EXTI_EMR_EM2 EXTI_EMR_MR2\r
+#define EXTI_EMR_EM3 EXTI_EMR_MR3\r
+#define EXTI_EMR_EM4 EXTI_EMR_MR4\r
+#define EXTI_EMR_EM5 EXTI_EMR_MR5\r
+#define EXTI_EMR_EM6 EXTI_EMR_MR6\r
+#define EXTI_EMR_EM7 EXTI_EMR_MR7\r
+#define EXTI_EMR_EM8 EXTI_EMR_MR8\r
+#define EXTI_EMR_EM9 EXTI_EMR_MR9\r
+#define EXTI_EMR_EM10 EXTI_EMR_MR10\r
+#define EXTI_EMR_EM11 EXTI_EMR_MR11\r
+#define EXTI_EMR_EM12 EXTI_EMR_MR12\r
+#define EXTI_EMR_EM13 EXTI_EMR_MR13\r
+#define EXTI_EMR_EM14 EXTI_EMR_MR14\r
+#define EXTI_EMR_EM15 EXTI_EMR_MR15\r
+#define EXTI_EMR_EM16 EXTI_EMR_MR16\r
+#define EXTI_EMR_EM17 EXTI_EMR_MR17\r
+#define EXTI_EMR_EM18 EXTI_EMR_MR18\r
+#define EXTI_EMR_EM19 EXTI_EMR_MR19\r
+#define EXTI_EMR_EM20 EXTI_EMR_MR20\r
+#define EXTI_EMR_EM21 EXTI_EMR_MR21\r
+#define EXTI_EMR_EM22 EXTI_EMR_MR22\r
+#define EXTI_EMR_EM23 EXTI_EMR_MR23\r
+\r
+\r
+/****************** Bit definition for EXTI_RTSR register *******************/\r
+#define EXTI_RTSR_TR0_Pos (0U)\r
+#define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */\r
+#define EXTI_RTSR_TR1_Pos (1U)\r
+#define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */\r
+#define EXTI_RTSR_TR2_Pos (2U)\r
+#define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */\r
+#define EXTI_RTSR_TR3_Pos (3U)\r
+#define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */\r
+#define EXTI_RTSR_TR4_Pos (4U)\r
+#define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */\r
+#define EXTI_RTSR_TR5_Pos (5U)\r
+#define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */\r
+#define EXTI_RTSR_TR6_Pos (6U)\r
+#define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */\r
+#define EXTI_RTSR_TR7_Pos (7U)\r
+#define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */\r
+#define EXTI_RTSR_TR8_Pos (8U)\r
+#define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */\r
+#define EXTI_RTSR_TR9_Pos (9U)\r
+#define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */\r
+#define EXTI_RTSR_TR10_Pos (10U)\r
+#define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */\r
+#define EXTI_RTSR_TR11_Pos (11U)\r
+#define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */\r
+#define EXTI_RTSR_TR12_Pos (12U)\r
+#define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */\r
+#define EXTI_RTSR_TR13_Pos (13U)\r
+#define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */\r
+#define EXTI_RTSR_TR14_Pos (14U)\r
+#define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */\r
+#define EXTI_RTSR_TR15_Pos (15U)\r
+#define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */\r
+#define EXTI_RTSR_TR16_Pos (16U)\r
+#define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */\r
+#define EXTI_RTSR_TR17_Pos (17U)\r
+#define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */\r
+#define EXTI_RTSR_TR18_Pos (18U)\r
+#define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */\r
+#define EXTI_RTSR_TR19_Pos (19U)\r
+#define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */\r
+#define EXTI_RTSR_TR20_Pos (20U)\r
+#define EXTI_RTSR_TR20_Msk (0x1UL << EXTI_RTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_RTSR_TR20 EXTI_RTSR_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */\r
+#define EXTI_RTSR_TR21_Pos (21U)\r
+#define EXTI_RTSR_TR21_Msk (0x1UL << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */\r
+#define EXTI_RTSR_TR22_Pos (22U)\r
+#define EXTI_RTSR_TR22_Msk (0x1UL << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */\r
+#define EXTI_RTSR_TR23_Pos (23U)\r
+#define EXTI_RTSR_TR23_Msk (0x1UL << EXTI_RTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_RTSR_TR23 EXTI_RTSR_TR23_Msk /*!< Rising trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_FTSR register *******************/\r
+#define EXTI_FTSR_TR0_Pos (0U)\r
+#define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */\r
+#define EXTI_FTSR_TR1_Pos (1U)\r
+#define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */\r
+#define EXTI_FTSR_TR2_Pos (2U)\r
+#define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */\r
+#define EXTI_FTSR_TR3_Pos (3U)\r
+#define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */\r
+#define EXTI_FTSR_TR4_Pos (4U)\r
+#define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */\r
+#define EXTI_FTSR_TR5_Pos (5U)\r
+#define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */\r
+#define EXTI_FTSR_TR6_Pos (6U)\r
+#define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */\r
+#define EXTI_FTSR_TR7_Pos (7U)\r
+#define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */\r
+#define EXTI_FTSR_TR8_Pos (8U)\r
+#define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */\r
+#define EXTI_FTSR_TR9_Pos (9U)\r
+#define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */\r
+#define EXTI_FTSR_TR10_Pos (10U)\r
+#define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */\r
+#define EXTI_FTSR_TR11_Pos (11U)\r
+#define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */\r
+#define EXTI_FTSR_TR12_Pos (12U)\r
+#define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */\r
+#define EXTI_FTSR_TR13_Pos (13U)\r
+#define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */\r
+#define EXTI_FTSR_TR14_Pos (14U)\r
+#define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */\r
+#define EXTI_FTSR_TR15_Pos (15U)\r
+#define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */\r
+#define EXTI_FTSR_TR16_Pos (16U)\r
+#define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */\r
+#define EXTI_FTSR_TR17_Pos (17U)\r
+#define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */\r
+#define EXTI_FTSR_TR18_Pos (18U)\r
+#define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */\r
+#define EXTI_FTSR_TR19_Pos (19U)\r
+#define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */\r
+#define EXTI_FTSR_TR20_Pos (20U)\r
+#define EXTI_FTSR_TR20_Msk (0x1UL << EXTI_FTSR_TR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_FTSR_TR20 EXTI_FTSR_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */\r
+#define EXTI_FTSR_TR21_Pos (21U)\r
+#define EXTI_FTSR_TR21_Msk (0x1UL << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */\r
+#define EXTI_FTSR_TR22_Pos (22U)\r
+#define EXTI_FTSR_TR22_Msk (0x1UL << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */\r
+#define EXTI_FTSR_TR23_Pos (23U)\r
+#define EXTI_FTSR_TR23_Msk (0x1UL << EXTI_FTSR_TR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_FTSR_TR23 EXTI_FTSR_TR23_Msk /*!< Falling trigger event configuration bit of line 23 */\r
+\r
+/****************** Bit definition for EXTI_SWIER register ******************/\r
+#define EXTI_SWIER_SWIER0_Pos (0U)\r
+#define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */\r
+#define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */\r
+#define EXTI_SWIER_SWIER1_Pos (1U)\r
+#define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */\r
+#define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */\r
+#define EXTI_SWIER_SWIER2_Pos (2U)\r
+#define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */\r
+#define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */\r
+#define EXTI_SWIER_SWIER3_Pos (3U)\r
+#define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */\r
+#define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */\r
+#define EXTI_SWIER_SWIER4_Pos (4U)\r
+#define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */\r
+#define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */\r
+#define EXTI_SWIER_SWIER5_Pos (5U)\r
+#define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */\r
+#define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */\r
+#define EXTI_SWIER_SWIER6_Pos (6U)\r
+#define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */\r
+#define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */\r
+#define EXTI_SWIER_SWIER7_Pos (7U)\r
+#define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */\r
+#define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */\r
+#define EXTI_SWIER_SWIER8_Pos (8U)\r
+#define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */\r
+#define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */\r
+#define EXTI_SWIER_SWIER9_Pos (9U)\r
+#define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */\r
+#define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */\r
+#define EXTI_SWIER_SWIER10_Pos (10U)\r
+#define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */\r
+#define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */\r
+#define EXTI_SWIER_SWIER11_Pos (11U)\r
+#define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */\r
+#define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */\r
+#define EXTI_SWIER_SWIER12_Pos (12U)\r
+#define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */\r
+#define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */\r
+#define EXTI_SWIER_SWIER13_Pos (13U)\r
+#define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */\r
+#define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */\r
+#define EXTI_SWIER_SWIER14_Pos (14U)\r
+#define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */\r
+#define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */\r
+#define EXTI_SWIER_SWIER15_Pos (15U)\r
+#define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */\r
+#define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */\r
+#define EXTI_SWIER_SWIER16_Pos (16U)\r
+#define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */\r
+#define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */\r
+#define EXTI_SWIER_SWIER17_Pos (17U)\r
+#define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */\r
+#define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */\r
+#define EXTI_SWIER_SWIER18_Pos (18U)\r
+#define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */\r
+#define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */\r
+#define EXTI_SWIER_SWIER19_Pos (19U)\r
+#define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */\r
+#define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */\r
+#define EXTI_SWIER_SWIER20_Pos (20U)\r
+#define EXTI_SWIER_SWIER20_Msk (0x1UL << EXTI_SWIER_SWIER20_Pos) /*!< 0x00100000 */\r
+#define EXTI_SWIER_SWIER20 EXTI_SWIER_SWIER20_Msk /*!< Software Interrupt on line 20 */\r
+#define EXTI_SWIER_SWIER21_Pos (21U)\r
+#define EXTI_SWIER_SWIER21_Msk (0x1UL << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */\r
+#define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */\r
+#define EXTI_SWIER_SWIER22_Pos (22U)\r
+#define EXTI_SWIER_SWIER22_Msk (0x1UL << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */\r
+#define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */\r
+#define EXTI_SWIER_SWIER23_Pos (23U)\r
+#define EXTI_SWIER_SWIER23_Msk (0x1UL << EXTI_SWIER_SWIER23_Pos) /*!< 0x00800000 */\r
+#define EXTI_SWIER_SWIER23 EXTI_SWIER_SWIER23_Msk /*!< Software Interrupt on line 23 */\r
+\r
+/******************* Bit definition for EXTI_PR register ********************/\r
+#define EXTI_PR_PR0_Pos (0U)\r
+#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */\r
+#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */\r
+#define EXTI_PR_PR1_Pos (1U)\r
+#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */\r
+#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */\r
+#define EXTI_PR_PR2_Pos (2U)\r
+#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */\r
+#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */\r
+#define EXTI_PR_PR3_Pos (3U)\r
+#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */\r
+#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */\r
+#define EXTI_PR_PR4_Pos (4U)\r
+#define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */\r
+#define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */\r
+#define EXTI_PR_PR5_Pos (5U)\r
+#define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */\r
+#define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */\r
+#define EXTI_PR_PR6_Pos (6U)\r
+#define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */\r
+#define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */\r
+#define EXTI_PR_PR7_Pos (7U)\r
+#define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */\r
+#define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */\r
+#define EXTI_PR_PR8_Pos (8U)\r
+#define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */\r
+#define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */\r
+#define EXTI_PR_PR9_Pos (9U)\r
+#define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */\r
+#define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */\r
+#define EXTI_PR_PR10_Pos (10U)\r
+#define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */\r
+#define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */\r
+#define EXTI_PR_PR11_Pos (11U)\r
+#define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */\r
+#define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */\r
+#define EXTI_PR_PR12_Pos (12U)\r
+#define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */\r
+#define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */\r
+#define EXTI_PR_PR13_Pos (13U)\r
+#define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */\r
+#define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */\r
+#define EXTI_PR_PR14_Pos (14U)\r
+#define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */\r
+#define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */\r
+#define EXTI_PR_PR15_Pos (15U)\r
+#define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */\r
+#define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */\r
+#define EXTI_PR_PR16_Pos (16U)\r
+#define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */\r
+#define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */\r
+#define EXTI_PR_PR17_Pos (17U)\r
+#define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */\r
+#define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */\r
+#define EXTI_PR_PR18_Pos (18U)\r
+#define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */\r
+#define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */\r
+#define EXTI_PR_PR19_Pos (19U)\r
+#define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */\r
+#define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */\r
+#define EXTI_PR_PR20_Pos (20U)\r
+#define EXTI_PR_PR20_Msk (0x1UL << EXTI_PR_PR20_Pos) /*!< 0x00100000 */\r
+#define EXTI_PR_PR20 EXTI_PR_PR20_Msk /*!< Pending bit for line 20 */\r
+#define EXTI_PR_PR21_Pos (21U)\r
+#define EXTI_PR_PR21_Msk (0x1UL << EXTI_PR_PR21_Pos) /*!< 0x00200000 */\r
+#define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit for line 21 */\r
+#define EXTI_PR_PR22_Pos (22U)\r
+#define EXTI_PR_PR22_Msk (0x1UL << EXTI_PR_PR22_Pos) /*!< 0x00400000 */\r
+#define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit for line 22 */\r
+#define EXTI_PR_PR23_Pos (23U)\r
+#define EXTI_PR_PR23_Msk (0x1UL << EXTI_PR_PR23_Pos) /*!< 0x00800000 */\r
+#define EXTI_PR_PR23 EXTI_PR_PR23_Msk /*!< Pending bit for line 23 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* FLASH */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+* @brief FLASH Total Sectors Number\r
+*/\r
+#define FLASH_SECTOR_TOTAL 4\r
+\r
+/******************* Bits definition for FLASH_ACR register *****************/\r
+#define FLASH_ACR_LATENCY_Pos (0U)\r
+#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */\r
+#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk\r
+#define FLASH_ACR_LATENCY_0WS 0x00000000U\r
+#define FLASH_ACR_LATENCY_1WS 0x00000001U\r
+#define FLASH_ACR_LATENCY_2WS 0x00000002U\r
+#define FLASH_ACR_LATENCY_3WS 0x00000003U\r
+#define FLASH_ACR_LATENCY_4WS 0x00000004U\r
+#define FLASH_ACR_LATENCY_5WS 0x00000005U\r
+#define FLASH_ACR_LATENCY_6WS 0x00000006U\r
+#define FLASH_ACR_LATENCY_7WS 0x00000007U\r
+#define FLASH_ACR_LATENCY_8WS 0x00000008U\r
+#define FLASH_ACR_LATENCY_9WS 0x00000009U\r
+#define FLASH_ACR_LATENCY_10WS 0x0000000AU\r
+#define FLASH_ACR_LATENCY_11WS 0x0000000BU\r
+#define FLASH_ACR_LATENCY_12WS 0x0000000CU\r
+#define FLASH_ACR_LATENCY_13WS 0x0000000DU\r
+#define FLASH_ACR_LATENCY_14WS 0x0000000EU\r
+#define FLASH_ACR_LATENCY_15WS 0x0000000FU\r
+#define FLASH_ACR_PRFTEN_Pos (8U)\r
+#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */\r
+#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk\r
+#define FLASH_ACR_ARTEN_Pos (9U)\r
+#define FLASH_ACR_ARTEN_Msk (0x1UL << FLASH_ACR_ARTEN_Pos) /*!< 0x00000200 */\r
+#define FLASH_ACR_ARTEN FLASH_ACR_ARTEN_Msk\r
+#define FLASH_ACR_ARTRST_Pos (11U)\r
+#define FLASH_ACR_ARTRST_Msk (0x1UL << FLASH_ACR_ARTRST_Pos) /*!< 0x00000800 */\r
+#define FLASH_ACR_ARTRST FLASH_ACR_ARTRST_Msk\r
+\r
+/******************* Bits definition for FLASH_SR register ******************/\r
+#define FLASH_SR_EOP_Pos (0U)\r
+#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */\r
+#define FLASH_SR_EOP FLASH_SR_EOP_Msk\r
+#define FLASH_SR_OPERR_Pos (1U)\r
+#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00000002 */\r
+#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk\r
+#define FLASH_SR_WRPERR_Pos (4U)\r
+#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */\r
+#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk\r
+#define FLASH_SR_PGAERR_Pos (5U)\r
+#define FLASH_SR_PGAERR_Msk (0x1UL << FLASH_SR_PGAERR_Pos) /*!< 0x00000020 */\r
+#define FLASH_SR_PGAERR FLASH_SR_PGAERR_Msk\r
+#define FLASH_SR_PGPERR_Pos (6U)\r
+#define FLASH_SR_PGPERR_Msk (0x1UL << FLASH_SR_PGPERR_Pos) /*!< 0x00000040 */\r
+#define FLASH_SR_PGPERR FLASH_SR_PGPERR_Msk\r
+#define FLASH_SR_ERSERR_Pos (7U)\r
+#define FLASH_SR_ERSERR_Msk (0x1UL << FLASH_SR_ERSERR_Pos) /*!< 0x00000080 */\r
+#define FLASH_SR_ERSERR FLASH_SR_ERSERR_Msk\r
+#define FLASH_SR_RDERR_Pos (8U)\r
+#define FLASH_SR_RDERR_Msk (0x1UL << FLASH_SR_RDERR_Pos) /*!< 0x00000100 */\r
+#define FLASH_SR_RDERR FLASH_SR_RDERR_Msk\r
+#define FLASH_SR_BSY_Pos (16U)\r
+#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */\r
+#define FLASH_SR_BSY FLASH_SR_BSY_Msk\r
+\r
+/******************* Bits definition for FLASH_CR register ******************/\r
+#define FLASH_CR_PG_Pos (0U)\r
+#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */\r
+#define FLASH_CR_PG FLASH_CR_PG_Msk\r
+#define FLASH_CR_SER_Pos (1U)\r
+#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000002 */\r
+#define FLASH_CR_SER FLASH_CR_SER_Msk\r
+#define FLASH_CR_MER_Pos (2U)\r
+#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */\r
+#define FLASH_CR_MER FLASH_CR_MER_Msk\r
+#define FLASH_CR_SNB_Pos (3U)\r
+#define FLASH_CR_SNB_Msk (0xFUL << FLASH_CR_SNB_Pos) /*!< 0x00000078 */\r
+#define FLASH_CR_SNB FLASH_CR_SNB_Msk\r
+#define FLASH_CR_SNB_0 0x00000008U\r
+#define FLASH_CR_SNB_1 0x00000010U\r
+#define FLASH_CR_SNB_2 0x00000020U\r
+#define FLASH_CR_SNB_3 0x00000040U\r
+#define FLASH_CR_PSIZE_Pos (8U)\r
+#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000300 */\r
+#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk\r
+#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000100 */\r
+#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000200 */\r
+#define FLASH_CR_STRT_Pos (16U)\r
+#define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00010000 */\r
+#define FLASH_CR_STRT FLASH_CR_STRT_Msk\r
+#define FLASH_CR_EOPIE_Pos (24U)\r
+#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */\r
+#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk\r
+#define FLASH_CR_ERRIE_Pos (25U)\r
+#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */\r
+#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk\r
+#define FLASH_CR_RDERRIE_Pos (26U)\r
+#define FLASH_CR_RDERRIE_Msk (0x1UL << FLASH_CR_RDERRIE_Pos) /*!< 0x04000000 */\r
+#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk\r
+#define FLASH_CR_LOCK_Pos (31U)\r
+#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */\r
+#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTCR register ***************/\r
+#define FLASH_OPTCR_OPTLOCK_Pos (0U)\r
+#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */\r
+#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk\r
+#define FLASH_OPTCR_OPTSTRT_Pos (1U)\r
+#define FLASH_OPTCR_OPTSTRT_Msk (0x1UL << FLASH_OPTCR_OPTSTRT_Pos) /*!< 0x00000002 */\r
+#define FLASH_OPTCR_OPTSTRT FLASH_OPTCR_OPTSTRT_Msk\r
+#define FLASH_OPTCR_BOR_LEV_Pos (2U)\r
+#define FLASH_OPTCR_BOR_LEV_Msk (0x3UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x0000000C */\r
+#define FLASH_OPTCR_BOR_LEV FLASH_OPTCR_BOR_LEV_Msk\r
+#define FLASH_OPTCR_BOR_LEV_0 (0x1UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000004 */\r
+#define FLASH_OPTCR_BOR_LEV_1 (0x2UL << FLASH_OPTCR_BOR_LEV_Pos) /*!< 0x00000008 */\r
+#define FLASH_OPTCR_WWDG_SW_Pos (4U)\r
+#define FLASH_OPTCR_WWDG_SW_Msk (0x1UL << FLASH_OPTCR_WWDG_SW_Pos) /*!< 0x00000010 */\r
+#define FLASH_OPTCR_WWDG_SW FLASH_OPTCR_WWDG_SW_Msk\r
+#define FLASH_OPTCR_IWDG_SW_Pos (5U)\r
+#define FLASH_OPTCR_IWDG_SW_Msk (0x1UL << FLASH_OPTCR_IWDG_SW_Pos) /*!< 0x00000020 */\r
+#define FLASH_OPTCR_IWDG_SW FLASH_OPTCR_IWDG_SW_Msk\r
+#define FLASH_OPTCR_nRST_STOP_Pos (6U)\r
+#define FLASH_OPTCR_nRST_STOP_Msk (0x1UL << FLASH_OPTCR_nRST_STOP_Pos) /*!< 0x00000040 */\r
+#define FLASH_OPTCR_nRST_STOP FLASH_OPTCR_nRST_STOP_Msk\r
+#define FLASH_OPTCR_nRST_STDBY_Pos (7U)\r
+#define FLASH_OPTCR_nRST_STDBY_Msk (0x1UL << FLASH_OPTCR_nRST_STDBY_Pos) /*!< 0x00000080 */\r
+#define FLASH_OPTCR_nRST_STDBY FLASH_OPTCR_nRST_STDBY_Msk\r
+#define FLASH_OPTCR_RDP_Pos (8U)\r
+#define FLASH_OPTCR_RDP_Msk (0xFFUL << FLASH_OPTCR_RDP_Pos) /*!< 0x0000FF00 */\r
+#define FLASH_OPTCR_RDP FLASH_OPTCR_RDP_Msk\r
+#define FLASH_OPTCR_RDP_0 (0x01UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000100 */\r
+#define FLASH_OPTCR_RDP_1 (0x02UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000200 */\r
+#define FLASH_OPTCR_RDP_2 (0x04UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000400 */\r
+#define FLASH_OPTCR_RDP_3 (0x08UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00000800 */\r
+#define FLASH_OPTCR_RDP_4 (0x10UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00001000 */\r
+#define FLASH_OPTCR_RDP_5 (0x20UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00002000 */\r
+#define FLASH_OPTCR_RDP_6 (0x40UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00004000 */\r
+#define FLASH_OPTCR_RDP_7 (0x80UL << FLASH_OPTCR_RDP_Pos) /*!< 0x00008000 */\r
+#define FLASH_OPTCR_nWRP_Pos (16U)\r
+#define FLASH_OPTCR_nWRP_Msk (0xFFUL << FLASH_OPTCR_nWRP_Pos) /*!< 0x00FF0000 */\r
+#define FLASH_OPTCR_nWRP FLASH_OPTCR_nWRP_Msk\r
+#define FLASH_OPTCR_nWRP_0 0x00010000U\r
+#define FLASH_OPTCR_nWRP_1 0x00020000U\r
+#define FLASH_OPTCR_nWRP_2 0x00040000U\r
+#define FLASH_OPTCR_nWRP_3 0x00080000U\r
+#define FLASH_OPTCR_nWRP_4 0x00100000U\r
+#define FLASH_OPTCR_nWRP_5 0x00200000U\r
+#define FLASH_OPTCR_nWRP_6 0x00400000U\r
+#define FLASH_OPTCR_nWRP_7 0x00800000U\r
+#define FLASH_OPTCR_IWDG_STDBY_Pos (30U)\r
+#define FLASH_OPTCR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTCR_IWDG_STDBY_Pos) /*!< 0x40000000 */\r
+#define FLASH_OPTCR_IWDG_STDBY FLASH_OPTCR_IWDG_STDBY_Msk\r
+#define FLASH_OPTCR_IWDG_STOP_Pos (31U)\r
+#define FLASH_OPTCR_IWDG_STOP_Msk (0x1UL << FLASH_OPTCR_IWDG_STOP_Pos) /*!< 0x80000000 */\r
+#define FLASH_OPTCR_IWDG_STOP FLASH_OPTCR_IWDG_STOP_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTCR1 register ***************/\r
+#define FLASH_OPTCR1_BOOT_ADD0_Pos (0U)\r
+#define FLASH_OPTCR1_BOOT_ADD0_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD0_Pos) /*!< 0x0000FFFF */\r
+#define FLASH_OPTCR1_BOOT_ADD0 FLASH_OPTCR1_BOOT_ADD0_Msk\r
+#define FLASH_OPTCR1_BOOT_ADD1_Pos (16U)\r
+#define FLASH_OPTCR1_BOOT_ADD1_Msk (0xFFFFUL << FLASH_OPTCR1_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */\r
+#define FLASH_OPTCR1_BOOT_ADD1 FLASH_OPTCR1_BOOT_ADD1_Msk\r
+\r
+/******************* Bits definition for FLASH_OPTCR2 register ***************/\r
+#define FLASH_OPTCR2_PCROP_Pos (0U)\r
+#define FLASH_OPTCR2_PCROP_Msk (0xFFUL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x000000FF */\r
+#define FLASH_OPTCR2_PCROP FLASH_OPTCR2_PCROP_Msk\r
+#define FLASH_OPTCR2_PCROP_0 (0x01UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000001 */\r
+#define FLASH_OPTCR2_PCROP_1 (0x02UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000002 */\r
+#define FLASH_OPTCR2_PCROP_2 (0x04UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000004 */\r
+#define FLASH_OPTCR2_PCROP_3 (0x08UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000008 */\r
+#define FLASH_OPTCR2_PCROP_4 (0x10UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000010 */\r
+#define FLASH_OPTCR2_PCROP_5 (0x20UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000020 */\r
+#define FLASH_OPTCR2_PCROP_6 (0x40UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000040 */\r
+#define FLASH_OPTCR2_PCROP_7 (0x80UL << FLASH_OPTCR2_PCROP_Pos) /*!< 0x00000080 */\r
+#define FLASH_OPTCR2_PCROP_RDP_Pos (31U)\r
+#define FLASH_OPTCR2_PCROP_RDP_Msk (0x1UL << FLASH_OPTCR2_PCROP_RDP_Pos) /*!< 0x80000000 */\r
+#define FLASH_OPTCR2_PCROP_RDP FLASH_OPTCR2_PCROP_RDP_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Flexible Memory Controller */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for FMC_BCR1 register *******************/\r
+#define FMC_BCR1_MBKEN_Pos (0U)\r
+#define FMC_BCR1_MBKEN_Msk (0x1UL << FMC_BCR1_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR1_MBKEN FMC_BCR1_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR1_MUXEN_Pos (1U)\r
+#define FMC_BCR1_MUXEN_Msk (0x1UL << FMC_BCR1_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR1_MUXEN FMC_BCR1_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR1_MTYP_Pos (2U)\r
+#define FMC_BCR1_MTYP_Msk (0x3UL << FMC_BCR1_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR1_MTYP FMC_BCR1_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR1_MTYP_0 (0x1UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR1_MTYP_1 (0x2UL << FMC_BCR1_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR1_MWID_Pos (4U)\r
+#define FMC_BCR1_MWID_Msk (0x3UL << FMC_BCR1_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR1_MWID FMC_BCR1_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR1_MWID_0 (0x1UL << FMC_BCR1_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR1_MWID_1 (0x2UL << FMC_BCR1_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR1_FACCEN_Pos (6U)\r
+#define FMC_BCR1_FACCEN_Msk (0x1UL << FMC_BCR1_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR1_FACCEN FMC_BCR1_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR1_BURSTEN_Pos (8U)\r
+#define FMC_BCR1_BURSTEN_Msk (0x1UL << FMC_BCR1_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR1_BURSTEN FMC_BCR1_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR1_WAITPOL_Pos (9U)\r
+#define FMC_BCR1_WAITPOL_Msk (0x1UL << FMC_BCR1_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR1_WAITPOL FMC_BCR1_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR1_WRAPMOD_Pos (10U)\r
+#define FMC_BCR1_WRAPMOD_Msk (0x1UL << FMC_BCR1_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR1_WRAPMOD FMC_BCR1_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR1_WAITCFG_Pos (11U)\r
+#define FMC_BCR1_WAITCFG_Msk (0x1UL << FMC_BCR1_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR1_WAITCFG FMC_BCR1_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR1_WREN_Pos (12U)\r
+#define FMC_BCR1_WREN_Msk (0x1UL << FMC_BCR1_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR1_WREN FMC_BCR1_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR1_WAITEN_Pos (13U)\r
+#define FMC_BCR1_WAITEN_Msk (0x1UL << FMC_BCR1_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR1_WAITEN FMC_BCR1_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR1_EXTMOD_Pos (14U)\r
+#define FMC_BCR1_EXTMOD_Msk (0x1UL << FMC_BCR1_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR1_EXTMOD FMC_BCR1_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR1_ASYNCWAIT_Pos (15U)\r
+#define FMC_BCR1_ASYNCWAIT_Msk (0x1UL << FMC_BCR1_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR1_ASYNCWAIT FMC_BCR1_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR1_CPSIZE_Pos (16U)\r
+#define FMC_BCR1_CPSIZE_Msk (0x7UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR1_CPSIZE FMC_BCR1_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR1_CPSIZE_0 (0x1UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR1_CPSIZE_1 (0x2UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR1_CPSIZE_2 (0x4UL << FMC_BCR1_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR1_CBURSTRW_Pos (19U)\r
+#define FMC_BCR1_CBURSTRW_Msk (0x1UL << FMC_BCR1_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR1_CBURSTRW FMC_BCR1_CBURSTRW_Msk /*!<Write burst enable */\r
+#define FMC_BCR1_CCLKEN_Pos (20U)\r
+#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */\r
+#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */\r
+#define FMC_BCR1_WFDIS_Pos (21U)\r
+#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */\r
+#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */\r
+\r
+/****************** Bit definition for FMC_BCR2 register *******************/\r
+#define FMC_BCR2_MBKEN_Pos (0U)\r
+#define FMC_BCR2_MBKEN_Msk (0x1UL << FMC_BCR2_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR2_MBKEN FMC_BCR2_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR2_MUXEN_Pos (1U)\r
+#define FMC_BCR2_MUXEN_Msk (0x1UL << FMC_BCR2_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR2_MUXEN FMC_BCR2_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR2_MTYP_Pos (2U)\r
+#define FMC_BCR2_MTYP_Msk (0x3UL << FMC_BCR2_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR2_MTYP FMC_BCR2_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR2_MTYP_0 (0x1UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR2_MTYP_1 (0x2UL << FMC_BCR2_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR2_MWID_Pos (4U)\r
+#define FMC_BCR2_MWID_Msk (0x3UL << FMC_BCR2_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR2_MWID FMC_BCR2_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR2_MWID_0 (0x1UL << FMC_BCR2_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR2_MWID_1 (0x2UL << FMC_BCR2_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR2_FACCEN_Pos (6U)\r
+#define FMC_BCR2_FACCEN_Msk (0x1UL << FMC_BCR2_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR2_FACCEN FMC_BCR2_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR2_BURSTEN_Pos (8U)\r
+#define FMC_BCR2_BURSTEN_Msk (0x1UL << FMC_BCR2_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR2_BURSTEN FMC_BCR2_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR2_WAITPOL_Pos (9U)\r
+#define FMC_BCR2_WAITPOL_Msk (0x1UL << FMC_BCR2_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR2_WAITPOL FMC_BCR2_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR2_WRAPMOD_Pos (10U)\r
+#define FMC_BCR2_WRAPMOD_Msk (0x1UL << FMC_BCR2_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR2_WRAPMOD FMC_BCR2_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR2_WAITCFG_Pos (11U)\r
+#define FMC_BCR2_WAITCFG_Msk (0x1UL << FMC_BCR2_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR2_WAITCFG FMC_BCR2_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR2_WREN_Pos (12U)\r
+#define FMC_BCR2_WREN_Msk (0x1UL << FMC_BCR2_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR2_WREN FMC_BCR2_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR2_WAITEN_Pos (13U)\r
+#define FMC_BCR2_WAITEN_Msk (0x1UL << FMC_BCR2_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR2_WAITEN FMC_BCR2_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR2_EXTMOD_Pos (14U)\r
+#define FMC_BCR2_EXTMOD_Msk (0x1UL << FMC_BCR2_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR2_EXTMOD FMC_BCR2_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR2_ASYNCWAIT_Pos (15U)\r
+#define FMC_BCR2_ASYNCWAIT_Msk (0x1UL << FMC_BCR2_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR2_ASYNCWAIT FMC_BCR2_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR2_CPSIZE_Pos (16U)\r
+#define FMC_BCR2_CPSIZE_Msk (0x7UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR2_CPSIZE FMC_BCR2_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR2_CPSIZE_0 (0x1UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR2_CPSIZE_1 (0x2UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR2_CPSIZE_2 (0x4UL << FMC_BCR2_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR2_CBURSTRW_Pos (19U)\r
+#define FMC_BCR2_CBURSTRW_Msk (0x1UL << FMC_BCR2_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR2_CBURSTRW FMC_BCR2_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR3 register *******************/\r
+#define FMC_BCR3_MBKEN_Pos (0U)\r
+#define FMC_BCR3_MBKEN_Msk (0x1UL << FMC_BCR3_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR3_MBKEN FMC_BCR3_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR3_MUXEN_Pos (1U)\r
+#define FMC_BCR3_MUXEN_Msk (0x1UL << FMC_BCR3_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR3_MUXEN FMC_BCR3_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR3_MTYP_Pos (2U)\r
+#define FMC_BCR3_MTYP_Msk (0x3UL << FMC_BCR3_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR3_MTYP FMC_BCR3_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR3_MTYP_0 (0x1UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR3_MTYP_1 (0x2UL << FMC_BCR3_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR3_MWID_Pos (4U)\r
+#define FMC_BCR3_MWID_Msk (0x3UL << FMC_BCR3_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR3_MWID FMC_BCR3_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR3_MWID_0 (0x1UL << FMC_BCR3_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR3_MWID_1 (0x2UL << FMC_BCR3_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR3_FACCEN_Pos (6U)\r
+#define FMC_BCR3_FACCEN_Msk (0x1UL << FMC_BCR3_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR3_FACCEN FMC_BCR3_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR3_BURSTEN_Pos (8U)\r
+#define FMC_BCR3_BURSTEN_Msk (0x1UL << FMC_BCR3_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR3_BURSTEN FMC_BCR3_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR3_WAITPOL_Pos (9U)\r
+#define FMC_BCR3_WAITPOL_Msk (0x1UL << FMC_BCR3_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR3_WAITPOL FMC_BCR3_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR3_WRAPMOD_Pos (10U)\r
+#define FMC_BCR3_WRAPMOD_Msk (0x1UL << FMC_BCR3_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR3_WRAPMOD FMC_BCR3_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR3_WAITCFG_Pos (11U)\r
+#define FMC_BCR3_WAITCFG_Msk (0x1UL << FMC_BCR3_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR3_WAITCFG FMC_BCR3_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR3_WREN_Pos (12U)\r
+#define FMC_BCR3_WREN_Msk (0x1UL << FMC_BCR3_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR3_WREN FMC_BCR3_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR3_WAITEN_Pos (13U)\r
+#define FMC_BCR3_WAITEN_Msk (0x1UL << FMC_BCR3_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR3_WAITEN FMC_BCR3_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR3_EXTMOD_Pos (14U)\r
+#define FMC_BCR3_EXTMOD_Msk (0x1UL << FMC_BCR3_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR3_EXTMOD FMC_BCR3_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR3_ASYNCWAIT_Pos (15U)\r
+#define FMC_BCR3_ASYNCWAIT_Msk (0x1UL << FMC_BCR3_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR3_ASYNCWAIT FMC_BCR3_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR3_CPSIZE_Pos (16U)\r
+#define FMC_BCR3_CPSIZE_Msk (0x7UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR3_CPSIZE FMC_BCR3_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR3_CPSIZE_0 (0x1UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR3_CPSIZE_1 (0x2UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR3_CPSIZE_2 (0x4UL << FMC_BCR3_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR3_CBURSTRW_Pos (19U)\r
+#define FMC_BCR3_CBURSTRW_Msk (0x1UL << FMC_BCR3_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR3_CBURSTRW FMC_BCR3_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BCR4 register *******************/\r
+#define FMC_BCR4_MBKEN_Pos (0U)\r
+#define FMC_BCR4_MBKEN_Msk (0x1UL << FMC_BCR4_MBKEN_Pos) /*!< 0x00000001 */\r
+#define FMC_BCR4_MBKEN FMC_BCR4_MBKEN_Msk /*!<Memory bank enable bit */\r
+#define FMC_BCR4_MUXEN_Pos (1U)\r
+#define FMC_BCR4_MUXEN_Msk (0x1UL << FMC_BCR4_MUXEN_Pos) /*!< 0x00000002 */\r
+#define FMC_BCR4_MUXEN FMC_BCR4_MUXEN_Msk /*!<Address/data multiplexing enable bit */\r
+#define FMC_BCR4_MTYP_Pos (2U)\r
+#define FMC_BCR4_MTYP_Msk (0x3UL << FMC_BCR4_MTYP_Pos) /*!< 0x0000000C */\r
+#define FMC_BCR4_MTYP FMC_BCR4_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */\r
+#define FMC_BCR4_MTYP_0 (0x1UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000004 */\r
+#define FMC_BCR4_MTYP_1 (0x2UL << FMC_BCR4_MTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_BCR4_MWID_Pos (4U)\r
+#define FMC_BCR4_MWID_Msk (0x3UL << FMC_BCR4_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_BCR4_MWID FMC_BCR4_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define FMC_BCR4_MWID_0 (0x1UL << FMC_BCR4_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_BCR4_MWID_1 (0x2UL << FMC_BCR4_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_BCR4_FACCEN_Pos (6U)\r
+#define FMC_BCR4_FACCEN_Msk (0x1UL << FMC_BCR4_FACCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_BCR4_FACCEN FMC_BCR4_FACCEN_Msk /*!<Flash access enable */\r
+#define FMC_BCR4_BURSTEN_Pos (8U)\r
+#define FMC_BCR4_BURSTEN_Msk (0x1UL << FMC_BCR4_BURSTEN_Pos) /*!< 0x00000100 */\r
+#define FMC_BCR4_BURSTEN FMC_BCR4_BURSTEN_Msk /*!<Burst enable bit */\r
+#define FMC_BCR4_WAITPOL_Pos (9U)\r
+#define FMC_BCR4_WAITPOL_Msk (0x1UL << FMC_BCR4_WAITPOL_Pos) /*!< 0x00000200 */\r
+#define FMC_BCR4_WAITPOL FMC_BCR4_WAITPOL_Msk /*!<Wait signal polarity bit */\r
+#define FMC_BCR4_WRAPMOD_Pos (10U)\r
+#define FMC_BCR4_WRAPMOD_Msk (0x1UL << FMC_BCR4_WRAPMOD_Pos) /*!< 0x00000400 */\r
+#define FMC_BCR4_WRAPMOD FMC_BCR4_WRAPMOD_Msk /*!<Wrapped burst mode support */\r
+#define FMC_BCR4_WAITCFG_Pos (11U)\r
+#define FMC_BCR4_WAITCFG_Msk (0x1UL << FMC_BCR4_WAITCFG_Pos) /*!< 0x00000800 */\r
+#define FMC_BCR4_WAITCFG FMC_BCR4_WAITCFG_Msk /*!<Wait timing configuration */\r
+#define FMC_BCR4_WREN_Pos (12U)\r
+#define FMC_BCR4_WREN_Msk (0x1UL << FMC_BCR4_WREN_Pos) /*!< 0x00001000 */\r
+#define FMC_BCR4_WREN FMC_BCR4_WREN_Msk /*!<Write enable bit */\r
+#define FMC_BCR4_WAITEN_Pos (13U)\r
+#define FMC_BCR4_WAITEN_Msk (0x1UL << FMC_BCR4_WAITEN_Pos) /*!< 0x00002000 */\r
+#define FMC_BCR4_WAITEN FMC_BCR4_WAITEN_Msk /*!<Wait enable bit */\r
+#define FMC_BCR4_EXTMOD_Pos (14U)\r
+#define FMC_BCR4_EXTMOD_Msk (0x1UL << FMC_BCR4_EXTMOD_Pos) /*!< 0x00004000 */\r
+#define FMC_BCR4_EXTMOD FMC_BCR4_EXTMOD_Msk /*!<Extended mode enable */\r
+#define FMC_BCR4_ASYNCWAIT_Pos (15U)\r
+#define FMC_BCR4_ASYNCWAIT_Msk (0x1UL << FMC_BCR4_ASYNCWAIT_Pos) /*!< 0x00008000 */\r
+#define FMC_BCR4_ASYNCWAIT FMC_BCR4_ASYNCWAIT_Msk /*!<Asynchronous wait */\r
+#define FMC_BCR4_CPSIZE_Pos (16U)\r
+#define FMC_BCR4_CPSIZE_Msk (0x7UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00070000 */\r
+#define FMC_BCR4_CPSIZE FMC_BCR4_CPSIZE_Msk /*!<CRAM page size */\r
+#define FMC_BCR4_CPSIZE_0 (0x1UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00010000 */\r
+#define FMC_BCR4_CPSIZE_1 (0x2UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00020000 */\r
+#define FMC_BCR4_CPSIZE_2 (0x4UL << FMC_BCR4_CPSIZE_Pos) /*!< 0x00040000 */\r
+#define FMC_BCR4_CBURSTRW_Pos (19U)\r
+#define FMC_BCR4_CBURSTRW_Msk (0x1UL << FMC_BCR4_CBURSTRW_Pos) /*!< 0x00080000 */\r
+#define FMC_BCR4_CBURSTRW FMC_BCR4_CBURSTRW_Msk /*!<Write burst enable */\r
+\r
+/****************** Bit definition for FMC_BTR1 register ******************/\r
+#define FMC_BTR1_ADDSET_Pos (0U)\r
+#define FMC_BTR1_ADDSET_Msk (0xFUL << FMC_BTR1_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR1_ADDSET FMC_BTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR1_ADDSET_0 (0x1UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR1_ADDSET_1 (0x2UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR1_ADDSET_2 (0x4UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR1_ADDSET_3 (0x8UL << FMC_BTR1_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR1_ADDHLD_Pos (4U)\r
+#define FMC_BTR1_ADDHLD_Msk (0xFUL << FMC_BTR1_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR1_ADDHLD FMC_BTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR1_ADDHLD_0 (0x1UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR1_ADDHLD_1 (0x2UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR1_ADDHLD_2 (0x4UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR1_ADDHLD_3 (0x8UL << FMC_BTR1_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR1_DATAST_Pos (8U)\r
+#define FMC_BTR1_DATAST_Msk (0xFFUL << FMC_BTR1_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR1_DATAST FMC_BTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR1_DATAST_0 (0x01UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR1_DATAST_1 (0x02UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR1_DATAST_2 (0x04UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR1_DATAST_3 (0x08UL << FMC_BTR1_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR1_DATAST_4 (0x10UL << FMC_BTR1_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR1_DATAST_5 (0x20UL << FMC_BTR1_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR1_DATAST_6 (0x40UL << FMC_BTR1_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR1_DATAST_7 (0x80UL << FMC_BTR1_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR1_BUSTURN_Pos (16U)\r
+#define FMC_BTR1_BUSTURN_Msk (0xFUL << FMC_BTR1_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR1_BUSTURN FMC_BTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR1_BUSTURN_0 (0x1UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR1_BUSTURN_1 (0x2UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR1_BUSTURN_2 (0x4UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR1_BUSTURN_3 (0x8UL << FMC_BTR1_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR1_CLKDIV_Pos (20U)\r
+#define FMC_BTR1_CLKDIV_Msk (0xFUL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR1_CLKDIV FMC_BTR1_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR1_CLKDIV_0 (0x1UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR1_CLKDIV_1 (0x2UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR1_CLKDIV_2 (0x4UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR1_CLKDIV_3 (0x8UL << FMC_BTR1_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR1_DATLAT_Pos (24U)\r
+#define FMC_BTR1_DATLAT_Msk (0xFUL << FMC_BTR1_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR1_DATLAT FMC_BTR1_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR1_DATLAT_0 (0x1UL << FMC_BTR1_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR1_DATLAT_1 (0x2UL << FMC_BTR1_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR1_DATLAT_2 (0x4UL << FMC_BTR1_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR1_DATLAT_3 (0x8UL << FMC_BTR1_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR1_ACCMOD_Pos (28U)\r
+#define FMC_BTR1_ACCMOD_Msk (0x3UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR1_ACCMOD FMC_BTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR1_ACCMOD_0 (0x1UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR1_ACCMOD_1 (0x2UL << FMC_BTR1_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BTR2 register *******************/\r
+#define FMC_BTR2_ADDSET_Pos (0U)\r
+#define FMC_BTR2_ADDSET_Msk (0xFUL << FMC_BTR2_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR2_ADDSET FMC_BTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR2_ADDSET_0 (0x1UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR2_ADDSET_1 (0x2UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR2_ADDSET_2 (0x4UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR2_ADDSET_3 (0x8UL << FMC_BTR2_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR2_ADDHLD_Pos (4U)\r
+#define FMC_BTR2_ADDHLD_Msk (0xFUL << FMC_BTR2_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR2_ADDHLD FMC_BTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR2_ADDHLD_0 (0x1UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR2_ADDHLD_1 (0x2UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR2_ADDHLD_2 (0x4UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR2_ADDHLD_3 (0x8UL << FMC_BTR2_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR2_DATAST_Pos (8U)\r
+#define FMC_BTR2_DATAST_Msk (0xFFUL << FMC_BTR2_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR2_DATAST FMC_BTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR2_DATAST_0 (0x01UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR2_DATAST_1 (0x02UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR2_DATAST_2 (0x04UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR2_DATAST_3 (0x08UL << FMC_BTR2_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR2_DATAST_4 (0x10UL << FMC_BTR2_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR2_DATAST_5 (0x20UL << FMC_BTR2_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR2_DATAST_6 (0x40UL << FMC_BTR2_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR2_DATAST_7 (0x80UL << FMC_BTR2_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR2_BUSTURN_Pos (16U)\r
+#define FMC_BTR2_BUSTURN_Msk (0xFUL << FMC_BTR2_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR2_BUSTURN FMC_BTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR2_BUSTURN_0 (0x1UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR2_BUSTURN_1 (0x2UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR2_BUSTURN_2 (0x4UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR2_BUSTURN_3 (0x8UL << FMC_BTR2_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR2_CLKDIV_Pos (20U)\r
+#define FMC_BTR2_CLKDIV_Msk (0xFUL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR2_CLKDIV FMC_BTR2_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR2_CLKDIV_0 (0x1UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR2_CLKDIV_1 (0x2UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR2_CLKDIV_2 (0x4UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR2_CLKDIV_3 (0x8UL << FMC_BTR2_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR2_DATLAT_Pos (24U)\r
+#define FMC_BTR2_DATLAT_Msk (0xFUL << FMC_BTR2_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR2_DATLAT FMC_BTR2_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR2_DATLAT_0 (0x1UL << FMC_BTR2_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR2_DATLAT_1 (0x2UL << FMC_BTR2_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR2_DATLAT_2 (0x4UL << FMC_BTR2_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR2_DATLAT_3 (0x8UL << FMC_BTR2_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR2_ACCMOD_Pos (28U)\r
+#define FMC_BTR2_ACCMOD_Msk (0x3UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR2_ACCMOD FMC_BTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR2_ACCMOD_0 (0x1UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR2_ACCMOD_1 (0x2UL << FMC_BTR2_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/******************* Bit definition for FMC_BTR3 register *******************/\r
+#define FMC_BTR3_ADDSET_Pos (0U)\r
+#define FMC_BTR3_ADDSET_Msk (0xFUL << FMC_BTR3_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR3_ADDSET FMC_BTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR3_ADDSET_0 (0x1UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR3_ADDSET_1 (0x2UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR3_ADDSET_2 (0x4UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR3_ADDSET_3 (0x8UL << FMC_BTR3_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR3_ADDHLD_Pos (4U)\r
+#define FMC_BTR3_ADDHLD_Msk (0xFUL << FMC_BTR3_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR3_ADDHLD FMC_BTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR3_ADDHLD_0 (0x1UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR3_ADDHLD_1 (0x2UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR3_ADDHLD_2 (0x4UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR3_ADDHLD_3 (0x8UL << FMC_BTR3_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR3_DATAST_Pos (8U)\r
+#define FMC_BTR3_DATAST_Msk (0xFFUL << FMC_BTR3_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR3_DATAST FMC_BTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR3_DATAST_0 (0x01UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR3_DATAST_1 (0x02UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR3_DATAST_2 (0x04UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR3_DATAST_3 (0x08UL << FMC_BTR3_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR3_DATAST_4 (0x10UL << FMC_BTR3_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR3_DATAST_5 (0x20UL << FMC_BTR3_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR3_DATAST_6 (0x40UL << FMC_BTR3_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR3_DATAST_7 (0x80UL << FMC_BTR3_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR3_BUSTURN_Pos (16U)\r
+#define FMC_BTR3_BUSTURN_Msk (0xFUL << FMC_BTR3_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR3_BUSTURN FMC_BTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR3_BUSTURN_0 (0x1UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR3_BUSTURN_1 (0x2UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR3_BUSTURN_2 (0x4UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR3_BUSTURN_3 (0x8UL << FMC_BTR3_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR3_CLKDIV_Pos (20U)\r
+#define FMC_BTR3_CLKDIV_Msk (0xFUL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR3_CLKDIV FMC_BTR3_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR3_CLKDIV_0 (0x1UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR3_CLKDIV_1 (0x2UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR3_CLKDIV_2 (0x4UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR3_CLKDIV_3 (0x8UL << FMC_BTR3_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR3_DATLAT_Pos (24U)\r
+#define FMC_BTR3_DATLAT_Msk (0xFUL << FMC_BTR3_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR3_DATLAT FMC_BTR3_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR3_DATLAT_0 (0x1UL << FMC_BTR3_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR3_DATLAT_1 (0x2UL << FMC_BTR3_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR3_DATLAT_2 (0x4UL << FMC_BTR3_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR3_DATLAT_3 (0x8UL << FMC_BTR3_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR3_ACCMOD_Pos (28U)\r
+#define FMC_BTR3_ACCMOD_Msk (0x3UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR3_ACCMOD FMC_BTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR3_ACCMOD_0 (0x1UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR3_ACCMOD_1 (0x2UL << FMC_BTR3_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BTR4 register *******************/\r
+#define FMC_BTR4_ADDSET_Pos (0U)\r
+#define FMC_BTR4_ADDSET_Msk (0xFUL << FMC_BTR4_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BTR4_ADDSET FMC_BTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BTR4_ADDSET_0 (0x1UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BTR4_ADDSET_1 (0x2UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BTR4_ADDSET_2 (0x4UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BTR4_ADDSET_3 (0x8UL << FMC_BTR4_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BTR4_ADDHLD_Pos (4U)\r
+#define FMC_BTR4_ADDHLD_Msk (0xFUL << FMC_BTR4_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BTR4_ADDHLD FMC_BTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BTR4_ADDHLD_0 (0x1UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BTR4_ADDHLD_1 (0x2UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BTR4_ADDHLD_2 (0x4UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BTR4_ADDHLD_3 (0x8UL << FMC_BTR4_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BTR4_DATAST_Pos (8U)\r
+#define FMC_BTR4_DATAST_Msk (0xFFUL << FMC_BTR4_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BTR4_DATAST FMC_BTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BTR4_DATAST_0 (0x01UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BTR4_DATAST_1 (0x02UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BTR4_DATAST_2 (0x04UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BTR4_DATAST_3 (0x08UL << FMC_BTR4_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BTR4_DATAST_4 (0x10UL << FMC_BTR4_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BTR4_DATAST_5 (0x20UL << FMC_BTR4_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BTR4_DATAST_6 (0x40UL << FMC_BTR4_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BTR4_DATAST_7 (0x80UL << FMC_BTR4_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BTR4_BUSTURN_Pos (16U)\r
+#define FMC_BTR4_BUSTURN_Msk (0xFUL << FMC_BTR4_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BTR4_BUSTURN FMC_BTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BTR4_BUSTURN_0 (0x1UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BTR4_BUSTURN_1 (0x2UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BTR4_BUSTURN_2 (0x4UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BTR4_BUSTURN_3 (0x8UL << FMC_BTR4_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BTR4_CLKDIV_Pos (20U)\r
+#define FMC_BTR4_CLKDIV_Msk (0xFUL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00F00000 */\r
+#define FMC_BTR4_CLKDIV FMC_BTR4_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define FMC_BTR4_CLKDIV_0 (0x1UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00100000 */\r
+#define FMC_BTR4_CLKDIV_1 (0x2UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00200000 */\r
+#define FMC_BTR4_CLKDIV_2 (0x4UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00400000 */\r
+#define FMC_BTR4_CLKDIV_3 (0x8UL << FMC_BTR4_CLKDIV_Pos) /*!< 0x00800000 */\r
+#define FMC_BTR4_DATLAT_Pos (24U)\r
+#define FMC_BTR4_DATLAT_Msk (0xFUL << FMC_BTR4_DATLAT_Pos) /*!< 0x0F000000 */\r
+#define FMC_BTR4_DATLAT FMC_BTR4_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */\r
+#define FMC_BTR4_DATLAT_0 (0x1UL << FMC_BTR4_DATLAT_Pos) /*!< 0x01000000 */\r
+#define FMC_BTR4_DATLAT_1 (0x2UL << FMC_BTR4_DATLAT_Pos) /*!< 0x02000000 */\r
+#define FMC_BTR4_DATLAT_2 (0x4UL << FMC_BTR4_DATLAT_Pos) /*!< 0x04000000 */\r
+#define FMC_BTR4_DATLAT_3 (0x8UL << FMC_BTR4_DATLAT_Pos) /*!< 0x08000000 */\r
+#define FMC_BTR4_ACCMOD_Pos (28U)\r
+#define FMC_BTR4_ACCMOD_Msk (0x3UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BTR4_ACCMOD FMC_BTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BTR4_ACCMOD_0 (0x1UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BTR4_ACCMOD_1 (0x2UL << FMC_BTR4_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR1 register ******************/\r
+#define FMC_BWTR1_ADDSET_Pos (0U)\r
+#define FMC_BWTR1_ADDSET_Msk (0xFUL << FMC_BWTR1_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR1_ADDSET FMC_BWTR1_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR1_ADDSET_0 (0x1UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR1_ADDSET_1 (0x2UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR1_ADDSET_2 (0x4UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR1_ADDSET_3 (0x8UL << FMC_BWTR1_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR1_ADDHLD_Pos (4U)\r
+#define FMC_BWTR1_ADDHLD_Msk (0xFUL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR1_ADDHLD FMC_BWTR1_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR1_ADDHLD_0 (0x1UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR1_ADDHLD_1 (0x2UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR1_ADDHLD_2 (0x4UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR1_ADDHLD_3 (0x8UL << FMC_BWTR1_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR1_DATAST_Pos (8U)\r
+#define FMC_BWTR1_DATAST_Msk (0xFFUL << FMC_BWTR1_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR1_DATAST FMC_BWTR1_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR1_DATAST_0 (0x01UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR1_DATAST_1 (0x02UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR1_DATAST_2 (0x04UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR1_DATAST_3 (0x08UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR1_DATAST_4 (0x10UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR1_DATAST_5 (0x20UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR1_DATAST_6 (0x40UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR1_DATAST_7 (0x80UL << FMC_BWTR1_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR1_BUSTURN_Pos (16U)\r
+#define FMC_BWTR1_BUSTURN_Msk (0xFUL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR1_BUSTURN FMC_BWTR1_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR1_BUSTURN_0 (0x1UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR1_BUSTURN_1 (0x2UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR1_BUSTURN_2 (0x4UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR1_BUSTURN_3 (0x8UL << FMC_BWTR1_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR1_ACCMOD_Pos (28U)\r
+#define FMC_BWTR1_ACCMOD_Msk (0x3UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR1_ACCMOD FMC_BWTR1_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR1_ACCMOD_0 (0x1UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR1_ACCMOD_1 (0x2UL << FMC_BWTR1_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR2 register ******************/\r
+#define FMC_BWTR2_ADDSET_Pos (0U)\r
+#define FMC_BWTR2_ADDSET_Msk (0xFUL << FMC_BWTR2_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR2_ADDSET FMC_BWTR2_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR2_ADDSET_0 (0x1UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR2_ADDSET_1 (0x2UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR2_ADDSET_2 (0x4UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR2_ADDSET_3 (0x8UL << FMC_BWTR2_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR2_ADDHLD_Pos (4U)\r
+#define FMC_BWTR2_ADDHLD_Msk (0xFUL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR2_ADDHLD FMC_BWTR2_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR2_ADDHLD_0 (0x1UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR2_ADDHLD_1 (0x2UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR2_ADDHLD_2 (0x4UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR2_ADDHLD_3 (0x8UL << FMC_BWTR2_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR2_DATAST_Pos (8U)\r
+#define FMC_BWTR2_DATAST_Msk (0xFFUL << FMC_BWTR2_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR2_DATAST FMC_BWTR2_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR2_DATAST_0 (0x01UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR2_DATAST_1 (0x02UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR2_DATAST_2 (0x04UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR2_DATAST_3 (0x08UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR2_DATAST_4 (0x10UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR2_DATAST_5 (0x20UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR2_DATAST_6 (0x40UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR2_DATAST_7 (0x80UL << FMC_BWTR2_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR2_BUSTURN_Pos (16U)\r
+#define FMC_BWTR2_BUSTURN_Msk (0xFUL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR2_BUSTURN FMC_BWTR2_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR2_BUSTURN_0 (0x1UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR2_BUSTURN_1 (0x2UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR2_BUSTURN_2 (0x4UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR2_BUSTURN_3 (0x8UL << FMC_BWTR2_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR2_ACCMOD_Pos (28U)\r
+#define FMC_BWTR2_ACCMOD_Msk (0x3UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR2_ACCMOD FMC_BWTR2_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR2_ACCMOD_0 (0x1UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR2_ACCMOD_1 (0x2UL << FMC_BWTR2_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR3 register ******************/\r
+#define FMC_BWTR3_ADDSET_Pos (0U)\r
+#define FMC_BWTR3_ADDSET_Msk (0xFUL << FMC_BWTR3_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR3_ADDSET FMC_BWTR3_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR3_ADDSET_0 (0x1UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR3_ADDSET_1 (0x2UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR3_ADDSET_2 (0x4UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR3_ADDSET_3 (0x8UL << FMC_BWTR3_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR3_ADDHLD_Pos (4U)\r
+#define FMC_BWTR3_ADDHLD_Msk (0xFUL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR3_ADDHLD FMC_BWTR3_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR3_ADDHLD_0 (0x1UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR3_ADDHLD_1 (0x2UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR3_ADDHLD_2 (0x4UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR3_ADDHLD_3 (0x8UL << FMC_BWTR3_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR3_DATAST_Pos (8U)\r
+#define FMC_BWTR3_DATAST_Msk (0xFFUL << FMC_BWTR3_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR3_DATAST FMC_BWTR3_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR3_DATAST_0 (0x01UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR3_DATAST_1 (0x02UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR3_DATAST_2 (0x04UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR3_DATAST_3 (0x08UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR3_DATAST_4 (0x10UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR3_DATAST_5 (0x20UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR3_DATAST_6 (0x40UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR3_DATAST_7 (0x80UL << FMC_BWTR3_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR3_BUSTURN_Pos (16U)\r
+#define FMC_BWTR3_BUSTURN_Msk (0xFUL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR3_BUSTURN FMC_BWTR3_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR3_BUSTURN_0 (0x1UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR3_BUSTURN_1 (0x2UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR3_BUSTURN_2 (0x4UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR3_BUSTURN_3 (0x8UL << FMC_BWTR3_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR3_ACCMOD_Pos (28U)\r
+#define FMC_BWTR3_ACCMOD_Msk (0x3UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR3_ACCMOD FMC_BWTR3_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR3_ACCMOD_0 (0x1UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR3_ACCMOD_1 (0x2UL << FMC_BWTR3_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_BWTR4 register ******************/\r
+#define FMC_BWTR4_ADDSET_Pos (0U)\r
+#define FMC_BWTR4_ADDSET_Msk (0xFUL << FMC_BWTR4_ADDSET_Pos) /*!< 0x0000000F */\r
+#define FMC_BWTR4_ADDSET FMC_BWTR4_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define FMC_BWTR4_ADDSET_0 (0x1UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000001 */\r
+#define FMC_BWTR4_ADDSET_1 (0x2UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000002 */\r
+#define FMC_BWTR4_ADDSET_2 (0x4UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000004 */\r
+#define FMC_BWTR4_ADDSET_3 (0x8UL << FMC_BWTR4_ADDSET_Pos) /*!< 0x00000008 */\r
+#define FMC_BWTR4_ADDHLD_Pos (4U)\r
+#define FMC_BWTR4_ADDHLD_Msk (0xFUL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x000000F0 */\r
+#define FMC_BWTR4_ADDHLD FMC_BWTR4_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define FMC_BWTR4_ADDHLD_0 (0x1UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000010 */\r
+#define FMC_BWTR4_ADDHLD_1 (0x2UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000020 */\r
+#define FMC_BWTR4_ADDHLD_2 (0x4UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000040 */\r
+#define FMC_BWTR4_ADDHLD_3 (0x8UL << FMC_BWTR4_ADDHLD_Pos) /*!< 0x00000080 */\r
+#define FMC_BWTR4_DATAST_Pos (8U)\r
+#define FMC_BWTR4_DATAST_Msk (0xFFUL << FMC_BWTR4_DATAST_Pos) /*!< 0x0000FF00 */\r
+#define FMC_BWTR4_DATAST FMC_BWTR4_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define FMC_BWTR4_DATAST_0 (0x01UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000100 */\r
+#define FMC_BWTR4_DATAST_1 (0x02UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000200 */\r
+#define FMC_BWTR4_DATAST_2 (0x04UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000400 */\r
+#define FMC_BWTR4_DATAST_3 (0x08UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00000800 */\r
+#define FMC_BWTR4_DATAST_4 (0x10UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00001000 */\r
+#define FMC_BWTR4_DATAST_5 (0x20UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00002000 */\r
+#define FMC_BWTR4_DATAST_6 (0x40UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00004000 */\r
+#define FMC_BWTR4_DATAST_7 (0x80UL << FMC_BWTR4_DATAST_Pos) /*!< 0x00008000 */\r
+#define FMC_BWTR4_BUSTURN_Pos (16U)\r
+#define FMC_BWTR4_BUSTURN_Msk (0xFUL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x000F0000 */\r
+#define FMC_BWTR4_BUSTURN FMC_BWTR4_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define FMC_BWTR4_BUSTURN_0 (0x1UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00010000 */\r
+#define FMC_BWTR4_BUSTURN_1 (0x2UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00020000 */\r
+#define FMC_BWTR4_BUSTURN_2 (0x4UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00040000 */\r
+#define FMC_BWTR4_BUSTURN_3 (0x8UL << FMC_BWTR4_BUSTURN_Pos) /*!< 0x00080000 */\r
+#define FMC_BWTR4_ACCMOD_Pos (28U)\r
+#define FMC_BWTR4_ACCMOD_Msk (0x3UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x30000000 */\r
+#define FMC_BWTR4_ACCMOD FMC_BWTR4_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define FMC_BWTR4_ACCMOD_0 (0x1UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x10000000 */\r
+#define FMC_BWTR4_ACCMOD_1 (0x2UL << FMC_BWTR4_ACCMOD_Pos) /*!< 0x20000000 */\r
+\r
+/****************** Bit definition for FMC_PCR register *******************/\r
+#define FMC_PCR_PWAITEN_Pos (1U)\r
+#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */\r
+#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */\r
+#define FMC_PCR_PBKEN_Pos (2U)\r
+#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */\r
+#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define FMC_PCR_PTYP_Pos (3U)\r
+#define FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) /*!< 0x00000008 */\r
+#define FMC_PCR_PTYP FMC_PCR_PTYP_Msk /*!<Memory type */\r
+#define FMC_PCR_PWID_Pos (4U)\r
+#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */\r
+#define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */\r
+#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */\r
+#define FMC_PCR_ECCEN_Pos (6U)\r
+#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */\r
+#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */\r
+#define FMC_PCR_TCLR_Pos (9U)\r
+#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */\r
+#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */\r
+#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */\r
+#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */\r
+#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */\r
+#define FMC_PCR_TAR_Pos (13U)\r
+#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */\r
+#define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */\r
+#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */\r
+#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */\r
+#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */\r
+#define FMC_PCR_ECCPS_Pos (17U)\r
+#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */\r
+#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */\r
+#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */\r
+#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */\r
+\r
+/******************* Bit definition for FMC_SR register *******************/\r
+#define FMC_SR_IRS_Pos (0U)\r
+#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */\r
+#define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */\r
+#define FMC_SR_ILS_Pos (1U)\r
+#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */\r
+#define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */\r
+#define FMC_SR_IFS_Pos (2U)\r
+#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */\r
+#define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */\r
+#define FMC_SR_IREN_Pos (3U)\r
+#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */\r
+#define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */\r
+#define FMC_SR_ILEN_Pos (4U)\r
+#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */\r
+#define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */\r
+#define FMC_SR_IFEN_Pos (5U)\r
+#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */\r
+#define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */\r
+#define FMC_SR_FEMPT_Pos (6U)\r
+#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */\r
+#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */\r
+\r
+/****************** Bit definition for FMC_PMEM register ******************/\r
+#define FMC_PMEM_MEMSET3_Pos (0U)\r
+#define FMC_PMEM_MEMSET3_Msk (0xFFUL << FMC_PMEM_MEMSET3_Pos) /*!< 0x000000FF */\r
+#define FMC_PMEM_MEMSET3 FMC_PMEM_MEMSET3_Msk /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define FMC_PMEM_MEMSET3_0 (0x01UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000001 */\r
+#define FMC_PMEM_MEMSET3_1 (0x02UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000002 */\r
+#define FMC_PMEM_MEMSET3_2 (0x04UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000004 */\r
+#define FMC_PMEM_MEMSET3_3 (0x08UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000008 */\r
+#define FMC_PMEM_MEMSET3_4 (0x10UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000010 */\r
+#define FMC_PMEM_MEMSET3_5 (0x20UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000020 */\r
+#define FMC_PMEM_MEMSET3_6 (0x40UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000040 */\r
+#define FMC_PMEM_MEMSET3_7 (0x80UL << FMC_PMEM_MEMSET3_Pos) /*!< 0x00000080 */\r
+#define FMC_PMEM_MEMWAIT3_Pos (8U)\r
+#define FMC_PMEM_MEMWAIT3_Msk (0xFFUL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PMEM_MEMWAIT3 FMC_PMEM_MEMWAIT3_Msk /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define FMC_PMEM_MEMWAIT3_0 (0x01UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000100 */\r
+#define FMC_PMEM_MEMWAIT3_1 (0x02UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000200 */\r
+#define FMC_PMEM_MEMWAIT3_2 (0x04UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000400 */\r
+#define FMC_PMEM_MEMWAIT3_3 (0x08UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00000800 */\r
+#define FMC_PMEM_MEMWAIT3_4 (0x10UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00001000 */\r
+#define FMC_PMEM_MEMWAIT3_5 (0x20UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00002000 */\r
+#define FMC_PMEM_MEMWAIT3_6 (0x40UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00004000 */\r
+#define FMC_PMEM_MEMWAIT3_7 (0x80UL << FMC_PMEM_MEMWAIT3_Pos) /*!< 0x00008000 */\r
+#define FMC_PMEM_MEMHOLD3_Pos (16U)\r
+#define FMC_PMEM_MEMHOLD3_Msk (0xFFUL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PMEM_MEMHOLD3 FMC_PMEM_MEMHOLD3_Msk /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define FMC_PMEM_MEMHOLD3_0 (0x01UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00010000 */\r
+#define FMC_PMEM_MEMHOLD3_1 (0x02UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00020000 */\r
+#define FMC_PMEM_MEMHOLD3_2 (0x04UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00040000 */\r
+#define FMC_PMEM_MEMHOLD3_3 (0x08UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00080000 */\r
+#define FMC_PMEM_MEMHOLD3_4 (0x10UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00100000 */\r
+#define FMC_PMEM_MEMHOLD3_5 (0x20UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00200000 */\r
+#define FMC_PMEM_MEMHOLD3_6 (0x40UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00400000 */\r
+#define FMC_PMEM_MEMHOLD3_7 (0x80UL << FMC_PMEM_MEMHOLD3_Pos) /*!< 0x00800000 */\r
+#define FMC_PMEM_MEMHIZ3_Pos (24U)\r
+#define FMC_PMEM_MEMHIZ3_Msk (0xFFUL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0xFF000000 */\r
+#define FMC_PMEM_MEMHIZ3 FMC_PMEM_MEMHIZ3_Msk /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define FMC_PMEM_MEMHIZ3_0 (0x01UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x01000000 */\r
+#define FMC_PMEM_MEMHIZ3_1 (0x02UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x02000000 */\r
+#define FMC_PMEM_MEMHIZ3_2 (0x04UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x04000000 */\r
+#define FMC_PMEM_MEMHIZ3_3 (0x08UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x08000000 */\r
+#define FMC_PMEM_MEMHIZ3_4 (0x10UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x10000000 */\r
+#define FMC_PMEM_MEMHIZ3_5 (0x20UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x20000000 */\r
+#define FMC_PMEM_MEMHIZ3_6 (0x40UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x40000000 */\r
+#define FMC_PMEM_MEMHIZ3_7 (0x80UL << FMC_PMEM_MEMHIZ3_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_PATT register ******************/\r
+#define FMC_PATT_ATTSET3_Pos (0U)\r
+#define FMC_PATT_ATTSET3_Msk (0xFFUL << FMC_PATT_ATTSET3_Pos) /*!< 0x000000FF */\r
+#define FMC_PATT_ATTSET3 FMC_PATT_ATTSET3_Msk /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define FMC_PATT_ATTSET3_0 (0x01UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000001 */\r
+#define FMC_PATT_ATTSET3_1 (0x02UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000002 */\r
+#define FMC_PATT_ATTSET3_2 (0x04UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000004 */\r
+#define FMC_PATT_ATTSET3_3 (0x08UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000008 */\r
+#define FMC_PATT_ATTSET3_4 (0x10UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000010 */\r
+#define FMC_PATT_ATTSET3_5 (0x20UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000020 */\r
+#define FMC_PATT_ATTSET3_6 (0x40UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000040 */\r
+#define FMC_PATT_ATTSET3_7 (0x80UL << FMC_PATT_ATTSET3_Pos) /*!< 0x00000080 */\r
+#define FMC_PATT_ATTWAIT3_Pos (8U)\r
+#define FMC_PATT_ATTWAIT3_Msk (0xFFUL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x0000FF00 */\r
+#define FMC_PATT_ATTWAIT3 FMC_PATT_ATTWAIT3_Msk /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define FMC_PATT_ATTWAIT3_0 (0x01UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000100 */\r
+#define FMC_PATT_ATTWAIT3_1 (0x02UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000200 */\r
+#define FMC_PATT_ATTWAIT3_2 (0x04UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000400 */\r
+#define FMC_PATT_ATTWAIT3_3 (0x08UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00000800 */\r
+#define FMC_PATT_ATTWAIT3_4 (0x10UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00001000 */\r
+#define FMC_PATT_ATTWAIT3_5 (0x20UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00002000 */\r
+#define FMC_PATT_ATTWAIT3_6 (0x40UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00004000 */\r
+#define FMC_PATT_ATTWAIT3_7 (0x80UL << FMC_PATT_ATTWAIT3_Pos) /*!< 0x00008000 */\r
+#define FMC_PATT_ATTHOLD3_Pos (16U)\r
+#define FMC_PATT_ATTHOLD3_Msk (0xFFUL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00FF0000 */\r
+#define FMC_PATT_ATTHOLD3 FMC_PATT_ATTHOLD3_Msk /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define FMC_PATT_ATTHOLD3_0 (0x01UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00010000 */\r
+#define FMC_PATT_ATTHOLD3_1 (0x02UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00020000 */\r
+#define FMC_PATT_ATTHOLD3_2 (0x04UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00040000 */\r
+#define FMC_PATT_ATTHOLD3_3 (0x08UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00080000 */\r
+#define FMC_PATT_ATTHOLD3_4 (0x10UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00100000 */\r
+#define FMC_PATT_ATTHOLD3_5 (0x20UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00200000 */\r
+#define FMC_PATT_ATTHOLD3_6 (0x40UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00400000 */\r
+#define FMC_PATT_ATTHOLD3_7 (0x80UL << FMC_PATT_ATTHOLD3_Pos) /*!< 0x00800000 */\r
+#define FMC_PATT_ATTHIZ3_Pos (24U)\r
+#define FMC_PATT_ATTHIZ3_Msk (0xFFUL << FMC_PATT_ATTHIZ3_Pos) /*!< 0xFF000000 */\r
+#define FMC_PATT_ATTHIZ3 FMC_PATT_ATTHIZ3_Msk /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define FMC_PATT_ATTHIZ3_0 (0x01UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x01000000 */\r
+#define FMC_PATT_ATTHIZ3_1 (0x02UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x02000000 */\r
+#define FMC_PATT_ATTHIZ3_2 (0x04UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x04000000 */\r
+#define FMC_PATT_ATTHIZ3_3 (0x08UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x08000000 */\r
+#define FMC_PATT_ATTHIZ3_4 (0x10UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x10000000 */\r
+#define FMC_PATT_ATTHIZ3_5 (0x20UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x20000000 */\r
+#define FMC_PATT_ATTHIZ3_6 (0x40UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x40000000 */\r
+#define FMC_PATT_ATTHIZ3_7 (0x80UL << FMC_PATT_ATTHIZ3_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for FMC_ECCR register ******************/\r
+#define FMC_ECCR_ECC3_Pos (0U)\r
+#define FMC_ECCR_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR_ECC3_Pos) /*!< 0xFFFFFFFF */\r
+#define FMC_ECCR_ECC3 FMC_ECCR_ECC3_Msk /*!<ECC result */\r
+\r
+/****************** Bit definition for FMC_SDCR1 register ******************/\r
+#define FMC_SDCR1_NC_Pos (0U)\r
+#define FMC_SDCR1_NC_Msk (0x3UL << FMC_SDCR1_NC_Pos) /*!< 0x00000003 */\r
+#define FMC_SDCR1_NC FMC_SDCR1_NC_Msk /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR1_NC_0 (0x1UL << FMC_SDCR1_NC_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCR1_NC_1 (0x2UL << FMC_SDCR1_NC_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCR1_NR_Pos (2U)\r
+#define FMC_SDCR1_NR_Msk (0x3UL << FMC_SDCR1_NR_Pos) /*!< 0x0000000C */\r
+#define FMC_SDCR1_NR FMC_SDCR1_NR_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_NR_0 (0x1UL << FMC_SDCR1_NR_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCR1_NR_1 (0x2UL << FMC_SDCR1_NR_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCR1_MWID_Pos (4U)\r
+#define FMC_SDCR1_MWID_Msk (0x3UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_SDCR1_MWID FMC_SDCR1_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR1_MWID_0 (0x1UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCR1_MWID_1 (0x2UL << FMC_SDCR1_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCR1_NB_Pos (6U)\r
+#define FMC_SDCR1_NB_Msk (0x1UL << FMC_SDCR1_NB_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCR1_NB FMC_SDCR1_NB_Msk /*!<Number of internal bank */\r
+#define FMC_SDCR1_CAS_Pos (7U)\r
+#define FMC_SDCR1_CAS_Msk (0x3UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000180 */\r
+#define FMC_SDCR1_CAS FMC_SDCR1_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR1_CAS_0 (0x1UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCR1_CAS_1 (0x2UL << FMC_SDCR1_CAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCR1_WP_Pos (9U)\r
+#define FMC_SDCR1_WP_Msk (0x1UL << FMC_SDCR1_WP_Pos) /*!< 0x00000200 */\r
+#define FMC_SDCR1_WP FMC_SDCR1_WP_Msk /*!<Write protection */\r
+#define FMC_SDCR1_SDCLK_Pos (10U)\r
+#define FMC_SDCR1_SDCLK_Msk (0x3UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000C00 */\r
+#define FMC_SDCR1_SDCLK FMC_SDCR1_SDCLK_Msk /*!<SDRAM clock configuration */\r
+#define FMC_SDCR1_SDCLK_0 (0x1UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000400 */\r
+#define FMC_SDCR1_SDCLK_1 (0x2UL << FMC_SDCR1_SDCLK_Pos) /*!< 0x00000800 */\r
+#define FMC_SDCR1_RBURST_Pos (12U)\r
+#define FMC_SDCR1_RBURST_Msk (0x1UL << FMC_SDCR1_RBURST_Pos) /*!< 0x00001000 */\r
+#define FMC_SDCR1_RBURST FMC_SDCR1_RBURST_Msk /*!<Read burst */\r
+#define FMC_SDCR1_RPIPE_Pos (13U)\r
+#define FMC_SDCR1_RPIPE_Msk (0x3UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00006000 */\r
+#define FMC_SDCR1_RPIPE FMC_SDCR1_RPIPE_Msk /*!<Write protection */\r
+#define FMC_SDCR1_RPIPE_0 (0x1UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00002000 */\r
+#define FMC_SDCR1_RPIPE_1 (0x2UL << FMC_SDCR1_RPIPE_Pos) /*!< 0x00004000 */\r
+\r
+/****************** Bit definition for FMC_SDCR2 register ******************/\r
+#define FMC_SDCR2_NC_Pos (0U)\r
+#define FMC_SDCR2_NC_Msk (0x3UL << FMC_SDCR2_NC_Pos) /*!< 0x00000003 */\r
+#define FMC_SDCR2_NC FMC_SDCR2_NC_Msk /*!<NC[1:0] bits (Number of column bits) */\r
+#define FMC_SDCR2_NC_0 (0x1UL << FMC_SDCR2_NC_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCR2_NC_1 (0x2UL << FMC_SDCR2_NC_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCR2_NR_Pos (2U)\r
+#define FMC_SDCR2_NR_Msk (0x3UL << FMC_SDCR2_NR_Pos) /*!< 0x0000000C */\r
+#define FMC_SDCR2_NR FMC_SDCR2_NR_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_NR_0 (0x1UL << FMC_SDCR2_NR_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCR2_NR_1 (0x2UL << FMC_SDCR2_NR_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCR2_MWID_Pos (4U)\r
+#define FMC_SDCR2_MWID_Msk (0x3UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000030 */\r
+#define FMC_SDCR2_MWID FMC_SDCR2_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */\r
+#define FMC_SDCR2_MWID_0 (0x1UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCR2_MWID_1 (0x2UL << FMC_SDCR2_MWID_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCR2_NB_Pos (6U)\r
+#define FMC_SDCR2_NB_Msk (0x1UL << FMC_SDCR2_NB_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCR2_NB FMC_SDCR2_NB_Msk /*!<Number of internal bank */\r
+#define FMC_SDCR2_CAS_Pos (7U)\r
+#define FMC_SDCR2_CAS_Msk (0x3UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000180 */\r
+#define FMC_SDCR2_CAS FMC_SDCR2_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */\r
+#define FMC_SDCR2_CAS_0 (0x1UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCR2_CAS_1 (0x2UL << FMC_SDCR2_CAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCR2_WP_Pos (9U)\r
+#define FMC_SDCR2_WP_Msk (0x1UL << FMC_SDCR2_WP_Pos) /*!< 0x00000200 */\r
+#define FMC_SDCR2_WP FMC_SDCR2_WP_Msk /*!<Write protection */\r
+#define FMC_SDCR2_SDCLK_Pos (10U)\r
+#define FMC_SDCR2_SDCLK_Msk (0x3UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000C00 */\r
+#define FMC_SDCR2_SDCLK FMC_SDCR2_SDCLK_Msk /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define FMC_SDCR2_SDCLK_0 (0x1UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000400 */\r
+#define FMC_SDCR2_SDCLK_1 (0x2UL << FMC_SDCR2_SDCLK_Pos) /*!< 0x00000800 */\r
+#define FMC_SDCR2_RBURST_Pos (12U)\r
+#define FMC_SDCR2_RBURST_Msk (0x1UL << FMC_SDCR2_RBURST_Pos) /*!< 0x00001000 */\r
+#define FMC_SDCR2_RBURST FMC_SDCR2_RBURST_Msk /*!<Read burst */\r
+#define FMC_SDCR2_RPIPE_Pos (13U)\r
+#define FMC_SDCR2_RPIPE_Msk (0x3UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00006000 */\r
+#define FMC_SDCR2_RPIPE FMC_SDCR2_RPIPE_Msk /*!<RPIPE[1:0](Read pipe) */\r
+#define FMC_SDCR2_RPIPE_0 (0x1UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00002000 */\r
+#define FMC_SDCR2_RPIPE_1 (0x2UL << FMC_SDCR2_RPIPE_Pos) /*!< 0x00004000 */\r
+\r
+/****************** Bit definition for FMC_SDTR1 register ******************/\r
+#define FMC_SDTR1_TMRD_Pos (0U)\r
+#define FMC_SDTR1_TMRD_Msk (0xFUL << FMC_SDTR1_TMRD_Pos) /*!< 0x0000000F */\r
+#define FMC_SDTR1_TMRD FMC_SDTR1_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR1_TMRD_0 (0x1UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000001 */\r
+#define FMC_SDTR1_TMRD_1 (0x2UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000002 */\r
+#define FMC_SDTR1_TMRD_2 (0x4UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000004 */\r
+#define FMC_SDTR1_TMRD_3 (0x8UL << FMC_SDTR1_TMRD_Pos) /*!< 0x00000008 */\r
+#define FMC_SDTR1_TXSR_Pos (4U)\r
+#define FMC_SDTR1_TXSR_Msk (0xFUL << FMC_SDTR1_TXSR_Pos) /*!< 0x000000F0 */\r
+#define FMC_SDTR1_TXSR FMC_SDTR1_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR1_TXSR_0 (0x1UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000010 */\r
+#define FMC_SDTR1_TXSR_1 (0x2UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000020 */\r
+#define FMC_SDTR1_TXSR_2 (0x4UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000040 */\r
+#define FMC_SDTR1_TXSR_3 (0x8UL << FMC_SDTR1_TXSR_Pos) /*!< 0x00000080 */\r
+#define FMC_SDTR1_TRAS_Pos (8U)\r
+#define FMC_SDTR1_TRAS_Msk (0xFUL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000F00 */\r
+#define FMC_SDTR1_TRAS FMC_SDTR1_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR1_TRAS_0 (0x1UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDTR1_TRAS_1 (0x2UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000200 */\r
+#define FMC_SDTR1_TRAS_2 (0x4UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000400 */\r
+#define FMC_SDTR1_TRAS_3 (0x8UL << FMC_SDTR1_TRAS_Pos) /*!< 0x00000800 */\r
+#define FMC_SDTR1_TRC_Pos (12U)\r
+#define FMC_SDTR1_TRC_Msk (0xFUL << FMC_SDTR1_TRC_Pos) /*!< 0x0000F000 */\r
+#define FMC_SDTR1_TRC FMC_SDTR1_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR1_TRC_0 (0x1UL << FMC_SDTR1_TRC_Pos) /*!< 0x00001000 */\r
+#define FMC_SDTR1_TRC_1 (0x2UL << FMC_SDTR1_TRC_Pos) /*!< 0x00002000 */\r
+#define FMC_SDTR1_TRC_2 (0x4UL << FMC_SDTR1_TRC_Pos) /*!< 0x00004000 */\r
+#define FMC_SDTR1_TWR_Pos (16U)\r
+#define FMC_SDTR1_TWR_Msk (0xFUL << FMC_SDTR1_TWR_Pos) /*!< 0x000F0000 */\r
+#define FMC_SDTR1_TWR FMC_SDTR1_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR1_TWR_0 (0x1UL << FMC_SDTR1_TWR_Pos) /*!< 0x00010000 */\r
+#define FMC_SDTR1_TWR_1 (0x2UL << FMC_SDTR1_TWR_Pos) /*!< 0x00020000 */\r
+#define FMC_SDTR1_TWR_2 (0x4UL << FMC_SDTR1_TWR_Pos) /*!< 0x00040000 */\r
+#define FMC_SDTR1_TRP_Pos (20U)\r
+#define FMC_SDTR1_TRP_Msk (0xFUL << FMC_SDTR1_TRP_Pos) /*!< 0x00F00000 */\r
+#define FMC_SDTR1_TRP FMC_SDTR1_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR1_TRP_0 (0x1UL << FMC_SDTR1_TRP_Pos) /*!< 0x00100000 */\r
+#define FMC_SDTR1_TRP_1 (0x2UL << FMC_SDTR1_TRP_Pos) /*!< 0x00200000 */\r
+#define FMC_SDTR1_TRP_2 (0x4UL << FMC_SDTR1_TRP_Pos) /*!< 0x00400000 */\r
+#define FMC_SDTR1_TRCD_Pos (24U)\r
+#define FMC_SDTR1_TRCD_Msk (0xFUL << FMC_SDTR1_TRCD_Pos) /*!< 0x0F000000 */\r
+#define FMC_SDTR1_TRCD FMC_SDTR1_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR1_TRCD_0 (0x1UL << FMC_SDTR1_TRCD_Pos) /*!< 0x01000000 */\r
+#define FMC_SDTR1_TRCD_1 (0x2UL << FMC_SDTR1_TRCD_Pos) /*!< 0x02000000 */\r
+#define FMC_SDTR1_TRCD_2 (0x4UL << FMC_SDTR1_TRCD_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for FMC_SDTR2 register ******************/\r
+#define FMC_SDTR2_TMRD_Pos (0U)\r
+#define FMC_SDTR2_TMRD_Msk (0xFUL << FMC_SDTR2_TMRD_Pos) /*!< 0x0000000F */\r
+#define FMC_SDTR2_TMRD FMC_SDTR2_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define FMC_SDTR2_TMRD_0 (0x1UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000001 */\r
+#define FMC_SDTR2_TMRD_1 (0x2UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000002 */\r
+#define FMC_SDTR2_TMRD_2 (0x4UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000004 */\r
+#define FMC_SDTR2_TMRD_3 (0x8UL << FMC_SDTR2_TMRD_Pos) /*!< 0x00000008 */\r
+#define FMC_SDTR2_TXSR_Pos (4U)\r
+#define FMC_SDTR2_TXSR_Msk (0xFUL << FMC_SDTR2_TXSR_Pos) /*!< 0x000000F0 */\r
+#define FMC_SDTR2_TXSR FMC_SDTR2_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define FMC_SDTR2_TXSR_0 (0x1UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000010 */\r
+#define FMC_SDTR2_TXSR_1 (0x2UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000020 */\r
+#define FMC_SDTR2_TXSR_2 (0x4UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000040 */\r
+#define FMC_SDTR2_TXSR_3 (0x8UL << FMC_SDTR2_TXSR_Pos) /*!< 0x00000080 */\r
+#define FMC_SDTR2_TRAS_Pos (8U)\r
+#define FMC_SDTR2_TRAS_Msk (0xFUL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000F00 */\r
+#define FMC_SDTR2_TRAS FMC_SDTR2_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define FMC_SDTR2_TRAS_0 (0x1UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDTR2_TRAS_1 (0x2UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000200 */\r
+#define FMC_SDTR2_TRAS_2 (0x4UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000400 */\r
+#define FMC_SDTR2_TRAS_3 (0x8UL << FMC_SDTR2_TRAS_Pos) /*!< 0x00000800 */\r
+#define FMC_SDTR2_TRC_Pos (12U)\r
+#define FMC_SDTR2_TRC_Msk (0xFUL << FMC_SDTR2_TRC_Pos) /*!< 0x0000F000 */\r
+#define FMC_SDTR2_TRC FMC_SDTR2_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define FMC_SDTR2_TRC_0 (0x1UL << FMC_SDTR2_TRC_Pos) /*!< 0x00001000 */\r
+#define FMC_SDTR2_TRC_1 (0x2UL << FMC_SDTR2_TRC_Pos) /*!< 0x00002000 */\r
+#define FMC_SDTR2_TRC_2 (0x4UL << FMC_SDTR2_TRC_Pos) /*!< 0x00004000 */\r
+#define FMC_SDTR2_TWR_Pos (16U)\r
+#define FMC_SDTR2_TWR_Msk (0xFUL << FMC_SDTR2_TWR_Pos) /*!< 0x000F0000 */\r
+#define FMC_SDTR2_TWR FMC_SDTR2_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define FMC_SDTR2_TWR_0 (0x1UL << FMC_SDTR2_TWR_Pos) /*!< 0x00010000 */\r
+#define FMC_SDTR2_TWR_1 (0x2UL << FMC_SDTR2_TWR_Pos) /*!< 0x00020000 */\r
+#define FMC_SDTR2_TWR_2 (0x4UL << FMC_SDTR2_TWR_Pos) /*!< 0x00040000 */\r
+#define FMC_SDTR2_TRP_Pos (20U)\r
+#define FMC_SDTR2_TRP_Msk (0xFUL << FMC_SDTR2_TRP_Pos) /*!< 0x00F00000 */\r
+#define FMC_SDTR2_TRP FMC_SDTR2_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define FMC_SDTR2_TRP_0 (0x1UL << FMC_SDTR2_TRP_Pos) /*!< 0x00100000 */\r
+#define FMC_SDTR2_TRP_1 (0x2UL << FMC_SDTR2_TRP_Pos) /*!< 0x00200000 */\r
+#define FMC_SDTR2_TRP_2 (0x4UL << FMC_SDTR2_TRP_Pos) /*!< 0x00400000 */\r
+#define FMC_SDTR2_TRCD_Pos (24U)\r
+#define FMC_SDTR2_TRCD_Msk (0xFUL << FMC_SDTR2_TRCD_Pos) /*!< 0x0F000000 */\r
+#define FMC_SDTR2_TRCD FMC_SDTR2_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */\r
+#define FMC_SDTR2_TRCD_0 (0x1UL << FMC_SDTR2_TRCD_Pos) /*!< 0x01000000 */\r
+#define FMC_SDTR2_TRCD_1 (0x2UL << FMC_SDTR2_TRCD_Pos) /*!< 0x02000000 */\r
+#define FMC_SDTR2_TRCD_2 (0x4UL << FMC_SDTR2_TRCD_Pos) /*!< 0x04000000 */\r
+\r
+/****************** Bit definition for FMC_SDCMR register ******************/\r
+#define FMC_SDCMR_MODE_Pos (0U)\r
+#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */\r
+#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */\r
+#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */\r
+#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */\r
+#define FMC_SDCMR_CTB2_Pos (3U)\r
+#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */\r
+#define FMC_SDCMR_CTB1_Pos (4U)\r
+#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */\r
+#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */\r
+#define FMC_SDCMR_NRFS_Pos (5U)\r
+#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */\r
+#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */\r
+#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */\r
+#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */\r
+#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */\r
+#define FMC_SDCMR_MRD_Pos (9U)\r
+#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */\r
+#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/****************** Bit definition for FMC_SDRTR register ******************/\r
+#define FMC_SDRTR_CRE_Pos (0U)\r
+#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */\r
+#define FMC_SDRTR_COUNT_Pos (1U)\r
+#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */\r
+#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */\r
+#define FMC_SDRTR_REIE_Pos (14U)\r
+#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */\r
+#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */\r
+\r
+/****************** Bit definition for FMC_SDSR register ******************/\r
+#define FMC_SDSR_RE_Pos (0U)\r
+#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */\r
+#define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */\r
+#define FMC_SDSR_MODES1_Pos (1U)\r
+#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */\r
+#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */\r
+#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */\r
+#define FMC_SDSR_MODES2_Pos (3U)\r
+#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */\r
+#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */\r
+#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */\r
+#define FMC_SDSR_BUSY_Pos (5U)\r
+#define FMC_SDSR_BUSY_Msk (0x1UL << FMC_SDSR_BUSY_Pos) /*!< 0x00000020 */\r
+#define FMC_SDSR_BUSY FMC_SDSR_BUSY_Msk /*!<Busy status */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* General Purpose I/O */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bits definition for GPIO_MODER register *****************/\r
+#define GPIO_MODER_MODER0_Pos (0U)\r
+#define GPIO_MODER_MODER0_Msk (0x3UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */\r
+#define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk\r
+#define GPIO_MODER_MODER0_0 (0x1UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */\r
+#define GPIO_MODER_MODER0_1 (0x2UL << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */\r
+#define GPIO_MODER_MODER1_Pos (2U)\r
+#define GPIO_MODER_MODER1_Msk (0x3UL << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */\r
+#define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk\r
+#define GPIO_MODER_MODER1_0 (0x1UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */\r
+#define GPIO_MODER_MODER1_1 (0x2UL << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */\r
+#define GPIO_MODER_MODER2_Pos (4U)\r
+#define GPIO_MODER_MODER2_Msk (0x3UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */\r
+#define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk\r
+#define GPIO_MODER_MODER2_0 (0x1UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */\r
+#define GPIO_MODER_MODER2_1 (0x2UL << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */\r
+#define GPIO_MODER_MODER3_Pos (6U)\r
+#define GPIO_MODER_MODER3_Msk (0x3UL << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk\r
+#define GPIO_MODER_MODER3_0 (0x1UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */\r
+#define GPIO_MODER_MODER3_1 (0x2UL << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */\r
+#define GPIO_MODER_MODER4_Pos (8U)\r
+#define GPIO_MODER_MODER4_Msk (0x3UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */\r
+#define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk\r
+#define GPIO_MODER_MODER4_0 (0x1UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */\r
+#define GPIO_MODER_MODER4_1 (0x2UL << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */\r
+#define GPIO_MODER_MODER5_Pos (10U)\r
+#define GPIO_MODER_MODER5_Msk (0x3UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk\r
+#define GPIO_MODER_MODER5_0 (0x1UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */\r
+#define GPIO_MODER_MODER5_1 (0x2UL << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */\r
+#define GPIO_MODER_MODER6_Pos (12U)\r
+#define GPIO_MODER_MODER6_Msk (0x3UL << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */\r
+#define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk\r
+#define GPIO_MODER_MODER6_0 (0x1UL << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */\r
+#define GPIO_MODER_MODER6_1 (0x2UL << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */\r
+#define GPIO_MODER_MODER7_Pos (14U)\r
+#define GPIO_MODER_MODER7_Msk (0x3UL << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk\r
+#define GPIO_MODER_MODER7_0 (0x1UL << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */\r
+#define GPIO_MODER_MODER7_1 (0x2UL << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */\r
+#define GPIO_MODER_MODER8_Pos (16U)\r
+#define GPIO_MODER_MODER8_Msk (0x3UL << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */\r
+#define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk\r
+#define GPIO_MODER_MODER8_0 (0x1UL << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */\r
+#define GPIO_MODER_MODER8_1 (0x2UL << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */\r
+#define GPIO_MODER_MODER9_Pos (18U)\r
+#define GPIO_MODER_MODER9_Msk (0x3UL << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk\r
+#define GPIO_MODER_MODER9_0 (0x1UL << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */\r
+#define GPIO_MODER_MODER9_1 (0x2UL << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */\r
+#define GPIO_MODER_MODER10_Pos (20U)\r
+#define GPIO_MODER_MODER10_Msk (0x3UL << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */\r
+#define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk\r
+#define GPIO_MODER_MODER10_0 (0x1UL << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */\r
+#define GPIO_MODER_MODER10_1 (0x2UL << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */\r
+#define GPIO_MODER_MODER11_Pos (22U)\r
+#define GPIO_MODER_MODER11_Msk (0x3UL << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk\r
+#define GPIO_MODER_MODER11_0 (0x1UL << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */\r
+#define GPIO_MODER_MODER11_1 (0x2UL << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */\r
+#define GPIO_MODER_MODER12_Pos (24U)\r
+#define GPIO_MODER_MODER12_Msk (0x3UL << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */\r
+#define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk\r
+#define GPIO_MODER_MODER12_0 (0x1UL << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */\r
+#define GPIO_MODER_MODER12_1 (0x2UL << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */\r
+#define GPIO_MODER_MODER13_Pos (26U)\r
+#define GPIO_MODER_MODER13_Msk (0x3UL << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk\r
+#define GPIO_MODER_MODER13_0 (0x1UL << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */\r
+#define GPIO_MODER_MODER13_1 (0x2UL << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */\r
+#define GPIO_MODER_MODER14_Pos (28U)\r
+#define GPIO_MODER_MODER14_Msk (0x3UL << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */\r
+#define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk\r
+#define GPIO_MODER_MODER14_0 (0x1UL << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */\r
+#define GPIO_MODER_MODER14_1 (0x2UL << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */\r
+#define GPIO_MODER_MODER15_Pos (30U)\r
+#define GPIO_MODER_MODER15_Msk (0x3UL << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk\r
+#define GPIO_MODER_MODER15_0 (0x1UL << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */\r
+#define GPIO_MODER_MODER15_1 (0x2UL << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_OTYPER register ****************/\r
+#define GPIO_OTYPER_OT0_Pos (0U) \r
+#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk \r
+#define GPIO_OTYPER_OT1_Pos (1U) \r
+#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */\r
+#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk \r
+#define GPIO_OTYPER_OT2_Pos (2U) \r
+#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */\r
+#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk \r
+#define GPIO_OTYPER_OT3_Pos (3U) \r
+#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */\r
+#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk \r
+#define GPIO_OTYPER_OT4_Pos (4U) \r
+#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */\r
+#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk \r
+#define GPIO_OTYPER_OT5_Pos (5U) \r
+#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */\r
+#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk \r
+#define GPIO_OTYPER_OT6_Pos (6U) \r
+#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */\r
+#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk \r
+#define GPIO_OTYPER_OT7_Pos (7U) \r
+#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */\r
+#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk \r
+#define GPIO_OTYPER_OT8_Pos (8U) \r
+#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */\r
+#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk \r
+#define GPIO_OTYPER_OT9_Pos (9U) \r
+#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */\r
+#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk \r
+#define GPIO_OTYPER_OT10_Pos (10U) \r
+#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */\r
+#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk \r
+#define GPIO_OTYPER_OT11_Pos (11U) \r
+#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */\r
+#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk \r
+#define GPIO_OTYPER_OT12_Pos (12U) \r
+#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */\r
+#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk \r
+#define GPIO_OTYPER_OT13_Pos (13U) \r
+#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */\r
+#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk \r
+#define GPIO_OTYPER_OT14_Pos (14U) \r
+#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */\r
+#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk \r
+#define GPIO_OTYPER_OT15_Pos (15U) \r
+#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */\r
+#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk \r
+\r
+/* Legacy defines */\r
+#define GPIO_OTYPER_OT_0 GPIO_OTYPER_OT0\r
+#define GPIO_OTYPER_OT_1 GPIO_OTYPER_OT1\r
+#define GPIO_OTYPER_OT_2 GPIO_OTYPER_OT2\r
+#define GPIO_OTYPER_OT_3 GPIO_OTYPER_OT3\r
+#define GPIO_OTYPER_OT_4 GPIO_OTYPER_OT4\r
+#define GPIO_OTYPER_OT_5 GPIO_OTYPER_OT5\r
+#define GPIO_OTYPER_OT_6 GPIO_OTYPER_OT6\r
+#define GPIO_OTYPER_OT_7 GPIO_OTYPER_OT7\r
+#define GPIO_OTYPER_OT_8 GPIO_OTYPER_OT8\r
+#define GPIO_OTYPER_OT_9 GPIO_OTYPER_OT9\r
+#define GPIO_OTYPER_OT_10 GPIO_OTYPER_OT10\r
+#define GPIO_OTYPER_OT_11 GPIO_OTYPER_OT11\r
+#define GPIO_OTYPER_OT_12 GPIO_OTYPER_OT12\r
+#define GPIO_OTYPER_OT_13 GPIO_OTYPER_OT13\r
+#define GPIO_OTYPER_OT_14 GPIO_OTYPER_OT14\r
+#define GPIO_OTYPER_OT_15 GPIO_OTYPER_OT15\r
+\r
+/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
+#define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)\r
+#define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR0_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_OSPEEDR_OSPEEDR0_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */\r
+#define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)\r
+#define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR1_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_OSPEEDR_OSPEEDR1_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */\r
+#define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)\r
+#define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR2_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_OSPEEDR_OSPEEDR2_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */\r
+#define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)\r
+#define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR3_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_OSPEEDR_OSPEEDR3_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */\r
+#define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)\r
+#define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR4_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_OSPEEDR_OSPEEDR4_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */\r
+#define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)\r
+#define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR5_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_OSPEEDR_OSPEEDR5_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */\r
+#define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)\r
+#define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR6_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_OSPEEDR_OSPEEDR6_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */\r
+#define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)\r
+#define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR7_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_OSPEEDR_OSPEEDR7_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */\r
+#define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)\r
+#define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR8_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_OSPEEDR_OSPEEDR8_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */\r
+#define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)\r
+#define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR9_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_OSPEEDR_OSPEEDR9_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */\r
+#define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)\r
+#define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR10_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_OSPEEDR_OSPEEDR10_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */\r
+#define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)\r
+#define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR11_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_OSPEEDR_OSPEEDR11_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */\r
+#define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)\r
+#define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR12_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR12_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)\r
+#define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR13_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR13_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)\r
+#define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR14_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR14_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)\r
+#define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk\r
+#define GPIO_OSPEEDR_OSPEEDR15_0 (0x1UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_OSPEEDR_OSPEEDR15_1 (0x2UL << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */\r
+\r
+/* legacy defines */\r
+#define GPIO_OSPEEDER_OSPEEDR0_Pos GPIO_OSPEEDR_OSPEEDR0_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR0_Msk GPIO_OSPEEDR_OSPEEDR0_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0\r
+#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0\r
+#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1\r
+#define GPIO_OSPEEDER_OSPEEDR1_Pos GPIO_OSPEEDR_OSPEEDR1_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR1_Msk GPIO_OSPEEDR_OSPEEDR1_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1\r
+#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0\r
+#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1\r
+#define GPIO_OSPEEDER_OSPEEDR2_Pos GPIO_OSPEEDR_OSPEEDR2_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR2_Msk GPIO_OSPEEDR_OSPEEDR2_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2\r
+#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0\r
+#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1\r
+#define GPIO_OSPEEDER_OSPEEDR3_Pos GPIO_OSPEEDR_OSPEEDR3_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR3_Msk GPIO_OSPEEDR_OSPEEDR3_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3\r
+#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0\r
+#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1\r
+#define GPIO_OSPEEDER_OSPEEDR4_Pos GPIO_OSPEEDR_OSPEEDR4_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR4_Msk GPIO_OSPEEDR_OSPEEDR4_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4\r
+#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0\r
+#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1\r
+#define GPIO_OSPEEDER_OSPEEDR5_Pos GPIO_OSPEEDR_OSPEEDR5_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR5_Msk GPIO_OSPEEDR_OSPEEDR5_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5\r
+#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0\r
+#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1\r
+#define GPIO_OSPEEDER_OSPEEDR6_Pos GPIO_OSPEEDR_OSPEEDR6_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR6_Msk GPIO_OSPEEDR_OSPEEDR6_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6\r
+#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0\r
+#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1\r
+#define GPIO_OSPEEDER_OSPEEDR7_Pos GPIO_OSPEEDR_OSPEEDR7_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR7_Msk GPIO_OSPEEDR_OSPEEDR7_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7\r
+#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0\r
+#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1\r
+#define GPIO_OSPEEDER_OSPEEDR8_Pos GPIO_OSPEEDR_OSPEEDR8_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR8_Msk GPIO_OSPEEDR_OSPEEDR8_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8\r
+#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0\r
+#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1\r
+#define GPIO_OSPEEDER_OSPEEDR9_Pos GPIO_OSPEEDR_OSPEEDR9_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR9_Msk GPIO_OSPEEDR_OSPEEDR9_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9\r
+#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0\r
+#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1\r
+#define GPIO_OSPEEDER_OSPEEDR10_Pos GPIO_OSPEEDR_OSPEEDR10_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR10_Msk GPIO_OSPEEDR_OSPEEDR10_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10\r
+#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0\r
+#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1\r
+#define GPIO_OSPEEDER_OSPEEDR11_Pos GPIO_OSPEEDR_OSPEEDR11_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR11_Msk GPIO_OSPEEDR_OSPEEDR11_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11\r
+#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0\r
+#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1\r
+#define GPIO_OSPEEDER_OSPEEDR12_Pos GPIO_OSPEEDR_OSPEEDR12_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR12_Msk GPIO_OSPEEDR_OSPEEDR12_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12\r
+#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0\r
+#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1\r
+#define GPIO_OSPEEDER_OSPEEDR13_Pos GPIO_OSPEEDR_OSPEEDR13_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR13_Msk GPIO_OSPEEDR_OSPEEDR13_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13\r
+#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0\r
+#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1\r
+#define GPIO_OSPEEDER_OSPEEDR14_Pos GPIO_OSPEEDR_OSPEEDR14_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR14_Msk GPIO_OSPEEDR_OSPEEDR14_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14\r
+#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0\r
+#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1\r
+#define GPIO_OSPEEDER_OSPEEDR15_Pos GPIO_OSPEEDR_OSPEEDR15_Pos\r
+#define GPIO_OSPEEDER_OSPEEDR15_Msk GPIO_OSPEEDR_OSPEEDR15_Msk\r
+#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15\r
+#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0\r
+#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1\r
+\r
+/****************** Bits definition for GPIO_PUPDR register *****************/\r
+#define GPIO_PUPDR_PUPDR0_Pos (0U)\r
+#define GPIO_PUPDR_PUPDR0_Msk (0x3UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */\r
+#define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk\r
+#define GPIO_PUPDR_PUPDR0_0 (0x1UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */\r
+#define GPIO_PUPDR_PUPDR0_1 (0x2UL << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */\r
+#define GPIO_PUPDR_PUPDR1_Pos (2U)\r
+#define GPIO_PUPDR_PUPDR1_Msk (0x3UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */\r
+#define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk\r
+#define GPIO_PUPDR_PUPDR1_0 (0x1UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */\r
+#define GPIO_PUPDR_PUPDR1_1 (0x2UL << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */\r
+#define GPIO_PUPDR_PUPDR2_Pos (4U)\r
+#define GPIO_PUPDR_PUPDR2_Msk (0x3UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */\r
+#define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk\r
+#define GPIO_PUPDR_PUPDR2_0 (0x1UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */\r
+#define GPIO_PUPDR_PUPDR2_1 (0x2UL << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */\r
+#define GPIO_PUPDR_PUPDR3_Pos (6U)\r
+#define GPIO_PUPDR_PUPDR3_Msk (0x3UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */\r
+#define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk\r
+#define GPIO_PUPDR_PUPDR3_0 (0x1UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */\r
+#define GPIO_PUPDR_PUPDR3_1 (0x2UL << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */\r
+#define GPIO_PUPDR_PUPDR4_Pos (8U)\r
+#define GPIO_PUPDR_PUPDR4_Msk (0x3UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */\r
+#define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk\r
+#define GPIO_PUPDR_PUPDR4_0 (0x1UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */\r
+#define GPIO_PUPDR_PUPDR4_1 (0x2UL << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */\r
+#define GPIO_PUPDR_PUPDR5_Pos (10U)\r
+#define GPIO_PUPDR_PUPDR5_Msk (0x3UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */\r
+#define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk\r
+#define GPIO_PUPDR_PUPDR5_0 (0x1UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */\r
+#define GPIO_PUPDR_PUPDR5_1 (0x2UL << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */\r
+#define GPIO_PUPDR_PUPDR6_Pos (12U)\r
+#define GPIO_PUPDR_PUPDR6_Msk (0x3UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */\r
+#define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk\r
+#define GPIO_PUPDR_PUPDR6_0 (0x1UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */\r
+#define GPIO_PUPDR_PUPDR6_1 (0x2UL << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */\r
+#define GPIO_PUPDR_PUPDR7_Pos (14U)\r
+#define GPIO_PUPDR_PUPDR7_Msk (0x3UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */\r
+#define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk\r
+#define GPIO_PUPDR_PUPDR7_0 (0x1UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */\r
+#define GPIO_PUPDR_PUPDR7_1 (0x2UL << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */\r
+#define GPIO_PUPDR_PUPDR8_Pos (16U)\r
+#define GPIO_PUPDR_PUPDR8_Msk (0x3UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */\r
+#define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk\r
+#define GPIO_PUPDR_PUPDR8_0 (0x1UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */\r
+#define GPIO_PUPDR_PUPDR8_1 (0x2UL << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */\r
+#define GPIO_PUPDR_PUPDR9_Pos (18U)\r
+#define GPIO_PUPDR_PUPDR9_Msk (0x3UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */\r
+#define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk\r
+#define GPIO_PUPDR_PUPDR9_0 (0x1UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */\r
+#define GPIO_PUPDR_PUPDR9_1 (0x2UL << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */\r
+#define GPIO_PUPDR_PUPDR10_Pos (20U)\r
+#define GPIO_PUPDR_PUPDR10_Msk (0x3UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */\r
+#define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk\r
+#define GPIO_PUPDR_PUPDR10_0 (0x1UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */\r
+#define GPIO_PUPDR_PUPDR10_1 (0x2UL << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */\r
+#define GPIO_PUPDR_PUPDR11_Pos (22U)\r
+#define GPIO_PUPDR_PUPDR11_Msk (0x3UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */\r
+#define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk\r
+#define GPIO_PUPDR_PUPDR11_0 (0x1UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */\r
+#define GPIO_PUPDR_PUPDR11_1 (0x2UL << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */\r
+#define GPIO_PUPDR_PUPDR12_Pos (24U)\r
+#define GPIO_PUPDR_PUPDR12_Msk (0x3UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */\r
+#define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk\r
+#define GPIO_PUPDR_PUPDR12_0 (0x1UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */\r
+#define GPIO_PUPDR_PUPDR12_1 (0x2UL << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */\r
+#define GPIO_PUPDR_PUPDR13_Pos (26U)\r
+#define GPIO_PUPDR_PUPDR13_Msk (0x3UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */\r
+#define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk\r
+#define GPIO_PUPDR_PUPDR13_0 (0x1UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */\r
+#define GPIO_PUPDR_PUPDR13_1 (0x2UL << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */\r
+#define GPIO_PUPDR_PUPDR14_Pos (28U)\r
+#define GPIO_PUPDR_PUPDR14_Msk (0x3UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */\r
+#define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk\r
+#define GPIO_PUPDR_PUPDR14_0 (0x1UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */\r
+#define GPIO_PUPDR_PUPDR14_1 (0x2UL << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */\r
+#define GPIO_PUPDR_PUPDR15_Pos (30U)\r
+#define GPIO_PUPDR_PUPDR15_Msk (0x3UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */\r
+#define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk\r
+#define GPIO_PUPDR_PUPDR15_0 (0x1UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */\r
+#define GPIO_PUPDR_PUPDR15_1 (0x2UL << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bits definition for GPIO_IDR register *******************/\r
+#define GPIO_IDR_ID0_Pos (0U) \r
+#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */\r
+#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk \r
+#define GPIO_IDR_ID1_Pos (1U) \r
+#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */\r
+#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk \r
+#define GPIO_IDR_ID2_Pos (2U) \r
+#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */\r
+#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk \r
+#define GPIO_IDR_ID3_Pos (3U) \r
+#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */\r
+#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk \r
+#define GPIO_IDR_ID4_Pos (4U) \r
+#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */\r
+#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk \r
+#define GPIO_IDR_ID5_Pos (5U) \r
+#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */\r
+#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk \r
+#define GPIO_IDR_ID6_Pos (6U) \r
+#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */\r
+#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk \r
+#define GPIO_IDR_ID7_Pos (7U) \r
+#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */\r
+#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk \r
+#define GPIO_IDR_ID8_Pos (8U) \r
+#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */\r
+#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk \r
+#define GPIO_IDR_ID9_Pos (9U) \r
+#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */\r
+#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk \r
+#define GPIO_IDR_ID10_Pos (10U) \r
+#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */\r
+#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk \r
+#define GPIO_IDR_ID11_Pos (11U) \r
+#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */\r
+#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk \r
+#define GPIO_IDR_ID12_Pos (12U) \r
+#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */\r
+#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk \r
+#define GPIO_IDR_ID13_Pos (13U) \r
+#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */\r
+#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk \r
+#define GPIO_IDR_ID14_Pos (14U) \r
+#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */\r
+#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk \r
+#define GPIO_IDR_ID15_Pos (15U) \r
+#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */\r
+#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk \r
+\r
+/* Legacy defines */\r
+#define GPIO_IDR_IDR_0 GPIO_IDR_ID0\r
+#define GPIO_IDR_IDR_1 GPIO_IDR_ID1\r
+#define GPIO_IDR_IDR_2 GPIO_IDR_ID2\r
+#define GPIO_IDR_IDR_3 GPIO_IDR_ID3\r
+#define GPIO_IDR_IDR_4 GPIO_IDR_ID4\r
+#define GPIO_IDR_IDR_5 GPIO_IDR_ID5\r
+#define GPIO_IDR_IDR_6 GPIO_IDR_ID6\r
+#define GPIO_IDR_IDR_7 GPIO_IDR_ID7\r
+#define GPIO_IDR_IDR_8 GPIO_IDR_ID8\r
+#define GPIO_IDR_IDR_9 GPIO_IDR_ID9\r
+#define GPIO_IDR_IDR_10 GPIO_IDR_ID10\r
+#define GPIO_IDR_IDR_11 GPIO_IDR_ID11\r
+#define GPIO_IDR_IDR_12 GPIO_IDR_ID12\r
+#define GPIO_IDR_IDR_13 GPIO_IDR_ID13\r
+#define GPIO_IDR_IDR_14 GPIO_IDR_ID14\r
+#define GPIO_IDR_IDR_15 GPIO_IDR_ID15\r
+\r
+/****************** Bits definition for GPIO_ODR register *******************/\r
+#define GPIO_ODR_OD0_Pos (0U) \r
+#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */\r
+#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk \r
+#define GPIO_ODR_OD1_Pos (1U) \r
+#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */\r
+#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk \r
+#define GPIO_ODR_OD2_Pos (2U) \r
+#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */\r
+#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk \r
+#define GPIO_ODR_OD3_Pos (3U) \r
+#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */\r
+#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk \r
+#define GPIO_ODR_OD4_Pos (4U) \r
+#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */\r
+#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk \r
+#define GPIO_ODR_OD5_Pos (5U) \r
+#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */\r
+#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk \r
+#define GPIO_ODR_OD6_Pos (6U) \r
+#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */\r
+#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk \r
+#define GPIO_ODR_OD7_Pos (7U) \r
+#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */\r
+#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk \r
+#define GPIO_ODR_OD8_Pos (8U) \r
+#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */\r
+#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk \r
+#define GPIO_ODR_OD9_Pos (9U) \r
+#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */\r
+#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk \r
+#define GPIO_ODR_OD10_Pos (10U) \r
+#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */\r
+#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk \r
+#define GPIO_ODR_OD11_Pos (11U) \r
+#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */\r
+#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk \r
+#define GPIO_ODR_OD12_Pos (12U) \r
+#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */\r
+#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk \r
+#define GPIO_ODR_OD13_Pos (13U) \r
+#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */\r
+#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk \r
+#define GPIO_ODR_OD14_Pos (14U) \r
+#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */\r
+#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk \r
+#define GPIO_ODR_OD15_Pos (15U) \r
+#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */\r
+#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk\r
+\r
+/* Legacy defines */\r
+#define GPIO_ODR_ODR_0 GPIO_ODR_OD0\r
+#define GPIO_ODR_ODR_1 GPIO_ODR_OD1\r
+#define GPIO_ODR_ODR_2 GPIO_ODR_OD2\r
+#define GPIO_ODR_ODR_3 GPIO_ODR_OD3\r
+#define GPIO_ODR_ODR_4 GPIO_ODR_OD4\r
+#define GPIO_ODR_ODR_5 GPIO_ODR_OD5\r
+#define GPIO_ODR_ODR_6 GPIO_ODR_OD6\r
+#define GPIO_ODR_ODR_7 GPIO_ODR_OD7\r
+#define GPIO_ODR_ODR_8 GPIO_ODR_OD8\r
+#define GPIO_ODR_ODR_9 GPIO_ODR_OD9\r
+#define GPIO_ODR_ODR_10 GPIO_ODR_OD10\r
+#define GPIO_ODR_ODR_11 GPIO_ODR_OD11\r
+#define GPIO_ODR_ODR_12 GPIO_ODR_OD12\r
+#define GPIO_ODR_ODR_13 GPIO_ODR_OD13\r
+#define GPIO_ODR_ODR_14 GPIO_ODR_OD14\r
+#define GPIO_ODR_ODR_15 GPIO_ODR_OD15\r
+\r
+/****************** Bits definition for GPIO_BSRR register ******************/\r
+#define GPIO_BSRR_BS0_Pos (0U) \r
+#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */\r
+#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk \r
+#define GPIO_BSRR_BS1_Pos (1U) \r
+#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */\r
+#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk \r
+#define GPIO_BSRR_BS2_Pos (2U) \r
+#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */\r
+#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk \r
+#define GPIO_BSRR_BS3_Pos (3U) \r
+#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */\r
+#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk \r
+#define GPIO_BSRR_BS4_Pos (4U) \r
+#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */\r
+#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk \r
+#define GPIO_BSRR_BS5_Pos (5U) \r
+#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */\r
+#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk \r
+#define GPIO_BSRR_BS6_Pos (6U) \r
+#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */\r
+#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk \r
+#define GPIO_BSRR_BS7_Pos (7U) \r
+#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */\r
+#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk \r
+#define GPIO_BSRR_BS8_Pos (8U) \r
+#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */\r
+#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk \r
+#define GPIO_BSRR_BS9_Pos (9U) \r
+#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */\r
+#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk \r
+#define GPIO_BSRR_BS10_Pos (10U) \r
+#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */\r
+#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk \r
+#define GPIO_BSRR_BS11_Pos (11U) \r
+#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */\r
+#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk \r
+#define GPIO_BSRR_BS12_Pos (12U) \r
+#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */\r
+#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk \r
+#define GPIO_BSRR_BS13_Pos (13U) \r
+#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */\r
+#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk \r
+#define GPIO_BSRR_BS14_Pos (14U) \r
+#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */\r
+#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk \r
+#define GPIO_BSRR_BS15_Pos (15U) \r
+#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */\r
+#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk \r
+#define GPIO_BSRR_BR0_Pos (16U) \r
+#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */\r
+#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk \r
+#define GPIO_BSRR_BR1_Pos (17U) \r
+#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */\r
+#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk \r
+#define GPIO_BSRR_BR2_Pos (18U) \r
+#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */\r
+#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk \r
+#define GPIO_BSRR_BR3_Pos (19U) \r
+#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */\r
+#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk \r
+#define GPIO_BSRR_BR4_Pos (20U) \r
+#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */\r
+#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk \r
+#define GPIO_BSRR_BR5_Pos (21U) \r
+#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */\r
+#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk \r
+#define GPIO_BSRR_BR6_Pos (22U) \r
+#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */\r
+#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk \r
+#define GPIO_BSRR_BR7_Pos (23U) \r
+#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */\r
+#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk \r
+#define GPIO_BSRR_BR8_Pos (24U) \r
+#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */\r
+#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk \r
+#define GPIO_BSRR_BR9_Pos (25U) \r
+#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */\r
+#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk \r
+#define GPIO_BSRR_BR10_Pos (26U) \r
+#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */\r
+#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk \r
+#define GPIO_BSRR_BR11_Pos (27U) \r
+#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */\r
+#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk \r
+#define GPIO_BSRR_BR12_Pos (28U) \r
+#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */\r
+#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk \r
+#define GPIO_BSRR_BR13_Pos (29U) \r
+#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */\r
+#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk \r
+#define GPIO_BSRR_BR14_Pos (30U) \r
+#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */\r
+#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk \r
+#define GPIO_BSRR_BR15_Pos (31U) \r
+#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */\r
+#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk \r
+\r
+/* Legacy defines */\r
+#define GPIO_BSRR_BS_0 GPIO_BSRR_BS0\r
+#define GPIO_BSRR_BS_1 GPIO_BSRR_BS1\r
+#define GPIO_BSRR_BS_2 GPIO_BSRR_BS2\r
+#define GPIO_BSRR_BS_3 GPIO_BSRR_BS3\r
+#define GPIO_BSRR_BS_4 GPIO_BSRR_BS4\r
+#define GPIO_BSRR_BS_5 GPIO_BSRR_BS5\r
+#define GPIO_BSRR_BS_6 GPIO_BSRR_BS6\r
+#define GPIO_BSRR_BS_7 GPIO_BSRR_BS7\r
+#define GPIO_BSRR_BS_8 GPIO_BSRR_BS8\r
+#define GPIO_BSRR_BS_9 GPIO_BSRR_BS9\r
+#define GPIO_BSRR_BS_10 GPIO_BSRR_BS10\r
+#define GPIO_BSRR_BS_11 GPIO_BSRR_BS11\r
+#define GPIO_BSRR_BS_12 GPIO_BSRR_BS12\r
+#define GPIO_BSRR_BS_13 GPIO_BSRR_BS13\r
+#define GPIO_BSRR_BS_14 GPIO_BSRR_BS14\r
+#define GPIO_BSRR_BS_15 GPIO_BSRR_BS15\r
+#define GPIO_BSRR_BR_0 GPIO_BSRR_BR0\r
+#define GPIO_BSRR_BR_1 GPIO_BSRR_BR1\r
+#define GPIO_BSRR_BR_2 GPIO_BSRR_BR2\r
+#define GPIO_BSRR_BR_3 GPIO_BSRR_BR3\r
+#define GPIO_BSRR_BR_4 GPIO_BSRR_BR4\r
+#define GPIO_BSRR_BR_5 GPIO_BSRR_BR5\r
+#define GPIO_BSRR_BR_6 GPIO_BSRR_BR6\r
+#define GPIO_BSRR_BR_7 GPIO_BSRR_BR7\r
+#define GPIO_BSRR_BR_8 GPIO_BSRR_BR8\r
+#define GPIO_BSRR_BR_9 GPIO_BSRR_BR9\r
+#define GPIO_BSRR_BR_10 GPIO_BSRR_BR10\r
+#define GPIO_BSRR_BR_11 GPIO_BSRR_BR11\r
+#define GPIO_BSRR_BR_12 GPIO_BSRR_BR12\r
+#define GPIO_BSRR_BR_13 GPIO_BSRR_BR13\r
+#define GPIO_BSRR_BR_14 GPIO_BSRR_BR14\r
+#define GPIO_BSRR_BR_15 GPIO_BSRR_BR15\r
+\r
+/****************** Bit definition for GPIO_LCKR register *********************/\r
+#define GPIO_LCKR_LCK0_Pos (0U)\r
+#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */\r
+#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk\r
+#define GPIO_LCKR_LCK1_Pos (1U)\r
+#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */\r
+#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk\r
+#define GPIO_LCKR_LCK2_Pos (2U)\r
+#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */\r
+#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk\r
+#define GPIO_LCKR_LCK3_Pos (3U)\r
+#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */\r
+#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk\r
+#define GPIO_LCKR_LCK4_Pos (4U)\r
+#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */\r
+#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk\r
+#define GPIO_LCKR_LCK5_Pos (5U)\r
+#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */\r
+#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk\r
+#define GPIO_LCKR_LCK6_Pos (6U)\r
+#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */\r
+#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk\r
+#define GPIO_LCKR_LCK7_Pos (7U)\r
+#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */\r
+#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk\r
+#define GPIO_LCKR_LCK8_Pos (8U)\r
+#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */\r
+#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk\r
+#define GPIO_LCKR_LCK9_Pos (9U)\r
+#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */\r
+#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk\r
+#define GPIO_LCKR_LCK10_Pos (10U)\r
+#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */\r
+#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk\r
+#define GPIO_LCKR_LCK11_Pos (11U)\r
+#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */\r
+#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk\r
+#define GPIO_LCKR_LCK12_Pos (12U)\r
+#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */\r
+#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk\r
+#define GPIO_LCKR_LCK13_Pos (13U)\r
+#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */\r
+#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk\r
+#define GPIO_LCKR_LCK14_Pos (14U)\r
+#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */\r
+#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk\r
+#define GPIO_LCKR_LCK15_Pos (15U)\r
+#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */\r
+#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk\r
+#define GPIO_LCKR_LCKK_Pos (16U)\r
+#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */\r
+#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk\r
+\r
+/****************** Bit definition for GPIO_AFRL register *********************/\r
+#define GPIO_AFRL_AFRL0_Pos (0U)\r
+#define GPIO_AFRL_AFRL0_Msk (0xFUL << GPIO_AFRL_AFRL0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFRL0_Msk\r
+#define GPIO_AFRL_AFRL0_0 (0x1UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRL_AFRL0_1 (0x2UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRL_AFRL0_2 (0x4UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRL_AFRL0_3 (0x8UL << GPIO_AFRL_AFRL0_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRL_AFRL1_Pos (4U)\r
+#define GPIO_AFRL_AFRL1_Msk (0xFUL << GPIO_AFRL_AFRL1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFRL1_Msk\r
+#define GPIO_AFRL_AFRL1_0 (0x1UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRL_AFRL1_1 (0x2UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRL_AFRL1_2 (0x4UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRL_AFRL1_3 (0x8UL << GPIO_AFRL_AFRL1_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRL_AFRL2_Pos (8U)\r
+#define GPIO_AFRL_AFRL2_Msk (0xFUL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFRL2_Msk\r
+#define GPIO_AFRL_AFRL2_0 (0x1UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRL_AFRL2_1 (0x2UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRL_AFRL2_2 (0x4UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRL_AFRL2_3 (0x8UL << GPIO_AFRL_AFRL2_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRL_AFRL3_Pos (12U)\r
+#define GPIO_AFRL_AFRL3_Msk (0xFUL << GPIO_AFRL_AFRL3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFRL3_Msk\r
+#define GPIO_AFRL_AFRL3_0 (0x1UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRL_AFRL3_1 (0x2UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRL_AFRL3_2 (0x4UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRL_AFRL3_3 (0x8UL << GPIO_AFRL_AFRL3_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRL_AFRL4_Pos (16U)\r
+#define GPIO_AFRL_AFRL4_Msk (0xFUL << GPIO_AFRL_AFRL4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFRL4_Msk\r
+#define GPIO_AFRL_AFRL4_0 (0x1UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRL_AFRL4_1 (0x2UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRL_AFRL4_2 (0x4UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRL_AFRL4_3 (0x8UL << GPIO_AFRL_AFRL4_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRL_AFRL5_Pos (20U)\r
+#define GPIO_AFRL_AFRL5_Msk (0xFUL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFRL5_Msk\r
+#define GPIO_AFRL_AFRL5_0 (0x1UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRL_AFRL5_1 (0x2UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRL_AFRL5_2 (0x4UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRL_AFRL5_3 (0x8UL << GPIO_AFRL_AFRL5_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRL_AFRL6_Pos (24U)\r
+#define GPIO_AFRL_AFRL6_Msk (0xFUL << GPIO_AFRL_AFRL6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFRL6_Msk\r
+#define GPIO_AFRL_AFRL6_0 (0x1UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRL_AFRL6_1 (0x2UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRL_AFRL6_2 (0x4UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRL_AFRL6_3 (0x8UL << GPIO_AFRL_AFRL6_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRL_AFRL7_Pos (28U)\r
+#define GPIO_AFRL_AFRL7_Msk (0xFUL << GPIO_AFRL_AFRL7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFRL7_Msk\r
+#define GPIO_AFRL_AFRL7_0 (0x1UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRL_AFRL7_1 (0x2UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRL_AFRL7_2 (0x4UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRL_AFRL7_3 (0x8UL << GPIO_AFRL_AFRL7_Pos) /*!< 0x80000000 */\r
+\r
+/****************** Bit definition for GPIO_AFRH register *********************/\r
+#define GPIO_AFRH_AFRH0_Pos (0U)\r
+#define GPIO_AFRH_AFRH0_Msk (0xFUL << GPIO_AFRH_AFRH0_Pos) /*!< 0x0000000F */\r
+#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFRH0_Msk\r
+#define GPIO_AFRH_AFRH0_0 (0x1UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000001 */\r
+#define GPIO_AFRH_AFRH0_1 (0x2UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000002 */\r
+#define GPIO_AFRH_AFRH0_2 (0x4UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000004 */\r
+#define GPIO_AFRH_AFRH0_3 (0x8UL << GPIO_AFRH_AFRH0_Pos) /*!< 0x00000008 */\r
+#define GPIO_AFRH_AFRH1_Pos (4U)\r
+#define GPIO_AFRH_AFRH1_Msk (0xFUL << GPIO_AFRH_AFRH1_Pos) /*!< 0x000000F0 */\r
+#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFRH1_Msk\r
+#define GPIO_AFRH_AFRH1_0 (0x1UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000010 */\r
+#define GPIO_AFRH_AFRH1_1 (0x2UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000020 */\r
+#define GPIO_AFRH_AFRH1_2 (0x4UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000040 */\r
+#define GPIO_AFRH_AFRH1_3 (0x8UL << GPIO_AFRH_AFRH1_Pos) /*!< 0x00000080 */\r
+#define GPIO_AFRH_AFRH2_Pos (8U)\r
+#define GPIO_AFRH_AFRH2_Msk (0xFUL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000F00 */\r
+#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFRH2_Msk\r
+#define GPIO_AFRH_AFRH2_0 (0x1UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000100 */\r
+#define GPIO_AFRH_AFRH2_1 (0x2UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000200 */\r
+#define GPIO_AFRH_AFRH2_2 (0x4UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000400 */\r
+#define GPIO_AFRH_AFRH2_3 (0x8UL << GPIO_AFRH_AFRH2_Pos) /*!< 0x00000800 */\r
+#define GPIO_AFRH_AFRH3_Pos (12U)\r
+#define GPIO_AFRH_AFRH3_Msk (0xFUL << GPIO_AFRH_AFRH3_Pos) /*!< 0x0000F000 */\r
+#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFRH3_Msk\r
+#define GPIO_AFRH_AFRH3_0 (0x1UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00001000 */\r
+#define GPIO_AFRH_AFRH3_1 (0x2UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00002000 */\r
+#define GPIO_AFRH_AFRH3_2 (0x4UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00004000 */\r
+#define GPIO_AFRH_AFRH3_3 (0x8UL << GPIO_AFRH_AFRH3_Pos) /*!< 0x00008000 */\r
+#define GPIO_AFRH_AFRH4_Pos (16U)\r
+#define GPIO_AFRH_AFRH4_Msk (0xFUL << GPIO_AFRH_AFRH4_Pos) /*!< 0x000F0000 */\r
+#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFRH4_Msk\r
+#define GPIO_AFRH_AFRH4_0 (0x1UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00010000 */\r
+#define GPIO_AFRH_AFRH4_1 (0x2UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00020000 */\r
+#define GPIO_AFRH_AFRH4_2 (0x4UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00040000 */\r
+#define GPIO_AFRH_AFRH4_3 (0x8UL << GPIO_AFRH_AFRH4_Pos) /*!< 0x00080000 */\r
+#define GPIO_AFRH_AFRH5_Pos (20U)\r
+#define GPIO_AFRH_AFRH5_Msk (0xFUL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00F00000 */\r
+#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFRH5_Msk\r
+#define GPIO_AFRH_AFRH5_0 (0x1UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00100000 */\r
+#define GPIO_AFRH_AFRH5_1 (0x2UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00200000 */\r
+#define GPIO_AFRH_AFRH5_2 (0x4UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00400000 */\r
+#define GPIO_AFRH_AFRH5_3 (0x8UL << GPIO_AFRH_AFRH5_Pos) /*!< 0x00800000 */\r
+#define GPIO_AFRH_AFRH6_Pos (24U)\r
+#define GPIO_AFRH_AFRH6_Msk (0xFUL << GPIO_AFRH_AFRH6_Pos) /*!< 0x0F000000 */\r
+#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFRH6_Msk\r
+#define GPIO_AFRH_AFRH6_0 (0x1UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x01000000 */\r
+#define GPIO_AFRH_AFRH6_1 (0x2UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x02000000 */\r
+#define GPIO_AFRH_AFRH6_2 (0x4UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x04000000 */\r
+#define GPIO_AFRH_AFRH6_3 (0x8UL << GPIO_AFRH_AFRH6_Pos) /*!< 0x08000000 */\r
+#define GPIO_AFRH_AFRH7_Pos (28U)\r
+#define GPIO_AFRH_AFRH7_Msk (0xFUL << GPIO_AFRH_AFRH7_Pos) /*!< 0xF0000000 */\r
+#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFRH7_Msk\r
+#define GPIO_AFRH_AFRH7_0 (0x1UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x10000000 */\r
+#define GPIO_AFRH_AFRH7_1 (0x2UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x20000000 */\r
+#define GPIO_AFRH_AFRH7_2 (0x4UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x40000000 */\r
+#define GPIO_AFRH_AFRH7_3 (0x8UL << GPIO_AFRH_AFRH7_Pos) /*!< 0x80000000 */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Inter-integrated Circuit Interface (I2C) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for I2C_CR1 register *******************/\r
+#define I2C_CR1_PE_Pos (0U)\r
+#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */\r
+#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */\r
+#define I2C_CR1_TXIE_Pos (1U)\r
+#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */\r
+#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */\r
+#define I2C_CR1_RXIE_Pos (2U)\r
+#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */\r
+#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */\r
+#define I2C_CR1_ADDRIE_Pos (3U)\r
+#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */\r
+#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */\r
+#define I2C_CR1_NACKIE_Pos (4U)\r
+#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */\r
+#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */\r
+#define I2C_CR1_STOPIE_Pos (5U)\r
+#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */\r
+#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */\r
+#define I2C_CR1_TCIE_Pos (6U)\r
+#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */\r
+#define I2C_CR1_ERRIE_Pos (7U)\r
+#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */\r
+#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */\r
+#define I2C_CR1_DNF_Pos (8U)\r
+#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */\r
+#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */\r
+#define I2C_CR1_ANFOFF_Pos (12U)\r
+#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */\r
+#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */\r
+#define I2C_CR1_TXDMAEN_Pos (14U)\r
+#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */\r
+#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */\r
+#define I2C_CR1_RXDMAEN_Pos (15U)\r
+#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */\r
+#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */\r
+#define I2C_CR1_SBC_Pos (16U)\r
+#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */\r
+#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */\r
+#define I2C_CR1_NOSTRETCH_Pos (17U)\r
+#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */\r
+#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */\r
+#define I2C_CR1_GCEN_Pos (19U)\r
+#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */\r
+#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */\r
+#define I2C_CR1_SMBHEN_Pos (20U)\r
+#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */\r
+#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */\r
+#define I2C_CR1_SMBDEN_Pos (21U)\r
+#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */\r
+#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */\r
+#define I2C_CR1_ALERTEN_Pos (22U)\r
+#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */\r
+#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */\r
+#define I2C_CR1_PECEN_Pos (23U)\r
+#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */\r
+#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */\r
+\r
+\r
+/****************** Bit definition for I2C_CR2 register ********************/\r
+#define I2C_CR2_SADD_Pos (0U)\r
+#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */\r
+#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */\r
+#define I2C_CR2_RD_WRN_Pos (10U)\r
+#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */\r
+#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */\r
+#define I2C_CR2_ADD10_Pos (11U)\r
+#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */\r
+#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */\r
+#define I2C_CR2_HEAD10R_Pos (12U)\r
+#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */\r
+#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */\r
+#define I2C_CR2_START_Pos (13U)\r
+#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */\r
+#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */\r
+#define I2C_CR2_STOP_Pos (14U)\r
+#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */\r
+#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */\r
+#define I2C_CR2_NACK_Pos (15U)\r
+#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */\r
+#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */\r
+#define I2C_CR2_NBYTES_Pos (16U)\r
+#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */\r
+#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */\r
+#define I2C_CR2_RELOAD_Pos (24U)\r
+#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */\r
+#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */\r
+#define I2C_CR2_AUTOEND_Pos (25U)\r
+#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */\r
+#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */\r
+#define I2C_CR2_PECBYTE_Pos (26U)\r
+#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */\r
+#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */\r
+\r
+/******************* Bit definition for I2C_OAR1 register ******************/\r
+#define I2C_OAR1_OA1_Pos (0U)\r
+#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */\r
+#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */\r
+#define I2C_OAR1_OA1MODE_Pos (10U)\r
+#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */\r
+#define I2C_OAR1_OA1EN_Pos (15U)\r
+#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */\r
+\r
+/******************* Bit definition for I2C_OAR2 register ******************/\r
+#define I2C_OAR2_OA2_Pos (1U)\r
+#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */\r
+#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */\r
+#define I2C_OAR2_OA2MSK_Pos (8U)\r
+#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */\r
+#define I2C_OAR2_OA2NOMASK 0x00000000U /*!< No mask */\r
+#define I2C_OAR2_OA2MASK01_Pos (8U)\r
+#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */\r
+#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */\r
+#define I2C_OAR2_OA2MASK02_Pos (9U)\r
+#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */\r
+#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */\r
+#define I2C_OAR2_OA2MASK03_Pos (8U)\r
+#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */\r
+#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */\r
+#define I2C_OAR2_OA2MASK04_Pos (10U)\r
+#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */\r
+#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */\r
+#define I2C_OAR2_OA2MASK05_Pos (8U)\r
+#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */\r
+#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */\r
+#define I2C_OAR2_OA2MASK06_Pos (9U)\r
+#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */\r
+#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */\r
+#define I2C_OAR2_OA2MASK07_Pos (8U)\r
+#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */\r
+#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */\r
+#define I2C_OAR2_OA2EN_Pos (15U)\r
+#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */\r
+#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */\r
+\r
+/******************* Bit definition for I2C_TIMINGR register *******************/\r
+#define I2C_TIMINGR_SCLL_Pos (0U)\r
+#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */\r
+#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */\r
+#define I2C_TIMINGR_SCLH_Pos (8U)\r
+#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */\r
+#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */\r
+#define I2C_TIMINGR_SDADEL_Pos (16U)\r
+#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */\r
+#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */\r
+#define I2C_TIMINGR_SCLDEL_Pos (20U)\r
+#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */\r
+#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */\r
+#define I2C_TIMINGR_PRESC_Pos (28U)\r
+#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */\r
+#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */\r
+\r
+/******************* Bit definition for I2C_TIMEOUTR register *******************/\r
+#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)\r
+#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */\r
+#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */\r
+#define I2C_TIMEOUTR_TIDLE_Pos (12U)\r
+#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */\r
+#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */\r
+#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)\r
+#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */\r
+#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */\r
+#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)\r
+#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */\r
+#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B */\r
+#define I2C_TIMEOUTR_TEXTEN_Pos (31U)\r
+#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */\r
+#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */\r
+\r
+/****************** Bit definition for I2C_ISR register *********************/\r
+#define I2C_ISR_TXE_Pos (0U)\r
+#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */\r
+#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */\r
+#define I2C_ISR_TXIS_Pos (1U)\r
+#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */\r
+#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */\r
+#define I2C_ISR_RXNE_Pos (2U)\r
+#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */\r
+#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */\r
+#define I2C_ISR_ADDR_Pos (3U)\r
+#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */\r
+#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode) */\r
+#define I2C_ISR_NACKF_Pos (4U)\r
+#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */\r
+#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */\r
+#define I2C_ISR_STOPF_Pos (5U)\r
+#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */\r
+#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */\r
+#define I2C_ISR_TC_Pos (6U)\r
+#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */\r
+#define I2C_ISR_TCR_Pos (7U)\r
+#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */\r
+#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */\r
+#define I2C_ISR_BERR_Pos (8U)\r
+#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */\r
+#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */\r
+#define I2C_ISR_ARLO_Pos (9U)\r
+#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */\r
+#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */\r
+#define I2C_ISR_OVR_Pos (10U)\r
+#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */\r
+#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */\r
+#define I2C_ISR_PECERR_Pos (11U)\r
+#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */\r
+#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */\r
+#define I2C_ISR_TIMEOUT_Pos (12U)\r
+#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */\r
+#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */\r
+#define I2C_ISR_ALERT_Pos (13U)\r
+#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */\r
+#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */\r
+#define I2C_ISR_BUSY_Pos (15U)\r
+#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */\r
+#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */\r
+#define I2C_ISR_DIR_Pos (16U)\r
+#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */\r
+#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */\r
+#define I2C_ISR_ADDCODE_Pos (17U)\r
+#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */\r
+#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */\r
+\r
+/****************** Bit definition for I2C_ICR register *********************/\r
+#define I2C_ICR_ADDRCF_Pos (3U)\r
+#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */\r
+#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */\r
+#define I2C_ICR_NACKCF_Pos (4U)\r
+#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */\r
+#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */\r
+#define I2C_ICR_STOPCF_Pos (5U)\r
+#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */\r
+#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */\r
+#define I2C_ICR_BERRCF_Pos (8U)\r
+#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */\r
+#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */\r
+#define I2C_ICR_ARLOCF_Pos (9U)\r
+#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */\r
+#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */\r
+#define I2C_ICR_OVRCF_Pos (10U)\r
+#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */\r
+#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */\r
+#define I2C_ICR_PECCF_Pos (11U)\r
+#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */\r
+#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */\r
+#define I2C_ICR_TIMOUTCF_Pos (12U)\r
+#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */\r
+#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */\r
+#define I2C_ICR_ALERTCF_Pos (13U)\r
+#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */\r
+#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */\r
+\r
+/****************** Bit definition for I2C_PECR register *********************/\r
+#define I2C_PECR_PEC_Pos (0U)\r
+#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */\r
+#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */\r
+\r
+/****************** Bit definition for I2C_RXDR register *********************/\r
+#define I2C_RXDR_RXDATA_Pos (0U)\r
+#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */\r
+\r
+/****************** Bit definition for I2C_TXDR register *********************/\r
+#define I2C_TXDR_TXDATA_Pos (0U)\r
+#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */\r
+#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Independent WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_KR_KEY_Pos (0U)\r
+#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */\r
+#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */\r
+\r
+/******************* Bit definition for IWDG_PR register ********************/\r
+#define IWDG_PR_PR_Pos (0U)\r
+#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */\r
+#define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */\r
+#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x01 */\r
+#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x02 */\r
+#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x04 */\r
+\r
+/******************* Bit definition for IWDG_RLR register *******************/\r
+#define IWDG_RLR_RL_Pos (0U)\r
+#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */\r
+#define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */\r
+\r
+/******************* Bit definition for IWDG_SR register ********************/\r
+#define IWDG_SR_PVU_Pos (0U)\r
+#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */\r
+#define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */\r
+#define IWDG_SR_RVU_Pos (1U)\r
+#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */\r
+#define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */\r
+#define IWDG_SR_WVU_Pos (2U)\r
+#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */\r
+#define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */\r
+\r
+/******************* Bit definition for IWDG_KR register ********************/\r
+#define IWDG_WINR_WIN_Pos (0U)\r
+#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */\r
+#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Power Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for PWR_CR1 register ********************/\r
+#define PWR_CR1_LPDS_Pos (0U)\r
+#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */\r
+#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low-Power Deepsleep */\r
+#define PWR_CR1_PDDS_Pos (1U)\r
+#define PWR_CR1_PDDS_Msk (0x1UL << PWR_CR1_PDDS_Pos) /*!< 0x00000002 */\r
+#define PWR_CR1_PDDS PWR_CR1_PDDS_Msk /*!< Power Down Deepsleep */\r
+#define PWR_CR1_CSBF_Pos (3U)\r
+#define PWR_CR1_CSBF_Msk (0x1UL << PWR_CR1_CSBF_Pos) /*!< 0x00000008 */\r
+#define PWR_CR1_CSBF PWR_CR1_CSBF_Msk /*!< Clear Standby Flag */\r
+#define PWR_CR1_PVDE_Pos (4U)\r
+#define PWR_CR1_PVDE_Msk (0x1UL << PWR_CR1_PVDE_Pos) /*!< 0x00000010 */\r
+#define PWR_CR1_PVDE PWR_CR1_PVDE_Msk /*!< Power Voltage Detector Enable */\r
+#define PWR_CR1_PLS_Pos (5U)\r
+#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */\r
+\r
+/*!< PVD level configuration */\r
+#define PWR_CR1_PLS_LEV0 0x00000000U /*!< PVD level 0 */\r
+#define PWR_CR1_PLS_LEV1_Pos (5U)\r
+#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */\r
+#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */\r
+#define PWR_CR1_PLS_LEV2_Pos (6U)\r
+#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */\r
+#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */\r
+#define PWR_CR1_PLS_LEV3_Pos (5U)\r
+#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */\r
+#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */\r
+#define PWR_CR1_PLS_LEV4_Pos (7U)\r
+#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */\r
+#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */\r
+#define PWR_CR1_PLS_LEV5_Pos (5U)\r
+#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */\r
+#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */\r
+#define PWR_CR1_PLS_LEV6_Pos (6U)\r
+#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */\r
+#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */\r
+#define PWR_CR1_PLS_LEV7_Pos (5U)\r
+#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */\r
+#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */\r
+#define PWR_CR1_DBP_Pos (8U)\r
+#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */\r
+#define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Backup Domain write protection */\r
+#define PWR_CR1_FPDS_Pos (9U)\r
+#define PWR_CR1_FPDS_Msk (0x1UL << PWR_CR1_FPDS_Pos) /*!< 0x00000200 */\r
+#define PWR_CR1_FPDS PWR_CR1_FPDS_Msk /*!< Flash power down in Stop mode */\r
+#define PWR_CR1_LPUDS_Pos (10U)\r
+#define PWR_CR1_LPUDS_Msk (0x1UL << PWR_CR1_LPUDS_Pos) /*!< 0x00000400 */\r
+#define PWR_CR1_LPUDS PWR_CR1_LPUDS_Msk /*!< Low-power regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_MRUDS_Pos (11U)\r
+#define PWR_CR1_MRUDS_Msk (0x1UL << PWR_CR1_MRUDS_Pos) /*!< 0x00000800 */\r
+#define PWR_CR1_MRUDS PWR_CR1_MRUDS_Msk /*!< Main regulator in deepsleep under-drive mode */\r
+#define PWR_CR1_ADCDC1_Pos (13U)\r
+#define PWR_CR1_ADCDC1_Msk (0x1UL << PWR_CR1_ADCDC1_Pos) /*!< 0x00002000 */\r
+#define PWR_CR1_ADCDC1 PWR_CR1_ADCDC1_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define PWR_CR1_VOS_Pos (14U)\r
+#define PWR_CR1_VOS_Msk (0x3UL << PWR_CR1_VOS_Pos) /*!< 0x0000C000 */\r
+#define PWR_CR1_VOS PWR_CR1_VOS_Msk /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define PWR_CR1_VOS_0 (0x1UL << PWR_CR1_VOS_Pos) /*!< 0x00004000 */\r
+#define PWR_CR1_VOS_1 (0x2UL << PWR_CR1_VOS_Pos) /*!< 0x00008000 */\r
+#define PWR_CR1_ODEN_Pos (16U)\r
+#define PWR_CR1_ODEN_Msk (0x1UL << PWR_CR1_ODEN_Pos) /*!< 0x00010000 */\r
+#define PWR_CR1_ODEN PWR_CR1_ODEN_Msk /*!< Over Drive enable */\r
+#define PWR_CR1_ODSWEN_Pos (17U)\r
+#define PWR_CR1_ODSWEN_Msk (0x1UL << PWR_CR1_ODSWEN_Pos) /*!< 0x00020000 */\r
+#define PWR_CR1_ODSWEN PWR_CR1_ODSWEN_Msk /*!< Over Drive switch enabled */\r
+#define PWR_CR1_UDEN_Pos (18U)\r
+#define PWR_CR1_UDEN_Msk (0x3UL << PWR_CR1_UDEN_Pos) /*!< 0x000C0000 */\r
+#define PWR_CR1_UDEN PWR_CR1_UDEN_Msk /*!< Under Drive enable in stop mode */\r
+#define PWR_CR1_UDEN_0 (0x1UL << PWR_CR1_UDEN_Pos) /*!< 0x00040000 */\r
+#define PWR_CR1_UDEN_1 (0x2UL << PWR_CR1_UDEN_Pos) /*!< 0x00080000 */\r
+\r
+/******************* Bit definition for PWR_CSR1 register ********************/\r
+#define PWR_CSR1_WUIF_Pos (0U)\r
+#define PWR_CSR1_WUIF_Msk (0x1UL << PWR_CSR1_WUIF_Pos) /*!< 0x00000001 */\r
+#define PWR_CSR1_WUIF PWR_CSR1_WUIF_Msk /*!< Wake up internal Flag */\r
+#define PWR_CSR1_SBF_Pos (1U)\r
+#define PWR_CSR1_SBF_Msk (0x1UL << PWR_CSR1_SBF_Pos) /*!< 0x00000002 */\r
+#define PWR_CSR1_SBF PWR_CSR1_SBF_Msk /*!< Standby Flag */\r
+#define PWR_CSR1_PVDO_Pos (2U)\r
+#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000004 */\r
+#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< PVD Output */\r
+#define PWR_CSR1_BRR_Pos (3U)\r
+#define PWR_CSR1_BRR_Msk (0x1UL << PWR_CSR1_BRR_Pos) /*!< 0x00000008 */\r
+#define PWR_CSR1_BRR PWR_CSR1_BRR_Msk /*!< Backup regulator ready */\r
+#define PWR_CSR1_EIWUP_Pos (8U)\r
+#define PWR_CSR1_EIWUP_Msk (0x1UL << PWR_CSR1_EIWUP_Pos) /*!< 0x00000100 */\r
+#define PWR_CSR1_EIWUP PWR_CSR1_EIWUP_Msk /*!< Enable internal wakeup */\r
+#define PWR_CSR1_BRE_Pos (9U)\r
+#define PWR_CSR1_BRE_Msk (0x1UL << PWR_CSR1_BRE_Pos) /*!< 0x00000200 */\r
+#define PWR_CSR1_BRE PWR_CSR1_BRE_Msk /*!< Backup regulator enable */\r
+#define PWR_CSR1_VOSRDY_Pos (14U)\r
+#define PWR_CSR1_VOSRDY_Msk (0x1UL << PWR_CSR1_VOSRDY_Pos) /*!< 0x00004000 */\r
+#define PWR_CSR1_VOSRDY PWR_CSR1_VOSRDY_Msk /*!< Regulator voltage scaling output selection ready */\r
+#define PWR_CSR1_ODRDY_Pos (16U)\r
+#define PWR_CSR1_ODRDY_Msk (0x1UL << PWR_CSR1_ODRDY_Pos) /*!< 0x00010000 */\r
+#define PWR_CSR1_ODRDY PWR_CSR1_ODRDY_Msk /*!< Over Drive generator ready */\r
+#define PWR_CSR1_ODSWRDY_Pos (17U)\r
+#define PWR_CSR1_ODSWRDY_Msk (0x1UL << PWR_CSR1_ODSWRDY_Pos) /*!< 0x00020000 */\r
+#define PWR_CSR1_ODSWRDY PWR_CSR1_ODSWRDY_Msk /*!< Over Drive Switch ready */\r
+#define PWR_CSR1_UDRDY_Pos (18U)\r
+#define PWR_CSR1_UDRDY_Msk (0x3UL << PWR_CSR1_UDRDY_Pos) /*!< 0x000C0000 */\r
+#define PWR_CSR1_UDRDY PWR_CSR1_UDRDY_Msk /*!< Under Drive ready */\r
+\r
+\r
+/******************** Bit definition for PWR_CR2 register ********************/\r
+#define PWR_CR2_CWUPF1_Pos (0U)\r
+#define PWR_CR2_CWUPF1_Msk (0x1UL << PWR_CR2_CWUPF1_Pos) /*!< 0x00000001 */\r
+#define PWR_CR2_CWUPF1 PWR_CR2_CWUPF1_Msk /*!< Clear Wakeup Pin Flag for PA0 */\r
+#define PWR_CR2_CWUPF2_Pos (1U)\r
+#define PWR_CR2_CWUPF2_Msk (0x1UL << PWR_CR2_CWUPF2_Pos) /*!< 0x00000002 */\r
+#define PWR_CR2_CWUPF2 PWR_CR2_CWUPF2_Msk /*!< Clear Wakeup Pin Flag for PA2 */\r
+#define PWR_CR2_CWUPF3_Pos (2U)\r
+#define PWR_CR2_CWUPF3_Msk (0x1UL << PWR_CR2_CWUPF3_Pos) /*!< 0x00000004 */\r
+#define PWR_CR2_CWUPF3 PWR_CR2_CWUPF3_Msk /*!< Clear Wakeup Pin Flag for PC1 */\r
+#define PWR_CR2_CWUPF4_Pos (3U)\r
+#define PWR_CR2_CWUPF4_Msk (0x1UL << PWR_CR2_CWUPF4_Pos) /*!< 0x00000008 */\r
+#define PWR_CR2_CWUPF4 PWR_CR2_CWUPF4_Msk /*!< Clear Wakeup Pin Flag for PC13 */\r
+#define PWR_CR2_CWUPF5_Pos (4U)\r
+#define PWR_CR2_CWUPF5_Msk (0x1UL << PWR_CR2_CWUPF5_Pos) /*!< 0x00000010 */\r
+#define PWR_CR2_CWUPF5 PWR_CR2_CWUPF5_Msk /*!< Clear Wakeup Pin Flag for PI8 */\r
+#define PWR_CR2_CWUPF6_Pos (5U)\r
+#define PWR_CR2_CWUPF6_Msk (0x1UL << PWR_CR2_CWUPF6_Pos) /*!< 0x00000020 */\r
+#define PWR_CR2_CWUPF6 PWR_CR2_CWUPF6_Msk /*!< Clear Wakeup Pin Flag for PI11 */\r
+#define PWR_CR2_WUPP1_Pos (8U)\r
+#define PWR_CR2_WUPP1_Msk (0x1UL << PWR_CR2_WUPP1_Pos) /*!< 0x00000100 */\r
+#define PWR_CR2_WUPP1 PWR_CR2_WUPP1_Msk /*!< Wakeup Pin Polarity bit for PA0 */\r
+#define PWR_CR2_WUPP2_Pos (9U)\r
+#define PWR_CR2_WUPP2_Msk (0x1UL << PWR_CR2_WUPP2_Pos) /*!< 0x00000200 */\r
+#define PWR_CR2_WUPP2 PWR_CR2_WUPP2_Msk /*!< Wakeup Pin Polarity bit for PA2 */\r
+#define PWR_CR2_WUPP3_Pos (10U)\r
+#define PWR_CR2_WUPP3_Msk (0x1UL << PWR_CR2_WUPP3_Pos) /*!< 0x00000400 */\r
+#define PWR_CR2_WUPP3 PWR_CR2_WUPP3_Msk /*!< Wakeup Pin Polarity bit for PC1 */\r
+#define PWR_CR2_WUPP4_Pos (11U)\r
+#define PWR_CR2_WUPP4_Msk (0x1UL << PWR_CR2_WUPP4_Pos) /*!< 0x00000800 */\r
+#define PWR_CR2_WUPP4 PWR_CR2_WUPP4_Msk /*!< Wakeup Pin Polarity bit for PC13 */\r
+#define PWR_CR2_WUPP5_Pos (12U)\r
+#define PWR_CR2_WUPP5_Msk (0x1UL << PWR_CR2_WUPP5_Pos) /*!< 0x00001000 */\r
+#define PWR_CR2_WUPP5 PWR_CR2_WUPP5_Msk /*!< Wakeup Pin Polarity bit for PI8 */\r
+#define PWR_CR2_WUPP6_Pos (13U)\r
+#define PWR_CR2_WUPP6_Msk (0x1UL << PWR_CR2_WUPP6_Pos) /*!< 0x00002000 */\r
+#define PWR_CR2_WUPP6 PWR_CR2_WUPP6_Msk /*!< Wakeup Pin Polarity bit for PI11 */\r
+\r
+/******************* Bit definition for PWR_CSR2 register ********************/\r
+#define PWR_CSR2_WUPF1_Pos (0U)\r
+#define PWR_CSR2_WUPF1_Msk (0x1UL << PWR_CSR2_WUPF1_Pos) /*!< 0x00000001 */\r
+#define PWR_CSR2_WUPF1 PWR_CSR2_WUPF1_Msk /*!< Wakeup Pin Flag for PA0 */\r
+#define PWR_CSR2_WUPF2_Pos (1U)\r
+#define PWR_CSR2_WUPF2_Msk (0x1UL << PWR_CSR2_WUPF2_Pos) /*!< 0x00000002 */\r
+#define PWR_CSR2_WUPF2 PWR_CSR2_WUPF2_Msk /*!< Wakeup Pin Flag for PA2 */\r
+#define PWR_CSR2_WUPF3_Pos (2U)\r
+#define PWR_CSR2_WUPF3_Msk (0x1UL << PWR_CSR2_WUPF3_Pos) /*!< 0x00000004 */\r
+#define PWR_CSR2_WUPF3 PWR_CSR2_WUPF3_Msk /*!< Wakeup Pin Flag for PC1 */\r
+#define PWR_CSR2_WUPF4_Pos (3U)\r
+#define PWR_CSR2_WUPF4_Msk (0x1UL << PWR_CSR2_WUPF4_Pos) /*!< 0x00000008 */\r
+#define PWR_CSR2_WUPF4 PWR_CSR2_WUPF4_Msk /*!< Wakeup Pin Flag for PC13 */\r
+#define PWR_CSR2_WUPF5_Pos (4U)\r
+#define PWR_CSR2_WUPF5_Msk (0x1UL << PWR_CSR2_WUPF5_Pos) /*!< 0x00000010 */\r
+#define PWR_CSR2_WUPF5 PWR_CSR2_WUPF5_Msk /*!< Wakeup Pin Flag for PI8 */\r
+#define PWR_CSR2_WUPF6_Pos (5U)\r
+#define PWR_CSR2_WUPF6_Msk (0x1UL << PWR_CSR2_WUPF6_Pos) /*!< 0x00000020 */\r
+#define PWR_CSR2_WUPF6 PWR_CSR2_WUPF6_Msk /*!< Wakeup Pin Flag for PI11 */\r
+#define PWR_CSR2_EWUP1_Pos (8U)\r
+#define PWR_CSR2_EWUP1_Msk (0x1UL << PWR_CSR2_EWUP1_Pos) /*!< 0x00000100 */\r
+#define PWR_CSR2_EWUP1 PWR_CSR2_EWUP1_Msk /*!< Enable Wakeup Pin PA0 */\r
+#define PWR_CSR2_EWUP2_Pos (9U)\r
+#define PWR_CSR2_EWUP2_Msk (0x1UL << PWR_CSR2_EWUP2_Pos) /*!< 0x00000200 */\r
+#define PWR_CSR2_EWUP2 PWR_CSR2_EWUP2_Msk /*!< Enable Wakeup Pin PA2 */\r
+#define PWR_CSR2_EWUP3_Pos (10U)\r
+#define PWR_CSR2_EWUP3_Msk (0x1UL << PWR_CSR2_EWUP3_Pos) /*!< 0x00000400 */\r
+#define PWR_CSR2_EWUP3 PWR_CSR2_EWUP3_Msk /*!< Enable Wakeup Pin PC1 */\r
+#define PWR_CSR2_EWUP4_Pos (11U)\r
+#define PWR_CSR2_EWUP4_Msk (0x1UL << PWR_CSR2_EWUP4_Pos) /*!< 0x00000800 */\r
+#define PWR_CSR2_EWUP4 PWR_CSR2_EWUP4_Msk /*!< Enable Wakeup Pin PC13 */\r
+#define PWR_CSR2_EWUP5_Pos (12U)\r
+#define PWR_CSR2_EWUP5_Msk (0x1UL << PWR_CSR2_EWUP5_Pos) /*!< 0x00001000 */\r
+#define PWR_CSR2_EWUP5 PWR_CSR2_EWUP5_Msk /*!< Enable Wakeup Pin PI8 */\r
+#define PWR_CSR2_EWUP6_Pos (13U)\r
+#define PWR_CSR2_EWUP6_Msk (0x1UL << PWR_CSR2_EWUP6_Pos) /*!< 0x00002000 */\r
+#define PWR_CSR2_EWUP6 PWR_CSR2_EWUP6_Msk /*!< Enable Wakeup Pin PI11 */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* QUADSPI */\r
+/* */\r
+/******************************************************************************/\r
+/***************** Bit definition for QUADSPI_CR register *******************/\r
+#define QUADSPI_CR_EN_Pos (0U)\r
+#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */\r
+#define QUADSPI_CR_ABORT_Pos (1U)\r
+#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */\r
+#define QUADSPI_CR_DMAEN_Pos (2U)\r
+#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */\r
+#define QUADSPI_CR_TCEN_Pos (3U)\r
+#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */\r
+#define QUADSPI_CR_SSHIFT_Pos (4U)\r
+#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< Sample Shift */\r
+#define QUADSPI_CR_DFM_Pos (6U)\r
+#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */\r
+#define QUADSPI_CR_FSEL_Pos (7U)\r
+#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */\r
+#define QUADSPI_CR_FTHRES_Pos (8U)\r
+#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */\r
+#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[4:0] FIFO Level */\r
+#define QUADSPI_CR_FTHRES_0 (0x01UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CR_FTHRES_1 (0x02UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CR_FTHRES_2 (0x04UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CR_FTHRES_3 (0x08UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_CR_TEIE_Pos (16U)\r
+#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */\r
+#define QUADSPI_CR_TCIE_Pos (17U)\r
+#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */\r
+#define QUADSPI_CR_FTIE_Pos (18U)\r
+#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */\r
+#define QUADSPI_CR_SMIE_Pos (19U)\r
+#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */\r
+#define QUADSPI_CR_TOIE_Pos (20U)\r
+#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */\r
+#define QUADSPI_CR_APMS_Pos (22U)\r
+#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */\r
+#define QUADSPI_CR_PMM_Pos (23U)\r
+#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */\r
+#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */\r
+#define QUADSPI_CR_PRESCALER_Pos (24U)\r
+#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */\r
+#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */\r
+#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */\r
+#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */\r
+\r
+/***************** Bit definition for QUADSPI_DCR register ******************/\r
+#define QUADSPI_DCR_CKMODE_Pos (0U)\r
+#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */\r
+#define QUADSPI_DCR_CSHT_Pos (8U)\r
+#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */\r
+#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */\r
+#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_DCR_FSIZE_Pos (16U)\r
+#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */\r
+#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */\r
+#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */\r
+\r
+/****************** Bit definition for QUADSPI_SR register *******************/\r
+#define QUADSPI_SR_TEF_Pos (0U)\r
+#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */\r
+#define QUADSPI_SR_TCF_Pos (1U)\r
+#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */\r
+#define QUADSPI_SR_FTF_Pos (2U)\r
+#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_SMF_Pos (3U)\r
+#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */\r
+#define QUADSPI_SR_TOF_Pos (4U)\r
+#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */\r
+#define QUADSPI_SR_BUSY_Pos (5U)\r
+#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */\r
+#define QUADSPI_SR_FLEVEL_Pos (8U)\r
+#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */\r
+#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */\r
+#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */\r
+\r
+/****************** Bit definition for QUADSPI_FCR register ******************/\r
+#define QUADSPI_FCR_CTEF_Pos (0U)\r
+#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */\r
+#define QUADSPI_FCR_CTCF_Pos (1U)\r
+#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */\r
+#define QUADSPI_FCR_CSMF_Pos (3U)\r
+#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */\r
+#define QUADSPI_FCR_CTOF_Pos (4U)\r
+#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */\r
+\r
+/****************** Bit definition for QUADSPI_DLR register ******************/\r
+#define QUADSPI_DLR_DL_Pos (0U)\r
+#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */\r
+\r
+/****************** Bit definition for QUADSPI_CCR register ******************/\r
+#define QUADSPI_CCR_INSTRUCTION_Pos (0U)\r
+#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */\r
+#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */\r
+#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */\r
+#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */\r
+#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */\r
+#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */\r
+#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */\r
+#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */\r
+#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */\r
+#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */\r
+#define QUADSPI_CCR_IMODE_Pos (8U)\r
+#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */\r
+#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */\r
+#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */\r
+#define QUADSPI_CCR_ADMODE_Pos (10U)\r
+#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */\r
+#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */\r
+#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */\r
+#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */\r
+#define QUADSPI_CCR_ADSIZE_Pos (12U)\r
+#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */\r
+#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */\r
+#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */\r
+#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */\r
+#define QUADSPI_CCR_ABMODE_Pos (14U)\r
+#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */\r
+#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */\r
+#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */\r
+#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */\r
+#define QUADSPI_CCR_ABSIZE_Pos (16U)\r
+#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */\r
+#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */\r
+#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */\r
+#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */\r
+#define QUADSPI_CCR_DCYC_Pos (18U)\r
+#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */\r
+#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */\r
+#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */\r
+#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */\r
+#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */\r
+#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */\r
+#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */\r
+#define QUADSPI_CCR_DMODE_Pos (24U)\r
+#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */\r
+#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */\r
+#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */\r
+#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */\r
+#define QUADSPI_CCR_FMODE_Pos (26U)\r
+#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */\r
+#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */\r
+#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */\r
+#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */\r
+#define QUADSPI_CCR_SIOO_Pos (28U)\r
+#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */\r
+#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */\r
+#define QUADSPI_CCR_DHHC_Pos (30U)\r
+#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */\r
+#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: Delay Half Hclk Cycle */\r
+#define QUADSPI_CCR_DDRM_Pos (31U)\r
+#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */\r
+#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */\r
+/****************** Bit definition for QUADSPI_AR register *******************/\r
+#define QUADSPI_AR_ADDRESS_Pos (0U)\r
+#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */\r
+\r
+/****************** Bit definition for QUADSPI_ABR register ******************/\r
+#define QUADSPI_ABR_ALTERNATE_Pos (0U)\r
+#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */\r
+\r
+/****************** Bit definition for QUADSPI_DR register *******************/\r
+#define QUADSPI_DR_DATA_Pos (0U)\r
+#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */\r
+\r
+/****************** Bit definition for QUADSPI_PSMKR register ****************/\r
+#define QUADSPI_PSMKR_MASK_Pos (0U)\r
+#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */\r
+\r
+/****************** Bit definition for QUADSPI_PSMAR register ****************/\r
+#define QUADSPI_PSMAR_MATCH_Pos (0U)\r
+#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */\r
+#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */\r
+\r
+/****************** Bit definition for QUADSPI_PIR register *****************/\r
+#define QUADSPI_PIR_INTERVAL_Pos (0U)\r
+#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */\r
+\r
+/****************** Bit definition for QUADSPI_LPTR register *****************/\r
+#define QUADSPI_LPTR_TIMEOUT_Pos (0U)\r
+#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */\r
+#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Reset and Clock Control */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for RCC_CR register ********************/\r
+#define RCC_CR_HSION_Pos (0U)\r
+#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CR_HSION RCC_CR_HSION_Msk\r
+#define RCC_CR_HSIRDY_Pos (1U)\r
+#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk\r
+#define RCC_CR_HSITRIM_Pos (3U)\r
+#define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */\r
+#define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk\r
+#define RCC_CR_HSITRIM_0 (0x01UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */\r
+#define RCC_CR_HSITRIM_1 (0x02UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */\r
+#define RCC_CR_HSITRIM_2 (0x04UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */\r
+#define RCC_CR_HSITRIM_3 (0x08UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */\r
+#define RCC_CR_HSITRIM_4 (0x10UL << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */\r
+#define RCC_CR_HSICAL_Pos (8U)\r
+#define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */\r
+#define RCC_CR_HSICAL RCC_CR_HSICAL_Msk\r
+#define RCC_CR_HSICAL_0 (0x01UL << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */\r
+#define RCC_CR_HSICAL_1 (0x02UL << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */\r
+#define RCC_CR_HSICAL_2 (0x04UL << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */\r
+#define RCC_CR_HSICAL_3 (0x08UL << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */\r
+#define RCC_CR_HSICAL_4 (0x10UL << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */\r
+#define RCC_CR_HSICAL_5 (0x20UL << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */\r
+#define RCC_CR_HSICAL_6 (0x40UL << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */\r
+#define RCC_CR_HSICAL_7 (0x80UL << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */\r
+#define RCC_CR_HSEON_Pos (16U)\r
+#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */\r
+#define RCC_CR_HSEON RCC_CR_HSEON_Msk\r
+#define RCC_CR_HSERDY_Pos (17U)\r
+#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */\r
+#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk\r
+#define RCC_CR_HSEBYP_Pos (18U)\r
+#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */\r
+#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk\r
+#define RCC_CR_CSSON_Pos (19U)\r
+#define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */\r
+#define RCC_CR_CSSON RCC_CR_CSSON_Msk\r
+#define RCC_CR_PLLON_Pos (24U)\r
+#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */\r
+#define RCC_CR_PLLON RCC_CR_PLLON_Msk\r
+#define RCC_CR_PLLRDY_Pos (25U)\r
+#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */\r
+#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk\r
+#define RCC_CR_PLLI2SON_Pos (26U)\r
+#define RCC_CR_PLLI2SON_Msk (0x1UL << RCC_CR_PLLI2SON_Pos) /*!< 0x04000000 */\r
+#define RCC_CR_PLLI2SON RCC_CR_PLLI2SON_Msk\r
+#define RCC_CR_PLLI2SRDY_Pos (27U)\r
+#define RCC_CR_PLLI2SRDY_Msk (0x1UL << RCC_CR_PLLI2SRDY_Pos) /*!< 0x08000000 */\r
+#define RCC_CR_PLLI2SRDY RCC_CR_PLLI2SRDY_Msk\r
+#define RCC_CR_PLLSAION_Pos (28U)\r
+#define RCC_CR_PLLSAION_Msk (0x1UL << RCC_CR_PLLSAION_Pos) /*!< 0x10000000 */\r
+#define RCC_CR_PLLSAION RCC_CR_PLLSAION_Msk\r
+#define RCC_CR_PLLSAIRDY_Pos (29U)\r
+#define RCC_CR_PLLSAIRDY_Msk (0x1UL << RCC_CR_PLLSAIRDY_Pos) /*!< 0x20000000 */\r
+#define RCC_CR_PLLSAIRDY RCC_CR_PLLSAIRDY_Msk\r
+\r
+/******************** Bit definition for RCC_PLLCFGR register ***************/\r
+#define RCC_PLLCFGR_PLLM_Pos (0U)\r
+#define RCC_PLLCFGR_PLLM_Msk (0x3FUL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x0000003F */\r
+#define RCC_PLLCFGR_PLLM RCC_PLLCFGR_PLLM_Msk\r
+#define RCC_PLLCFGR_PLLM_0 (0x01UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000001 */\r
+#define RCC_PLLCFGR_PLLM_1 (0x02UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000002 */\r
+#define RCC_PLLCFGR_PLLM_2 (0x04UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000004 */\r
+#define RCC_PLLCFGR_PLLM_3 (0x08UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000008 */\r
+#define RCC_PLLCFGR_PLLM_4 (0x10UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000010 */\r
+#define RCC_PLLCFGR_PLLM_5 (0x20UL << RCC_PLLCFGR_PLLM_Pos) /*!< 0x00000020 */\r
+#define RCC_PLLCFGR_PLLN_Pos (6U)\r
+#define RCC_PLLCFGR_PLLN_Msk (0x1FFUL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLCFGR_PLLN RCC_PLLCFGR_PLLN_Msk\r
+#define RCC_PLLCFGR_PLLN_0 (0x001UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLCFGR_PLLN_1 (0x002UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLCFGR_PLLN_2 (0x004UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLCFGR_PLLN_3 (0x008UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLCFGR_PLLN_4 (0x010UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLCFGR_PLLN_5 (0x020UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLCFGR_PLLP_Pos (16U)\r
+#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */\r
+#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk\r
+#define RCC_PLLCFGR_PLLP_0 (0x1UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLCFGR_PLLP_1 (0x2UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLCFGR_PLLSRC_Pos (22U)\r
+#define RCC_PLLCFGR_PLLSRC_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCFGR_PLLSRC RCC_PLLCFGR_PLLSRC_Msk\r
+#define RCC_PLLCFGR_PLLSRC_HSE_Pos (22U)\r
+#define RCC_PLLCFGR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCFGR_PLLSRC_HSE_Pos) /*!< 0x00400000 */\r
+#define RCC_PLLCFGR_PLLSRC_HSE RCC_PLLCFGR_PLLSRC_HSE_Msk\r
+#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U\r
+#define RCC_PLLCFGR_PLLQ_Pos (24U)\r
+#define RCC_PLLCFGR_PLLQ_Msk (0xFUL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLCFGR_PLLQ RCC_PLLCFGR_PLLQ_Msk\r
+#define RCC_PLLCFGR_PLLQ_0 (0x1UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLCFGR_PLLQ_1 (0x2UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLCFGR_PLLQ_2 (0x4UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLCFGR_PLLQ_3 (0x8UL << RCC_PLLCFGR_PLLQ_Pos) /*!< 0x08000000 */\r
+\r
+\r
+/******************** Bit definition for RCC_CFGR register ******************/\r
+/*!< SW configuration */\r
+#define RCC_CFGR_SW_Pos (0U)\r
+#define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */\r
+#define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */\r
+#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */\r
+#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */\r
+#define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */\r
+#define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */\r
+#define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define RCC_CFGR_SWS_Pos (2U)\r
+#define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */\r
+#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */\r
+#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */\r
+#define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */\r
+#define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */\r
+#define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define RCC_CFGR_HPRE_Pos (4U)\r
+#define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */\r
+#define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */\r
+#define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */\r
+#define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */\r
+#define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */\r
+\r
+#define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */\r
+#define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */\r
+#define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */\r
+#define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */\r
+#define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */\r
+#define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */\r
+#define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */\r
+#define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */\r
+#define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define RCC_CFGR_PPRE1_Pos (10U)\r
+#define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001C00 */\r
+#define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */\r
+#define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000800 */\r
+#define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00001000 */\r
+\r
+#define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE1_DIV2 0x00001000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE1_DIV4 0x00001400U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE1_DIV8 0x00001800U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define RCC_CFGR_PPRE2_Pos (13U)\r
+#define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x0000E000 */\r
+#define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */\r
+#define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00004000 */\r
+#define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00008000 */\r
+\r
+#define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */\r
+#define RCC_CFGR_PPRE2_DIV2 0x00008000U /*!< HCLK divided by 2 */\r
+#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /*!< HCLK divided by 4 */\r
+#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /*!< HCLK divided by 8 */\r
+#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define RCC_CFGR_RTCPRE_Pos (16U)\r
+#define RCC_CFGR_RTCPRE_Msk (0x1FUL << RCC_CFGR_RTCPRE_Pos) /*!< 0x001F0000 */\r
+#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk\r
+#define RCC_CFGR_RTCPRE_0 (0x01UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00010000 */\r
+#define RCC_CFGR_RTCPRE_1 (0x02UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00020000 */\r
+#define RCC_CFGR_RTCPRE_2 (0x04UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00040000 */\r
+#define RCC_CFGR_RTCPRE_3 (0x08UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00080000 */\r
+#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00100000 */\r
+\r
+/*!< MCO1 configuration */\r
+#define RCC_CFGR_MCO1_Pos (21U)\r
+#define RCC_CFGR_MCO1_Msk (0x3UL << RCC_CFGR_MCO1_Pos) /*!< 0x00600000 */\r
+#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk\r
+#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00200000 */\r
+#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */\r
+\r
+#define RCC_CFGR_I2SSRC_Pos (23U)\r
+#define RCC_CFGR_I2SSRC_Msk (0x1UL << RCC_CFGR_I2SSRC_Pos) /*!< 0x00800000 */\r
+#define RCC_CFGR_I2SSRC RCC_CFGR_I2SSRC_Msk\r
+\r
+#define RCC_CFGR_MCO1PRE_Pos (24U)\r
+#define RCC_CFGR_MCO1PRE_Msk (0x7UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x07000000 */\r
+#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk\r
+#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x01000000 */\r
+#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x02000000 */\r
+#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x04000000 */\r
+\r
+#define RCC_CFGR_MCO2PRE_Pos (27U)\r
+#define RCC_CFGR_MCO2PRE_Msk (0x7UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x38000000 */\r
+#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk\r
+#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */\r
+#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */\r
+#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x20000000 */\r
+\r
+#define RCC_CFGR_MCO2_Pos (30U)\r
+#define RCC_CFGR_MCO2_Msk (0x3UL << RCC_CFGR_MCO2_Pos) /*!< 0xC0000000 */\r
+#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk\r
+#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */\r
+#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for RCC_CIR register *******************/\r
+#define RCC_CIR_LSIRDYF_Pos (0U)\r
+#define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */\r
+#define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk\r
+#define RCC_CIR_LSERDYF_Pos (1U)\r
+#define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */\r
+#define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk\r
+#define RCC_CIR_HSIRDYF_Pos (2U)\r
+#define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */\r
+#define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk\r
+#define RCC_CIR_HSERDYF_Pos (3U)\r
+#define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */\r
+#define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk\r
+#define RCC_CIR_PLLRDYF_Pos (4U)\r
+#define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */\r
+#define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk\r
+#define RCC_CIR_PLLI2SRDYF_Pos (5U)\r
+#define RCC_CIR_PLLI2SRDYF_Msk (0x1UL << RCC_CIR_PLLI2SRDYF_Pos) /*!< 0x00000020 */\r
+#define RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF_Msk\r
+#define RCC_CIR_PLLSAIRDYF_Pos (6U)\r
+#define RCC_CIR_PLLSAIRDYF_Msk (0x1UL << RCC_CIR_PLLSAIRDYF_Pos) /*!< 0x00000040 */\r
+#define RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF_Msk\r
+#define RCC_CIR_CSSF_Pos (7U)\r
+#define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */\r
+#define RCC_CIR_CSSF RCC_CIR_CSSF_Msk\r
+#define RCC_CIR_LSIRDYIE_Pos (8U)\r
+#define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */\r
+#define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk\r
+#define RCC_CIR_LSERDYIE_Pos (9U)\r
+#define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */\r
+#define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk\r
+#define RCC_CIR_HSIRDYIE_Pos (10U)\r
+#define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */\r
+#define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk\r
+#define RCC_CIR_HSERDYIE_Pos (11U)\r
+#define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */\r
+#define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk\r
+#define RCC_CIR_PLLRDYIE_Pos (12U)\r
+#define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */\r
+#define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk\r
+#define RCC_CIR_PLLI2SRDYIE_Pos (13U)\r
+#define RCC_CIR_PLLI2SRDYIE_Msk (0x1UL << RCC_CIR_PLLI2SRDYIE_Pos) /*!< 0x00002000 */\r
+#define RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE_Msk\r
+#define RCC_CIR_PLLSAIRDYIE_Pos (14U)\r
+#define RCC_CIR_PLLSAIRDYIE_Msk (0x1UL << RCC_CIR_PLLSAIRDYIE_Pos) /*!< 0x00004000 */\r
+#define RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE_Msk\r
+#define RCC_CIR_LSIRDYC_Pos (16U)\r
+#define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */\r
+#define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk\r
+#define RCC_CIR_LSERDYC_Pos (17U)\r
+#define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */\r
+#define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk\r
+#define RCC_CIR_HSIRDYC_Pos (18U)\r
+#define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */\r
+#define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk\r
+#define RCC_CIR_HSERDYC_Pos (19U)\r
+#define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */\r
+#define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk\r
+#define RCC_CIR_PLLRDYC_Pos (20U)\r
+#define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */\r
+#define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk\r
+#define RCC_CIR_PLLI2SRDYC_Pos (21U)\r
+#define RCC_CIR_PLLI2SRDYC_Msk (0x1UL << RCC_CIR_PLLI2SRDYC_Pos) /*!< 0x00200000 */\r
+#define RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC_Msk\r
+#define RCC_CIR_PLLSAIRDYC_Pos (22U)\r
+#define RCC_CIR_PLLSAIRDYC_Msk (0x1UL << RCC_CIR_PLLSAIRDYC_Pos) /*!< 0x00400000 */\r
+#define RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC_Msk\r
+#define RCC_CIR_CSSC_Pos (23U)\r
+#define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */\r
+#define RCC_CIR_CSSC RCC_CIR_CSSC_Msk\r
+\r
+/******************** Bit definition for RCC_AHB1RSTR register **************/\r
+#define RCC_AHB1RSTR_GPIOARST_Pos (0U)\r
+#define RCC_AHB1RSTR_GPIOARST_Msk (0x1UL << RCC_AHB1RSTR_GPIOARST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1RSTR_GPIOARST RCC_AHB1RSTR_GPIOARST_Msk\r
+#define RCC_AHB1RSTR_GPIOBRST_Pos (1U)\r
+#define RCC_AHB1RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOBRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1RSTR_GPIOBRST RCC_AHB1RSTR_GPIOBRST_Msk\r
+#define RCC_AHB1RSTR_GPIOCRST_Pos (2U)\r
+#define RCC_AHB1RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOCRST_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1RSTR_GPIOCRST RCC_AHB1RSTR_GPIOCRST_Msk\r
+#define RCC_AHB1RSTR_GPIODRST_Pos (3U)\r
+#define RCC_AHB1RSTR_GPIODRST_Msk (0x1UL << RCC_AHB1RSTR_GPIODRST_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1RSTR_GPIODRST RCC_AHB1RSTR_GPIODRST_Msk\r
+#define RCC_AHB1RSTR_GPIOERST_Pos (4U)\r
+#define RCC_AHB1RSTR_GPIOERST_Msk (0x1UL << RCC_AHB1RSTR_GPIOERST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1RSTR_GPIOERST RCC_AHB1RSTR_GPIOERST_Msk\r
+#define RCC_AHB1RSTR_GPIOFRST_Pos (5U)\r
+#define RCC_AHB1RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOFRST_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1RSTR_GPIOFRST RCC_AHB1RSTR_GPIOFRST_Msk\r
+#define RCC_AHB1RSTR_GPIOGRST_Pos (6U)\r
+#define RCC_AHB1RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1RSTR_GPIOGRST RCC_AHB1RSTR_GPIOGRST_Msk\r
+#define RCC_AHB1RSTR_GPIOHRST_Pos (7U)\r
+#define RCC_AHB1RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOHRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1RSTR_GPIOHRST RCC_AHB1RSTR_GPIOHRST_Msk\r
+#define RCC_AHB1RSTR_GPIOIRST_Pos (8U)\r
+#define RCC_AHB1RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB1RSTR_GPIOIRST_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1RSTR_GPIOIRST RCC_AHB1RSTR_GPIOIRST_Msk\r
+#define RCC_AHB1RSTR_CRCRST_Pos (12U)\r
+#define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk\r
+#define RCC_AHB1RSTR_DMA1RST_Pos (21U)\r
+#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk\r
+#define RCC_AHB1RSTR_DMA2RST_Pos (22U)\r
+#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk\r
+#define RCC_AHB1RSTR_OTGHRST_Pos (29U)\r
+#define RCC_AHB1RSTR_OTGHRST_Msk (0x1UL << RCC_AHB1RSTR_OTGHRST_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1RSTR_OTGHRST RCC_AHB1RSTR_OTGHRST_Msk\r
+\r
+/******************** Bit definition for RCC_AHB2RSTR register **************/\r
+#define RCC_AHB2RSTR_AESRST_Pos (4U)\r
+#define RCC_AHB2RSTR_AESRST_Msk (0x1UL << RCC_AHB2RSTR_AESRST_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2RSTR_AESRST RCC_AHB2RSTR_AESRST_Msk\r
+#define RCC_AHB2RSTR_RNGRST_Pos (6U)\r
+#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk\r
+#define RCC_AHB2RSTR_OTGFSRST_Pos (7U)\r
+#define RCC_AHB2RSTR_OTGFSRST_Msk (0x1UL << RCC_AHB2RSTR_OTGFSRST_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2RSTR_OTGFSRST RCC_AHB2RSTR_OTGFSRST_Msk\r
+\r
+/******************** Bit definition for RCC_AHB3RSTR register **************/\r
+\r
+#define RCC_AHB3RSTR_FMCRST_Pos (0U)\r
+#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk\r
+#define RCC_AHB3RSTR_QSPIRST_Pos (1U)\r
+#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk\r
+\r
+/******************** Bit definition for RCC_APB1RSTR register **************/\r
+#define RCC_APB1RSTR_TIM2RST_Pos (0U)\r
+#define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk\r
+#define RCC_APB1RSTR_TIM3RST_Pos (1U)\r
+#define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk\r
+#define RCC_APB1RSTR_TIM4RST_Pos (2U)\r
+#define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk\r
+#define RCC_APB1RSTR_TIM5RST_Pos (3U)\r
+#define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk\r
+#define RCC_APB1RSTR_TIM6RST_Pos (4U)\r
+#define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk\r
+#define RCC_APB1RSTR_TIM7RST_Pos (5U)\r
+#define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk\r
+#define RCC_APB1RSTR_TIM12RST_Pos (6U)\r
+#define RCC_APB1RSTR_TIM12RST_Msk (0x1UL << RCC_APB1RSTR_TIM12RST_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1RSTR_TIM12RST RCC_APB1RSTR_TIM12RST_Msk\r
+#define RCC_APB1RSTR_TIM13RST_Pos (7U)\r
+#define RCC_APB1RSTR_TIM13RST_Msk (0x1UL << RCC_APB1RSTR_TIM13RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1RSTR_TIM13RST RCC_APB1RSTR_TIM13RST_Msk\r
+#define RCC_APB1RSTR_TIM14RST_Pos (8U)\r
+#define RCC_APB1RSTR_TIM14RST_Msk (0x1UL << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk\r
+#define RCC_APB1RSTR_LPTIM1RST_Pos (9U)\r
+#define RCC_APB1RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1RSTR_LPTIM1RST_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1RSTR_LPTIM1RST RCC_APB1RSTR_LPTIM1RST_Msk\r
+#define RCC_APB1RSTR_WWDGRST_Pos (11U)\r
+#define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk\r
+#define RCC_APB1RSTR_SPI2RST_Pos (14U)\r
+#define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk\r
+#define RCC_APB1RSTR_SPI3RST_Pos (15U)\r
+#define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk\r
+#define RCC_APB1RSTR_USART2RST_Pos (17U)\r
+#define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk\r
+#define RCC_APB1RSTR_USART3RST_Pos (18U)\r
+#define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk\r
+#define RCC_APB1RSTR_UART4RST_Pos (19U)\r
+#define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk\r
+#define RCC_APB1RSTR_UART5RST_Pos (20U)\r
+#define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk\r
+#define RCC_APB1RSTR_I2C1RST_Pos (21U)\r
+#define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk\r
+#define RCC_APB1RSTR_I2C2RST_Pos (22U)\r
+#define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk\r
+#define RCC_APB1RSTR_I2C3RST_Pos (23U)\r
+#define RCC_APB1RSTR_I2C3RST_Msk (0x1UL << RCC_APB1RSTR_I2C3RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1RSTR_I2C3RST RCC_APB1RSTR_I2C3RST_Msk\r
+#define RCC_APB1RSTR_CAN1RST_Pos (25U)\r
+#define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk\r
+#define RCC_APB1RSTR_PWRRST_Pos (28U)\r
+#define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk\r
+#define RCC_APB1RSTR_DACRST_Pos (29U)\r
+#define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk\r
+#define RCC_APB1RSTR_UART7RST_Pos (30U)\r
+#define RCC_APB1RSTR_UART7RST_Msk (0x1UL << RCC_APB1RSTR_UART7RST_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1RSTR_UART7RST RCC_APB1RSTR_UART7RST_Msk\r
+#define RCC_APB1RSTR_UART8RST_Pos (31U)\r
+#define RCC_APB1RSTR_UART8RST_Msk (0x1UL << RCC_APB1RSTR_UART8RST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1RSTR_UART8RST RCC_APB1RSTR_UART8RST_Msk\r
+\r
+/******************** Bit definition for RCC_APB2RSTR register **************/\r
+#define RCC_APB2RSTR_TIM1RST_Pos (0U)\r
+#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk\r
+#define RCC_APB2RSTR_TIM8RST_Pos (1U)\r
+#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk\r
+#define RCC_APB2RSTR_USART1RST_Pos (4U)\r
+#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk\r
+#define RCC_APB2RSTR_USART6RST_Pos (5U)\r
+#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk\r
+#define RCC_APB2RSTR_SDMMC2RST_Pos (7U)\r
+#define RCC_APB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC2RST_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2RSTR_SDMMC2RST RCC_APB2RSTR_SDMMC2RST_Msk\r
+#define RCC_APB2RSTR_ADCRST_Pos (8U)\r
+#define RCC_APB2RSTR_ADCRST_Msk (0x1UL << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk\r
+#define RCC_APB2RSTR_SDMMC1RST_Pos (11U)\r
+#define RCC_APB2RSTR_SDMMC1RST_Msk (0x1UL << RCC_APB2RSTR_SDMMC1RST_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2RSTR_SDMMC1RST RCC_APB2RSTR_SDMMC1RST_Msk\r
+#define RCC_APB2RSTR_SPI1RST_Pos (12U)\r
+#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk\r
+#define RCC_APB2RSTR_SPI4RST_Pos (13U)\r
+#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk\r
+#define RCC_APB2RSTR_SYSCFGRST_Pos (14U)\r
+#define RCC_APB2RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk\r
+#define RCC_APB2RSTR_TIM9RST_Pos (16U)\r
+#define RCC_APB2RSTR_TIM9RST_Msk (0x1UL << RCC_APB2RSTR_TIM9RST_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2RSTR_TIM9RST RCC_APB2RSTR_TIM9RST_Msk\r
+#define RCC_APB2RSTR_TIM10RST_Pos (17U)\r
+#define RCC_APB2RSTR_TIM10RST_Msk (0x1UL << RCC_APB2RSTR_TIM10RST_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2RSTR_TIM10RST RCC_APB2RSTR_TIM10RST_Msk\r
+#define RCC_APB2RSTR_TIM11RST_Pos (18U)\r
+#define RCC_APB2RSTR_TIM11RST_Msk (0x1UL << RCC_APB2RSTR_TIM11RST_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2RSTR_TIM11RST RCC_APB2RSTR_TIM11RST_Msk\r
+#define RCC_APB2RSTR_SPI5RST_Pos (20U)\r
+#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk\r
+#define RCC_APB2RSTR_SAI1RST_Pos (22U)\r
+#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk\r
+#define RCC_APB2RSTR_SAI2RST_Pos (23U)\r
+#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk\r
+#define RCC_APB2RSTR_OTGPHYCRST_Pos (31U)\r
+#define RCC_APB2RSTR_OTGPHYCRST_Msk (0x1UL << RCC_APB2RSTR_OTGPHYCRST_Pos) /*!< 0x80000000 */\r
+#define RCC_APB2RSTR_OTGPHYCRST RCC_APB2RSTR_OTGPHYCRST_Msk\r
+\r
+/******************** Bit definition for RCC_AHB1ENR register ***************/\r
+#define RCC_AHB1ENR_GPIOAEN_Pos (0U)\r
+#define RCC_AHB1ENR_GPIOAEN_Msk (0x1UL << RCC_AHB1ENR_GPIOAEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1ENR_GPIOAEN RCC_AHB1ENR_GPIOAEN_Msk\r
+#define RCC_AHB1ENR_GPIOBEN_Pos (1U)\r
+#define RCC_AHB1ENR_GPIOBEN_Msk (0x1UL << RCC_AHB1ENR_GPIOBEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1ENR_GPIOBEN RCC_AHB1ENR_GPIOBEN_Msk\r
+#define RCC_AHB1ENR_GPIOCEN_Pos (2U)\r
+#define RCC_AHB1ENR_GPIOCEN_Msk (0x1UL << RCC_AHB1ENR_GPIOCEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1ENR_GPIOCEN RCC_AHB1ENR_GPIOCEN_Msk\r
+#define RCC_AHB1ENR_GPIODEN_Pos (3U)\r
+#define RCC_AHB1ENR_GPIODEN_Msk (0x1UL << RCC_AHB1ENR_GPIODEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1ENR_GPIODEN RCC_AHB1ENR_GPIODEN_Msk\r
+#define RCC_AHB1ENR_GPIOEEN_Pos (4U)\r
+#define RCC_AHB1ENR_GPIOEEN_Msk (0x1UL << RCC_AHB1ENR_GPIOEEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1ENR_GPIOEEN RCC_AHB1ENR_GPIOEEN_Msk\r
+#define RCC_AHB1ENR_GPIOFEN_Pos (5U)\r
+#define RCC_AHB1ENR_GPIOFEN_Msk (0x1UL << RCC_AHB1ENR_GPIOFEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1ENR_GPIOFEN RCC_AHB1ENR_GPIOFEN_Msk\r
+#define RCC_AHB1ENR_GPIOGEN_Pos (6U)\r
+#define RCC_AHB1ENR_GPIOGEN_Msk (0x1UL << RCC_AHB1ENR_GPIOGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1ENR_GPIOGEN RCC_AHB1ENR_GPIOGEN_Msk\r
+#define RCC_AHB1ENR_GPIOHEN_Pos (7U)\r
+#define RCC_AHB1ENR_GPIOHEN_Msk (0x1UL << RCC_AHB1ENR_GPIOHEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1ENR_GPIOHEN RCC_AHB1ENR_GPIOHEN_Msk\r
+#define RCC_AHB1ENR_GPIOIEN_Pos (8U)\r
+#define RCC_AHB1ENR_GPIOIEN_Msk (0x1UL << RCC_AHB1ENR_GPIOIEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1ENR_GPIOIEN RCC_AHB1ENR_GPIOIEN_Msk\r
+#define RCC_AHB1ENR_CRCEN_Pos (12U)\r
+#define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk\r
+#define RCC_AHB1ENR_BKPSRAMEN_Pos (18U)\r
+#define RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk\r
+#define RCC_AHB1ENR_DTCMRAMEN_Pos (20U)\r
+#define RCC_AHB1ENR_DTCMRAMEN_Msk (0x1UL << RCC_AHB1ENR_DTCMRAMEN_Pos) /*!< 0x00100000 */\r
+#define RCC_AHB1ENR_DTCMRAMEN RCC_AHB1ENR_DTCMRAMEN_Msk\r
+#define RCC_AHB1ENR_DMA1EN_Pos (21U)\r
+#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk\r
+#define RCC_AHB1ENR_DMA2EN_Pos (22U)\r
+#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk\r
+#define RCC_AHB1ENR_OTGHSEN_Pos (29U)\r
+#define RCC_AHB1ENR_OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1ENR_OTGHSEN RCC_AHB1ENR_OTGHSEN_Msk\r
+#define RCC_AHB1ENR_OTGHSULPIEN_Pos (30U)\r
+#define RCC_AHB1ENR_OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_OTGHSULPIEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB1ENR_OTGHSULPIEN RCC_AHB1ENR_OTGHSULPIEN_Msk\r
+\r
+/******************** Bit definition for RCC_AHB2ENR register ***************/\r
+#define RCC_AHB2ENR_AESEN_Pos (4U)\r
+#define RCC_AHB2ENR_AESEN_Msk (0x1UL << RCC_AHB2ENR_AESEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2ENR_AESEN RCC_AHB2ENR_AESEN_Msk\r
+#define RCC_AHB2ENR_RNGEN_Pos (6U)\r
+#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk\r
+#define RCC_AHB2ENR_OTGFSEN_Pos (7U)\r
+#define RCC_AHB2ENR_OTGFSEN_Msk (0x1UL << RCC_AHB2ENR_OTGFSEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2ENR_OTGFSEN RCC_AHB2ENR_OTGFSEN_Msk\r
+\r
+/******************** Bit definition for RCC_AHB3ENR register ***************/\r
+#define RCC_AHB3ENR_FMCEN_Pos (0U)\r
+#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk\r
+#define RCC_AHB3ENR_QSPIEN_Pos (1U)\r
+#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB1ENR register ***************/\r
+#define RCC_APB1ENR_TIM2EN_Pos (0U)\r
+#define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk\r
+#define RCC_APB1ENR_TIM3EN_Pos (1U)\r
+#define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk\r
+#define RCC_APB1ENR_TIM4EN_Pos (2U)\r
+#define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk\r
+#define RCC_APB1ENR_TIM5EN_Pos (3U)\r
+#define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk\r
+#define RCC_APB1ENR_TIM6EN_Pos (4U)\r
+#define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk\r
+#define RCC_APB1ENR_TIM7EN_Pos (5U)\r
+#define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk\r
+#define RCC_APB1ENR_TIM12EN_Pos (6U)\r
+#define RCC_APB1ENR_TIM12EN_Msk (0x1UL << RCC_APB1ENR_TIM12EN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1ENR_TIM12EN RCC_APB1ENR_TIM12EN_Msk\r
+#define RCC_APB1ENR_TIM13EN_Pos (7U)\r
+#define RCC_APB1ENR_TIM13EN_Msk (0x1UL << RCC_APB1ENR_TIM13EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1ENR_TIM13EN RCC_APB1ENR_TIM13EN_Msk\r
+#define RCC_APB1ENR_TIM14EN_Pos (8U)\r
+#define RCC_APB1ENR_TIM14EN_Msk (0x1UL << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk\r
+#define RCC_APB1ENR_LPTIM1EN_Pos (9U)\r
+#define RCC_APB1ENR_LPTIM1EN_Msk (0x1UL << RCC_APB1ENR_LPTIM1EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1ENR_LPTIM1EN RCC_APB1ENR_LPTIM1EN_Msk\r
+#define RCC_APB1ENR_RTCEN_Pos (10U)\r
+#define RCC_APB1ENR_RTCEN_Msk (0x1UL << RCC_APB1ENR_RTCEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB1ENR_RTCEN RCC_APB1ENR_RTCEN_Msk\r
+#define RCC_APB1ENR_WWDGEN_Pos (11U)\r
+#define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk\r
+#define RCC_APB1ENR_SPI2EN_Pos (14U)\r
+#define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk\r
+#define RCC_APB1ENR_SPI3EN_Pos (15U)\r
+#define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk\r
+#define RCC_APB1ENR_USART2EN_Pos (17U)\r
+#define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk\r
+#define RCC_APB1ENR_USART3EN_Pos (18U)\r
+#define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk\r
+#define RCC_APB1ENR_UART4EN_Pos (19U)\r
+#define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk\r
+#define RCC_APB1ENR_UART5EN_Pos (20U)\r
+#define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk\r
+#define RCC_APB1ENR_I2C1EN_Pos (21U)\r
+#define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk\r
+#define RCC_APB1ENR_I2C2EN_Pos (22U)\r
+#define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk\r
+#define RCC_APB1ENR_I2C3EN_Pos (23U)\r
+#define RCC_APB1ENR_I2C3EN_Msk (0x1UL << RCC_APB1ENR_I2C3EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1ENR_I2C3EN RCC_APB1ENR_I2C3EN_Msk\r
+#define RCC_APB1ENR_CAN1EN_Pos (25U)\r
+#define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk\r
+#define RCC_APB1ENR_PWREN_Pos (28U)\r
+#define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk\r
+#define RCC_APB1ENR_DACEN_Pos (29U)\r
+#define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk\r
+#define RCC_APB1ENR_UART7EN_Pos (30U)\r
+#define RCC_APB1ENR_UART7EN_Msk (0x1UL << RCC_APB1ENR_UART7EN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1ENR_UART7EN RCC_APB1ENR_UART7EN_Msk\r
+#define RCC_APB1ENR_UART8EN_Pos (31U)\r
+#define RCC_APB1ENR_UART8EN_Msk (0x1UL << RCC_APB1ENR_UART8EN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1ENR_UART8EN RCC_APB1ENR_UART8EN_Msk\r
+\r
+/******************** Bit definition for RCC_APB2ENR register ***************/\r
+#define RCC_APB2ENR_TIM1EN_Pos (0U)\r
+#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk\r
+#define RCC_APB2ENR_TIM8EN_Pos (1U)\r
+#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk\r
+#define RCC_APB2ENR_USART1EN_Pos (4U)\r
+#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk\r
+#define RCC_APB2ENR_USART6EN_Pos (5U)\r
+#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk\r
+#define RCC_APB2ENR_SDMMC2EN_Pos (7U)\r
+#define RCC_APB2ENR_SDMMC2EN_Msk (0x1UL << RCC_APB2ENR_SDMMC2EN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2ENR_SDMMC2EN RCC_APB2ENR_SDMMC2EN_Msk\r
+#define RCC_APB2ENR_ADC1EN_Pos (8U)\r
+#define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk\r
+#define RCC_APB2ENR_ADC2EN_Pos (9U)\r
+#define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk\r
+#define RCC_APB2ENR_ADC3EN_Pos (10U)\r
+#define RCC_APB2ENR_ADC3EN_Msk (0x1UL << RCC_APB2ENR_ADC3EN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2ENR_ADC3EN RCC_APB2ENR_ADC3EN_Msk\r
+#define RCC_APB2ENR_SDMMC1EN_Pos (11U)\r
+#define RCC_APB2ENR_SDMMC1EN_Msk (0x1UL << RCC_APB2ENR_SDMMC1EN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2ENR_SDMMC1EN RCC_APB2ENR_SDMMC1EN_Msk\r
+#define RCC_APB2ENR_SPI1EN_Pos (12U)\r
+#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk\r
+#define RCC_APB2ENR_SPI4EN_Pos (13U)\r
+#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk\r
+#define RCC_APB2ENR_SYSCFGEN_Pos (14U)\r
+#define RCC_APB2ENR_SYSCFGEN_Msk (0x1UL << RCC_APB2ENR_SYSCFGEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGEN_Msk\r
+#define RCC_APB2ENR_TIM9EN_Pos (16U)\r
+#define RCC_APB2ENR_TIM9EN_Msk (0x1UL << RCC_APB2ENR_TIM9EN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2ENR_TIM9EN RCC_APB2ENR_TIM9EN_Msk\r
+#define RCC_APB2ENR_TIM10EN_Pos (17U)\r
+#define RCC_APB2ENR_TIM10EN_Msk (0x1UL << RCC_APB2ENR_TIM10EN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2ENR_TIM10EN RCC_APB2ENR_TIM10EN_Msk\r
+#define RCC_APB2ENR_TIM11EN_Pos (18U)\r
+#define RCC_APB2ENR_TIM11EN_Msk (0x1UL << RCC_APB2ENR_TIM11EN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2ENR_TIM11EN RCC_APB2ENR_TIM11EN_Msk\r
+#define RCC_APB2ENR_SPI5EN_Pos (20U)\r
+#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk\r
+#define RCC_APB2ENR_SAI1EN_Pos (22U)\r
+#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk\r
+#define RCC_APB2ENR_SAI2EN_Pos (23U)\r
+#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk\r
+#define RCC_APB2ENR_OTGPHYCEN_Pos (31U)\r
+#define RCC_APB2ENR_OTGPHYCEN_Msk (0x1UL << RCC_APB2ENR_OTGPHYCEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB2ENR_OTGPHYCEN RCC_APB2ENR_OTGPHYCEN_Msk\r
+\r
+/******************** Bit definition for RCC_AHB1LPENR register *************/\r
+#define RCC_AHB1LPENR_GPIOALPEN_Pos (0U)\r
+#define RCC_AHB1LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB1LPENR_GPIOALPEN RCC_AHB1LPENR_GPIOALPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOBLPEN_Pos (1U)\r
+#define RCC_AHB1LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB1LPENR_GPIOBLPEN RCC_AHB1LPENR_GPIOBLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOCLPEN_Pos (2U)\r
+#define RCC_AHB1LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_AHB1LPENR_GPIOCLPEN RCC_AHB1LPENR_GPIOCLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIODLPEN_Pos (3U)\r
+#define RCC_AHB1LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_AHB1LPENR_GPIODLPEN RCC_AHB1LPENR_GPIODLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOELPEN_Pos (4U)\r
+#define RCC_AHB1LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB1LPENR_GPIOELPEN RCC_AHB1LPENR_GPIOELPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOFLPEN_Pos (5U)\r
+#define RCC_AHB1LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_AHB1LPENR_GPIOFLPEN RCC_AHB1LPENR_GPIOFLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOGLPEN_Pos (6U)\r
+#define RCC_AHB1LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB1LPENR_GPIOGLPEN RCC_AHB1LPENR_GPIOGLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOHLPEN_Pos (7U)\r
+#define RCC_AHB1LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB1LPENR_GPIOHLPEN RCC_AHB1LPENR_GPIOHLPEN_Msk\r
+#define RCC_AHB1LPENR_GPIOILPEN_Pos (8U)\r
+#define RCC_AHB1LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB1LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_AHB1LPENR_GPIOILPEN RCC_AHB1LPENR_GPIOILPEN_Msk\r
+#define RCC_AHB1LPENR_CRCLPEN_Pos (12U)\r
+#define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk\r
+#define RCC_AHB1LPENR_AXILPEN_Pos (13U)\r
+#define RCC_AHB1LPENR_AXILPEN_Msk (0x1UL << RCC_AHB1LPENR_AXILPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_AHB1LPENR_AXILPEN RCC_AHB1LPENR_AXILPEN_Msk\r
+#define RCC_AHB1LPENR_FLITFLPEN_Pos (15U)\r
+#define RCC_AHB1LPENR_FLITFLPEN_Msk (0x1UL << RCC_AHB1LPENR_FLITFLPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_AHB1LPENR_FLITFLPEN RCC_AHB1LPENR_FLITFLPEN_Msk\r
+#define RCC_AHB1LPENR_SRAM1LPEN_Pos (16U)\r
+#define RCC_AHB1LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM1LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_AHB1LPENR_SRAM1LPEN RCC_AHB1LPENR_SRAM1LPEN_Msk\r
+#define RCC_AHB1LPENR_SRAM2LPEN_Pos (17U)\r
+#define RCC_AHB1LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB1LPENR_SRAM2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_AHB1LPENR_SRAM2LPEN RCC_AHB1LPENR_SRAM2LPEN_Msk\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Pos (18U)\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN_Msk (0x1UL << RCC_AHB1LPENR_BKPSRAMLPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_AHB1LPENR_BKPSRAMLPEN RCC_AHB1LPENR_BKPSRAMLPEN_Msk\r
+#define RCC_AHB1LPENR_DTCMLPEN_Pos (20U)\r
+#define RCC_AHB1LPENR_DTCMLPEN_Msk (0x1UL << RCC_AHB1LPENR_DTCMLPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_AHB1LPENR_DTCMLPEN RCC_AHB1LPENR_DTCMLPEN_Msk\r
+#define RCC_AHB1LPENR_DMA1LPEN_Pos (21U)\r
+#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk\r
+#define RCC_AHB1LPENR_DMA2LPEN_Pos (22U)\r
+#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk\r
+#define RCC_AHB1LPENR_OTGHSLPEN_Pos (29U)\r
+#define RCC_AHB1LPENR_OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_AHB1LPENR_OTGHSLPEN RCC_AHB1LPENR_OTGHSLPEN_Msk\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Pos (30U)\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_OTGHSULPILPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_AHB1LPENR_OTGHSULPILPEN RCC_AHB1LPENR_OTGHSULPILPEN_Msk\r
+\r
+/******************** Bit definition for RCC_AHB2LPENR register *************/\r
+#define RCC_AHB2LPENR_AESLPEN_Pos (4U)\r
+#define RCC_AHB2LPENR_AESLPEN_Msk (0x1UL << RCC_AHB2LPENR_AESLPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_AHB2LPENR_AESLPEN RCC_AHB2LPENR_AESLPEN_Msk\r
+#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)\r
+#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk\r
+#define RCC_AHB2LPENR_OTGFSLPEN_Pos (7U)\r
+#define RCC_AHB2LPENR_OTGFSLPEN_Msk (0x1UL << RCC_AHB2LPENR_OTGFSLPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_AHB2LPENR_OTGFSLPEN RCC_AHB2LPENR_OTGFSLPEN_Msk\r
+\r
+/******************** Bit definition for RCC_AHB3LPENR register *************/\r
+#define RCC_AHB3LPENR_FMCLPEN_Pos (0U)\r
+#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk\r
+#define RCC_AHB3LPENR_QSPILPEN_Pos (1U)\r
+#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk\r
+/******************** Bit definition for RCC_APB1LPENR register *************/\r
+#define RCC_APB1LPENR_TIM2LPEN_Pos (0U)\r
+#define RCC_APB1LPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM2LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB1LPENR_TIM2LPEN RCC_APB1LPENR_TIM2LPEN_Msk\r
+#define RCC_APB1LPENR_TIM3LPEN_Pos (1U)\r
+#define RCC_APB1LPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM3LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB1LPENR_TIM3LPEN RCC_APB1LPENR_TIM3LPEN_Msk\r
+#define RCC_APB1LPENR_TIM4LPEN_Pos (2U)\r
+#define RCC_APB1LPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM4LPEN_Pos) /*!< 0x00000004 */\r
+#define RCC_APB1LPENR_TIM4LPEN RCC_APB1LPENR_TIM4LPEN_Msk\r
+#define RCC_APB1LPENR_TIM5LPEN_Pos (3U)\r
+#define RCC_APB1LPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM5LPEN_Pos) /*!< 0x00000008 */\r
+#define RCC_APB1LPENR_TIM5LPEN RCC_APB1LPENR_TIM5LPEN_Msk\r
+#define RCC_APB1LPENR_TIM6LPEN_Pos (4U)\r
+#define RCC_APB1LPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM6LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB1LPENR_TIM6LPEN RCC_APB1LPENR_TIM6LPEN_Msk\r
+#define RCC_APB1LPENR_TIM7LPEN_Pos (5U)\r
+#define RCC_APB1LPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM7LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB1LPENR_TIM7LPEN RCC_APB1LPENR_TIM7LPEN_Msk\r
+#define RCC_APB1LPENR_TIM12LPEN_Pos (6U)\r
+#define RCC_APB1LPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM12LPEN_Pos) /*!< 0x00000040 */\r
+#define RCC_APB1LPENR_TIM12LPEN RCC_APB1LPENR_TIM12LPEN_Msk\r
+#define RCC_APB1LPENR_TIM13LPEN_Pos (7U)\r
+#define RCC_APB1LPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM13LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB1LPENR_TIM13LPEN RCC_APB1LPENR_TIM13LPEN_Msk\r
+#define RCC_APB1LPENR_TIM14LPEN_Pos (8U)\r
+#define RCC_APB1LPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LPENR_TIM14LPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB1LPENR_TIM14LPEN RCC_APB1LPENR_TIM14LPEN_Msk\r
+#define RCC_APB1LPENR_LPTIM1LPEN_Pos (9U)\r
+#define RCC_APB1LPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB1LPENR_LPTIM1LPEN RCC_APB1LPENR_LPTIM1LPEN_Msk\r
+#define RCC_APB1LPENR_RTCLPEN_Pos (10U)\r
+#define RCC_APB1LPENR_RTCLPEN_Msk (0x1UL << RCC_APB1LPENR_RTCLPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB1LPENR_RTCLPEN RCC_APB1LPENR_RTCLPEN_Msk\r
+#define RCC_APB1LPENR_WWDGLPEN_Pos (11U)\r
+#define RCC_APB1LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB1LPENR_WWDGLPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB1LPENR_WWDGLPEN RCC_APB1LPENR_WWDGLPEN_Msk\r
+#define RCC_APB1LPENR_SPI2LPEN_Pos (14U)\r
+#define RCC_APB1LPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI2LPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB1LPENR_SPI2LPEN RCC_APB1LPENR_SPI2LPEN_Msk\r
+#define RCC_APB1LPENR_SPI3LPEN_Pos (15U)\r
+#define RCC_APB1LPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LPENR_SPI3LPEN_Pos) /*!< 0x00008000 */\r
+#define RCC_APB1LPENR_SPI3LPEN RCC_APB1LPENR_SPI3LPEN_Msk\r
+#define RCC_APB1LPENR_USART2LPEN_Pos (17U)\r
+#define RCC_APB1LPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LPENR_USART2LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB1LPENR_USART2LPEN RCC_APB1LPENR_USART2LPEN_Msk\r
+#define RCC_APB1LPENR_USART3LPEN_Pos (18U)\r
+#define RCC_APB1LPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LPENR_USART3LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB1LPENR_USART3LPEN RCC_APB1LPENR_USART3LPEN_Msk\r
+#define RCC_APB1LPENR_UART4LPEN_Pos (19U)\r
+#define RCC_APB1LPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LPENR_UART4LPEN_Pos) /*!< 0x00080000 */\r
+#define RCC_APB1LPENR_UART4LPEN RCC_APB1LPENR_UART4LPEN_Msk\r
+#define RCC_APB1LPENR_UART5LPEN_Pos (20U)\r
+#define RCC_APB1LPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LPENR_UART5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB1LPENR_UART5LPEN RCC_APB1LPENR_UART5LPEN_Msk\r
+#define RCC_APB1LPENR_I2C1LPEN_Pos (21U)\r
+#define RCC_APB1LPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C1LPEN_Pos) /*!< 0x00200000 */\r
+#define RCC_APB1LPENR_I2C1LPEN RCC_APB1LPENR_I2C1LPEN_Msk\r
+#define RCC_APB1LPENR_I2C2LPEN_Pos (22U)\r
+#define RCC_APB1LPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C2LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB1LPENR_I2C2LPEN RCC_APB1LPENR_I2C2LPEN_Msk\r
+#define RCC_APB1LPENR_I2C3LPEN_Pos (23U)\r
+#define RCC_APB1LPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LPENR_I2C3LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB1LPENR_I2C3LPEN RCC_APB1LPENR_I2C3LPEN_Msk\r
+#define RCC_APB1LPENR_CAN1LPEN_Pos (25U)\r
+#define RCC_APB1LPENR_CAN1LPEN_Msk (0x1UL << RCC_APB1LPENR_CAN1LPEN_Pos) /*!< 0x02000000 */\r
+#define RCC_APB1LPENR_CAN1LPEN RCC_APB1LPENR_CAN1LPEN_Msk\r
+#define RCC_APB1LPENR_PWRLPEN_Pos (28U)\r
+#define RCC_APB1LPENR_PWRLPEN_Msk (0x1UL << RCC_APB1LPENR_PWRLPEN_Pos) /*!< 0x10000000 */\r
+#define RCC_APB1LPENR_PWRLPEN RCC_APB1LPENR_PWRLPEN_Msk\r
+#define RCC_APB1LPENR_DACLPEN_Pos (29U)\r
+#define RCC_APB1LPENR_DACLPEN_Msk (0x1UL << RCC_APB1LPENR_DACLPEN_Pos) /*!< 0x20000000 */\r
+#define RCC_APB1LPENR_DACLPEN RCC_APB1LPENR_DACLPEN_Msk\r
+#define RCC_APB1LPENR_UART7LPEN_Pos (30U)\r
+#define RCC_APB1LPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LPENR_UART7LPEN_Pos) /*!< 0x40000000 */\r
+#define RCC_APB1LPENR_UART7LPEN RCC_APB1LPENR_UART7LPEN_Msk\r
+#define RCC_APB1LPENR_UART8LPEN_Pos (31U)\r
+#define RCC_APB1LPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LPENR_UART8LPEN_Pos) /*!< 0x80000000 */\r
+#define RCC_APB1LPENR_UART8LPEN RCC_APB1LPENR_UART8LPEN_Msk\r
+\r
+/******************** Bit definition for RCC_APB2LPENR register *************/\r
+#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)\r
+#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */\r
+#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk\r
+#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)\r
+#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */\r
+#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk\r
+#define RCC_APB2LPENR_USART1LPEN_Pos (4U)\r
+#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */\r
+#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk\r
+#define RCC_APB2LPENR_USART6LPEN_Pos (5U)\r
+#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */\r
+#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk\r
+#define RCC_APB2LPENR_SDMMC2LPEN_Pos (7U)\r
+#define RCC_APB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000080 */\r
+#define RCC_APB2LPENR_SDMMC2LPEN RCC_APB2LPENR_SDMMC2LPEN_Msk\r
+#define RCC_APB2LPENR_ADC1LPEN_Pos (8U)\r
+#define RCC_APB2LPENR_ADC1LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC1LPEN_Pos) /*!< 0x00000100 */\r
+#define RCC_APB2LPENR_ADC1LPEN RCC_APB2LPENR_ADC1LPEN_Msk\r
+#define RCC_APB2LPENR_ADC2LPEN_Pos (9U)\r
+#define RCC_APB2LPENR_ADC2LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC2LPEN_Pos) /*!< 0x00000200 */\r
+#define RCC_APB2LPENR_ADC2LPEN RCC_APB2LPENR_ADC2LPEN_Msk\r
+#define RCC_APB2LPENR_ADC3LPEN_Pos (10U)\r
+#define RCC_APB2LPENR_ADC3LPEN_Msk (0x1UL << RCC_APB2LPENR_ADC3LPEN_Pos) /*!< 0x00000400 */\r
+#define RCC_APB2LPENR_ADC3LPEN RCC_APB2LPENR_ADC3LPEN_Msk\r
+#define RCC_APB2LPENR_SDMMC1LPEN_Pos (11U)\r
+#define RCC_APB2LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_APB2LPENR_SDMMC1LPEN_Pos) /*!< 0x00000800 */\r
+#define RCC_APB2LPENR_SDMMC1LPEN RCC_APB2LPENR_SDMMC1LPEN_Msk\r
+#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)\r
+#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */\r
+#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk\r
+#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)\r
+#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */\r
+#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk\r
+#define RCC_APB2LPENR_SYSCFGLPEN_Pos (14U)\r
+#define RCC_APB2LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB2LPENR_SYSCFGLPEN_Pos) /*!< 0x00004000 */\r
+#define RCC_APB2LPENR_SYSCFGLPEN RCC_APB2LPENR_SYSCFGLPEN_Msk\r
+#define RCC_APB2LPENR_TIM9LPEN_Pos (16U)\r
+#define RCC_APB2LPENR_TIM9LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM9LPEN_Pos) /*!< 0x00010000 */\r
+#define RCC_APB2LPENR_TIM9LPEN RCC_APB2LPENR_TIM9LPEN_Msk\r
+#define RCC_APB2LPENR_TIM10LPEN_Pos (17U)\r
+#define RCC_APB2LPENR_TIM10LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM10LPEN_Pos) /*!< 0x00020000 */\r
+#define RCC_APB2LPENR_TIM10LPEN RCC_APB2LPENR_TIM10LPEN_Msk\r
+#define RCC_APB2LPENR_TIM11LPEN_Pos (18U)\r
+#define RCC_APB2LPENR_TIM11LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM11LPEN_Pos) /*!< 0x00040000 */\r
+#define RCC_APB2LPENR_TIM11LPEN RCC_APB2LPENR_TIM11LPEN_Msk\r
+#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)\r
+#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */\r
+#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk\r
+#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)\r
+#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */\r
+#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk\r
+#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)\r
+#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */\r
+#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk\r
+\r
+/******************** Bit definition for RCC_BDCR register ******************/\r
+#define RCC_BDCR_LSEON_Pos (0U)\r
+#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */\r
+#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk\r
+#define RCC_BDCR_LSERDY_Pos (1U)\r
+#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */\r
+#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk\r
+#define RCC_BDCR_LSEBYP_Pos (2U)\r
+#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */\r
+#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk\r
+#define RCC_BDCR_LSEDRV_Pos (3U)\r
+#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */\r
+#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk\r
+#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */\r
+#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */\r
+#define RCC_BDCR_RTCSEL_Pos (8U)\r
+#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */\r
+#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk\r
+#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */\r
+#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */\r
+#define RCC_BDCR_RTCEN_Pos (15U)\r
+#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */\r
+#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk\r
+#define RCC_BDCR_BDRST_Pos (16U)\r
+#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */\r
+#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk\r
+\r
+/******************** Bit definition for RCC_CSR register *******************/\r
+#define RCC_CSR_LSION_Pos (0U)\r
+#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */\r
+#define RCC_CSR_LSION RCC_CSR_LSION_Msk\r
+#define RCC_CSR_LSIRDY_Pos (1U)\r
+#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */\r
+#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk\r
+#define RCC_CSR_RMVF_Pos (24U)\r
+#define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */\r
+#define RCC_CSR_RMVF RCC_CSR_RMVF_Msk\r
+#define RCC_CSR_BORRSTF_Pos (25U)\r
+#define RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) /*!< 0x02000000 */\r
+#define RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk\r
+#define RCC_CSR_PINRSTF_Pos (26U)\r
+#define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */\r
+#define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk\r
+#define RCC_CSR_PORRSTF_Pos (27U)\r
+#define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */\r
+#define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk\r
+#define RCC_CSR_SFTRSTF_Pos (28U)\r
+#define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */\r
+#define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk\r
+#define RCC_CSR_IWDGRSTF_Pos (29U)\r
+#define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */\r
+#define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk\r
+#define RCC_CSR_WWDGRSTF_Pos (30U)\r
+#define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */\r
+#define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk\r
+#define RCC_CSR_LPWRRSTF_Pos (31U)\r
+#define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */\r
+#define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk\r
+\r
+/******************** Bit definition for RCC_SSCGR register *****************/\r
+#define RCC_SSCGR_MODPER_Pos (0U)\r
+#define RCC_SSCGR_MODPER_Msk (0x1FFFUL << RCC_SSCGR_MODPER_Pos) /*!< 0x00001FFF */\r
+#define RCC_SSCGR_MODPER RCC_SSCGR_MODPER_Msk\r
+#define RCC_SSCGR_INCSTEP_Pos (13U)\r
+#define RCC_SSCGR_INCSTEP_Msk (0x7FFFUL << RCC_SSCGR_INCSTEP_Pos) /*!< 0x0FFFE000 */\r
+#define RCC_SSCGR_INCSTEP RCC_SSCGR_INCSTEP_Msk\r
+#define RCC_SSCGR_SPREADSEL_Pos (30U)\r
+#define RCC_SSCGR_SPREADSEL_Msk (0x1UL << RCC_SSCGR_SPREADSEL_Pos) /*!< 0x40000000 */\r
+#define RCC_SSCGR_SPREADSEL RCC_SSCGR_SPREADSEL_Msk\r
+#define RCC_SSCGR_SSCGEN_Pos (31U)\r
+#define RCC_SSCGR_SSCGEN_Msk (0x1UL << RCC_SSCGR_SSCGEN_Pos) /*!< 0x80000000 */\r
+#define RCC_SSCGR_SSCGEN RCC_SSCGR_SSCGEN_Msk\r
+\r
+/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
+#define RCC_PLLI2SCFGR_PLLI2SN_Pos (6U)\r
+#define RCC_PLLI2SCFGR_PLLI2SN_Msk (0x1FFUL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN_Msk\r
+#define RCC_PLLI2SCFGR_PLLI2SN_0 (0x001UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_1 (0x002UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_2 (0x004UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_3 (0x008UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_4 (0x010UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_5 (0x020UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_6 (0x040UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_7 (0x080UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SN_8 (0x100UL << RCC_PLLI2SCFGR_PLLI2SN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_Pos (24U)\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_Msk (0xFUL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ_Msk\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SQ_3 (0x8UL << RCC_PLLI2SCFGR_PLLI2SQ_Pos) /*!< 0x08000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_Pos (28U)\r
+#define RCC_PLLI2SCFGR_PLLI2SR_Msk (0x7UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x70000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR_Msk\r
+#define RCC_PLLI2SCFGR_PLLI2SR_0 (0x1UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x10000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_1 (0x2UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x20000000 */\r
+#define RCC_PLLI2SCFGR_PLLI2SR_2 (0x4UL << RCC_PLLI2SCFGR_PLLI2SR_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
+#define RCC_PLLSAICFGR_PLLSAIN_Pos (6U)\r
+#define RCC_PLLSAICFGR_PLLSAIN_Msk (0x1FFUL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00007FC0 */\r
+#define RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN_Msk\r
+#define RCC_PLLSAICFGR_PLLSAIN_0 (0x001UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000040 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_1 (0x002UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000080 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_2 (0x004UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000100 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_3 (0x008UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000200 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_4 (0x010UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000400 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_5 (0x020UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00000800 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_6 (0x040UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00001000 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_7 (0x080UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00002000 */\r
+#define RCC_PLLSAICFGR_PLLSAIN_8 (0x100UL << RCC_PLLSAICFGR_PLLSAIN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP_Pos (16U)\r
+#define RCC_PLLSAICFGR_PLLSAIP_Msk (0x3UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00030000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP_Msk\r
+#define RCC_PLLSAICFGR_PLLSAIP_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00010000 */\r
+#define RCC_PLLSAICFGR_PLLSAIP_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIP_Pos) /*!< 0x00020000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_Pos (24U)\r
+#define RCC_PLLSAICFGR_PLLSAIQ_Msk (0xFUL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x0F000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ_Msk\r
+#define RCC_PLLSAICFGR_PLLSAIQ_0 (0x1UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x01000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_1 (0x2UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x02000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_2 (0x4UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x04000000 */\r
+#define RCC_PLLSAICFGR_PLLSAIQ_3 (0x8UL << RCC_PLLSAICFGR_PLLSAIQ_Pos) /*!< 0x08000000 */\r
+\r
+/******************** Bit definition for RCC_DCKCFGR1 register ***************/\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_Pos (0U)\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x0000001F */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ_Msk\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000001 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000002 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000004 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000008 */\r
+#define RCC_DCKCFGR1_PLLI2SDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLI2SDIVQ_Pos) /*!< 0x00000010 */\r
+\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_Pos (8U)\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_Msk (0x1FUL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001F00 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ_Msk\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_0 (0x01UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000100 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_1 (0x02UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000200 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_2 (0x04UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000400 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_3 (0x08UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00000800 */\r
+#define RCC_DCKCFGR1_PLLSAIDIVQ_4 (0x10UL << RCC_DCKCFGR1_PLLSAIDIVQ_Pos) /*!< 0x00001000 */\r
+\r
+\r
+#define RCC_DCKCFGR1_SAI1SEL_Pos (20U)\r
+#define RCC_DCKCFGR1_SAI1SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00300000 */\r
+#define RCC_DCKCFGR1_SAI1SEL RCC_DCKCFGR1_SAI1SEL_Msk\r
+#define RCC_DCKCFGR1_SAI1SEL_0 (0x1UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00100000 */\r
+#define RCC_DCKCFGR1_SAI1SEL_1 (0x2UL << RCC_DCKCFGR1_SAI1SEL_Pos) /*!< 0x00200000 */\r
+\r
+#define RCC_DCKCFGR1_SAI2SEL_Pos (22U)\r
+#define RCC_DCKCFGR1_SAI2SEL_Msk (0x3UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00C00000 */\r
+#define RCC_DCKCFGR1_SAI2SEL RCC_DCKCFGR1_SAI2SEL_Msk\r
+#define RCC_DCKCFGR1_SAI2SEL_0 (0x1UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00400000 */\r
+#define RCC_DCKCFGR1_SAI2SEL_1 (0x2UL << RCC_DCKCFGR1_SAI2SEL_Pos) /*!< 0x00800000 */\r
+\r
+#define RCC_DCKCFGR1_TIMPRE_Pos (24U)\r
+#define RCC_DCKCFGR1_TIMPRE_Msk (0x1UL << RCC_DCKCFGR1_TIMPRE_Pos) /*!< 0x01000000 */\r
+#define RCC_DCKCFGR1_TIMPRE RCC_DCKCFGR1_TIMPRE_Msk\r
+\r
+/******************** Bit definition for RCC_DCKCFGR2 register ***************/\r
+#define RCC_DCKCFGR2_USART1SEL_Pos (0U)\r
+#define RCC_DCKCFGR2_USART1SEL_Msk (0x3UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000003 */\r
+#define RCC_DCKCFGR2_USART1SEL RCC_DCKCFGR2_USART1SEL_Msk\r
+#define RCC_DCKCFGR2_USART1SEL_0 (0x1UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000001 */\r
+#define RCC_DCKCFGR2_USART1SEL_1 (0x2UL << RCC_DCKCFGR2_USART1SEL_Pos) /*!< 0x00000002 */\r
+#define RCC_DCKCFGR2_USART2SEL_Pos (2U)\r
+#define RCC_DCKCFGR2_USART2SEL_Msk (0x3UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x0000000C */\r
+#define RCC_DCKCFGR2_USART2SEL RCC_DCKCFGR2_USART2SEL_Msk\r
+#define RCC_DCKCFGR2_USART2SEL_0 (0x1UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000004 */\r
+#define RCC_DCKCFGR2_USART2SEL_1 (0x2UL << RCC_DCKCFGR2_USART2SEL_Pos) /*!< 0x00000008 */\r
+#define RCC_DCKCFGR2_USART3SEL_Pos (4U)\r
+#define RCC_DCKCFGR2_USART3SEL_Msk (0x3UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000030 */\r
+#define RCC_DCKCFGR2_USART3SEL RCC_DCKCFGR2_USART3SEL_Msk\r
+#define RCC_DCKCFGR2_USART3SEL_0 (0x1UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000010 */\r
+#define RCC_DCKCFGR2_USART3SEL_1 (0x2UL << RCC_DCKCFGR2_USART3SEL_Pos) /*!< 0x00000020 */\r
+#define RCC_DCKCFGR2_UART4SEL_Pos (6U)\r
+#define RCC_DCKCFGR2_UART4SEL_Msk (0x3UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x000000C0 */\r
+#define RCC_DCKCFGR2_UART4SEL RCC_DCKCFGR2_UART4SEL_Msk\r
+#define RCC_DCKCFGR2_UART4SEL_0 (0x1UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000040 */\r
+#define RCC_DCKCFGR2_UART4SEL_1 (0x2UL << RCC_DCKCFGR2_UART4SEL_Pos) /*!< 0x00000080 */\r
+#define RCC_DCKCFGR2_UART5SEL_Pos (8U)\r
+#define RCC_DCKCFGR2_UART5SEL_Msk (0x3UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000300 */\r
+#define RCC_DCKCFGR2_UART5SEL RCC_DCKCFGR2_UART5SEL_Msk\r
+#define RCC_DCKCFGR2_UART5SEL_0 (0x1UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000100 */\r
+#define RCC_DCKCFGR2_UART5SEL_1 (0x2UL << RCC_DCKCFGR2_UART5SEL_Pos) /*!< 0x00000200 */\r
+#define RCC_DCKCFGR2_USART6SEL_Pos (10U)\r
+#define RCC_DCKCFGR2_USART6SEL_Msk (0x3UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000C00 */\r
+#define RCC_DCKCFGR2_USART6SEL RCC_DCKCFGR2_USART6SEL_Msk\r
+#define RCC_DCKCFGR2_USART6SEL_0 (0x1UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000400 */\r
+#define RCC_DCKCFGR2_USART6SEL_1 (0x2UL << RCC_DCKCFGR2_USART6SEL_Pos) /*!< 0x00000800 */\r
+#define RCC_DCKCFGR2_UART7SEL_Pos (12U)\r
+#define RCC_DCKCFGR2_UART7SEL_Msk (0x3UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00003000 */\r
+#define RCC_DCKCFGR2_UART7SEL RCC_DCKCFGR2_UART7SEL_Msk\r
+#define RCC_DCKCFGR2_UART7SEL_0 (0x1UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00001000 */\r
+#define RCC_DCKCFGR2_UART7SEL_1 (0x2UL << RCC_DCKCFGR2_UART7SEL_Pos) /*!< 0x00002000 */\r
+#define RCC_DCKCFGR2_UART8SEL_Pos (14U)\r
+#define RCC_DCKCFGR2_UART8SEL_Msk (0x3UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x0000C000 */\r
+#define RCC_DCKCFGR2_UART8SEL RCC_DCKCFGR2_UART8SEL_Msk\r
+#define RCC_DCKCFGR2_UART8SEL_0 (0x1UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00004000 */\r
+#define RCC_DCKCFGR2_UART8SEL_1 (0x2UL << RCC_DCKCFGR2_UART8SEL_Pos) /*!< 0x00008000 */\r
+#define RCC_DCKCFGR2_I2C1SEL_Pos (16U)\r
+#define RCC_DCKCFGR2_I2C1SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00030000 */\r
+#define RCC_DCKCFGR2_I2C1SEL RCC_DCKCFGR2_I2C1SEL_Msk\r
+#define RCC_DCKCFGR2_I2C1SEL_0 (0x1UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00010000 */\r
+#define RCC_DCKCFGR2_I2C1SEL_1 (0x2UL << RCC_DCKCFGR2_I2C1SEL_Pos) /*!< 0x00020000 */\r
+#define RCC_DCKCFGR2_I2C2SEL_Pos (18U)\r
+#define RCC_DCKCFGR2_I2C2SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x000C0000 */\r
+#define RCC_DCKCFGR2_I2C2SEL RCC_DCKCFGR2_I2C2SEL_Msk\r
+#define RCC_DCKCFGR2_I2C2SEL_0 (0x1UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00040000 */\r
+#define RCC_DCKCFGR2_I2C2SEL_1 (0x2UL << RCC_DCKCFGR2_I2C2SEL_Pos) /*!< 0x00080000 */\r
+#define RCC_DCKCFGR2_I2C3SEL_Pos (20U)\r
+#define RCC_DCKCFGR2_I2C3SEL_Msk (0x3UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00300000 */\r
+#define RCC_DCKCFGR2_I2C3SEL RCC_DCKCFGR2_I2C3SEL_Msk\r
+#define RCC_DCKCFGR2_I2C3SEL_0 (0x1UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00100000 */\r
+#define RCC_DCKCFGR2_I2C3SEL_1 (0x2UL << RCC_DCKCFGR2_I2C3SEL_Pos) /*!< 0x00200000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL_Pos (24U)\r
+#define RCC_DCKCFGR2_LPTIM1SEL_Msk (0x3UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x03000000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL RCC_DCKCFGR2_LPTIM1SEL_Msk\r
+#define RCC_DCKCFGR2_LPTIM1SEL_0 (0x1UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x01000000 */\r
+#define RCC_DCKCFGR2_LPTIM1SEL_1 (0x2UL << RCC_DCKCFGR2_LPTIM1SEL_Pos) /*!< 0x02000000 */\r
+#define RCC_DCKCFGR2_CK48MSEL_Pos (27U)\r
+#define RCC_DCKCFGR2_CK48MSEL_Msk (0x1UL << RCC_DCKCFGR2_CK48MSEL_Pos) /*!< 0x08000000 */\r
+#define RCC_DCKCFGR2_CK48MSEL RCC_DCKCFGR2_CK48MSEL_Msk\r
+#define RCC_DCKCFGR2_SDMMC1SEL_Pos (28U)\r
+#define RCC_DCKCFGR2_SDMMC1SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC1SEL_Pos) /*!< 0x10000000 */\r
+#define RCC_DCKCFGR2_SDMMC1SEL RCC_DCKCFGR2_SDMMC1SEL_Msk\r
+#define RCC_DCKCFGR2_SDMMC2SEL_Pos (29U)\r
+#define RCC_DCKCFGR2_SDMMC2SEL_Msk (0x1UL << RCC_DCKCFGR2_SDMMC2SEL_Pos) /*!< 0x20000000 */\r
+#define RCC_DCKCFGR2_SDMMC2SEL RCC_DCKCFGR2_SDMMC2SEL_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* RNG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RNG_CR register *******************/\r
+#define RNG_CR_RNGEN_Pos (2U)\r
+#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */\r
+#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk\r
+#define RNG_CR_IE_Pos (3U)\r
+#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */\r
+#define RNG_CR_IE RNG_CR_IE_Msk\r
+\r
+/******************** Bits definition for RNG_SR register *******************/\r
+#define RNG_SR_DRDY_Pos (0U)\r
+#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */\r
+#define RNG_SR_DRDY RNG_SR_DRDY_Msk\r
+#define RNG_SR_CECS_Pos (1U)\r
+#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */\r
+#define RNG_SR_CECS RNG_SR_CECS_Msk\r
+#define RNG_SR_SECS_Pos (2U)\r
+#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */\r
+#define RNG_SR_SECS RNG_SR_SECS_Msk\r
+#define RNG_SR_CEIS_Pos (5U)\r
+#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */\r
+#define RNG_SR_CEIS RNG_SR_CEIS_Msk\r
+#define RNG_SR_SEIS_Pos (6U)\r
+#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */\r
+#define RNG_SR_SEIS RNG_SR_SEIS_Msk\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Real-Time Clock (RTC) */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bits definition for RTC_TR register *******************/\r
+#define RTC_TR_PM_Pos (22U)\r
+#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TR_PM RTC_TR_PM_Msk\r
+#define RTC_TR_HT_Pos (20U)\r
+#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TR_HT RTC_TR_HT_Msk\r
+#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TR_HU_Pos (16U)\r
+#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TR_HU RTC_TR_HU_Msk\r
+#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TR_MNT_Pos (12U)\r
+#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TR_MNT RTC_TR_MNT_Msk\r
+#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TR_MNU_Pos (8U)\r
+#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TR_MNU RTC_TR_MNU_Msk\r
+#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TR_ST_Pos (4U)\r
+#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TR_ST RTC_TR_ST_Msk\r
+#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TR_SU_Pos (0U)\r
+#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TR_SU RTC_TR_SU_Msk\r
+#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_DR register *******************/\r
+#define RTC_DR_YT_Pos (20U)\r
+#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */\r
+#define RTC_DR_YT RTC_DR_YT_Msk\r
+#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */\r
+#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */\r
+#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */\r
+#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */\r
+#define RTC_DR_YU_Pos (16U)\r
+#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */\r
+#define RTC_DR_YU RTC_DR_YU_Msk\r
+#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */\r
+#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */\r
+#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */\r
+#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */\r
+#define RTC_DR_WDU_Pos (13U)\r
+#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_DR_WDU RTC_DR_WDU_Msk\r
+#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_DR_MT_Pos (12U)\r
+#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_DR_MT RTC_DR_MT_Msk\r
+#define RTC_DR_MU_Pos (8U)\r
+#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_DR_MU RTC_DR_MU_Msk\r
+#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_DR_DT_Pos (4U)\r
+#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_DR_DT RTC_DR_DT_Msk\r
+#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_DR_DU_Pos (0U)\r
+#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_DR_DU RTC_DR_DU_Msk\r
+#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_CR register *******************/\r
+#define RTC_CR_ITSE_Pos (24U)\r
+#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */\r
+#define RTC_CR_ITSE RTC_CR_ITSE_Msk\r
+#define RTC_CR_COE_Pos (23U)\r
+#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */\r
+#define RTC_CR_COE RTC_CR_COE_Msk\r
+#define RTC_CR_OSEL_Pos (21U)\r
+#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */\r
+#define RTC_CR_OSEL RTC_CR_OSEL_Msk\r
+#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */\r
+#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */\r
+#define RTC_CR_POL_Pos (20U)\r
+#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */\r
+#define RTC_CR_POL RTC_CR_POL_Msk\r
+#define RTC_CR_COSEL_Pos (19U)\r
+#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */\r
+#define RTC_CR_COSEL RTC_CR_COSEL_Msk\r
+#define RTC_CR_BKP_Pos (18U)\r
+#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */\r
+#define RTC_CR_BKP RTC_CR_BKP_Msk\r
+#define RTC_CR_SUB1H_Pos (17U)\r
+#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */\r
+#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk\r
+#define RTC_CR_ADD1H_Pos (16U)\r
+#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */\r
+#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk\r
+#define RTC_CR_TSIE_Pos (15U)\r
+#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */\r
+#define RTC_CR_TSIE RTC_CR_TSIE_Msk\r
+#define RTC_CR_WUTIE_Pos (14U)\r
+#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */\r
+#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk\r
+#define RTC_CR_ALRBIE_Pos (13U)\r
+#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */\r
+#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk\r
+#define RTC_CR_ALRAIE_Pos (12U)\r
+#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */\r
+#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk\r
+#define RTC_CR_TSE_Pos (11U)\r
+#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */\r
+#define RTC_CR_TSE RTC_CR_TSE_Msk\r
+#define RTC_CR_WUTE_Pos (10U)\r
+#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */\r
+#define RTC_CR_WUTE RTC_CR_WUTE_Msk\r
+#define RTC_CR_ALRBE_Pos (9U)\r
+#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */\r
+#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk\r
+#define RTC_CR_ALRAE_Pos (8U)\r
+#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */\r
+#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk\r
+#define RTC_CR_FMT_Pos (6U)\r
+#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */\r
+#define RTC_CR_FMT RTC_CR_FMT_Msk\r
+#define RTC_CR_BYPSHAD_Pos (5U)\r
+#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */\r
+#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk\r
+#define RTC_CR_REFCKON_Pos (4U)\r
+#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */\r
+#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk\r
+#define RTC_CR_TSEDGE_Pos (3U)\r
+#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */\r
+#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk\r
+#define RTC_CR_WUCKSEL_Pos (0U)\r
+#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */\r
+#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk\r
+#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */\r
+#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */\r
+\r
+/* Legacy define */\r
+#define RTC_CR_BCK RTC_CR_BKP\r
+\r
+/******************** Bits definition for RTC_ISR register ******************/\r
+#define RTC_ISR_ITSF_Pos (17U)\r
+#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */\r
+#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk\r
+#define RTC_ISR_RECALPF_Pos (16U)\r
+#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */\r
+#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk\r
+#define RTC_ISR_TAMP3F_Pos (15U)\r
+#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */\r
+#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk\r
+#define RTC_ISR_TAMP2F_Pos (14U)\r
+#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */\r
+#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk\r
+#define RTC_ISR_TAMP1F_Pos (13U)\r
+#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */\r
+#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk\r
+#define RTC_ISR_TSOVF_Pos (12U)\r
+#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */\r
+#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk\r
+#define RTC_ISR_TSF_Pos (11U)\r
+#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */\r
+#define RTC_ISR_TSF RTC_ISR_TSF_Msk\r
+#define RTC_ISR_WUTF_Pos (10U)\r
+#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */\r
+#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk\r
+#define RTC_ISR_ALRBF_Pos (9U)\r
+#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */\r
+#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk\r
+#define RTC_ISR_ALRAF_Pos (8U)\r
+#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */\r
+#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk\r
+#define RTC_ISR_INIT_Pos (7U)\r
+#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */\r
+#define RTC_ISR_INIT RTC_ISR_INIT_Msk\r
+#define RTC_ISR_INITF_Pos (6U)\r
+#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */\r
+#define RTC_ISR_INITF RTC_ISR_INITF_Msk\r
+#define RTC_ISR_RSF_Pos (5U)\r
+#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */\r
+#define RTC_ISR_RSF RTC_ISR_RSF_Msk\r
+#define RTC_ISR_INITS_Pos (4U)\r
+#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */\r
+#define RTC_ISR_INITS RTC_ISR_INITS_Msk\r
+#define RTC_ISR_SHPF_Pos (3U)\r
+#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */\r
+#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk\r
+#define RTC_ISR_WUTWF_Pos (2U)\r
+#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */\r
+#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk\r
+#define RTC_ISR_ALRBWF_Pos (1U)\r
+#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */\r
+#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk\r
+#define RTC_ISR_ALRAWF_Pos (0U)\r
+#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */\r
+#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk\r
+\r
+/******************** Bits definition for RTC_PRER register *****************/\r
+#define RTC_PRER_PREDIV_A_Pos (16U)\r
+#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */\r
+#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk\r
+#define RTC_PRER_PREDIV_S_Pos (0U)\r
+#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */\r
+#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk\r
+\r
+/******************** Bits definition for RTC_WUTR register *****************/\r
+#define RTC_WUTR_WUT_Pos (0U)\r
+#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */\r
+#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk\r
+\r
+/******************** Bits definition for RTC_ALRMAR register ***************/\r
+#define RTC_ALRMAR_MSK4_Pos (31U)\r
+#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk\r
+#define RTC_ALRMAR_WDSEL_Pos (30U)\r
+#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk\r
+#define RTC_ALRMAR_DT_Pos (28U)\r
+#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk\r
+#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMAR_DU_Pos (24U)\r
+#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk\r
+#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMAR_MSK3_Pos (23U)\r
+#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk\r
+#define RTC_ALRMAR_PM_Pos (22U)\r
+#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk\r
+#define RTC_ALRMAR_HT_Pos (20U)\r
+#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk\r
+#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMAR_HU_Pos (16U)\r
+#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk\r
+#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMAR_MSK2_Pos (15U)\r
+#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk\r
+#define RTC_ALRMAR_MNT_Pos (12U)\r
+#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk\r
+#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMAR_MNU_Pos (8U)\r
+#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk\r
+#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMAR_MSK1_Pos (7U)\r
+#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk\r
+#define RTC_ALRMAR_ST_Pos (4U)\r
+#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk\r
+#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMAR_SU_Pos (0U)\r
+#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk\r
+#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_ALRMBR register ***************/\r
+#define RTC_ALRMBR_MSK4_Pos (31U)\r
+#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */\r
+#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk\r
+#define RTC_ALRMBR_WDSEL_Pos (30U)\r
+#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */\r
+#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk\r
+#define RTC_ALRMBR_DT_Pos (28U)\r
+#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */\r
+#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk\r
+#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */\r
+#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */\r
+#define RTC_ALRMBR_DU_Pos (24U)\r
+#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk\r
+#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBR_MSK3_Pos (23U)\r
+#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */\r
+#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk\r
+#define RTC_ALRMBR_PM_Pos (22U)\r
+#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk\r
+#define RTC_ALRMBR_HT_Pos (20U)\r
+#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk\r
+#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_ALRMBR_HU_Pos (16U)\r
+#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk\r
+#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_ALRMBR_MSK2_Pos (15U)\r
+#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */\r
+#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk\r
+#define RTC_ALRMBR_MNT_Pos (12U)\r
+#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk\r
+#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_ALRMBR_MNU_Pos (8U)\r
+#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk\r
+#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_ALRMBR_MSK1_Pos (7U)\r
+#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */\r
+#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk\r
+#define RTC_ALRMBR_ST_Pos (4U)\r
+#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk\r
+#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_ALRMBR_SU_Pos (0U)\r
+#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk\r
+#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_WPR register ******************/\r
+#define RTC_WPR_KEY_Pos (0U)\r
+#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */\r
+#define RTC_WPR_KEY RTC_WPR_KEY_Msk\r
+\r
+/******************** Bits definition for RTC_SSR register ******************/\r
+#define RTC_SSR_SS_Pos (0U)\r
+#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_SSR_SS RTC_SSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_SHIFTR register ***************/\r
+#define RTC_SHIFTR_SUBFS_Pos (0U)\r
+#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */\r
+#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk\r
+#define RTC_SHIFTR_ADD1S_Pos (31U)\r
+#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */\r
+#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk\r
+\r
+/******************** Bits definition for RTC_TSTR register *****************/\r
+#define RTC_TSTR_PM_Pos (22U)\r
+#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */\r
+#define RTC_TSTR_PM RTC_TSTR_PM_Msk\r
+#define RTC_TSTR_HT_Pos (20U)\r
+#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */\r
+#define RTC_TSTR_HT RTC_TSTR_HT_Msk\r
+#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */\r
+#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */\r
+#define RTC_TSTR_HU_Pos (16U)\r
+#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */\r
+#define RTC_TSTR_HU RTC_TSTR_HU_Msk\r
+#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */\r
+#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */\r
+#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */\r
+#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */\r
+#define RTC_TSTR_MNT_Pos (12U)\r
+#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */\r
+#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk\r
+#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */\r
+#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */\r
+#define RTC_TSTR_MNU_Pos (8U)\r
+#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk\r
+#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSTR_ST_Pos (4U)\r
+#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */\r
+#define RTC_TSTR_ST RTC_TSTR_ST_Msk\r
+#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */\r
+#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */\r
+#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */\r
+#define RTC_TSTR_SU_Pos (0U)\r
+#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSTR_SU RTC_TSTR_SU_Msk\r
+#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSDR register *****************/\r
+#define RTC_TSDR_WDU_Pos (13U)\r
+#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */\r
+#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk\r
+#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */\r
+#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */\r
+#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */\r
+#define RTC_TSDR_MT_Pos (12U)\r
+#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */\r
+#define RTC_TSDR_MT RTC_TSDR_MT_Msk\r
+#define RTC_TSDR_MU_Pos (8U)\r
+#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */\r
+#define RTC_TSDR_MU RTC_TSDR_MU_Msk\r
+#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */\r
+#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */\r
+#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */\r
+#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */\r
+#define RTC_TSDR_DT_Pos (4U)\r
+#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */\r
+#define RTC_TSDR_DT RTC_TSDR_DT_Msk\r
+#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */\r
+#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */\r
+#define RTC_TSDR_DU_Pos (0U)\r
+#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */\r
+#define RTC_TSDR_DU RTC_TSDR_DU_Msk\r
+#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */\r
+#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */\r
+#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */\r
+#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */\r
+\r
+/******************** Bits definition for RTC_TSSSR register ****************/\r
+#define RTC_TSSSR_SS_Pos (0U)\r
+#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */\r
+#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_CAL register *****************/\r
+#define RTC_CALR_CALP_Pos (15U)\r
+#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */\r
+#define RTC_CALR_CALP RTC_CALR_CALP_Msk\r
+#define RTC_CALR_CALW8_Pos (14U)\r
+#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */\r
+#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk\r
+#define RTC_CALR_CALW16_Pos (13U)\r
+#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */\r
+#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk\r
+#define RTC_CALR_CALM_Pos (0U)\r
+#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */\r
+#define RTC_CALR_CALM RTC_CALR_CALM_Msk\r
+#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */\r
+#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */\r
+#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */\r
+#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */\r
+#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */\r
+#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */\r
+#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */\r
+#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */\r
+#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */\r
+\r
+/******************** Bits definition for RTC_TAMPCR register ****************/\r
+#define RTC_TAMPCR_TAMP3MF_Pos (24U)\r
+#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */\r
+#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk\r
+#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)\r
+#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */\r
+#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP3IE_Pos (22U)\r
+#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */\r
+#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk\r
+#define RTC_TAMPCR_TAMP2MF_Pos (21U)\r
+#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */\r
+#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk\r
+#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)\r
+#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */\r
+#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP2IE_Pos (19U)\r
+#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */\r
+#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk\r
+#define RTC_TAMPCR_TAMP1MF_Pos (18U)\r
+#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */\r
+#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk\r
+#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)\r
+#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */\r
+#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk\r
+#define RTC_TAMPCR_TAMP1IE_Pos (16U)\r
+#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */\r
+#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk\r
+#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)\r
+#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */\r
+#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_Pos (13U)\r
+#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */\r
+#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk\r
+#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */\r
+#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */\r
+#define RTC_TAMPCR_TAMPFLT_Pos (11U)\r
+#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */\r
+#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk\r
+#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */\r
+#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */\r
+#define RTC_TAMPCR_TAMPFREQ_Pos (8U)\r
+#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */\r
+#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk\r
+#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */\r
+#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */\r
+#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */\r
+#define RTC_TAMPCR_TAMPTS_Pos (7U)\r
+#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */\r
+#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk\r
+#define RTC_TAMPCR_TAMP3TRG_Pos (6U)\r
+#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */\r
+#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk\r
+#define RTC_TAMPCR_TAMP3E_Pos (5U)\r
+#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */\r
+#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk\r
+#define RTC_TAMPCR_TAMP2TRG_Pos (4U)\r
+#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */\r
+#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk\r
+#define RTC_TAMPCR_TAMP2E_Pos (3U)\r
+#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */\r
+#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk\r
+#define RTC_TAMPCR_TAMPIE_Pos (2U)\r
+#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */\r
+#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk\r
+#define RTC_TAMPCR_TAMP1TRG_Pos (1U)\r
+#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */\r
+#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk\r
+#define RTC_TAMPCR_TAMP1E_Pos (0U)\r
+#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */\r
+#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk\r
+\r
+\r
+/******************** Bits definition for RTC_ALRMASSR register *************/\r
+#define RTC_ALRMASSR_MASKSS_Pos (24U)\r
+#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk\r
+#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMASSR_SS_Pos (0U)\r
+#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_ALRMBSSR register *************/\r
+#define RTC_ALRMBSSR_MASKSS_Pos (24U)\r
+#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */\r
+#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk\r
+#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */\r
+#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */\r
+#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */\r
+#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */\r
+#define RTC_ALRMBSSR_SS_Pos (0U)\r
+#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */\r
+#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk\r
+\r
+/******************** Bits definition for RTC_OR register ****************/\r
+#define RTC_OR_TSINSEL_Pos (1U)\r
+#define RTC_OR_TSINSEL_Msk (0x3UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000006 */\r
+#define RTC_OR_TSINSEL RTC_OR_TSINSEL_Msk\r
+#define RTC_OR_TSINSEL_0 (0x1UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000002 */\r
+#define RTC_OR_TSINSEL_1 (0x2UL << RTC_OR_TSINSEL_Pos) /*!< 0x00000004 */\r
+#define RTC_OR_ALARMOUTTYPE_Pos (3U)\r
+#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000008 */\r
+#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk\r
+/* Legacy defines*/\r
+#define RTC_OR_ALARMTYPE RTC_OR_ALARMOUTTYPE\r
+\r
+/******************** Bits definition for RTC_BKP0R register ****************/\r
+#define RTC_BKP0R_Pos (0U)\r
+#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP0R RTC_BKP0R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP1R register ****************/\r
+#define RTC_BKP1R_Pos (0U)\r
+#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP1R RTC_BKP1R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP2R register ****************/\r
+#define RTC_BKP2R_Pos (0U)\r
+#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP2R RTC_BKP2R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP3R register ****************/\r
+#define RTC_BKP3R_Pos (0U)\r
+#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP3R RTC_BKP3R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP4R register ****************/\r
+#define RTC_BKP4R_Pos (0U)\r
+#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP4R RTC_BKP4R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP5R register ****************/\r
+#define RTC_BKP5R_Pos (0U)\r
+#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP5R RTC_BKP5R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP6R register ****************/\r
+#define RTC_BKP6R_Pos (0U)\r
+#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP6R RTC_BKP6R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP7R register ****************/\r
+#define RTC_BKP7R_Pos (0U)\r
+#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP7R RTC_BKP7R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP8R register ****************/\r
+#define RTC_BKP8R_Pos (0U)\r
+#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP8R RTC_BKP8R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP9R register ****************/\r
+#define RTC_BKP9R_Pos (0U)\r
+#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP9R RTC_BKP9R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP10R register ***************/\r
+#define RTC_BKP10R_Pos (0U)\r
+#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP10R RTC_BKP10R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP11R register ***************/\r
+#define RTC_BKP11R_Pos (0U)\r
+#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP11R RTC_BKP11R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP12R register ***************/\r
+#define RTC_BKP12R_Pos (0U)\r
+#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP12R RTC_BKP12R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP13R register ***************/\r
+#define RTC_BKP13R_Pos (0U)\r
+#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP13R RTC_BKP13R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP14R register ***************/\r
+#define RTC_BKP14R_Pos (0U)\r
+#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP14R RTC_BKP14R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP15R register ***************/\r
+#define RTC_BKP15R_Pos (0U)\r
+#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP15R RTC_BKP15R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP16R register ***************/\r
+#define RTC_BKP16R_Pos (0U)\r
+#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP16R RTC_BKP16R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP17R register ***************/\r
+#define RTC_BKP17R_Pos (0U)\r
+#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP17R RTC_BKP17R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP18R register ***************/\r
+#define RTC_BKP18R_Pos (0U)\r
+#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP18R RTC_BKP18R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP19R register ***************/\r
+#define RTC_BKP19R_Pos (0U)\r
+#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP19R RTC_BKP19R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP20R register ***************/\r
+#define RTC_BKP20R_Pos (0U)\r
+#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP20R RTC_BKP20R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP21R register ***************/\r
+#define RTC_BKP21R_Pos (0U)\r
+#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP21R RTC_BKP21R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP22R register ***************/\r
+#define RTC_BKP22R_Pos (0U)\r
+#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP22R RTC_BKP22R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP23R register ***************/\r
+#define RTC_BKP23R_Pos (0U)\r
+#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP23R RTC_BKP23R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP24R register ***************/\r
+#define RTC_BKP24R_Pos (0U)\r
+#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP24R RTC_BKP24R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP25R register ***************/\r
+#define RTC_BKP25R_Pos (0U)\r
+#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP25R RTC_BKP25R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP26R register ***************/\r
+#define RTC_BKP26R_Pos (0U)\r
+#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP26R RTC_BKP26R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP27R register ***************/\r
+#define RTC_BKP27R_Pos (0U)\r
+#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP27R RTC_BKP27R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP28R register ***************/\r
+#define RTC_BKP28R_Pos (0U)\r
+#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP28R RTC_BKP28R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP29R register ***************/\r
+#define RTC_BKP29R_Pos (0U)\r
+#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP29R RTC_BKP29R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP30R register ***************/\r
+#define RTC_BKP30R_Pos (0U)\r
+#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP30R RTC_BKP30R_Msk\r
+\r
+/******************** Bits definition for RTC_BKP31R register ***************/\r
+#define RTC_BKP31R_Pos (0U)\r
+#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */\r
+#define RTC_BKP31R RTC_BKP31R_Msk\r
+\r
+/******************** Number of backup registers ******************************/\r
+#define RTC_BKP_NUMBER 0x00000020U\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Audio Interface */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for SAI_GCR register *******************/\r
+#define SAI_GCR_SYNCIN_Pos (0U)\r
+#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */\r
+#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
+#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */\r
+#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_GCR_SYNCOUT_Pos (4U)\r
+#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */\r
+#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */\r
+#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */\r
+\r
+/******************* Bit definition for SAI_xCR1 register *******************/\r
+#define SAI_xCR1_MODE_Pos (0U)\r
+#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */\r
+#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */\r
+#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */\r
+\r
+#define SAI_xCR1_PRTCFG_Pos (2U)\r
+#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */\r
+#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
+#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */\r
+\r
+#define SAI_xCR1_DS_Pos (5U)\r
+#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */\r
+#define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */\r
+#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xCR1_LSBFIRST_Pos (8U)\r
+#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */\r
+#define SAI_xCR1_CKSTR_Pos (9U)\r
+#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */\r
+\r
+#define SAI_xCR1_SYNCEN_Pos (10U)\r
+#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */\r
+#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xCR1_MONO_Pos (12U)\r
+#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */\r
+#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */\r
+#define SAI_xCR1_OUTDRIV_Pos (13U)\r
+#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */\r
+#define SAI_xCR1_SAIEN_Pos (16U)\r
+#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */\r
+#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */\r
+#define SAI_xCR1_DMAEN_Pos (17U)\r
+#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */\r
+#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */\r
+#define SAI_xCR1_NODIV_Pos (19U)\r
+#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */\r
+#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */\r
+\r
+#define SAI_xCR1_MCKDIV_Pos (20U)\r
+#define SAI_xCR1_MCKDIV_Msk (0xFUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00F00000 */\r
+#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
+#define SAI_xCR1_MCKDIV_0 (0x1UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */\r
+#define SAI_xCR1_MCKDIV_1 (0x2UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */\r
+#define SAI_xCR1_MCKDIV_2 (0x4UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */\r
+#define SAI_xCR1_MCKDIV_3 (0x8UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */\r
+\r
+/******************* Bit definition for SAI_xCR2 register *******************/\r
+#define SAI_xCR2_FTH_Pos (0U)\r
+#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */\r
+#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */\r
+#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */\r
+#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */\r
+#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */\r
+\r
+#define SAI_xCR2_FFLUSH_Pos (3U)\r
+#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */\r
+#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */\r
+#define SAI_xCR2_TRIS_Pos (4U)\r
+#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */\r
+#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */\r
+#define SAI_xCR2_MUTE_Pos (5U)\r
+#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */\r
+#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */\r
+#define SAI_xCR2_MUTEVAL_Pos (6U)\r
+#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */\r
+#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */\r
+\r
+#define SAI_xCR2_MUTECNT_Pos (7U)\r
+#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */\r
+#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */\r
+#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */\r
+#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */\r
+#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */\r
+#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */\r
+#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */\r
+\r
+#define SAI_xCR2_CPL_Pos (13U)\r
+#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */\r
+#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */\r
+\r
+#define SAI_xCR2_COMP_Pos (14U)\r
+#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */\r
+#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */\r
+#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */\r
+#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */\r
+\r
+/****************** Bit definition for SAI_xFRCR register *******************/\r
+#define SAI_xFRCR_FRL_Pos (0U)\r
+#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */\r
+#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](Frame length) */\r
+#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */\r
+#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */\r
+#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */\r
+#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */\r
+#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */\r
+#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */\r
+#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */\r
+#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xFRCR_FSALL_Pos (8U)\r
+#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */\r
+#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FRL[6:0] (Frame synchronization active level length) */\r
+#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */\r
+#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */\r
+#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */\r
+#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */\r
+#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */\r
+#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */\r
+#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */\r
+\r
+#define SAI_xFRCR_FSDEF_Pos (16U)\r
+#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */\r
+#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */\r
+#define SAI_xFRCR_FSPOL_Pos (17U)\r
+#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */\r
+#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */\r
+#define SAI_xFRCR_FSOFF_Pos (18U)\r
+#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */\r
+#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */\r
+\r
+/* Legacy define */\r
+#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL\r
+\r
+/****************** Bit definition for SAI_xSLOTR register *******************/\r
+#define SAI_xSLOTR_FBOFF_Pos (0U)\r
+#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */\r
+#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FRL[4:0](First Bit Offset) */\r
+#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */\r
+#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */\r
+#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */\r
+#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */\r
+#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */\r
+\r
+#define SAI_xSLOTR_SLOTSZ_Pos (6U)\r
+#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */\r
+#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */\r
+#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */\r
+#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */\r
+\r
+#define SAI_xSLOTR_NBSLOT_Pos (8U)\r
+#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */\r
+#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
+#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */\r
+#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */\r
+#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */\r
+#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */\r
+\r
+#define SAI_xSLOTR_SLOTEN_Pos (16U)\r
+#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */\r
+#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */\r
+\r
+/******************* Bit definition for SAI_xIMR register *******************/\r
+#define SAI_xIMR_OVRUDRIE_Pos (0U)\r
+#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */\r
+#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */\r
+#define SAI_xIMR_MUTEDETIE_Pos (1U)\r
+#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */\r
+#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */\r
+#define SAI_xIMR_WCKCFGIE_Pos (2U)\r
+#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */\r
+#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */\r
+#define SAI_xIMR_FREQIE_Pos (3U)\r
+#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */\r
+#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */\r
+#define SAI_xIMR_CNRDYIE_Pos (4U)\r
+#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */\r
+#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */\r
+#define SAI_xIMR_AFSDETIE_Pos (5U)\r
+#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */\r
+#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */\r
+#define SAI_xIMR_LFSDETIE_Pos (6U)\r
+#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */\r
+#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */\r
+\r
+/******************** Bit definition for SAI_xSR register *******************/\r
+#define SAI_xSR_OVRUDR_Pos (0U)\r
+#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */\r
+#define SAI_xSR_MUTEDET_Pos (1U)\r
+#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */\r
+#define SAI_xSR_WCKCFG_Pos (2U)\r
+#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */\r
+#define SAI_xSR_FREQ_Pos (3U)\r
+#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */\r
+#define SAI_xSR_CNRDY_Pos (4U)\r
+#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */\r
+#define SAI_xSR_AFSDET_Pos (5U)\r
+#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */\r
+#define SAI_xSR_LFSDET_Pos (6U)\r
+#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */\r
+\r
+#define SAI_xSR_FLVL_Pos (16U)\r
+#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */\r
+#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */\r
+#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */\r
+#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */\r
+#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */\r
+\r
+/****************** Bit definition for SAI_xCLRFR register ******************/\r
+#define SAI_xCLRFR_COVRUDR_Pos (0U)\r
+#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */\r
+#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */\r
+#define SAI_xCLRFR_CMUTEDET_Pos (1U)\r
+#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */\r
+#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */\r
+#define SAI_xCLRFR_CWCKCFG_Pos (2U)\r
+#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */\r
+#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */\r
+#define SAI_xCLRFR_CFREQ_Pos (3U)\r
+#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */\r
+#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */\r
+#define SAI_xCLRFR_CCNRDY_Pos (4U)\r
+#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */\r
+#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */\r
+#define SAI_xCLRFR_CAFSDET_Pos (5U)\r
+#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */\r
+#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */\r
+#define SAI_xCLRFR_CLFSDET_Pos (6U)\r
+#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */\r
+#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */\r
+\r
+/****************** Bit definition for SAI_xDR register *********************/\r
+#define SAI_xDR_DATA_Pos (0U)\r
+#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SAI_xDR_DATA SAI_xDR_DATA_Msk\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SD host Interface */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SDMMC_POWER register ******************/\r
+#define SDMMC_POWER_PWRCTRL_Pos (0U)\r
+#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */\r
+#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x01 */\r
+#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x02 */\r
+\r
+/****************** Bit definition for SDMMC_CLKCR register ******************/\r
+#define SDMMC_CLKCR_CLKDIV_Pos (0U)\r
+#define SDMMC_CLKCR_CLKDIV_Msk (0xFFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000000FF */\r
+#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */\r
+#define SDMMC_CLKCR_CLKEN_Pos (8U)\r
+#define SDMMC_CLKCR_CLKEN_Msk (0x1UL << SDMMC_CLKCR_CLKEN_Pos) /*!< 0x00000100 */\r
+#define SDMMC_CLKCR_CLKEN SDMMC_CLKCR_CLKEN_Msk /*!<Clock enable bit */\r
+#define SDMMC_CLKCR_PWRSAV_Pos (9U)\r
+#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00000200 */\r
+#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */\r
+#define SDMMC_CLKCR_BYPASS_Pos (10U)\r
+#define SDMMC_CLKCR_BYPASS_Msk (0x1UL << SDMMC_CLKCR_BYPASS_Pos) /*!< 0x00000400 */\r
+#define SDMMC_CLKCR_BYPASS SDMMC_CLKCR_BYPASS_Msk /*!<Clock divider bypass enable bit */\r
+\r
+#define SDMMC_CLKCR_WIDBUS_Pos (11U)\r
+#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00001800 */\r
+#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0800 */\r
+#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x1000 */\r
+\r
+#define SDMMC_CLKCR_NEGEDGE_Pos (13U)\r
+#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00002000 */\r
+#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */\r
+#define SDMMC_CLKCR_HWFC_EN_Pos (14U)\r
+#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00004000 */\r
+#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */\r
+\r
+/******************* Bit definition for SDMMC_ARG register *******************/\r
+#define SDMMC_ARG_CMDARG_Pos (0U)\r
+#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */\r
+\r
+/******************* Bit definition for SDMMC_CMD register *******************/\r
+#define SDMMC_CMD_CMDINDEX_Pos (0U)\r
+#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */\r
+#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */\r
+\r
+#define SDMMC_CMD_WAITRESP_Pos (6U)\r
+#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x000000C0 */\r
+#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0040 */\r
+#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x0080 */\r
+\r
+#define SDMMC_CMD_WAITINT_Pos (8U)\r
+#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000100 */\r
+#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */\r
+#define SDMMC_CMD_WAITPEND_Pos (9U)\r
+#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000200 */\r
+#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define SDMMC_CMD_CPSMEN_Pos (10U)\r
+#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00000400 */\r
+#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */\r
+#define SDMMC_CMD_SDIOSUSPEND_Pos (11U)\r
+#define SDMMC_CMD_SDIOSUSPEND_Msk (0x1UL << SDMMC_CMD_SDIOSUSPEND_Pos) /*!< 0x00000800 */\r
+#define SDMMC_CMD_SDIOSUSPEND SDMMC_CMD_SDIOSUSPEND_Msk /*!<SD I/O suspend command */\r
+\r
+/***************** Bit definition for SDMMC_RESPCMD register *****************/\r
+#define SDMMC_RESPCMD_RESPCMD_Pos (0U)\r
+#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */\r
+#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */\r
+\r
+/****************** Bit definition for SDMMC_RESP0 register ******************/\r
+#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)\r
+#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP1 register ******************/\r
+#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)\r
+#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP2 register ******************/\r
+#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)\r
+#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP3 register ******************/\r
+#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)\r
+#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_RESP4 register ******************/\r
+#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)\r
+#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */\r
+\r
+/****************** Bit definition for SDMMC_DTIMER register *****************/\r
+#define SDMMC_DTIMER_DATATIME_Pos (0U)\r
+#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */\r
+\r
+/****************** Bit definition for SDMMC_DLEN register *******************/\r
+#define SDMMC_DLEN_DATALENGTH_Pos (0U)\r
+#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */\r
+\r
+/****************** Bit definition for SDMMC_DCTRL register ******************/\r
+#define SDMMC_DCTRL_DTEN_Pos (0U)\r
+#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */\r
+#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */\r
+#define SDMMC_DCTRL_DTDIR_Pos (1U)\r
+#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */\r
+#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */\r
+#define SDMMC_DCTRL_DTMODE_Pos (2U)\r
+#define SDMMC_DCTRL_DTMODE_Msk (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<Data transfer mode selection */\r
+#define SDMMC_DCTRL_DMAEN_Pos (3U)\r
+#define SDMMC_DCTRL_DMAEN_Msk (0x1UL << SDMMC_DCTRL_DMAEN_Pos) /*!< 0x00000008 */\r
+#define SDMMC_DCTRL_DMAEN SDMMC_DCTRL_DMAEN_Msk /*!<DMA enabled bit */\r
+\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)\r
+#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0010 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0020 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0040 */\r
+#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x0080 */\r
+\r
+#define SDMMC_DCTRL_RWSTART_Pos (8U)\r
+#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */\r
+#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */\r
+#define SDMMC_DCTRL_RWSTOP_Pos (9U)\r
+#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */\r
+#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */\r
+#define SDMMC_DCTRL_RWMOD_Pos (10U)\r
+#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */\r
+#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */\r
+#define SDMMC_DCTRL_SDIOEN_Pos (11U)\r
+#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */\r
+#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */\r
+\r
+/****************** Bit definition for SDMMC_DCOUNT register *****************/\r
+#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)\r
+#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */\r
+#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */\r
+\r
+/****************** Bit definition for SDMMC_STA registe ********************/\r
+#define SDMMC_STA_CCRCFAIL_Pos (0U)\r
+#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */\r
+#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */\r
+#define SDMMC_STA_DCRCFAIL_Pos (1U)\r
+#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */\r
+#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */\r
+#define SDMMC_STA_CTIMEOUT_Pos (2U)\r
+#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */\r
+#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */\r
+#define SDMMC_STA_DTIMEOUT_Pos (3U)\r
+#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */\r
+#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */\r
+#define SDMMC_STA_TXUNDERR_Pos (4U)\r
+#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */\r
+#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */\r
+#define SDMMC_STA_RXOVERR_Pos (5U)\r
+#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */\r
+#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */\r
+#define SDMMC_STA_CMDREND_Pos (6U)\r
+#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */\r
+#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */\r
+#define SDMMC_STA_CMDSENT_Pos (7U)\r
+#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */\r
+#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */\r
+#define SDMMC_STA_DATAEND_Pos (8U)\r
+#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */\r
+#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
+#define SDMMC_STA_DBCKEND_Pos (10U)\r
+#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */\r
+#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */\r
+#define SDMMC_STA_CMDACT_Pos (11U)\r
+#define SDMMC_STA_CMDACT_Msk (0x1UL << SDMMC_STA_CMDACT_Pos) /*!< 0x00000800 */\r
+#define SDMMC_STA_CMDACT SDMMC_STA_CMDACT_Msk /*!<Command transfer in progress */\r
+#define SDMMC_STA_TXACT_Pos (12U)\r
+#define SDMMC_STA_TXACT_Msk (0x1UL << SDMMC_STA_TXACT_Pos) /*!< 0x00001000 */\r
+#define SDMMC_STA_TXACT SDMMC_STA_TXACT_Msk /*!<Data transmit in progress */\r
+#define SDMMC_STA_RXACT_Pos (13U)\r
+#define SDMMC_STA_RXACT_Msk (0x1UL << SDMMC_STA_RXACT_Pos) /*!< 0x00002000 */\r
+#define SDMMC_STA_RXACT SDMMC_STA_RXACT_Msk /*!<Data receive in progress */\r
+#define SDMMC_STA_TXFIFOHE_Pos (14U)\r
+#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define SDMMC_STA_RXFIFOHF_Pos (15U)\r
+#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */\r
+#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define SDMMC_STA_TXFIFOF_Pos (16U)\r
+#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */\r
+#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */\r
+#define SDMMC_STA_RXFIFOF_Pos (17U)\r
+#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */\r
+#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */\r
+#define SDMMC_STA_TXFIFOE_Pos (18U)\r
+#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */\r
+#define SDMMC_STA_RXFIFOE_Pos (19U)\r
+#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */\r
+#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */\r
+#define SDMMC_STA_TXDAVL_Pos (20U)\r
+#define SDMMC_STA_TXDAVL_Msk (0x1UL << SDMMC_STA_TXDAVL_Pos) /*!< 0x00100000 */\r
+#define SDMMC_STA_TXDAVL SDMMC_STA_TXDAVL_Msk /*!<Data available in transmit FIFO */\r
+#define SDMMC_STA_RXDAVL_Pos (21U)\r
+#define SDMMC_STA_RXDAVL_Msk (0x1UL << SDMMC_STA_RXDAVL_Pos) /*!< 0x00200000 */\r
+#define SDMMC_STA_RXDAVL SDMMC_STA_RXDAVL_Msk /*!<Data available in receive FIFO */\r
+#define SDMMC_STA_SDIOIT_Pos (22U)\r
+#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */\r
+#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDMMC interrupt received */\r
+\r
+/******************* Bit definition for SDMMC_ICR register *******************/\r
+#define SDMMC_ICR_CCRCFAILC_Pos (0U)\r
+#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */\r
+#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_DCRCFAILC_Pos (1U)\r
+#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */\r
+#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */\r
+#define SDMMC_ICR_CTIMEOUTC_Pos (2U)\r
+#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */\r
+#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_DTIMEOUTC_Pos (3U)\r
+#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */\r
+#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */\r
+#define SDMMC_ICR_TXUNDERRC_Pos (4U)\r
+#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */\r
+#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */\r
+#define SDMMC_ICR_RXOVERRC_Pos (5U)\r
+#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */\r
+#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */\r
+#define SDMMC_ICR_CMDRENDC_Pos (6U)\r
+#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */\r
+#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */\r
+#define SDMMC_ICR_CMDSENTC_Pos (7U)\r
+#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */\r
+#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */\r
+#define SDMMC_ICR_DATAENDC_Pos (8U)\r
+#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */\r
+#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */\r
+#define SDMMC_ICR_DBCKENDC_Pos (10U)\r
+#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */\r
+#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */\r
+#define SDMMC_ICR_SDIOITC_Pos (22U)\r
+#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */\r
+#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDMMCIT flag clear bit */\r
+\r
+/****************** Bit definition for SDMMC_MASK register *******************/\r
+#define SDMMC_MASK_CCRCFAILIE_Pos (0U)\r
+#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */\r
+#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_DCRCFAILIE_Pos (1U)\r
+#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */\r
+#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */\r
+#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)\r
+#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */\r
+#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)\r
+#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */\r
+#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */\r
+#define SDMMC_MASK_TXUNDERRIE_Pos (4U)\r
+#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */\r
+#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
+#define SDMMC_MASK_RXOVERRIE_Pos (5U)\r
+#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */\r
+#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */\r
+#define SDMMC_MASK_CMDRENDIE_Pos (6U)\r
+#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */\r
+#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */\r
+#define SDMMC_MASK_CMDSENTIE_Pos (7U)\r
+#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */\r
+#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */\r
+#define SDMMC_MASK_DATAENDIE_Pos (8U)\r
+#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */\r
+#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */\r
+#define SDMMC_MASK_DBCKENDIE_Pos (10U)\r
+#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */\r
+#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */\r
+#define SDMMC_MASK_CMDACTIE_Pos (11U)\r
+#define SDMMC_MASK_CMDACTIE_Msk (0x1UL << SDMMC_MASK_CMDACTIE_Pos) /*!< 0x00000800 */\r
+#define SDMMC_MASK_CMDACTIE SDMMC_MASK_CMDACTIE_Msk /*!<CCommand Acting Interrupt Enable */\r
+#define SDMMC_MASK_TXACTIE_Pos (12U)\r
+#define SDMMC_MASK_TXACTIE_Msk (0x1UL << SDMMC_MASK_TXACTIE_Pos) /*!< 0x00001000 */\r
+#define SDMMC_MASK_TXACTIE SDMMC_MASK_TXACTIE_Msk /*!<Data Transmit Acting Interrupt Enable */\r
+#define SDMMC_MASK_RXACTIE_Pos (13U)\r
+#define SDMMC_MASK_RXACTIE_Msk (0x1UL << SDMMC_MASK_RXACTIE_Pos) /*!< 0x00002000 */\r
+#define SDMMC_MASK_RXACTIE SDMMC_MASK_RXACTIE_Msk /*!<Data receive acting interrupt enabled */\r
+#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)\r
+#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */\r
+#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)\r
+#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */\r
+#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOFIE_Pos (16U)\r
+#define SDMMC_MASK_TXFIFOFIE_Msk (0x1UL << SDMMC_MASK_TXFIFOFIE_Pos) /*!< 0x00010000 */\r
+#define SDMMC_MASK_TXFIFOFIE SDMMC_MASK_TXFIFOFIE_Msk /*!<Tx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOFIE_Pos (17U)\r
+#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */\r
+#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */\r
+#define SDMMC_MASK_TXFIFOEIE_Pos (18U)\r
+#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */\r
+#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_RXFIFOEIE_Pos (19U)\r
+#define SDMMC_MASK_RXFIFOEIE_Msk (0x1UL << SDMMC_MASK_RXFIFOEIE_Pos) /*!< 0x00080000 */\r
+#define SDMMC_MASK_RXFIFOEIE SDMMC_MASK_RXFIFOEIE_Msk /*!<Rx FIFO Empty interrupt Enable */\r
+#define SDMMC_MASK_TXDAVLIE_Pos (20U)\r
+#define SDMMC_MASK_TXDAVLIE_Msk (0x1UL << SDMMC_MASK_TXDAVLIE_Pos) /*!< 0x00100000 */\r
+#define SDMMC_MASK_TXDAVLIE SDMMC_MASK_TXDAVLIE_Msk /*!<Data available in Tx FIFO interrupt Enable */\r
+#define SDMMC_MASK_RXDAVLIE_Pos (21U)\r
+#define SDMMC_MASK_RXDAVLIE_Msk (0x1UL << SDMMC_MASK_RXDAVLIE_Pos) /*!< 0x00200000 */\r
+#define SDMMC_MASK_RXDAVLIE SDMMC_MASK_RXDAVLIE_Msk /*!<Data available in Rx FIFO interrupt Enable */\r
+#define SDMMC_MASK_SDIOITIE_Pos (22U)\r
+#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */\r
+#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */\r
+\r
+/***************** Bit definition for SDMMC_FIFOCNT register *****************/\r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Pos (0U)\r
+#define SDMMC_FIFOCNT_FIFOCOUNT_Msk (0xFFFFFFUL << SDMMC_FIFOCNT_FIFOCOUNT_Pos) /*!< 0x00FFFFFF */\r
+#define SDMMC_FIFOCNT_FIFOCOUNT SDMMC_FIFOCNT_FIFOCOUNT_Msk /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/****************** Bit definition for SDMMC_FIFO register *******************/\r
+#define SDMMC_FIFO_FIFODATA_Pos (0U)\r
+#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */\r
+#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Serial Peripheral Interface (SPI) */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for SPI_CR1 register ********************/\r
+#define SPI_CR1_CPHA_Pos (0U)\r
+#define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */\r
+#define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */\r
+#define SPI_CR1_CPOL_Pos (1U)\r
+#define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */\r
+#define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */\r
+#define SPI_CR1_MSTR_Pos (2U)\r
+#define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */\r
+#define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */\r
+#define SPI_CR1_BR_Pos (3U)\r
+#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */\r
+#define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */\r
+#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */\r
+#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */\r
+#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */\r
+#define SPI_CR1_SPE_Pos (6U)\r
+#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */\r
+#define SPI_CR1_LSBFIRST_Pos (7U)\r
+#define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */\r
+#define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */\r
+#define SPI_CR1_SSI_Pos (8U)\r
+#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */\r
+#define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */\r
+#define SPI_CR1_SSM_Pos (9U)\r
+#define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */\r
+#define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */\r
+#define SPI_CR1_RXONLY_Pos (10U)\r
+#define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */\r
+#define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */\r
+#define SPI_CR1_CRCL_Pos (11U)\r
+#define SPI_CR1_CRCL_Msk (0x1UL << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */\r
+#define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */\r
+#define SPI_CR1_CRCNEXT_Pos (12U)\r
+#define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */\r
+#define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */\r
+#define SPI_CR1_CRCEN_Pos (13U)\r
+#define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */\r
+#define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */\r
+#define SPI_CR1_BIDIOE_Pos (14U)\r
+#define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */\r
+#define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */\r
+#define SPI_CR1_BIDIMODE_Pos (15U)\r
+#define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */\r
+#define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */\r
+\r
+/******************* Bit definition for SPI_CR2 register ********************/\r
+#define SPI_CR2_RXDMAEN_Pos (0U)\r
+#define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */\r
+#define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */\r
+#define SPI_CR2_TXDMAEN_Pos (1U)\r
+#define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */\r
+#define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */\r
+#define SPI_CR2_SSOE_Pos (2U)\r
+#define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */\r
+#define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */\r
+#define SPI_CR2_NSSP_Pos (3U)\r
+#define SPI_CR2_NSSP_Msk (0x1UL << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */\r
+#define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */\r
+#define SPI_CR2_FRF_Pos (4U)\r
+#define SPI_CR2_FRF_Msk (0x1UL << SPI_CR2_FRF_Pos) /*!< 0x00000010 */\r
+#define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */\r
+#define SPI_CR2_ERRIE_Pos (5U)\r
+#define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */\r
+#define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */\r
+#define SPI_CR2_RXNEIE_Pos (6U)\r
+#define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */\r
+#define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */\r
+#define SPI_CR2_TXEIE_Pos (7U)\r
+#define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */\r
+#define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */\r
+#define SPI_CR2_DS_Pos (8U)\r
+#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */\r
+#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */\r
+#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */\r
+#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */\r
+#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */\r
+#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */\r
+#define SPI_CR2_FRXTH_Pos (12U)\r
+#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */\r
+#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */\r
+#define SPI_CR2_LDMARX_Pos (13U)\r
+#define SPI_CR2_LDMARX_Msk (0x1UL << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */\r
+#define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */\r
+#define SPI_CR2_LDMATX_Pos (14U)\r
+#define SPI_CR2_LDMATX_Msk (0x1UL << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */\r
+#define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */\r
+\r
+/******************** Bit definition for SPI_SR register ********************/\r
+#define SPI_SR_RXNE_Pos (0U)\r
+#define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */\r
+#define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */\r
+#define SPI_SR_TXE_Pos (1U)\r
+#define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */\r
+#define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */\r
+#define SPI_SR_CHSIDE_Pos (2U)\r
+#define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */\r
+#define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */\r
+#define SPI_SR_UDR_Pos (3U)\r
+#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */\r
+#define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */\r
+#define SPI_SR_CRCERR_Pos (4U)\r
+#define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */\r
+#define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */\r
+#define SPI_SR_MODF_Pos (5U)\r
+#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */\r
+#define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */\r
+#define SPI_SR_OVR_Pos (6U)\r
+#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */\r
+#define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */\r
+#define SPI_SR_BSY_Pos (7U)\r
+#define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */\r
+#define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */\r
+#define SPI_SR_FRE_Pos (8U)\r
+#define SPI_SR_FRE_Msk (0x1UL << SPI_SR_FRE_Pos) /*!< 0x00000100 */\r
+#define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */\r
+#define SPI_SR_FRLVL_Pos (9U)\r
+#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */\r
+#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */\r
+#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */\r
+#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */\r
+#define SPI_SR_FTLVL_Pos (11U)\r
+#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */\r
+#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */\r
+#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */\r
+#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */\r
+\r
+/******************** Bit definition for SPI_DR register ********************/\r
+#define SPI_DR_DR_Pos (0U)\r
+#define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */\r
+#define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */\r
+\r
+/******************* Bit definition for SPI_CRCPR register ******************/\r
+#define SPI_CRCPR_CRCPOLY_Pos (0U)\r
+#define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */\r
+#define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */\r
+\r
+/****************** Bit definition for SPI_RXCRCR register ******************/\r
+#define SPI_RXCRCR_RXCRC_Pos (0U)\r
+#define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */\r
+\r
+/****************** Bit definition for SPI_TXCRCR register ******************/\r
+#define SPI_TXCRCR_TXCRC_Pos (0U)\r
+#define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */\r
+#define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */\r
+\r
+/****************** Bit definition for SPI_I2SCFGR register *****************/\r
+#define SPI_I2SCFGR_CHLEN_Pos (0U)\r
+#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */\r
+#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */\r
+#define SPI_I2SCFGR_DATLEN_Pos (1U)\r
+#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */\r
+#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
+#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */\r
+#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */\r
+#define SPI_I2SCFGR_CKPOL_Pos (3U)\r
+#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */\r
+#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */\r
+#define SPI_I2SCFGR_I2SSTD_Pos (4U)\r
+#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */\r
+#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */\r
+#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */\r
+#define SPI_I2SCFGR_PCMSYNC_Pos (7U)\r
+#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */\r
+#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */\r
+#define SPI_I2SCFGR_I2SCFG_Pos (8U)\r
+#define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */\r
+#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SCFGR_I2SE_Pos (10U)\r
+#define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */\r
+#define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */\r
+#define SPI_I2SCFGR_I2SMOD_Pos (11U)\r
+#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */\r
+#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */\r
+#define SPI_I2SCFGR_ASTRTEN_Pos (12U)\r
+#define SPI_I2SCFGR_ASTRTEN_Msk (0x1UL << SPI_I2SCFGR_ASTRTEN_Pos) /*!< 0x00001000 */\r
+#define SPI_I2SCFGR_ASTRTEN SPI_I2SCFGR_ASTRTEN_Msk /*!<Asynchronous start enable */\r
+\r
+/****************** Bit definition for SPI_I2SPR register *******************/\r
+#define SPI_I2SPR_I2SDIV_Pos (0U)\r
+#define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */\r
+#define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */\r
+#define SPI_I2SPR_ODD_Pos (8U)\r
+#define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */\r
+#define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */\r
+#define SPI_I2SPR_MCKOE_Pos (9U)\r
+#define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */\r
+#define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* SYSCFG */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for SYSCFG_MEMRMP register ***************/\r
+#define SYSCFG_MEMRMP_MEM_BOOT_Pos (0U)\r
+#define SYSCFG_MEMRMP_MEM_BOOT_Msk (0x1UL << SYSCFG_MEMRMP_MEM_BOOT_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_MEMRMP_MEM_BOOT SYSCFG_MEMRMP_MEM_BOOT_Msk /*!< Boot information after Reset */\r
+\r
+\r
+#define SYSCFG_MEMRMP_SWP_FMC_Pos (10U)\r
+#define SYSCFG_MEMRMP_SWP_FMC_Msk (0x3UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000C00 */\r
+#define SYSCFG_MEMRMP_SWP_FMC SYSCFG_MEMRMP_SWP_FMC_Msk /*!< FMC Memory Mapping swapping */\r
+#define SYSCFG_MEMRMP_SWP_FMC_0 (0x1UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000400 */\r
+#define SYSCFG_MEMRMP_SWP_FMC_1 (0x2UL << SYSCFG_MEMRMP_SWP_FMC_Pos) /*!< 0x00000800 */\r
+\r
+/****************** Bit definition for SYSCFG_PMC register ******************/\r
+#define SYSCFG_PMC_I2C1_FMP_Pos (0U)\r
+#define SYSCFG_PMC_I2C1_FMP_Msk (0x1UL << SYSCFG_PMC_I2C1_FMP_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_PMC_I2C1_FMP SYSCFG_PMC_I2C1_FMP_Msk /*!< I2C1_FMP I2C1 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C2_FMP_Pos (1U)\r
+#define SYSCFG_PMC_I2C2_FMP_Msk (0x1UL << SYSCFG_PMC_I2C2_FMP_Pos) /*!< 0x00000002 */\r
+#define SYSCFG_PMC_I2C2_FMP SYSCFG_PMC_I2C2_FMP_Msk /*!< I2C2_FMP I2C2 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C3_FMP_Pos (2U)\r
+#define SYSCFG_PMC_I2C3_FMP_Msk (0x1UL << SYSCFG_PMC_I2C3_FMP_Pos) /*!< 0x00000004 */\r
+#define SYSCFG_PMC_I2C3_FMP SYSCFG_PMC_I2C3_FMP_Msk /*!< I2C3_FMP I2C3 Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB6_FMP_Pos (4U)\r
+#define SYSCFG_PMC_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB6_FMP_Pos) /*!< 0x00000010 */\r
+#define SYSCFG_PMC_I2C_PB6_FMP SYSCFG_PMC_I2C_PB6_FMP_Msk /*!< PB6_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB7_FMP_Pos (5U)\r
+#define SYSCFG_PMC_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB7_FMP_Pos) /*!< 0x00000020 */\r
+#define SYSCFG_PMC_I2C_PB7_FMP SYSCFG_PMC_I2C_PB7_FMP_Msk /*!< PB7_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB8_FMP_Pos (6U)\r
+#define SYSCFG_PMC_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB8_FMP_Pos) /*!< 0x00000040 */\r
+#define SYSCFG_PMC_I2C_PB8_FMP SYSCFG_PMC_I2C_PB8_FMP_Msk /*!< PB8_FMP Fast Mode + Enable */\r
+#define SYSCFG_PMC_I2C_PB9_FMP_Pos (7U)\r
+#define SYSCFG_PMC_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMC_I2C_PB9_FMP_Pos) /*!< 0x00000080 */\r
+#define SYSCFG_PMC_I2C_PB9_FMP SYSCFG_PMC_I2C_PB9_FMP_Msk /*!< PB9_FMP Fast Mode + Enable */\r
+\r
+#define SYSCFG_PMC_ADCxDC2_Pos (16U)\r
+#define SYSCFG_PMC_ADCxDC2_Msk (0x7UL << SYSCFG_PMC_ADCxDC2_Pos) /*!< 0x00070000 */\r
+#define SYSCFG_PMC_ADCxDC2 SYSCFG_PMC_ADCxDC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC1DC2_Pos (16U)\r
+#define SYSCFG_PMC_ADC1DC2_Msk (0x1UL << SYSCFG_PMC_ADC1DC2_Pos) /*!< 0x00010000 */\r
+#define SYSCFG_PMC_ADC1DC2 SYSCFG_PMC_ADC1DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC2DC2_Pos (17U)\r
+#define SYSCFG_PMC_ADC2DC2_Msk (0x1UL << SYSCFG_PMC_ADC2DC2_Pos) /*!< 0x00020000 */\r
+#define SYSCFG_PMC_ADC2DC2 SYSCFG_PMC_ADC2DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+#define SYSCFG_PMC_ADC3DC2_Pos (18U)\r
+#define SYSCFG_PMC_ADC3DC2_Msk (0x1UL << SYSCFG_PMC_ADC3DC2_Pos) /*!< 0x00040000 */\r
+#define SYSCFG_PMC_ADC3DC2 SYSCFG_PMC_ADC3DC2_Msk /*!< Refer to AN4073 on how to use this bit */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
+#define SYSCFG_EXTICR1_EXTI0_Pos (0U)\r
+#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1_Pos (4U)\r
+#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2_Pos (8U)\r
+#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3_Pos (12U)\r
+#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */\r
+/**\r
+ * @brief EXTI0 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /*!<PI[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /*!<PK[0] pin */\r
+\r
+/**\r
+ * @brief EXTI1 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /*!<PI[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /*!<PK[1] pin */\r
+\r
+/**\r
+ * @brief EXTI2 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /*!<PI[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /*!<PK[2] pin */\r
+\r
+/**\r
+ * @brief EXTI3 configuration\r
+ */\r
+#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /*!<PI[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /*!<PK[3] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
+#define SYSCFG_EXTICR2_EXTI4_Pos (0U)\r
+#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5_Pos (4U)\r
+#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6_Pos (8U)\r
+#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7_Pos (12U)\r
+#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */\r
+/**\r
+ * @brief EXTI4 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /*!<PI[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /*!<PK[4] pin */\r
+\r
+/**\r
+ * @brief EXTI5 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /*!<PI[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /*!<PK[5] pin */\r
+\r
+/**\r
+ * @brief EXTI6 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /*!<PI[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /*!<PK[6] pin */\r
+\r
+/**\r
+ * @brief EXTI7 configuration\r
+ */\r
+#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /*!<PI[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /*!<PK[7] pin */\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
+#define SYSCFG_EXTICR3_EXTI8_Pos (0U)\r
+#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9_Pos (4U)\r
+#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10_Pos (8U)\r
+#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11_Pos (12U)\r
+#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */\r
+\r
+/**\r
+ * @brief EXTI8 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /*!<PI[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /*!<PJ[8] pin */\r
+\r
+/**\r
+ * @brief EXTI9 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /*!<PI[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /*!<PJ[9] pin */\r
+\r
+/**\r
+ * @brief EXTI10 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /*!<PI[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /*!<PJ[10] pin */\r
+\r
+/**\r
+ * @brief EXTI11 configuration\r
+ */\r
+#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /*!<PI[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /*!<PJ[11] pin */\r
+\r
+\r
+/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
+#define SYSCFG_EXTICR4_EXTI12_Pos (0U)\r
+#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */\r
+#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13_Pos (4U)\r
+#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */\r
+#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14_Pos (8U)\r
+#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */\r
+#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15_Pos (12U)\r
+#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */\r
+#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */\r
+/**\r
+ * @brief EXTI12 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /*!<PH[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /*!<PJ[12] pin */\r
+\r
+/**\r
+ * @brief EXTI13 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /*!<PH[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /*!<PJ[13] pin */\r
+\r
+/**\r
+ * @brief EXTI14 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /*!<PH[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /*!<PJ[14] pin */\r
+\r
+/**\r
+ * @brief EXTI15 configuration\r
+ */\r
+#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /*!<PH[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /*!<PJ[15] pin */\r
+\r
+\r
+/****************** Bit definition for SYSCFG_CMPCR register ****************/\r
+#define SYSCFG_CMPCR_CMP_PD_Pos (0U)\r
+#define SYSCFG_CMPCR_CMP_PD_Msk (0x1UL << SYSCFG_CMPCR_CMP_PD_Pos) /*!< 0x00000001 */\r
+#define SYSCFG_CMPCR_CMP_PD SYSCFG_CMPCR_CMP_PD_Msk /*!<Compensation cell power-down */\r
+#define SYSCFG_CMPCR_READY_Pos (8U)\r
+#define SYSCFG_CMPCR_READY_Msk (0x1UL << SYSCFG_CMPCR_READY_Pos) /*!< 0x00000100 */\r
+#define SYSCFG_CMPCR_READY SYSCFG_CMPCR_READY_Msk /*!<Compensation cell ready flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* TIM */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for TIM_CR1 register ********************/\r
+#define TIM_CR1_CEN_Pos (0U)\r
+#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */\r
+#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */\r
+#define TIM_CR1_UDIS_Pos (1U)\r
+#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */\r
+#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */\r
+#define TIM_CR1_URS_Pos (2U)\r
+#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */\r
+#define TIM_CR1_OPM_Pos (3U)\r
+#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */\r
+#define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */\r
+#define TIM_CR1_DIR_Pos (4U)\r
+#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */\r
+#define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */\r
+\r
+#define TIM_CR1_CMS_Pos (5U)\r
+#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */\r
+#define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x0020 */\r
+#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_CR1_ARPE_Pos (7U)\r
+#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */\r
+#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */\r
+\r
+#define TIM_CR1_CKD_Pos (8U)\r
+#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */\r
+#define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */\r
+#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x0100 */\r
+#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x0200 */\r
+#define TIM_CR1_UIFREMAP_Pos (11U)\r
+#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */\r
+#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<UIF status bit */\r
+\r
+/******************* Bit definition for TIM_CR2 register ********************/\r
+#define TIM_CR2_CCPC_Pos (0U)\r
+#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */\r
+#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */\r
+#define TIM_CR2_CCUS_Pos (2U)\r
+#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */\r
+#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */\r
+#define TIM_CR2_CCDS_Pos (3U)\r
+#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */\r
+#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */\r
+\r
+#define TIM_CR2_OIS5_Pos (16U)\r
+#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */\r
+#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */\r
+#define TIM_CR2_OIS6_Pos (18U)\r
+#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00040000 */\r
+#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */\r
+\r
+#define TIM_CR2_MMS_Pos (4U)\r
+#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */\r
+#define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x0010 */\r
+#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x0020 */\r
+#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_CR2_MMS2_Pos (20U)\r
+#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */\r
+#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */\r
+#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */\r
+#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */\r
+#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */\r
+\r
+#define TIM_CR2_TI1S_Pos (7U)\r
+#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */\r
+#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */\r
+#define TIM_CR2_OIS1_Pos (8U)\r
+#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */\r
+#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */\r
+#define TIM_CR2_OIS1N_Pos (9U)\r
+#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */\r
+#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */\r
+#define TIM_CR2_OIS2_Pos (10U)\r
+#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */\r
+#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */\r
+#define TIM_CR2_OIS2N_Pos (11U)\r
+#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */\r
+#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */\r
+#define TIM_CR2_OIS3_Pos (12U)\r
+#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */\r
+#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */\r
+#define TIM_CR2_OIS3N_Pos (13U)\r
+#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */\r
+#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */\r
+#define TIM_CR2_OIS4_Pos (14U)\r
+#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */\r
+#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */\r
+\r
+/******************* Bit definition for TIM_SMCR register *******************/\r
+#define TIM_SMCR_SMS_Pos (0U)\r
+#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */\r
+#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */\r
+#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */\r
+#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */\r
+#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */\r
+#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_SMCR_TS_Pos (4U)\r
+#define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */\r
+#define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */\r
+#define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x0010 */\r
+#define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x0020 */\r
+#define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x0040 */\r
+\r
+#define TIM_SMCR_MSM_Pos (7U)\r
+#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */\r
+#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */\r
+\r
+#define TIM_SMCR_ETF_Pos (8U)\r
+#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */\r
+#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */\r
+#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x0100 */\r
+#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x0200 */\r
+#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x0400 */\r
+#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_SMCR_ETPS_Pos (12U)\r
+#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */\r
+#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x1000 */\r
+#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x2000 */\r
+\r
+#define TIM_SMCR_ECE_Pos (14U)\r
+#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */\r
+#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */\r
+#define TIM_SMCR_ETP_Pos (15U)\r
+#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */\r
+#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */\r
+\r
+/******************* Bit definition for TIM_DIER register *******************/\r
+#define TIM_DIER_UIE_Pos (0U)\r
+#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */\r
+#define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */\r
+#define TIM_DIER_CC1IE_Pos (1U)\r
+#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */\r
+#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */\r
+#define TIM_DIER_CC2IE_Pos (2U)\r
+#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */\r
+#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */\r
+#define TIM_DIER_CC3IE_Pos (3U)\r
+#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */\r
+#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */\r
+#define TIM_DIER_CC4IE_Pos (4U)\r
+#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */\r
+#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */\r
+#define TIM_DIER_COMIE_Pos (5U)\r
+#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */\r
+#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */\r
+#define TIM_DIER_TIE_Pos (6U)\r
+#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */\r
+#define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */\r
+#define TIM_DIER_BIE_Pos (7U)\r
+#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */\r
+#define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */\r
+#define TIM_DIER_UDE_Pos (8U)\r
+#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */\r
+#define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */\r
+#define TIM_DIER_CC1DE_Pos (9U)\r
+#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */\r
+#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */\r
+#define TIM_DIER_CC2DE_Pos (10U)\r
+#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */\r
+#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */\r
+#define TIM_DIER_CC3DE_Pos (11U)\r
+#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */\r
+#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */\r
+#define TIM_DIER_CC4DE_Pos (12U)\r
+#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */\r
+#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */\r
+#define TIM_DIER_COMDE_Pos (13U)\r
+#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */\r
+#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */\r
+#define TIM_DIER_TDE_Pos (14U)\r
+#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */\r
+#define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */\r
+\r
+/******************** Bit definition for TIM_SR register ********************/\r
+#define TIM_SR_UIF_Pos (0U)\r
+#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */\r
+#define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */\r
+#define TIM_SR_CC1IF_Pos (1U)\r
+#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */\r
+#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */\r
+#define TIM_SR_CC2IF_Pos (2U)\r
+#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */\r
+#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */\r
+#define TIM_SR_CC3IF_Pos (3U)\r
+#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */\r
+#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */\r
+#define TIM_SR_CC4IF_Pos (4U)\r
+#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */\r
+#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */\r
+#define TIM_SR_COMIF_Pos (5U)\r
+#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */\r
+#define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */\r
+#define TIM_SR_TIF_Pos (6U)\r
+#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */\r
+#define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */\r
+#define TIM_SR_BIF_Pos (7U)\r
+#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */\r
+#define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */\r
+#define TIM_SR_B2IF_Pos (8U)\r
+#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */\r
+#define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */\r
+#define TIM_SR_CC1OF_Pos (9U)\r
+#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */\r
+#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */\r
+#define TIM_SR_CC2OF_Pos (10U)\r
+#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */\r
+#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */\r
+#define TIM_SR_CC3OF_Pos (11U)\r
+#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */\r
+#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */\r
+#define TIM_SR_CC4OF_Pos (12U)\r
+#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */\r
+#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */\r
+#define TIM_SR_SBIF_Pos (13U)\r
+#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */\r
+#define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!<System Break interrupt Flag */\r
+#define TIM_SR_CC5IF_Pos (16U)\r
+#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */\r
+#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */\r
+#define TIM_SR_CC6IF_Pos (17U)\r
+#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */\r
+#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */\r
+\r
+/******************* Bit definition for TIM_EGR register ********************/\r
+#define TIM_EGR_UG_Pos (0U)\r
+#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */\r
+#define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */\r
+#define TIM_EGR_CC1G_Pos (1U)\r
+#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */\r
+#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */\r
+#define TIM_EGR_CC2G_Pos (2U)\r
+#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */\r
+#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */\r
+#define TIM_EGR_CC3G_Pos (3U)\r
+#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */\r
+#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */\r
+#define TIM_EGR_CC4G_Pos (4U)\r
+#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */\r
+#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */\r
+#define TIM_EGR_COMG_Pos (5U)\r
+#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */\r
+#define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */\r
+#define TIM_EGR_TG_Pos (6U)\r
+#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */\r
+#define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */\r
+#define TIM_EGR_BG_Pos (7U)\r
+#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */\r
+#define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */\r
+#define TIM_EGR_B2G_Pos (8U)\r
+#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */\r
+#define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break2 Generation */\r
+\r
+/****************** Bit definition for TIM_CCMR1 register *******************/\r
+#define TIM_CCMR1_CC1S_Pos (0U)\r
+#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR1_OC1FE_Pos (2U)\r
+#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */\r
+#define TIM_CCMR1_OC1PE_Pos (3U)\r
+#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */\r
+\r
+#define TIM_CCMR1_OC1M_Pos (4U)\r
+#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
+#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR1_OC1CE_Pos (7U)\r
+#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */\r
+\r
+#define TIM_CCMR1_CC2S_Pos (8U)\r
+#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR1_OC2FE_Pos (10U)\r
+#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */\r
+#define TIM_CCMR1_OC2PE_Pos (11U)\r
+#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */\r
+\r
+#define TIM_CCMR1_OC2M_Pos (12U)\r
+#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
+#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR1_OC2CE_Pos (15U)\r
+#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR1_IC1PSC_Pos (2U)\r
+#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0004 */\r
+#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0008 */\r
+\r
+#define TIM_CCMR1_IC1F_Pos (4U)\r
+#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
+#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0010 */\r
+#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0020 */\r
+#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0040 */\r
+#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x0080 */\r
+\r
+#define TIM_CCMR1_IC2PSC_Pos (10U)\r
+#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
+#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0400 */\r
+#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_CCMR1_IC2F_Pos (12U)\r
+#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
+#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x1000 */\r
+#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x2000 */\r
+#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x4000 */\r
+#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x8000 */\r
+\r
+/****************** Bit definition for TIM_CCMR2 register *******************/\r
+#define TIM_CCMR2_CC3S_Pos (0U)\r
+#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */\r
+#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
+#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */\r
+#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */\r
+\r
+#define TIM_CCMR2_OC3FE_Pos (2U)\r
+#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */\r
+#define TIM_CCMR2_OC3PE_Pos (3U)\r
+#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */\r
+\r
+#define TIM_CCMR2_OC3M_Pos (4U)\r
+#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */\r
+\r
+\r
+\r
+#define TIM_CCMR2_OC3CE_Pos (7U)\r
+#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */\r
+\r
+#define TIM_CCMR2_CC4S_Pos (8U)\r
+#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */\r
+#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */\r
+#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_CCMR2_OC4FE_Pos (10U)\r
+#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR2_OC4PE_Pos (11U)\r
+#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR2_OC4M_Pos (12U)\r
+#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR2_OC4CE_Pos (15U)\r
+#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define TIM_CCMR2_IC3PSC_Pos (2U)\r
+#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */\r
+#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0004 */\r
+#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0008 */\r
+\r
+#define TIM_CCMR2_IC3F_Pos (4U)\r
+#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */\r
+#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0010 */\r
+#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0020 */\r
+#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0040 */\r
+#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x0080 */\r
+\r
+#define TIM_CCMR2_IC4PSC_Pos (10U)\r
+#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */\r
+#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0400 */\r
+#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x0800 */\r
+\r
+#define TIM_CCMR2_IC4F_Pos (12U)\r
+#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */\r
+#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x1000 */\r
+#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x2000 */\r
+#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x4000 */\r
+#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x8000 */\r
+\r
+/******************* Bit definition for TIM_CCER register *******************/\r
+#define TIM_CCER_CC1E_Pos (0U)\r
+#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */\r
+#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */\r
+#define TIM_CCER_CC1P_Pos (1U)\r
+#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */\r
+#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */\r
+#define TIM_CCER_CC1NE_Pos (2U)\r
+#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */\r
+#define TIM_CCER_CC1NP_Pos (3U)\r
+#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */\r
+#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define TIM_CCER_CC2E_Pos (4U)\r
+#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */\r
+#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */\r
+#define TIM_CCER_CC2P_Pos (5U)\r
+#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */\r
+#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */\r
+#define TIM_CCER_CC2NE_Pos (6U)\r
+#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */\r
+#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */\r
+#define TIM_CCER_CC2NP_Pos (7U)\r
+#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */\r
+#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define TIM_CCER_CC3E_Pos (8U)\r
+#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */\r
+#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */\r
+#define TIM_CCER_CC3P_Pos (9U)\r
+#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */\r
+#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */\r
+#define TIM_CCER_CC3NE_Pos (10U)\r
+#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */\r
+#define TIM_CCER_CC3NP_Pos (11U)\r
+#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */\r
+#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define TIM_CCER_CC4E_Pos (12U)\r
+#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */\r
+#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */\r
+#define TIM_CCER_CC4P_Pos (13U)\r
+#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */\r
+#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */\r
+#define TIM_CCER_CC4NP_Pos (15U)\r
+#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */\r
+#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */\r
+#define TIM_CCER_CC5E_Pos (16U)\r
+#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */\r
+#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */\r
+#define TIM_CCER_CC5P_Pos (17U)\r
+#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */\r
+#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */\r
+#define TIM_CCER_CC6E_Pos (20U)\r
+#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */\r
+#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */\r
+#define TIM_CCER_CC6P_Pos (21U)\r
+#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */\r
+#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */\r
+\r
+\r
+/******************* Bit definition for TIM_CNT register ********************/\r
+#define TIM_CNT_CNT_Pos (0U)\r
+#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */\r
+#define TIM_CNT_UIFCPY_Pos (31U)\r
+#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */\r
+#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy (if UIFREMAP=1) */\r
+\r
+/******************* Bit definition for TIM_PSC register ********************/\r
+#define TIM_PSC_PSC_Pos (0U)\r
+#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */\r
+#define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */\r
+\r
+/******************* Bit definition for TIM_ARR register ********************/\r
+#define TIM_ARR_ARR_Pos (0U)\r
+#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */\r
+\r
+/******************* Bit definition for TIM_RCR register ********************/\r
+#define TIM_RCR_REP_Pos (0U)\r
+#define TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) /*!< 0x0000FFFF */\r
+#define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */\r
+\r
+/******************* Bit definition for TIM_CCR1 register *******************/\r
+#define TIM_CCR1_CCR1_Pos (0U)\r
+#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */\r
+\r
+/******************* Bit definition for TIM_CCR2 register *******************/\r
+#define TIM_CCR2_CCR2_Pos (0U)\r
+#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */\r
+\r
+/******************* Bit definition for TIM_CCR3 register *******************/\r
+#define TIM_CCR3_CCR3_Pos (0U)\r
+#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */\r
+\r
+/******************* Bit definition for TIM_CCR4 register *******************/\r
+#define TIM_CCR4_CCR4_Pos (0U)\r
+#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */\r
+#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */\r
+\r
+/******************* Bit definition for TIM_BDTR register *******************/\r
+#define TIM_BDTR_DTG_Pos (0U)\r
+#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */\r
+#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */\r
+#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */\r
+#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */\r
+#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */\r
+#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */\r
+#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */\r
+#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */\r
+#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */\r
+\r
+#define TIM_BDTR_LOCK_Pos (8U)\r
+#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */\r
+#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */\r
+#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */\r
+\r
+#define TIM_BDTR_OSSI_Pos (10U)\r
+#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */\r
+#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */\r
+#define TIM_BDTR_OSSR_Pos (11U)\r
+#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */\r
+#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */\r
+#define TIM_BDTR_BKE_Pos (12U)\r
+#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */\r
+#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */\r
+#define TIM_BDTR_BKP_Pos (13U)\r
+#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */\r
+#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */\r
+#define TIM_BDTR_AOE_Pos (14U)\r
+#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */\r
+#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */\r
+#define TIM_BDTR_MOE_Pos (15U)\r
+#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */\r
+#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */\r
+#define TIM_BDTR_BKF_Pos (16U)\r
+#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */\r
+#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */\r
+#define TIM_BDTR_BK2F_Pos (20U)\r
+#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */\r
+#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */\r
+#define TIM_BDTR_BK2E_Pos (24U)\r
+#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */\r
+#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */\r
+#define TIM_BDTR_BK2P_Pos (25U)\r
+#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */\r
+#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */\r
+\r
+/******************* Bit definition for TIM_DCR register ********************/\r
+#define TIM_DCR_DBA_Pos (0U)\r
+#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */\r
+#define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x0001 */\r
+#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x0002 */\r
+#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x0004 */\r
+#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x0008 */\r
+#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x0010 */\r
+\r
+#define TIM_DCR_DBL_Pos (8U)\r
+#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */\r
+#define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x0100 */\r
+#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x0200 */\r
+#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x0400 */\r
+#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x0800 */\r
+#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x1000 */\r
+\r
+/******************* Bit definition for TIM_DMAR register *******************/\r
+#define TIM_DMAR_DMAB_Pos (0U)\r
+#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */\r
+#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */\r
+\r
+/******************* Bit definition for TIM_OR regiter *********************/\r
+#define TIM_OR_TI4_RMP_Pos (6U)\r
+#define TIM_OR_TI4_RMP_Msk (0x3UL << TIM_OR_TI4_RMP_Pos) /*!< 0x000000C0 */\r
+#define TIM_OR_TI4_RMP TIM_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
+#define TIM_OR_TI4_RMP_0 (0x1UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0040 */\r
+#define TIM_OR_TI4_RMP_1 (0x2UL << TIM_OR_TI4_RMP_Pos) /*!< 0x0080 */\r
+#define TIM_OR_ITR1_RMP_Pos (10U)\r
+#define TIM_OR_ITR1_RMP_Msk (0x3UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */\r
+#define TIM_OR_ITR1_RMP TIM_OR_ITR1_RMP_Msk /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0 (0x1UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0400 */\r
+#define TIM_OR_ITR1_RMP_1 (0x2UL << TIM_OR_ITR1_RMP_Pos) /*!< 0x0800 */\r
+\r
+/******************* Bit definition for TIM2_OR register *******************/\r
+#define TIM2_OR_ITR1_RMP_Pos (10U)\r
+#define TIM2_OR_ITR1_RMP_Msk (0x3UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000C00 */\r
+#define TIM2_OR_ITR1_RMP TIM2_OR_ITR1_RMP_Msk /*!<TIM2 Internal trigger 1 remap */\r
+#define TIM2_OR_ITR1_RMP_0 (0x1UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000400 */\r
+#define TIM2_OR_ITR1_RMP_1 (0x2UL << TIM2_OR_ITR1_RMP_Pos) /*!< 0x00000800 */\r
+\r
+/******************* Bit definition for TIM5_OR register *******************/\r
+#define TIM5_OR_TI4_RMP_Pos (6U)\r
+#define TIM5_OR_TI4_RMP_Msk (0x3UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x000000C0 */\r
+#define TIM5_OR_TI4_RMP TIM5_OR_TI4_RMP_Msk /*!<TI4_RMP[1:0] bits (TIM5 Input Capture 4 remap) */\r
+#define TIM5_OR_TI4_RMP_0 (0x1UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000040 */\r
+#define TIM5_OR_TI4_RMP_1 (0x2UL << TIM5_OR_TI4_RMP_Pos) /*!< 0x00000080 */\r
+\r
+/******************* Bit definition for TIM11_OR register *******************/\r
+#define TIM11_OR_TI1_RMP_Pos (0U)\r
+#define TIM11_OR_TI1_RMP_Msk (0x3UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000003 */\r
+#define TIM11_OR_TI1_RMP TIM11_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM11 Input Capture 1 remap) */\r
+#define TIM11_OR_TI1_RMP_0 (0x1UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000001 */\r
+#define TIM11_OR_TI1_RMP_1 (0x2UL << TIM11_OR_TI1_RMP_Pos) /*!< 0x00000002 */\r
+\r
+/****************** Bit definition for TIM_CCMR3 register *******************/\r
+#define TIM_CCMR3_OC5FE_Pos (2U)\r
+#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */\r
+#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */\r
+#define TIM_CCMR3_OC5PE_Pos (3U)\r
+#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */\r
+#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */\r
+\r
+#define TIM_CCMR3_OC5M_Pos (4U)\r
+#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010070 */\r
+#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */\r
+#define TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */\r
+#define TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */\r
+#define TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */\r
+#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */\r
+\r
+#define TIM_CCMR3_OC5CE_Pos (7U)\r
+#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */\r
+#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */\r
+\r
+#define TIM_CCMR3_OC6FE_Pos (10U)\r
+#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */\r
+#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */\r
+#define TIM_CCMR3_OC6PE_Pos (11U)\r
+#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */\r
+#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */\r
+\r
+#define TIM_CCMR3_OC6M_Pos (12U)\r
+#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01007000 */\r
+#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */\r
+#define TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */\r
+#define TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */\r
+#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) /*!< 0x01000000 */\r
+\r
+#define TIM_CCMR3_OC6CE_Pos (15U)\r
+#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */\r
+#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */\r
+\r
+/******************* Bit definition for TIM_CCR5 register *******************/\r
+#define TIM_CCR5_CCR5_Pos (0U)\r
+#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */\r
+#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */\r
+#define TIM_CCR5_GC5C1_Pos (29U)\r
+#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */\r
+#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */\r
+#define TIM_CCR5_GC5C2_Pos (30U)\r
+#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */\r
+#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */\r
+#define TIM_CCR5_GC5C3_Pos (31U)\r
+#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */\r
+#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */\r
+\r
+/******************* Bit definition for TIM_CCR6 register *******************/\r
+#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /*!<Capture/Compare 6 Value */\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Low Power Timer (LPTIM) */\r
+/* */\r
+/******************************************************************************/\r
+/****************** Bit definition for LPTIM_ISR register *******************/\r
+#define LPTIM_ISR_CMPM_Pos (0U)\r
+#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */\r
+#define LPTIM_ISR_ARRM_Pos (1U)\r
+#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */\r
+#define LPTIM_ISR_EXTTRIG_Pos (2U)\r
+#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */\r
+#define LPTIM_ISR_CMPOK_Pos (3U)\r
+#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */\r
+#define LPTIM_ISR_ARROK_Pos (4U)\r
+#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */\r
+#define LPTIM_ISR_UP_Pos (5U)\r
+#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */\r
+#define LPTIM_ISR_DOWN_Pos (6U)\r
+#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */\r
+\r
+/****************** Bit definition for LPTIM_ICR register *******************/\r
+#define LPTIM_ICR_CMPMCF_Pos (0U)\r
+#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */\r
+#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */\r
+#define LPTIM_ICR_ARRMCF_Pos (1U)\r
+#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */\r
+#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */\r
+#define LPTIM_ICR_EXTTRIGCF_Pos (2U)\r
+#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */\r
+#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */\r
+#define LPTIM_ICR_CMPOKCF_Pos (3U)\r
+#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */\r
+#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */\r
+#define LPTIM_ICR_ARROKCF_Pos (4U)\r
+#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */\r
+#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */\r
+#define LPTIM_ICR_UPCF_Pos (5U)\r
+#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */\r
+#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */\r
+#define LPTIM_ICR_DOWNCF_Pos (6U)\r
+#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */\r
+#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */\r
+\r
+/****************** Bit definition for LPTIM_IER register *******************/\r
+#define LPTIM_IER_CMPMIE_Pos (0U)\r
+#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */\r
+#define LPTIM_IER_ARRMIE_Pos (1U)\r
+#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */\r
+#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */\r
+#define LPTIM_IER_EXTTRIGIE_Pos (2U)\r
+#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */\r
+#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */\r
+#define LPTIM_IER_CMPOKIE_Pos (3U)\r
+#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */\r
+#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */\r
+#define LPTIM_IER_ARROKIE_Pos (4U)\r
+#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */\r
+#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */\r
+#define LPTIM_IER_UPIE_Pos (5U)\r
+#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */\r
+#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */\r
+#define LPTIM_IER_DOWNIE_Pos (6U)\r
+#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */\r
+#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */\r
+\r
+/****************** Bit definition for LPTIM_CFGR register*******************/\r
+#define LPTIM_CFGR_CKSEL_Pos (0U)\r
+#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */\r
+\r
+#define LPTIM_CFGR_CKPOL_Pos (1U)\r
+#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */\r
+#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */\r
+#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */\r
+\r
+#define LPTIM_CFGR_CKFLT_Pos (3U)\r
+#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */\r
+#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */\r
+#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */\r
+#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */\r
+\r
+#define LPTIM_CFGR_TRGFLT_Pos (6U)\r
+#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */\r
+#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */\r
+#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */\r
+#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */\r
+\r
+#define LPTIM_CFGR_PRESC_Pos (9U)\r
+#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */\r
+#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */\r
+#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */\r
+#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */\r
+#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */\r
+\r
+#define LPTIM_CFGR_TRIGSEL_Pos (13U)\r
+#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */\r
+#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */\r
+#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */\r
+#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */\r
+#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */\r
+\r
+#define LPTIM_CFGR_TRIGEN_Pos (17U)\r
+#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */\r
+#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */\r
+#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */\r
+#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */\r
+\r
+#define LPTIM_CFGR_TIMOUT_Pos (19U)\r
+#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */\r
+#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */\r
+#define LPTIM_CFGR_WAVE_Pos (20U)\r
+#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */\r
+#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */\r
+#define LPTIM_CFGR_WAVPOL_Pos (21U)\r
+#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */\r
+#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */\r
+#define LPTIM_CFGR_PRELOAD_Pos (22U)\r
+#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */\r
+#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */\r
+#define LPTIM_CFGR_COUNTMODE_Pos (23U)\r
+#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */\r
+#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */\r
+#define LPTIM_CFGR_ENC_Pos (24U)\r
+#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */\r
+#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */\r
+\r
+/****************** Bit definition for LPTIM_CR register ********************/\r
+#define LPTIM_CR_ENABLE_Pos (0U)\r
+#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */\r
+#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */\r
+#define LPTIM_CR_SNGSTRT_Pos (1U)\r
+#define LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00000002 */\r
+#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */\r
+#define LPTIM_CR_CNTSTRT_Pos (2U)\r
+#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */\r
+#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */\r
+\r
+/****************** Bit definition for LPTIM_CMP register *******************/\r
+#define LPTIM_CMP_CMP_Pos (0U)\r
+#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */\r
+\r
+/****************** Bit definition for LPTIM_ARR register *******************/\r
+#define LPTIM_ARR_ARR_Pos (0U)\r
+#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */\r
+\r
+/****************** Bit definition for LPTIM_CNT register *******************/\r
+#define LPTIM_CNT_CNT_Pos (0U)\r
+#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */\r
+#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */\r
+/******************************************************************************/\r
+/* */\r
+/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */\r
+/* */\r
+/******************************************************************************/\r
+/*\r
+ * @brief Specific device feature definitions (not present on all devices in the STM32F7 serie)\r
+ */\r
+/* Support of TCBGT feature : Supported from USART IP version c7amba_sci3 v1.3 */\r
+#define USART_TCBGT_SUPPORT\r
+/****************** Bit definition for USART_CR1 register *******************/\r
+#define USART_CR1_UE_Pos (0U)\r
+#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */\r
+#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */\r
+#define USART_CR1_RE_Pos (2U)\r
+#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */\r
+#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */\r
+#define USART_CR1_TE_Pos (3U)\r
+#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */\r
+#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */\r
+#define USART_CR1_IDLEIE_Pos (4U)\r
+#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */\r
+#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */\r
+#define USART_CR1_RXNEIE_Pos (5U)\r
+#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */\r
+#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */\r
+#define USART_CR1_TCIE_Pos (6U)\r
+#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */\r
+#define USART_CR1_TXEIE_Pos (7U)\r
+#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */\r
+#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */\r
+#define USART_CR1_PEIE_Pos (8U)\r
+#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */\r
+#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */\r
+#define USART_CR1_PS_Pos (9U)\r
+#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */\r
+#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */\r
+#define USART_CR1_PCE_Pos (10U)\r
+#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */\r
+#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */\r
+#define USART_CR1_WAKE_Pos (11U)\r
+#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */\r
+#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */\r
+#define USART_CR1_M_Pos (12U)\r
+#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */\r
+#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */\r
+#define USART_CR1_M0 (0x00001UL << USART_CR1_M_Pos) /*!< 0x00001000 */\r
+#define USART_CR1_MME_Pos (13U)\r
+#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */\r
+#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */\r
+#define USART_CR1_CMIE_Pos (14U)\r
+#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */\r
+#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */\r
+#define USART_CR1_OVER8_Pos (15U)\r
+#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */\r
+#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */\r
+#define USART_CR1_DEDT_Pos (16U)\r
+#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */\r
+#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */\r
+#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */\r
+#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */\r
+#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */\r
+#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */\r
+#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */\r
+#define USART_CR1_DEAT_Pos (21U)\r
+#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */\r
+#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */\r
+#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */\r
+#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */\r
+#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */\r
+#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */\r
+#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */\r
+#define USART_CR1_RTOIE_Pos (26U)\r
+#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */\r
+#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */\r
+#define USART_CR1_EOBIE_Pos (27U)\r
+#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */\r
+#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */\r
+#define USART_CR1_M1 0x10000000U /*!< Word length - Bit 1 */\r
+\r
+/* Legacy defines */\r
+#define USART_CR1_M_0 USART_CR1_M0 /*!< Word length - Bit 0 */\r
+#define USART_CR1_M_1 USART_CR1_M1 /*!< Word length - Bit 1 */\r
+\r
+/****************** Bit definition for USART_CR2 register *******************/\r
+#define USART_CR2_ADDM7_Pos (4U)\r
+#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */\r
+#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */\r
+#define USART_CR2_LBDL_Pos (5U)\r
+#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */\r
+#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */\r
+#define USART_CR2_LBDIE_Pos (6U)\r
+#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */\r
+#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */\r
+#define USART_CR2_LBCL_Pos (8U)\r
+#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */\r
+#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */\r
+#define USART_CR2_CPHA_Pos (9U)\r
+#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */\r
+#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */\r
+#define USART_CR2_CPOL_Pos (10U)\r
+#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */\r
+#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */\r
+#define USART_CR2_CLKEN_Pos (11U)\r
+#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */\r
+#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */\r
+#define USART_CR2_STOP_Pos (12U)\r
+#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */\r
+#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */\r
+#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */\r
+#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */\r
+#define USART_CR2_LINEN_Pos (14U)\r
+#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */\r
+#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */\r
+#define USART_CR2_SWAP_Pos (15U)\r
+#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */\r
+#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */\r
+#define USART_CR2_RXINV_Pos (16U)\r
+#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */\r
+#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */\r
+#define USART_CR2_TXINV_Pos (17U)\r
+#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */\r
+#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */\r
+#define USART_CR2_DATAINV_Pos (18U)\r
+#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */\r
+#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */\r
+#define USART_CR2_MSBFIRST_Pos (19U)\r
+#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */\r
+#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */\r
+#define USART_CR2_ABREN_Pos (20U)\r
+#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */\r
+#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable */\r
+#define USART_CR2_ABRMODE_Pos (21U)\r
+#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */\r
+#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */\r
+#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */\r
+#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */\r
+#define USART_CR2_RTOEN_Pos (23U)\r
+#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */\r
+#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */\r
+#define USART_CR2_ADD_Pos (24U)\r
+#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */\r
+#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */\r
+\r
+/****************** Bit definition for USART_CR3 register *******************/\r
+#define USART_CR3_EIE_Pos (0U)\r
+#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */\r
+#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */\r
+#define USART_CR3_IREN_Pos (1U)\r
+#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */\r
+#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */\r
+#define USART_CR3_IRLP_Pos (2U)\r
+#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */\r
+#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */\r
+#define USART_CR3_HDSEL_Pos (3U)\r
+#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */\r
+#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */\r
+#define USART_CR3_NACK_Pos (4U)\r
+#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */\r
+#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */\r
+#define USART_CR3_SCEN_Pos (5U)\r
+#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */\r
+#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */\r
+#define USART_CR3_DMAR_Pos (6U)\r
+#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */\r
+#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */\r
+#define USART_CR3_DMAT_Pos (7U)\r
+#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */\r
+#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */\r
+#define USART_CR3_RTSE_Pos (8U)\r
+#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */\r
+#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */\r
+#define USART_CR3_CTSE_Pos (9U)\r
+#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */\r
+#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */\r
+#define USART_CR3_CTSIE_Pos (10U)\r
+#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */\r
+#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */\r
+#define USART_CR3_ONEBIT_Pos (11U)\r
+#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */\r
+#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */\r
+#define USART_CR3_OVRDIS_Pos (12U)\r
+#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */\r
+#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */\r
+#define USART_CR3_DDRE_Pos (13U)\r
+#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */\r
+#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */\r
+#define USART_CR3_DEM_Pos (14U)\r
+#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */\r
+#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */\r
+#define USART_CR3_DEP_Pos (15U)\r
+#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */\r
+#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */\r
+#define USART_CR3_SCARCNT_Pos (17U)\r
+#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */\r
+#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */\r
+#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */\r
+#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */\r
+#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */\r
+#define USART_CR3_TCBGTIE_Pos (24U)\r
+#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */\r
+#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission complete before guard time interrupt enable */\r
+\r
+/****************** Bit definition for USART_BRR register *******************/\r
+#define USART_BRR_DIV_FRACTION_Pos (0U)\r
+#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */\r
+#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */\r
+#define USART_BRR_DIV_MANTISSA_Pos (4U)\r
+#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */\r
+#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */\r
+\r
+/****************** Bit definition for USART_GTPR register ******************/\r
+#define USART_GTPR_PSC_Pos (0U)\r
+#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */\r
+#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */\r
+#define USART_GTPR_GT_Pos (8U)\r
+#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */\r
+#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */\r
+\r
+\r
+/******************* Bit definition for USART_RTOR register *****************/\r
+#define USART_RTOR_RTO_Pos (0U)\r
+#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */\r
+#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */\r
+#define USART_RTOR_BLEN_Pos (24U)\r
+#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */\r
+#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */\r
+\r
+/******************* Bit definition for USART_RQR register ******************/\r
+#define USART_RQR_ABRRQ_Pos (0U)\r
+#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */\r
+#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */\r
+#define USART_RQR_SBKRQ_Pos (1U)\r
+#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */\r
+#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */\r
+#define USART_RQR_MMRQ_Pos (2U)\r
+#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */\r
+#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */\r
+#define USART_RQR_RXFRQ_Pos (3U)\r
+#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */\r
+#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */\r
+#define USART_RQR_TXFRQ_Pos (4U)\r
+#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */\r
+#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */\r
+\r
+/******************* Bit definition for USART_ISR register ******************/\r
+#define USART_ISR_PE_Pos (0U)\r
+#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */\r
+#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */\r
+#define USART_ISR_FE_Pos (1U)\r
+#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */\r
+#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */\r
+#define USART_ISR_NE_Pos (2U)\r
+#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */\r
+#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */\r
+#define USART_ISR_ORE_Pos (3U)\r
+#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */\r
+#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */\r
+#define USART_ISR_IDLE_Pos (4U)\r
+#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */\r
+#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */\r
+#define USART_ISR_RXNE_Pos (5U)\r
+#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */\r
+#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */\r
+#define USART_ISR_TC_Pos (6U)\r
+#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */\r
+#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */\r
+#define USART_ISR_TXE_Pos (7U)\r
+#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */\r
+#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */\r
+#define USART_ISR_LBDF_Pos (8U)\r
+#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */\r
+#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */\r
+#define USART_ISR_CTSIF_Pos (9U)\r
+#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */\r
+#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */\r
+#define USART_ISR_CTS_Pos (10U)\r
+#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */\r
+#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */\r
+#define USART_ISR_RTOF_Pos (11U)\r
+#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */\r
+#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */\r
+#define USART_ISR_EOBF_Pos (12U)\r
+#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */\r
+#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */\r
+#define USART_ISR_ABRE_Pos (14U)\r
+#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */\r
+#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */\r
+#define USART_ISR_ABRF_Pos (15U)\r
+#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */\r
+#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */\r
+#define USART_ISR_BUSY_Pos (16U)\r
+#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */\r
+#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */\r
+#define USART_ISR_CMF_Pos (17U)\r
+#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */\r
+#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */\r
+#define USART_ISR_SBKF_Pos (18U)\r
+#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */\r
+#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */\r
+#define USART_ISR_RWU_Pos (19U)\r
+#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */\r
+#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */\r
+#define USART_ISR_TEACK_Pos (21U)\r
+#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */\r
+#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */\r
+#define USART_ISR_TCBGT_Pos (25U)\r
+#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */\r
+#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time flag */\r
+\r
+/******************* Bit definition for USART_ICR register ******************/\r
+#define USART_ICR_PECF_Pos (0U)\r
+#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */\r
+#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */\r
+#define USART_ICR_FECF_Pos (1U)\r
+#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */\r
+#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */\r
+#define USART_ICR_NCF_Pos (2U)\r
+#define USART_ICR_NCF_Msk (0x1UL << USART_ICR_NCF_Pos) /*!< 0x00000004 */\r
+#define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */\r
+#define USART_ICR_ORECF_Pos (3U)\r
+#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */\r
+#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */\r
+#define USART_ICR_IDLECF_Pos (4U)\r
+#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */\r
+#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */\r
+#define USART_ICR_TCCF_Pos (6U)\r
+#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */\r
+#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */\r
+#define USART_ICR_TCBGTCF_Pos (7U)\r
+#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */\r
+#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time clear flag */\r
+#define USART_ICR_LBDCF_Pos (8U)\r
+#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */\r
+#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */\r
+#define USART_ICR_CTSCF_Pos (9U)\r
+#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */\r
+#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */\r
+#define USART_ICR_RTOCF_Pos (11U)\r
+#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */\r
+#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */\r
+#define USART_ICR_EOBCF_Pos (12U)\r
+#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */\r
+#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */\r
+#define USART_ICR_CMCF_Pos (17U)\r
+#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */\r
+#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */\r
+\r
+/******************* Bit definition for USART_RDR register ******************/\r
+#define USART_RDR_RDR_Pos (0U)\r
+#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */\r
+#define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */\r
+\r
+/******************* Bit definition for USART_TDR register ******************/\r
+#define USART_TDR_TDR_Pos (0U)\r
+#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */\r
+#define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* Window WATCHDOG */\r
+/* */\r
+/******************************************************************************/\r
+/******************* Bit definition for WWDG_CR register ********************/\r
+#define WWDG_CR_T_Pos (0U)\r
+#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */\r
+#define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x01 */\r
+#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x02 */\r
+#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x04 */\r
+#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x08 */\r
+#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x10 */\r
+#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x20 */\r
+#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x40 */\r
+\r
+\r
+#define WWDG_CR_WDGA_Pos (7U)\r
+#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */\r
+#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */\r
+\r
+/******************* Bit definition for WWDG_CFR register *******************/\r
+#define WWDG_CFR_W_Pos (0U)\r
+#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */\r
+#define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */\r
+#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x0001 */\r
+#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x0002 */\r
+#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x0004 */\r
+#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x0008 */\r
+#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x0010 */\r
+#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x0020 */\r
+#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x0040 */\r
+\r
+\r
+#define WWDG_CFR_WDGTB_Pos (7U)\r
+#define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */\r
+#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0080 */\r
+#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x0100 */\r
+\r
+\r
+#define WWDG_CFR_EWI_Pos (9U)\r
+#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */\r
+#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */\r
+\r
+/******************* Bit definition for WWDG_SR register ********************/\r
+#define WWDG_SR_EWIF_Pos (0U)\r
+#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */\r
+#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* DBG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for DBGMCU_IDCODE register *************/\r
+#define DBGMCU_IDCODE_DEV_ID_Pos (0U)\r
+#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */\r
+#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk\r
+#define DBGMCU_IDCODE_REV_ID_Pos (16U)\r
+#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */\r
+#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk\r
+\r
+/******************** Bit definition for DBGMCU_CR register *****************/\r
+#define DBGMCU_CR_DBG_SLEEP_Pos (0U)\r
+#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk\r
+#define DBGMCU_CR_DBG_STOP_Pos (1U)\r
+#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk\r
+#define DBGMCU_CR_DBG_STANDBY_Pos (2U)\r
+#define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk\r
+#define DBGMCU_CR_TRACE_IOEN_Pos (5U)\r
+#define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk\r
+\r
+#define DBGMCU_CR_TRACE_MODE_Pos (6U)\r
+#define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */\r
+#define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk\r
+#define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */\r
+\r
+/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos (2U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos) /*!< 0x00000004 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos (3U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos) /*!< 0x00000008 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos (4U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos (5U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos (6U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM12_STOP_Pos) /*!< 0x00000040 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos (7U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM13_STOP_Pos) /*!< 0x00000080 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */\r
+#define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos (9U)\r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Pos) /*!< 0x00000200 */\r
+#define DBGMCU_APB1_FZ_DBG_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */\r
+#define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */\r
+#define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */\r
+#define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U)\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos (23U)\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Pos) /*!< 0x00800000 */\r
+#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT_Msk\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos (25U)\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_APB1_FZ_DBG_CAN1_STOP_Pos) /*!< 0x02000000 */\r
+#define DBGMCU_APB1_FZ_DBG_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP_Msk\r
+\r
+/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (0U)\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000001 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk\r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos (1U)\r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM8_STOP_Pos) /*!< 0x00000002 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP_Msk\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos (16U)\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos) /*!< 0x00010000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos (17U)\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos) /*!< 0x00020000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U)\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */\r
+#define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk\r
+\r
+\r
+/******************************************************************************/\r
+/* */\r
+/* USB_OTG */\r
+/* */\r
+/******************************************************************************/\r
+/******************** Bit definition for USB_OTG_GOTGCTL register ********************/\r
+#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)\r
+#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */\r
+#define USB_OTG_GOTGCTL_SRQ_Pos (1U)\r
+#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)\r
+#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)\r
+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */\r
+#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)\r
+#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)\r
+#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)\r
+#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)\r
+#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */\r
+#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)\r
+#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)\r
+#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */\r
+#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)\r
+#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */\r
+#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)\r
+#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */\r
+#define USB_OTG_GOTGCTL_EHEN_Pos (12U)\r
+#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */\r
+#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)\r
+#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */\r
+#define USB_OTG_GOTGCTL_DBCT_Pos (17U)\r
+#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */\r
+#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)\r
+#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */\r
+#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)\r
+#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */\r
+#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)\r
+#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */\r
+\r
+/******************** Bit definition for USB_OTG_HCFG register ********************/\r
+#define USB_OTG_HCFG_FSLSPCS_Pos (0U)\r
+#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */\r
+#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCFG_FSLSS_Pos (2U)\r
+#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */\r
+\r
+/******************** Bit definition for USB_OTG_DCFG register ********************/\r
+#define USB_OTG_DCFG_DSPD_Pos (0U)\r
+#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */\r
+#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */\r
+#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)\r
+#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */\r
+\r
+#define USB_OTG_DCFG_DAD_Pos (4U)\r
+#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */\r
+#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */\r
+#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */\r
+\r
+#define USB_OTG_DCFG_PFIVL_Pos (11U)\r
+#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */\r
+#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */\r
+#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */\r
+\r
+#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)\r
+#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */\r
+#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */\r
+\r
+/******************** Bit definition for USB_OTG_PCGCR register ********************/\r
+#define USB_OTG_PCGCR_STPPCLK_Pos (0U)\r
+#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */\r
+#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)\r
+#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */\r
+#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)\r
+#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */\r
+\r
+/******************** Bit definition for USB_OTG_GOTGINT register ********************/\r
+#define USB_OTG_GOTGINT_SEDET_Pos (2U)\r
+#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */\r
+#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)\r
+#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */\r
+#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)\r
+#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */\r
+#define USB_OTG_GOTGINT_HNGDET_Pos (17U)\r
+#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */\r
+#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)\r
+#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */\r
+#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)\r
+#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */\r
+#define USB_OTG_GOTGINT_IDCHNG_Pos (20U)\r
+#define USB_OTG_GOTGINT_IDCHNG_Msk (0x1UL << USB_OTG_GOTGINT_IDCHNG_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GOTGINT_IDCHNG USB_OTG_GOTGINT_IDCHNG_Msk /*!< Change in ID pin input value */\r
+\r
+/******************** Bit definition for USB_OTG_DCTL register ********************/\r
+#define USB_OTG_DCTL_RWUSIG_Pos (0U)\r
+#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */\r
+#define USB_OTG_DCTL_SDIS_Pos (1U)\r
+#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */\r
+#define USB_OTG_DCTL_GINSTS_Pos (2U)\r
+#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */\r
+#define USB_OTG_DCTL_GONSTS_Pos (3U)\r
+#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */\r
+\r
+#define USB_OTG_DCTL_TCTL_Pos (4U)\r
+#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */\r
+#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */\r
+#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DCTL_SGINAK_Pos (7U)\r
+#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */\r
+#define USB_OTG_DCTL_CGINAK_Pos (8U)\r
+#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */\r
+#define USB_OTG_DCTL_SGONAK_Pos (9U)\r
+#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */\r
+#define USB_OTG_DCTL_CGONAK_Pos (10U)\r
+#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */\r
+#define USB_OTG_DCTL_POPRGDNE_Pos (11U)\r
+#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */\r
+\r
+/******************** Bit definition for USB_OTG_HFIR register ********************/\r
+#define USB_OTG_HFIR_FRIVL_Pos (0U)\r
+#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */\r
+\r
+/******************** Bit definition for USB_OTG_HFNUM register ********************/\r
+#define USB_OTG_HFNUM_FRNUM_Pos (0U)\r
+#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */\r
+#define USB_OTG_HFNUM_FTREM_Pos (16U)\r
+#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */\r
+\r
+/******************** Bit definition for USB_OTG_DSTS register ********************/\r
+#define USB_OTG_DSTS_SUSPSTS_Pos (0U)\r
+#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */\r
+\r
+#define USB_OTG_DSTS_ENUMSPD_Pos (1U)\r
+#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */\r
+#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */\r
+#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DSTS_EERR_Pos (3U)\r
+#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */\r
+#define USB_OTG_DSTS_FNSOF_Pos (8U)\r
+#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */\r
+#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */\r
+\r
+/******************** Bit definition for USB_OTG_GAHBCFG register ********************/\r
+#define USB_OTG_GAHBCFG_GINT_Pos (0U)\r
+#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)\r
+#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */\r
+#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */\r
+#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */\r
+#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)\r
+#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */\r
+#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)\r
+#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)\r
+#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */\r
+\r
+/******************** Bit definition for USB_OTG_GUSBCFG register ********************/\r
+#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)\r
+#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */\r
+#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */\r
+#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GUSBCFG_PHYIF_Pos (3U)\r
+#define USB_OTG_GUSBCFG_PHYIF_Msk (0x1UL << USB_OTG_GUSBCFG_PHYIF_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GUSBCFG_PHYIF USB_OTG_GUSBCFG_PHYIF_Msk /*!< PHY Interface (PHYIf) */\r
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos (4U)\r
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk (0x1UL << USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GUSBCFG_ULPI_UTMI_SEL USB_OTG_GUSBCFG_ULPI_UTMI_SEL_Msk /*!< ULPI or UTMI+ Select (ULPI_UTMI_Sel) */\r
+#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)\r
+#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */\r
+#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)\r
+#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */\r
+#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)\r
+#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */\r
+#define USB_OTG_GUSBCFG_TRDT_Pos (10U)\r
+#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */\r
+#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */\r
+#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)\r
+#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)\r
+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */\r
+#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)\r
+#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */\r
+#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)\r
+#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */\r
+#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)\r
+#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */\r
+#define USB_OTG_GUSBCFG_PCCI_Pos (23U)\r
+#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */\r
+#define USB_OTG_GUSBCFG_PTCI_Pos (24U)\r
+#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)\r
+#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */\r
+#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)\r
+#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */\r
+#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)\r
+#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */\r
+#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)\r
+#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */\r
+\r
+/******************** Bit definition for USB_OTG_GRSTCTL register ********************/\r
+#define USB_OTG_GRSTCTL_CSRST_Pos (0U)\r
+#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */\r
+#define USB_OTG_GRSTCTL_HSRST_Pos (1U)\r
+#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */\r
+#define USB_OTG_GRSTCTL_FCRST_Pos (2U)\r
+#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)\r
+#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)\r
+#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */\r
+#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)\r
+#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */\r
+#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)\r
+#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */\r
+#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)\r
+#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPMSK register ********************/\r
+#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPMSK_EPDM_Pos (1U)\r
+#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPMSK_TOM_Pos (3U)\r
+#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)\r
+#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)\r
+#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)\r
+#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPMSK_BIM_Pos (9U)\r
+#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXSTS register ********************/\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)\r
+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)\r
+#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)\r
+#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */\r
+\r
+/******************** Bit definition for USB_OTG_HAINT register ********************/\r
+#define USB_OTG_HAINT_HAINT_Pos (0U)\r
+#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPMSK register ********************/\r
+#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPMSK_EPDM_Pos (1U)\r
+#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)\r
+#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */\r
+#define USB_OTG_DOEPMSK_STUPM_Pos (3U)\r
+#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */\r
+#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)\r
+#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)\r
+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)\r
+#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */\r
+#define USB_OTG_DOEPMSK_OPEM_Pos (8U)\r
+#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPMSK_BOIM_Pos (9U)\r
+#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPMSK_BERRM_Pos (12U)\r
+#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */\r
+#define USB_OTG_DOEPMSK_NAKM_Pos (13U)\r
+#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */\r
+#define USB_OTG_DOEPMSK_NYETM_Pos (14U)\r
+#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GINTSTS register ********************/\r
+#define USB_OTG_GINTSTS_CMOD_Pos (0U)\r
+#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */\r
+#define USB_OTG_GINTSTS_MMIS_Pos (1U)\r
+#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */\r
+#define USB_OTG_GINTSTS_OTGINT_Pos (2U)\r
+#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */\r
+#define USB_OTG_GINTSTS_SOF_Pos (3U)\r
+#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */\r
+#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)\r
+#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */\r
+#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)\r
+#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)\r
+#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */\r
+#define USB_OTG_GINTSTS_ESUSP_Pos (10U)\r
+#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */\r
+#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)\r
+#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */\r
+#define USB_OTG_GINTSTS_USBRST_Pos (12U)\r
+#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */\r
+#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)\r
+#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */\r
+#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)\r
+#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */\r
+#define USB_OTG_GINTSTS_EOPF_Pos (15U)\r
+#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */\r
+#define USB_OTG_GINTSTS_IEPINT_Pos (18U)\r
+#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */\r
+#define USB_OTG_GINTSTS_OEPINT_Pos (19U)\r
+#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */\r
+#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)\r
+#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)\r
+#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */\r
+#define USB_OTG_GINTSTS_RSTDET_Pos (23U)\r
+#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */\r
+#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)\r
+#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */\r
+#define USB_OTG_GINTSTS_HCINT_Pos (25U)\r
+#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */\r
+#define USB_OTG_GINTSTS_PTXFE_Pos (26U)\r
+#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */\r
+#define USB_OTG_GINTSTS_LPMINT_Pos (27U)\r
+#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */\r
+#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)\r
+#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */\r
+#define USB_OTG_GINTSTS_DISCINT_Pos (29U)\r
+#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */\r
+#define USB_OTG_GINTSTS_SRQINT_Pos (30U)\r
+#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */\r
+#define USB_OTG_GINTSTS_WKUINT_Pos (31U)\r
+#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_GINTMSK register ********************/\r
+#define USB_OTG_GINTMSK_MMISM_Pos (1U)\r
+#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_OTGINT_Pos (2U)\r
+#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */\r
+#define USB_OTG_GINTMSK_SOFM_Pos (3U)\r
+#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */\r
+#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)\r
+#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */\r
+#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)\r
+#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)\r
+#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)\r
+#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */\r
+#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)\r
+#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */\r
+#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)\r
+#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */\r
+#define USB_OTG_GINTMSK_USBRST_Pos (12U)\r
+#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)\r
+#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */\r
+#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)\r
+#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */\r
+#define USB_OTG_GINTMSK_EOPFM_Pos (15U)\r
+#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */\r
+#define USB_OTG_GINTMSK_EPMISM_Pos (17U)\r
+#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */\r
+#define USB_OTG_GINTMSK_IEPINT_Pos (18U)\r
+#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_OEPINT_Pos (19U)\r
+#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)\r
+#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */\r
+#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)\r
+#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */\r
+#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)\r
+#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */\r
+#define USB_OTG_GINTMSK_PRTIM_Pos (24U)\r
+#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */\r
+#define USB_OTG_GINTMSK_HCIM_Pos (25U)\r
+#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */\r
+#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)\r
+#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */\r
+#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)\r
+#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)\r
+#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */\r
+#define USB_OTG_GINTMSK_DISCINT_Pos (29U)\r
+#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */\r
+#define USB_OTG_GINTMSK_SRQIM_Pos (30U)\r
+#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */\r
+#define USB_OTG_GINTMSK_WUIM_Pos (31U)\r
+#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_DAINT register ********************/\r
+#define USB_OTG_DAINT_IEPINT_Pos (0U)\r
+#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */\r
+#define USB_OTG_DAINT_OEPINT_Pos (16U)\r
+#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */\r
+\r
+/******************** Bit definition for USB_OTG_HAINTMSK register ********************/\r
+#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)\r
+#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_GRXSTSP register ********************/\r
+#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)\r
+#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_BCNT_Pos (4U)\r
+#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_DPID_Pos (15U)\r
+#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */\r
+#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)\r
+#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DAINTMSK register ********************/\r
+#define USB_OTG_DAINTMSK_IEPM_Pos (0U)\r
+#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */\r
+#define USB_OTG_DAINTMSK_OEPM_Pos (16U)\r
+#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+\r
+#define USB_OTG_CHNUM_Pos (0U)\r
+#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */\r
+#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_BCNT_Pos (4U)\r
+#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */\r
+#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */\r
+\r
+#define USB_OTG_DPID_Pos (15U)\r
+#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */\r
+#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_PKTSTS_Pos (17U)\r
+#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */\r
+#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */\r
+\r
+#define USB_OTG_EPNUM_Pos (0U)\r
+#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */\r
+#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */\r
+\r
+#define USB_OTG_FRMNUM_Pos (21U)\r
+#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */\r
+#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */\r
+#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */\r
+\r
+/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/\r
+#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)\r
+#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)\r
+#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */\r
+\r
+/******************** Bit definition for OTG register ********************/\r
+#define USB_OTG_NPTXFSA_Pos (0U)\r
+#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */\r
+#define USB_OTG_NPTXFD_Pos (16U)\r
+#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */\r
+#define USB_OTG_TX0FSA_Pos (0U)\r
+#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */\r
+#define USB_OTG_TX0FD_Pos (16U)\r
+#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)\r
+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */\r
+#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */\r
+\r
+/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */\r
+\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for USB_OTG_DTHRCTL register ********************/\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)\r
+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)\r
+#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)\r
+#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */\r
+\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)\r
+#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINT register ********************/\r
+#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)\r
+#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */\r
+#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)\r
+#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */\r
+\r
+/******************** Bit definition for USB_OTG_GCCFG register ********************/\r
+#define USB_OTG_GCCFG_DCDET_Pos (0U)\r
+#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */\r
+#define USB_OTG_GCCFG_PDET_Pos (1U)\r
+#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */\r
+#define USB_OTG_GCCFG_SDET_Pos (2U)\r
+#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */\r
+#define USB_OTG_GCCFG_PS2DET_Pos (3U)\r
+#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */\r
+#define USB_OTG_GCCFG_PWRDWN_Pos (16U)\r
+#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */\r
+#define USB_OTG_GCCFG_BCDEN_Pos (17U)\r
+#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */\r
+#define USB_OTG_GCCFG_DCDEN_Pos (18U)\r
+#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/\r
+#define USB_OTG_GCCFG_PDEN_Pos (19U)\r
+#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/\r
+#define USB_OTG_GCCFG_SDEN_Pos (20U)\r
+#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */\r
+#define USB_OTG_GCCFG_VBDEN_Pos (21U)\r
+#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< VBUS mode enable */\r
+#define USB_OTG_GCCFG_OTGIDEN_Pos (22U)\r
+#define USB_OTG_GCCFG_OTGIDEN_Msk (0x1UL << USB_OTG_GCCFG_OTGIDEN_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_GCCFG_OTGIDEN USB_OTG_GCCFG_OTGIDEN_Msk /*!< OTG Id enable */\r
+#define USB_OTG_GCCFG_PHYHSEN_Pos (23U)\r
+#define USB_OTG_GCCFG_PHYHSEN_Msk (0x1UL << USB_OTG_GCCFG_PHYHSEN_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_GCCFG_PHYHSEN USB_OTG_GCCFG_PHYHSEN_Msk /*!< HS PHY enable */\r
+\r
+/******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */\r
+\r
+/******************** Bit definition for USB_OTG_CID register ********************/\r
+#define USB_OTG_CID_PRODUCT_ID_Pos (0U)\r
+#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */\r
+\r
+/******************** Bit definition for USB_OTG_GLPMCFG register ********************/\r
+#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)\r
+#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */\r
+#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)\r
+#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */\r
+#define USB_OTG_GLPMCFG_BESL_Pos (2U)\r
+#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */\r
+#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)\r
+#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */\r
+#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)\r
+#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)\r
+#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */\r
+#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */\r
+#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)\r
+#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */\r
+#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)\r
+#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */\r
+#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */\r
+#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)\r
+#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)\r
+#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)\r
+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */\r
+#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)\r
+#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */\r
+#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)\r
+#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */\r
+#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */\r
+#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)\r
+#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)\r
+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)\r
+#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)\r
+#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)\r
+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPRT register ********************/\r
+#define USB_OTG_HPRT_PCSTS_Pos (0U)\r
+#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */\r
+#define USB_OTG_HPRT_PCDET_Pos (1U)\r
+#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */\r
+#define USB_OTG_HPRT_PENA_Pos (2U)\r
+#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */\r
+#define USB_OTG_HPRT_PENCHNG_Pos (3U)\r
+#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */\r
+#define USB_OTG_HPRT_POCA_Pos (4U)\r
+#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */\r
+#define USB_OTG_HPRT_POCCHNG_Pos (5U)\r
+#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */\r
+#define USB_OTG_HPRT_PRES_Pos (6U)\r
+#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */\r
+#define USB_OTG_HPRT_PSUSP_Pos (7U)\r
+#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */\r
+#define USB_OTG_HPRT_PRST_Pos (8U)\r
+#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */\r
+\r
+#define USB_OTG_HPRT_PLSTS_Pos (10U)\r
+#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */\r
+#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */\r
+#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HPRT_PPWR_Pos (12U)\r
+#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */\r
+\r
+#define USB_OTG_HPRT_PTCTL_Pos (13U)\r
+#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */\r
+#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */\r
+#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */\r
+\r
+#define USB_OTG_HPRT_PSPD_Pos (17U)\r
+#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */\r
+#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */\r
+#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)\r
+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)\r
+#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)\r
+#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)\r
+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)\r
+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)\r
+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */\r
+\r
+/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)\r
+#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)\r
+#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPCTL register ********************/\r
+#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)\r
+#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */\r
+#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)\r
+#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)\r
+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */\r
+#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)\r
+#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */\r
+\r
+#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)\r
+#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DIEPCTL_STALL_Pos (21U)\r
+#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */\r
+\r
+#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)\r
+#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */\r
+#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_DIEPCTL_CNAK_Pos (26U)\r
+#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DIEPCTL_SNAK_Pos (27U)\r
+#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)\r
+#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)\r
+#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DIEPCTL_EPENA_Pos (31U)\r
+#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCCHAR register ********************/\r
+#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)\r
+#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */\r
+\r
+#define USB_OTG_HCCHAR_EPNUM_Pos (11U)\r
+#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */\r
+#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */\r
+#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCCHAR_EPDIR_Pos (15U)\r
+#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */\r
+#define USB_OTG_HCCHAR_LSDEV_Pos (17U)\r
+#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */\r
+\r
+#define USB_OTG_HCCHAR_EPTYP_Pos (18U)\r
+#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */\r
+\r
+#define USB_OTG_HCCHAR_MC_Pos (20U)\r
+#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */\r
+#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */\r
+#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */\r
+\r
+#define USB_OTG_HCCHAR_DAD_Pos (22U)\r
+#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */\r
+#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */\r
+#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */\r
+#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */\r
+#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */\r
+#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */\r
+#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)\r
+#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */\r
+#define USB_OTG_HCCHAR_CHDIS_Pos (30U)\r
+#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */\r
+#define USB_OTG_HCCHAR_CHENA_Pos (31U)\r
+#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCSPLT register ********************/\r
+\r
+#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)\r
+#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */\r
+#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */\r
+#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */\r
+\r
+#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)\r
+#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */\r
+#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */\r
+#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */\r
+\r
+#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)\r
+#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */\r
+#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */\r
+#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)\r
+#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */\r
+#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */\r
+#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)\r
+#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */\r
+\r
+/******************** Bit definition for USB_OTG_HCINT register ********************/\r
+#define USB_OTG_HCINT_XFRC_Pos (0U)\r
+#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */\r
+#define USB_OTG_HCINT_CHH_Pos (1U)\r
+#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */\r
+#define USB_OTG_HCINT_AHBERR_Pos (2U)\r
+#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINT_STALL_Pos (3U)\r
+#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */\r
+#define USB_OTG_HCINT_NAK_Pos (4U)\r
+#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */\r
+#define USB_OTG_HCINT_ACK_Pos (5U)\r
+#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */\r
+#define USB_OTG_HCINT_NYET_Pos (6U)\r
+#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */\r
+#define USB_OTG_HCINT_TXERR_Pos (7U)\r
+#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */\r
+#define USB_OTG_HCINT_BBERR_Pos (8U)\r
+#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */\r
+#define USB_OTG_HCINT_FRMOR_Pos (9U)\r
+#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */\r
+#define USB_OTG_HCINT_DTERR_Pos (10U)\r
+#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPINT register ********************/\r
+#define USB_OTG_DIEPINT_XFRC_Pos (0U)\r
+#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DIEPINT_EPDISD_Pos (1U)\r
+#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DIEPINT_AHBERR_Pos (2U)\r
+#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */\r
+#define USB_OTG_DIEPINT_TOC_Pos (3U)\r
+#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */\r
+#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)\r
+#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */\r
+#define USB_OTG_DIEPINT_INEPNM_Pos (5U)\r
+#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */\r
+#define USB_OTG_DIEPINT_INEPNE_Pos (6U)\r
+#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */\r
+#define USB_OTG_DIEPINT_TXFE_Pos (7U)\r
+#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */\r
+#define USB_OTG_DIEPINT_BNA_Pos (9U)\r
+#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)\r
+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */\r
+#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */\r
+#define USB_OTG_DIEPINT_BERR_Pos (12U)\r
+#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */\r
+#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */\r
+#define USB_OTG_DIEPINT_NAK_Pos (13U)\r
+#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */\r
+\r
+/******************** Bit definition for USB_OTG_HCINTMSK register ********************/\r
+#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)\r
+#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */\r
+#define USB_OTG_HCINTMSK_CHHM_Pos (1U)\r
+#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */\r
+#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)\r
+#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */\r
+#define USB_OTG_HCINTMSK_STALLM_Pos (3U)\r
+#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_NAKM_Pos (4U)\r
+#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_ACKM_Pos (5U)\r
+#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */\r
+#define USB_OTG_HCINTMSK_NYET_Pos (6U)\r
+#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */\r
+#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)\r
+#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */\r
+#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */\r
+#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)\r
+#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */\r
+#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)\r
+#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */\r
+#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */\r
+#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)\r
+#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */\r
+#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/\r
+\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)\r
+#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */\r
+/******************** Bit definition for USB_OTG_HCTSIZ register ********************/\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */\r
+#define USB_OTG_HCTSIZ_DOPING_Pos (31U)\r
+#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */\r
+#define USB_OTG_HCTSIZ_DPID_Pos (29U)\r
+#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */\r
+#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPDMA register ********************/\r
+#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)\r
+#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_HCDMA register ********************/\r
+#define USB_OTG_HCDMA_DMAADDR_Pos (0U)\r
+#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */\r
+#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */\r
+\r
+/******************** Bit definition for USB_OTG_DTXFSTS register ********************/\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)\r
+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */\r
+\r
+/******************** Bit definition for USB_OTG_DIEPTXF register ********************/\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)\r
+#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */\r
+#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)\r
+#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */\r
+#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPCTL register ********************/\r
+#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)\r
+#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */\r
+#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */\r
+#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)\r
+#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */\r
+#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)\r
+#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */\r
+#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */\r
+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */\r
+#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)\r
+#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */\r
+#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)\r
+#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */\r
+#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */\r
+#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */\r
+#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */\r
+#define USB_OTG_DOEPCTL_SNPM_Pos (20U)\r
+#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */\r
+#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */\r
+#define USB_OTG_DOEPCTL_STALL_Pos (21U)\r
+#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */\r
+#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */\r
+#define USB_OTG_DOEPCTL_CNAK_Pos (26U)\r
+#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */\r
+#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */\r
+#define USB_OTG_DOEPCTL_SNAK_Pos (27U)\r
+#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */\r
+#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */\r
+#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)\r
+#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */\r
+#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */\r
+#define USB_OTG_DOEPCTL_EPENA_Pos (31U)\r
+#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */\r
+#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPINT register ********************/\r
+#define USB_OTG_DOEPINT_XFRC_Pos (0U)\r
+#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */\r
+#define USB_OTG_DOEPINT_EPDISD_Pos (1U)\r
+#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */\r
+#define USB_OTG_DOEPINT_AHBERR_Pos (2U)\r
+#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */\r
+#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */\r
+#define USB_OTG_DOEPINT_STUP_Pos (3U)\r
+#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */\r
+#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */\r
+#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)\r
+#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */\r
+#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)\r
+#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */\r
+#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */\r
+#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)\r
+#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */\r
+#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */\r
+#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)\r
+#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */\r
+#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */\r
+#define USB_OTG_DOEPINT_NAK_Pos (13U)\r
+#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */\r
+#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */\r
+#define USB_OTG_DOEPINT_NYET_Pos (14U)\r
+#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */\r
+#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */\r
+#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)\r
+#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */\r
+#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */\r
+\r
+/******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */\r
+#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)\r
+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */\r
+#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */\r
+\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */\r
+#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */\r
+\r
+/******************** Bit definition for PCGCCTL register ********************/\r
+#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)\r
+#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */\r
+#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */\r
+#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)\r
+#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */\r
+#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)\r
+#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */\r
+#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */\r
+\r
+/******************** Bit definition for USBPHYC_PLL1 register ********************/\r
+#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U)\r
+#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1UL << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */\r
+#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U)\r
+#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */\r
+#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */\r
+\r
+#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */\r
+#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */\r
+\r
+/******************** Bit definition for USBPHYC_LDO register ********************/\r
+#define USB_HS_PHYC_LDO_USED_Pos (0U)\r
+#define USB_HS_PHYC_LDO_USED_Msk (0x1UL << USB_HS_PHYC_LDO_USED_Pos) /*!< 0x00000001 */\r
+#define USB_HS_PHYC_LDO_USED USB_HS_PHYC_LDO_USED_Msk /*!< Monitors the usage status of the PHY's LDO */\r
+#define USB_HS_PHYC_LDO_STATUS_Pos (1U)\r
+#define USB_HS_PHYC_LDO_STATUS_Msk (0x1UL << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */\r
+#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */\r
+#define USB_HS_PHYC_LDO_DISABLE_Pos (2U)\r
+#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1UL << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */\r
+#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */\r
+\r
+/* Legacy */\r
+#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos\r
+#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk\r
+#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN\r
+#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos\r
+#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk\r
+#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL\r
+#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1\r
+#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2\r
+#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3\r
+\r
+#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos\r
+#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk\r
+#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE\r
+\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macros\r
+ * @{\r
+ */\r
+\r
+/******************************* ADC Instances ********************************/\r
+#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) || \\r
+ ((__INSTANCE__) == ADC2) || \\r
+ ((__INSTANCE__) == ADC3))\r
+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)\r
+\r
+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)\r
+\r
+/******************************* CAN Instances ********************************/\r
+#define IS_CAN_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CAN1)\r
+/******************************* CRC Instances ********************************/\r
+#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)\r
+\r
+/******************************* DAC Instances ********************************/\r
+#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC1)\r
+\r
+\r
+\r
+\r
+/******************************** DMA Instances *******************************/\r
+#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) || \\r
+ ((__INSTANCE__) == DMA1_Stream1) || \\r
+ ((__INSTANCE__) == DMA1_Stream2) || \\r
+ ((__INSTANCE__) == DMA1_Stream3) || \\r
+ ((__INSTANCE__) == DMA1_Stream4) || \\r
+ ((__INSTANCE__) == DMA1_Stream5) || \\r
+ ((__INSTANCE__) == DMA1_Stream6) || \\r
+ ((__INSTANCE__) == DMA1_Stream7) || \\r
+ ((__INSTANCE__) == DMA2_Stream0) || \\r
+ ((__INSTANCE__) == DMA2_Stream1) || \\r
+ ((__INSTANCE__) == DMA2_Stream2) || \\r
+ ((__INSTANCE__) == DMA2_Stream3) || \\r
+ ((__INSTANCE__) == DMA2_Stream4) || \\r
+ ((__INSTANCE__) == DMA2_Stream5) || \\r
+ ((__INSTANCE__) == DMA2_Stream6) || \\r
+ ((__INSTANCE__) == DMA2_Stream7))\r
+\r
+/******************************* GPIO Instances *******************************/\r
+#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI))\r
+\r
+#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) || \\r
+ ((__INSTANCE__) == GPIOB) || \\r
+ ((__INSTANCE__) == GPIOC) || \\r
+ ((__INSTANCE__) == GPIOD) || \\r
+ ((__INSTANCE__) == GPIOE) || \\r
+ ((__INSTANCE__) == GPIOF) || \\r
+ ((__INSTANCE__) == GPIOG) || \\r
+ ((__INSTANCE__) == GPIOH) || \\r
+ ((__INSTANCE__) == GPIOI))\r
+\r
+\r
+/****************************** QSPI Instances *********************************/\r
+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)\r
+\r
+\r
+/******************************** I2C Instances *******************************/\r
+#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3))\r
+\r
+/****************************** SMBUS Instances *******************************/\r
+#define IS_SMBUS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) || \\r
+ ((__INSTANCE__) == I2C2) || \\r
+ ((__INSTANCE__) == I2C3))\r
+\r
+\r
+/******************************** I2S Instances *******************************/\r
+#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3))\r
+\r
+/******************************* LPTIM Instances ********************************/\r
+#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)\r
+\r
+\r
+\r
+\r
+/******************************* AES Instances ********************************/\r
+#define IS_AES_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == AES)\r
+\r
+/******************************* RNG Instances ********************************/\r
+#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)\r
+\r
+/****************************** RTC Instances *********************************/\r
+#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)\r
+\r
+/******************************* SAI Instances ********************************/\r
+#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) || \\r
+ ((__PERIPH__) == SAI1_Block_B) || \\r
+ ((__PERIPH__) == SAI2_Block_A) || \\r
+ ((__PERIPH__) == SAI2_Block_B))\r
+/* Legacy define */\r
+#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE\r
+\r
+/******************************** SDMMC Instances *******************************/\r
+#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SDMMC1) || \\r
+ ((__INSTANCE__) == SDMMC2))\r
+\r
+\r
+/******************************** SPI Instances *******************************/\r
+#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) || \\r
+ ((__INSTANCE__) == SPI2) || \\r
+ ((__INSTANCE__) == SPI3) || \\r
+ ((__INSTANCE__) == SPI4) || \\r
+ ((__INSTANCE__) == SPI5))\r
+\r
+/****************** TIM Instances : All supported instances *******************/\r
+#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/****************** TIM Instances : supporting 32 bits counter ****************/\r
+#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/****************** TIM Instances : supporting the break function *************/\r
+#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/************** TIM Instances : supporting Break source selection *************/\r
+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/****************** TIM Instances : supporting 2 break inputs *****************/\r
+#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \\r
+ ((INSTANCE) == TIM8))\r
+\r
+/************* TIM Instances : at least 1 capture/compare channel *************/\r
+#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/************ TIM Instances : at least 2 capture/compare channels *************/\r
+#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/************ TIM Instances : at least 3 capture/compare channels *************/\r
+#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : at least 4 capture/compare channels *************/\r
+#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : at least 5 capture/compare channels *******/\r
+#define IS_TIM_CC5_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : at least 6 capture/compare channels *******/\r
+#define IS_TIM_CC6_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/************ TIM Instances : DMA requests generation (TIMx_DIER.COMDE) *******/\r
+#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/\r
+#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7))\r
+\r
+/************ TIM Instances : DMA requests generation (CCxDE) *****************/\r
+#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** TIM Instances : DMA burst feature ***********************/\r
+#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting combined 3-phase PWM mode ******/\r
+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting counting mode selection ********/\r
+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting encoder interface **************/\r
+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting OCxREF clear *******************/\r
+#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5))\r
+\r
+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/\r
+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/\r
+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** TIM Instances : Advanced-control timers *****************/\r
+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************* TIM Instances : Timer input XOR function *****************/\r
+#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/\r
+#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM6) || \\r
+ ((__INSTANCE__) == TIM7) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/\r
+#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/***************** TIM Instances : external trigger input available ************/\r
+#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : remapping capability **********************/\r
+#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM11))\r
+\r
+/******************* TIM Instances : output(s) available **********************/\r
+#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM2) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM3) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM4) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM5) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_4) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_5) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_6))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM9) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM10) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM11) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM12) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM13) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM14) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1))))\r
+\r
+/************ TIM Instances : complementary output(s) available ***************/\r
+#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \\r
+ ((((__INSTANCE__) == TIM1) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))) \\r
+ || \\r
+ (((__INSTANCE__) == TIM8) && \\r
+ (((__CHANNEL__) == TIM_CHANNEL_1) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_2) || \\r
+ ((__CHANNEL__) == TIM_CHANNEL_3))))\r
+\r
+/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/\r
+#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\\r
+ (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8) )\r
+\r
+/****************** TIM Instances : supporting clock division *****************/\r
+#define IS_TIM_CLOCK_DIVISION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM10) || \\r
+ ((__INSTANCE__) == TIM11) || \\r
+ ((__INSTANCE__) == TIM12) || \\r
+ ((__INSTANCE__) == TIM13) || \\r
+ ((__INSTANCE__) == TIM14))\r
+\r
+/****************** TIM Instances : supporting repetition counter *************/\r
+#define IS_TIM_REPETITION_COUNTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8) || \\r
+ ((__INSTANCE__) == TIM9) || \\r
+ ((__INSTANCE__) == TIM12))\r
+\r
+/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/\r
+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting Hall sensor interface **********/\r
+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM2) || \\r
+ ((__INSTANCE__) == TIM3) || \\r
+ ((__INSTANCE__) == TIM4) || \\r
+ ((__INSTANCE__) == TIM5) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/****************** TIM Instances : supporting commutation event generation ***/\r
+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \\r
+ ((__INSTANCE__) == TIM8))\r
+\r
+/******************** USART Instances : Synchronous mode **********************/\r
+#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/******************** UART Instances : Asynchronous mode **********************/\r
+#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Auto Baud Rate detection ****************/\r
+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/****************** UART Instances : Driver Enable *****************/\r
+#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/******************** UART Instances : Half-Duplex mode **********************/\r
+#define IS_UART_HALFDUPLEX_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************** UART Instances : Hardware Flow control ********************/\r
+#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/******************** UART Instances : LIN mode **********************/\r
+#define IS_UART_LIN_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/********************* UART Instances : Smart card mode ***********************/\r
+#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == USART6))\r
+\r
+/*********************** UART Instances : IRDA mode ***************************/\r
+#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) || \\r
+ ((__INSTANCE__) == USART2) || \\r
+ ((__INSTANCE__) == USART3) || \\r
+ ((__INSTANCE__) == UART4) || \\r
+ ((__INSTANCE__) == UART5) || \\r
+ ((__INSTANCE__) == USART6) || \\r
+ ((__INSTANCE__) == UART7) || \\r
+ ((__INSTANCE__) == UART8))\r
+\r
+/****************************** IWDG Instances ********************************/\r
+#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)\r
+\r
+/****************************** WWDG Instances ********************************/\r
+#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)\r
+\r
+/*********************** PCD Instances ****************************************/\r
+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/*********************** HCD Instances ****************************************/\r
+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \\r
+ ((INSTANCE) == USB_OTG_HS))\r
+\r
+/******************************************************************************/\r
+/* For a painless codes migration between the STM32F7xx device product */\r
+/* lines, the aliases defined below are put in place to overcome the */\r
+/* differences in the interrupt handlers and IRQn definitions. */\r
+/* No need to update developed interrupt code when moving across */\r
+/* product lines within the same STM32F7 Family */\r
+/******************************************************************************/\r
+\r
+/* Aliases for __IRQn */\r
+#define HASH_RNG_IRQn RNG_IRQn\r
+\r
+/* Aliases for __IRQHandler */\r
+#define HASH_RNG_IRQHandler RNG_IRQHandler\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F730xx_H */\r
+\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.\r
+ *\r
+ * The file is the unique include file that the application programmer\r
+ * is using in the C source code, usually in main.c. This file contains:\r
+ * - Configuration section that allows to select:\r
+ * - The STM32F7xx device used in the target application\r
+ * - To use or not the peripheral's drivers in application code(i.e.\r
+ * code will be based on direct access to peripheral's registers\r
+ * rather than drivers API), this option is controlled by\r
+ * "#define USE_HAL_DRIVER"\r
+ *\r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.\r
+ *\r
+ * This software is licensed under terms that can be found in the LICENSE file\r
+ * in the root directory of this software component.\r
+ * If no LICENSE file comes with this software, it is provided AS-IS.\r
+ *\r
+ ******************************************************************************\r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx\r
+ * @{\r
+ */\r
+\r
+#ifndef __STM32F7xx_H\r
+#define __STM32F7xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+\r
+/** @addtogroup Library_configuration_section\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @brief STM32 Family\r
+ */\r
+#if !defined (STM32F7)\r
+#define STM32F7\r
+#endif /* STM32F7 */\r
+\r
+/* Uncomment the line below according to the target STM32 device used in your\r
+ application\r
+ */\r
+#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F765xx) && \\r
+ !defined (STM32F767xx) && !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && \\r
+ !defined (STM32F722xx) && !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && \\r
+ !defined (STM32F730xx) && !defined (STM32F750xx)\r
+\r
+ /* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,\r
+ STM32F756NG Devices */\r
+ /* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,\r
+ STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */\r
+ /* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */\r
+ /* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,\r
+ STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */\r
+ /* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,\r
+ STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */\r
+ /* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,\r
+ STM32F769NG, STM32F769NI, STM32F768AI Devices */\r
+ /* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */\r
+ /* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */\r
+ /* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,\r
+ STM32F722VC, STM32F722RC Devices */\r
+ /* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */\r
+ /* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */\r
+ /* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */\r
+ /* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */\r
+ /* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */\r
+#endif\r
+\r
+/* Tip: To avoid modifying this file each time you need to switch between these\r
+ devices, you can define the device in your toolchain compiler preprocessor.\r
+ */\r
+\r
+#if !defined (USE_HAL_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+ In this case, these drivers will not be included and the application code will\r
+ be based on direct access to peripherals registers\r
+ */\r
+ /*#define USE_HAL_DRIVER */\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+/**\r
+ * @brief CMSIS Device version number V1.2.8\r
+ */\r
+#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */\r
+#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */\r
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */\r
+#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB1 << 16)\\r
+ |(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\\r
+ |(__STM32F7_CMSIS_VERSION_RC))\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Device_Included\r
+ * @{\r
+ */\r
+#if defined(STM32F722xx)\r
+ #include "stm32f722xx.h"\r
+#elif defined(STM32F723xx)\r
+ #include "stm32f723xx.h"\r
+#elif defined(STM32F732xx)\r
+ #include "stm32f732xx.h"\r
+#elif defined(STM32F733xx)\r
+ #include "stm32f733xx.h"\r
+#elif defined(STM32F756xx)\r
+ #include "stm32f756xx.h"\r
+#elif defined(STM32F746xx)\r
+ #include "stm32f746xx.h"\r
+#elif defined(STM32F745xx)\r
+ #include "stm32f745xx.h"\r
+#elif defined(STM32F765xx)\r
+ #include "stm32f765xx.h"\r
+#elif defined(STM32F767xx)\r
+ #include "stm32f767xx.h"\r
+#elif defined(STM32F769xx)\r
+ #include "stm32f769xx.h"\r
+#elif defined(STM32F777xx)\r
+ #include "stm32f777xx.h"\r
+#elif defined(STM32F779xx)\r
+ #include "stm32f779xx.h"\r
+#elif defined(STM32F730xx)\r
+ #include "stm32f730xx.h"\r
+#elif defined(STM32F750xx)\r
+ #include "stm32f750xx.h"\r
+#else\r
+ #error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"\r
+#endif\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_types\r
+ * @{\r
+ */\r
+typedef enum\r
+{\r
+ RESET = 0U,\r
+ SET = !RESET\r
+} FlagStatus, ITStatus;\r
+\r
+typedef enum\r
+{\r
+ DISABLE = 0U,\r
+ ENABLE = !DISABLE\r
+} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum\r
+{\r
+ SUCCESS = 0U,\r
+ ERROR = !SUCCESS\r
+} ErrorStatus;\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup Exported_macro\r
+ * @{\r
+ */\r
+#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG) ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
+\r
+#define READ_REG(REG) ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))\r
+\r
+/* Use of CMSIS compiler intrinsics for register exclusive access */\r
+/* Atomic 32-bit register access macro to set one or several bits */\r
+#define ATOMIC_SET_BIT(REG, BIT) \\r
+ do { \\r
+ uint32_t val; \\r
+ do { \\r
+ val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \\r
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/* Atomic 32-bit register access macro to clear one or several bits */\r
+#define ATOMIC_CLEAR_BIT(REG, BIT) \\r
+ do { \\r
+ uint32_t val; \\r
+ do { \\r
+ val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \\r
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/* Atomic 32-bit register access macro to clear and set one or several bits */\r
+#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \\r
+ do { \\r
+ uint32_t val; \\r
+ do { \\r
+ val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\r
+ } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/* Atomic 16-bit register access macro to set one or several bits */\r
+#define ATOMIC_SETH_BIT(REG, BIT) \\r
+ do { \\r
+ uint16_t val; \\r
+ do { \\r
+ val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \\r
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/* Atomic 16-bit register access macro to clear one or several bits */\r
+#define ATOMIC_CLEARH_BIT(REG, BIT) \\r
+ do { \\r
+ uint16_t val; \\r
+ do { \\r
+ val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \\r
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/* Atomic 16-bit register access macro to clear and set one or several bits */\r
+#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \\r
+ do { \\r
+ uint16_t val; \\r
+ do { \\r
+ val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \\r
+ } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \\r
+ } while(0)\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef USE_HAL_DRIVER\r
+ #include "stm32f7xx_hal.h"\r
+#endif /* USE_HAL_DRIVER */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F7xx_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
--- /dev/null
+/**\r
+ ******************************************************************************\r
+ * @file system_stm32f7xx.h\r
+ * @author MCD Application Team\r
+ * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. \r
+ ******************************************************************************\r
+ * @attention\r
+ *\r
+ * Copyright (c) 2016 STMicroelectronics.\r
+ * All rights reserved.\r
+ *\r
+ * This software is licensed under terms that can be found in the LICENSE file\r
+ * in the root directory of this software component.\r
+ * If no LICENSE file comes with this software, it is provided AS-IS.\r
+ *\r
+ ****************************************************************************** \r
+ */\r
+\r
+/** @addtogroup CMSIS\r
+ * @{\r
+ */\r
+\r
+/** @addtogroup stm32f7xx_system\r
+ * @{\r
+ */ \r
+ \r
+/**\r
+ * @brief Define to prevent recursive inclusion\r
+ */\r
+#ifndef __SYSTEM_STM32F7XX_H\r
+#define __SYSTEM_STM32F7XX_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif \r
+\r
+/** @addtogroup STM32F7xx_System_Includes\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Variables\r
+ * @{\r
+ */\r
+ /* The SystemCoreClock variable is updated in three ways:\r
+ 1) by calling CMSIS function SystemCoreClockUpdate()\r
+ 2) by calling HAL API function HAL_RCC_GetSysClockFreq()\r
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency \r
+ Note: If you use this function to configure the system clock; then there\r
+ is no need to call the 2 first functions listed above, since SystemCoreClock\r
+ variable is updated automatically.\r
+ */\r
+extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */\r
+\r
+extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */\r
+extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */\r
+\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Constants\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Macros\r
+ * @{\r
+ */\r
+\r
+/**\r
+ * @}\r
+ */\r
+\r
+/** @addtogroup STM32F7xx_System_Exported_Functions\r
+ * @{\r
+ */\r
+ \r
+extern void SystemInit(void);\r
+extern void SystemCoreClockUpdate(void);\r
+/**\r
+ * @}\r
+ */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /*__SYSTEM_STM32F7XX_H */\r
+\r
+/**\r
+ * @}\r
+ */\r
+ \r
+/**\r
+ * @}\r
+ */ \r
--- /dev/null
+#include <assert.h>
+#include <cstdint>
+#include <stddef.h>
+
+#define byte4 0xFF, 0xFF, 0xFF, 0xFF
+#define byte8 byte4, byte4
+#define byte16 byte8, byte8
+#define byte32 byte16, byte16
+#define byte64 byte32, byte32
+#define byte128 byte64, byte64
+#define byte256 byte128, byte128
+#define byte512 byte256, byte256
+#define byte1K byte512, byte512
+#define byte2K byte1K, byte1K
+#define byte4K byte2K, byte2K
+
+#define EXAM_BUFFER_CONTENT byte4K
+
+constexpr static int ExamModeBufferSize = 4*1024;
+
+uint32_t staticStorageArea = {0};
+
+class KernelHeader {
+ public:
+ constexpr KernelHeader() :
+ m_header(Magic),
+ m_version{"0.0.0"},
+ m_patchLevel{"zeta"},
+ m_footer(Magic) { }
+ const char * version() const {
+ assert(m_header == Magic);
+ assert(m_footer == Magic);
+ return m_version;
+ }
+ const char * patchLevel() const {
+ assert(m_header == Magic);
+ assert(m_footer == Magic);
+ return m_patchLevel;
+ }
+ private:
+ constexpr static uint32_t Magic = 0xDEC00DF0;
+ uint32_t m_header;
+ const char m_version[8];
+ const char m_patchLevel[8];
+ uint32_t m_footer;
+};
+
+class UserlandHeader {
+public:
+ constexpr UserlandHeader():
+ m_header(Magic),
+ m_expectedEpsilonVersion{"0.0.1"},
+ m_storageAddressRAM(0x20000AE8),
+ m_storageSizeRAM(0x0000EA60),
+ m_externalAppsFlashStart(0xFFFFFFFF),
+ m_externalAppsFlashEnd(0xFFFFFFFF),
+ m_externalAppsRAMStart(0xFFFFFFFF),
+ m_externalAppsRAMEnd(0xFFFFFFFF),
+ m_footer(Magic),
+ m_omegaMagicHeader(OmegaMagic),
+ m_omegaVersion{"0.0.2"},
+ m_username{"Ayabusa"},
+
+ m_omegaMagicFooter(OmegaMagic),
+ m_upsilonMagicHeader(UpsilonMagic),
+ m_UpsilonVersion{"0.0.3"},
+ m_osType(OSType),
+ m_upsilonMagicFooter(UpsilonMagic) { }
+
+ const char * omegaVersion() const {
+ assert(m_header == Magic);
+ assert(m_footer == Magic);
+ assert(m_omegaMagicHeader == OmegaMagic);
+ assert(m_omegaMagicFooter == OmegaMagic);
+ return m_omegaVersion;
+ }
+ const char * upsilonVersion() const {
+ assert(m_header == Magic);
+ assert(m_footer == Magic);
+ assert(m_omegaMagicHeader == OmegaMagic);
+ assert(m_omegaMagicFooter == OmegaMagic);
+ return m_UpsilonVersion;
+ }
+ const volatile char * username() const volatile {
+ assert(m_header == Magic);
+ assert(m_footer == Magic);
+ assert(m_omegaMagicHeader == OmegaMagic);
+ assert(m_omegaMagicFooter == OmegaMagic);
+ return m_username;
+ }
+ const void * storage_address() const {
+ return &staticStorageArea;
+ }
+
+ private:
+ constexpr static uint32_t Magic = 0xDEC0EDFE; // FEEDCODE in hex editor
+ constexpr static uint32_t OmegaMagic = 0xEFBEADDE; // DEADBEEF in hex editor
+ constexpr static uint32_t UpsilonMagic = 0x55707369; // Upsi (reverse) in hex editor (ASCII)
+ constexpr static uint32_t OSType = 0x79827178;
+ uint32_t m_header;
+ const char m_expectedEpsilonVersion[8];
+ uint32_t m_storageAddressRAM;
+ uint32_t m_storageSizeRAM;
+ /* We store the range addresses of external apps memory because storing the
+ * size is complicated due to c++11 constexpr. */
+ uint32_t m_externalAppsFlashStart;
+ uint32_t m_externalAppsFlashEnd;
+ uint32_t m_externalAppsRAMStart;
+ uint32_t m_externalAppsRAMEnd;
+ uint32_t m_footer;
+ uint32_t m_omegaMagicHeader;
+ const char m_omegaVersion[16];
+ const volatile char m_username[16];
+ uint32_t m_omegaMagicFooter;
+ uint32_t m_upsilonMagicHeader;
+ const char m_UpsilonVersion[16];
+ uint32_t m_osType;
+ uint32_t m_upsilonMagicFooter;
+};
+
+// kernel header defined in linker
+const KernelHeader __attribute__((section(".kernel_header"), used)) k_kernelHeader;
+// userland header defined in linker
+const UserlandHeader __attribute__((section(".userland_header"), used)) k_userlandHeader;
+
+// Exam mode defined in linker
+char ones[ExamModeBufferSize]
+ __attribute__((section(".exam_mode_buffer")))
+ __attribute__((used))
+= {EXAM_BUFFER_CONTENT};
\ No newline at end of file
--- /dev/null
+/* Label for the program's entry point */
+/*ENTRY(reset_handler)*/
+/* End of RAM / Start of stack */
+/* (4KB SRAM) */
+_estack = 0x20262144;
+
+/* epsilon stuff */
+STACK_SIZE = 32K;
+FIRST_FLASH_SECTOR_SIZE = 4K;
+SIGNED_PAYLOAD_LENGTH = 8;
+USERLAND_OFFSET = 64K;
+
+/* Set minimum size for stack and dynamic memory. */
+/* (The linker will generate an error if there is
+ * less than this much RAM leftover.) */
+/* (1KB) */
+_Min_Leftover_RAM = 0x400;
+MEMORY
+{
+ FLASH ( rx ) : ORIGIN = 0x90400000, LENGTH = 4M /* This is for the B slot */
+ RAM ( rxw ) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+SECTIONS
+{
+ /* epsilon stuff */
+ .signed_payload_prefix ORIGIN(FLASH) : {
+ FILL(0xFF);
+ BYTE(0xFF)
+ . = ORIGIN(FLASH) + SIGNED_PAYLOAD_LENGTH;
+ } >FLASH
+
+ .kernel_header : {
+ KEEP(*(.kernel_header))
+ } >FLASH
+
+ .slot_info : {
+ *(.slot_info*)
+ } >RAM
+
+ /* The vector table goes at the start of flash. */
+ .isr_vector_table ORIGIN(RAM) + 512 : AT(ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header)) {
+ /* When booting, the STM32F412 fetches the content of address 0x0, and
+ * extracts from it various key infos: the initial value of the PC register
+ * (program counter), the initial value of the stack pointer, and various
+ * entry points to interrupt service routines. This data is called the ISR
+ * vector table.
+ *
+ * Note that address 0x0 is always an alias. It points to the beginning of
+ * Flash, SRAM, or integrated bootloader depending on the boot mode chosen.
+ * (This mode is chosen by setting the BOOTn pins on the chip).
+ *
+ * We're generating the ISR vector table in code because it's very
+ * convenient: using function pointers, we can easily point to the service
+ * routine for each interrupt. */
+ _isr_vector_table_start_flash = LOADADDR(.isr_vector_table);
+ _isr_vector_table_start_ram = .;
+ KEEP(*(.isr_vector_table))
+ _isr_vector_table_end_ram = .;
+ } >RAM
+
+ .exam_mode_buffer ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header) + SIZEOF(.isr_vector_table) : {
+ . = ALIGN(4K);
+ _exam_mode_buffer_start = .;
+ KEEP(*(.exam_mode_buffer))
+ /* Note: We don't increment "." here, we set it. */
+ . = . + FIRST_FLASH_SECTOR_SIZE;
+ _exam_mode_buffer_end = .;
+ } >FLASH
+
+ /* External flash memory */
+ .userland_header : {
+ . = ORIGIN(FLASH) + USERLAND_OFFSET;
+ KEEP(*(.userland_header));
+ } > FLASH
+
+ .text : {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ } >FLASH
+ /* The 'rodata' section contains read-only data,
+ * constants, strings, information that won't change. */
+ .rodata : {
+ *(.rodata)
+ *(.rodata.*)
+ } >FLASH
+
+ /* The 'data' section is space set aside in RAM for
+ * things like variables, which can change. */
+ .data : {
+ /* The data section is written to Flash but linked as if it were in RAM.
+ *
+ * This is required because its initial value matters (so it has to be in
+ * persistant memory in the first place), but it is a R/W area of memory
+ * so it will have to live in RAM upon execution (in linker lingo, that
+ * translates to the data section having a LMA in Flash and a VMA in RAM).
+ *
+ * This means we'll have to copy it from Flash to RAM on initialization.
+ * To do this, we'll need to know the source location of the data section
+ * (in Flash), the target location (in RAM), and the size of the section.
+ * That's why we're defining three symbols that we'll use in the initial-
+ * -ization routine. */
+ . = ALIGN(4);
+ _data_section_start_flash = LOADADDR(.data);
+ _data_section_start_ram = .;
+ *(.data)
+ *(.data.*)
+ _data_section_end_ram = .;
+ } >RAM AT> FLASH
+
+ /* The 'bss' section is similar to the 'data' section,
+ * but its space is initialized to all 0s at the
+ * start of the program. */
+ .bss : {
+ /* The bss section contains data for all uninitialized variables
+ * So like the .data section, it will go in RAM, but unlike the data section
+ * we don't care at all about an initial value.
+ *
+ * Before execution, crt0 will erase that section of memory though, so we'll
+ * need pointers to the beginning and end of this section. */
+ . = ALIGN(4);
+ _bss_section_start_ram = .;
+ *(.bss)
+ *(.bss.*)
+ /* The compiler may choose to allocate uninitialized global variables as
+ * COMMON blocks. This can be disabled with -fno-common if needed. */
+ *(COMMON)
+ _bss_section_end_ram = .;
+ } >RAM
+
+ .heap : {
+ _heap_start = .;
+ /* Note: We don't increment "." here, we set it. */
+ . = (ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE);
+ _heap_end = .;
+ } >RAM
+
+ .stack : {
+ . = ALIGN(8);
+ _stack_end = .;
+ . += (STACK_SIZE - 8);
+ . = ALIGN(8);
+ _stack_start = .;
+ } >RAM
+
+ /DISCARD/ : {
+ /* exidx and extab are needed for unwinding, which we don't use */
+ *(.ARM.exidx*)
+ *(.ARM.extab*)
+ }
+}
\ No newline at end of file
--- /dev/null
+#include "main.h"
+
+/* Main program. */
+int main(void) {
+ // Enable the GPIOa and GPIOC peripheral in RCC.
+ RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ;
+
+ // C0 is connected to the LED
+ // It should be set to push-pull low-speed output.
+ GPIOB->MODER &= ~(0x3 << (LED_PIN*2));
+ GPIOB->MODER |= (0x1 << (LED_PIN*2));
+ GPIOB->OTYPER &= ~(1 << LED_PIN);
+
+ // set the led on
+ GPIOB->ODR = (1 << LED_PIN);
+ while (0)
+ {
+ GPIOB->ODR = (1 << LED_PIN);
+ }
+
+}
\ No newline at end of file
--- /dev/null
+#ifndef _VVC_MAIN_H
+#define _VVC_MAIN_H
+#include <stdint.h>
+#include "device/stm32f730xx.h"
+// Define GPIOB pin mappings for our LED and button.
+#define LED_PIN (3) // led on PC0
+#endif
\ No newline at end of file
--- /dev/null
+#include "vector_table.h"
+#include <stddef.h>
+
+typedef void (*cxx_constructor)();
+
+extern "C" {
+ extern char _data_section_start_flash;
+ extern char _data_section_start_ram;
+ extern char _data_section_end_ram;
+ extern char _bss_section_start_ram;
+ extern char _bss_section_end_ram;
+ extern cxx_constructor _init_array_start;
+ extern cxx_constructor _init_array_end;
+}
+
+
+void* memcpy_custom(void* destination, const void* source, size_t num_bytes) {
+ char* dest_ptr = (char*)destination;
+ const char* src_ptr = (const char*)source;
+
+ // Copy each byte from source to destination
+ for (size_t i = 0; i < num_bytes; ++i) {
+ dest_ptr[i] = src_ptr[i];
+ }
+
+ return destination;
+}
+
+void* memset_custom(void* ptr, int value, size_t num_bytes) {
+ unsigned char* p = (unsigned char*)ptr;
+ unsigned char v = (unsigned char)value;
+
+ // Set each byte in the memory block to the specified value
+ for (size_t i = 0; i < num_bytes; ++i) {
+ p[i] = v;
+ }
+
+ return ptr;
+}
+
+void __attribute__((noinline)) start() {
+ /* Copy data section to RAM
+ * The data section is R/W but its initialization value matters. It's stored
+ * in Flash, but linked as if it were in RAM. Now's our opportunity to copy
+ * it. Note that until then the data section (e.g. global variables) contains
+ * garbage values and should not be used. */
+ size_t dataSectionLength = (&_data_section_end_ram - &_data_section_start_ram);
+ memcpy_custom(&_data_section_start_ram, &_data_section_start_flash, dataSectionLength);
+
+ /* Zero-out the bss section in RAM
+ * Until we do, any uninitialized global variable will be unusable. */
+ size_t bssSectionLength = (&_bss_section_end_ram - &_bss_section_start_ram);
+ memset_custom(&_bss_section_start_ram, 0, bssSectionLength);
+
+ while (0)
+ {
+ /* code */
+ }
+}
\ No newline at end of file
--- /dev/null
+#include "vector_table.h"
+extern const void * _estack;
+
+/* Interrupt Service Routines are void->void functions */
+typedef void(*ISR)(void);
+
+/* Notice: The Cortex-M4 expects all jumps to be made at an odd address when
+ * jumping to Thumb code. For example, if you want to execute Thumb code at
+ * address 0x100, you'll have to jump to 0x101. Luckily, this idiosyncrasy is
+ * properly handled by the C compiler that will generate proper addresses when
+ * using function pointers. */
+
+#define INITIALISATION_VECTOR_SIZE 0x71
+
+ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
+ __attribute__((section(".isr_vector_table")))
+ __attribute__((used))
+ = {
+ (ISR)&_estack, // Stack start
+ start, // Reset service routine,
+ 0, // NMI service routine,
+ 0, // HardFault service routine,
+ 0, // MemManage service routine,
+ 0, // BusFault service routine,
+ 0, // UsageFault service routine,
+ 0, 0, 0, 0, // Reserved
+ 0, // SVCall service routine,
+ 0, // DebugMonitor service routine,
+ 0, // Reserved
+ 0, // PendSV service routine,
+ 0, // SysTick service routine
+ 0, // WWDG service routine
+ 0, // PVD service routine
+ 0, // TampStamp service routine
+ 0, // RtcWakeup service routine
+ 0, // Flash service routine
+ 0, // RCC service routine
+ 0, // EXTI0 service routine
+ 0, // EXTI1 service routine
+ 0, // EXTI2 service routine
+ 0, // EXTI3 service routine
+ 0, // EXTI4 service routine
+ 0, // DMA1Stream0 service routine
+ 0, // DMA1Stream1 service routine
+ 0, // DMA1Stream2 service routine
+ 0, // DMA1Stream3 service routine
+ 0, // DMA1Stream4 service routine
+ 0, // DMA1Stream5 service routine
+ 0, // DMA1Stream6 service routine
+ 0, // ADC1 global interrupt
+ 0, // CAN1 TX interrupt
+ 0, // CAN1 RX0 interrupt
+ 0, // CAN1 RX1 interrupt
+ 0, // CAN1 SCE interrupt
+ 0, // EXTI Line[9:5] interrupts
+ 0, // TIM1 Break interrupt and TIM9 global interrupt
+ 0, // TIM1 update interrupt and TIM10 global interrupt
+ 0, // TIM1 Trigger & Commutation interrupts and TIM11 global interrupt
+ 0, // TIM1 Capture Compare interrupt
+ 0, // TIM2 global interrupt
+ 0, // TIM3 global interrupt
+ 0, // TIM4 global interrupt
+ 0, // I2C1 global event interrupt
+ 0, // I2C1 global error interrupt
+ 0, // I2C2 global event interrupt
+ 0, // I2C2 global error interrupt
+ 0, // SPI1 global interrupt
+ 0, // SPI2 global interrupt
+ 0, // USART1 global interrupt
+ 0, // USART2 global interrupt
+ 0, // USART3 global interrupt
+ 0, // EXTI Line[15:10] interrupts
+ 0, // EXTI Line 17 interrupt RTC Alarms (A and B) through EXTI line interrupt
+ 0, // EXTI Line 18 interrupt / USB On-The-Go FS Wakeup through EXTI line interrupt
+ 0, // TIM8 Break interrupt TIM12 global interrupt
+ 0, // TIM8 Update interrupt TIM13 global interrupt
+ 0, // TIM8 Trigger & Commutation interrupt TIM14 global interrupt
+ 0, // TIM8 Cap/Com interrupt
+ 0, // DMA1 global interrupt Channel 7
+ 0, // FSMC global interrupt
+ 0, // SDIO global interrupt
+ 0, // TIM5 global interrupt
+ 0, // SPI3 global interrupt
+ 0, // ?
+ 0, // ?
+ 0, // TIM6 global interrupt
+ 0, // TIM7 global interrupt
+ 0, // DMA2 Stream0 global interrupt
+ 0, // DMA2 Stream1 global interrupt
+ 0, // DMA2 Stream2 global interrupt
+ 0, // DMA2 Stream3 global interrupt
+ 0, // DMA2 Stream4 global interrupt
+ 0, // SD filter0 global interrupt
+ 0, // SD filter1 global interrupt
+ 0, // CAN2 TX interrupt
+ 0, // BXCAN2 RX0 interrupt
+ 0, // BXCAN2 RX1 interrupt
+ 0, // CAN2 SCE interrupt
+ 0, // USB On The Go FS global interrupt
+ 0, // DMA2 Stream5 global interrupts
+ 0, // DMA2 Stream6 global interrupt
+ 0, // DMA2 Stream7 global interrupt
+ 0, // USART6 global interrupt
+ 0, // I2C3 event interrupt
+ 0, // I2C3 error interrupt
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // RNG global interrupt
+ 0, // FPU global interrupt
+ 0, // ?
+ 0, // ?
+ 0, // SPI4 global interrupt
+ 0, // SPI5 global interrupt
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // ?
+ 0, // Quad-SPI global interrupt
+ 0, // ?
+ 0, // ?
+ 0, // I2CFMP1 event interrupt
+ 0 // I2CFMP1 error interrupt
+};
--- /dev/null
+#ifndef VECTOR_TABLE_H
+#define VECTOR_TABLE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void start();
+void abort();
+void isr_systick();
+
+// Fault handlers
+
+void hard_fault_handler();
+void mem_fault_handler();
+void usage_fault_handler();
+void bus_fault_handler();
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
+++ /dev/null
-.syntax unified
-.cpu cortex-m0
-.fpu softvfp
-.thumb
-
-// Global values.
-.global reset_handler
-
-/*
- * The Reset handler. Called on reset.
- */
-.type reset_handler, %function
-reset_handler:
- // Set the stack pointer to the end of the stack.
- // The '_estack' value is defined in our linker script.
- LDR r0, =_estack
- MOV sp, r0
-
- // Copy data from flash to RAM data init section.
- // R2 will store our progress along the sidata section.
- MOVS r0, #0
- // Load the start/end addresses of the data section,
- // and the start of the data init section.
- LDR r1, =_sdata
- LDR r2, =_edata
- LDR r3, =_sidata
- B copy_sidata_loop
-
- copy_sidata:
- // Offset the data init section by our copy progress.
- LDR r4, [r3, r0]
- // Copy the current word into data, and increment.
- STR r4, [r1, r0]
- ADDS r0, r0, #4
-
- copy_sidata_loop:
- // Unless we've copied the whole data section, copy the
- // next word from sidata->data.
- ADDS r4, r0, r1
- CMP r4, r2
- BCC copy_sidata
-
- // Once we are done copying the data section into RAM,
- // move on to filling the BSS section with 0s.
- MOVS r0, #0
- LDR r1, =_sbss
- LDR r2, =_ebss
- B reset_bss_loop
-
- // Zero out the BSS segment.
- reset_bss:
- // Store a 0 and increment by a word.
- STR r0, [r1]
- ADDS r1, r1, #4
-
- reset_bss_loop:
- // We'll use R1 to count progress here; if we aren't
- // done, reset the next word and increment.
- CMP r1, r2
- BCC reset_bss
-
- // Branch to the 'main' method.
- B main
-.size reset_handler, .-reset_handler
+++ /dev/null
-/**************************************************************************//**\r
- * @file cmsis_gcc.h\r
- * @brief CMSIS Cortex-M Core Function/Instruction Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#ifndef __CMSIS_GCC_H\r
-#define __CMSIS_GCC_H\r
-\r
-/* ignore some GCC warnings */\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic push\r
-#pragma GCC diagnostic ignored "-Wsign-conversion"\r
-#pragma GCC diagnostic ignored "-Wconversion"\r
-#pragma GCC diagnostic ignored "-Wunused-parameter"\r
-#endif\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
- */\r
-\r
-/**\r
- \brief Enable IRQ Interrupts\r
- \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
-{\r
- __ASM volatile ("cpsie i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable IRQ Interrupts\r
- \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
-{\r
- __ASM volatile ("cpsid i" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Control Register\r
- \details Returns the content of the Control Register.\r
- \return Control Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, control" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Control Register\r
- \details Writes the given value to the Control Register.\r
- \param [in] control Control Register value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
-{\r
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get IPSR Register\r
- \details Returns the content of the IPSR Register.\r
- \return IPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get APSR Register\r
- \details Returns the content of the APSR Register.\r
- \return APSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get xPSR Register\r
- \details Returns the content of the xPSR Register.\r
-\r
- \return xPSR Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Get Process Stack Pointer\r
- \details Returns the current value of the Process Stack Pointer (PSP).\r
- \return PSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Process Stack Pointer\r
- \details Assigns the given value to the Process Stack Pointer (PSP).\r
- \param [in] topOfProcStack Process Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
-{\r
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Main Stack Pointer\r
- \details Returns the current value of the Main Stack Pointer (MSP).\r
- \return MSP Register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
-{\r
- register uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Main Stack Pointer\r
- \details Assigns the given value to the Main Stack Pointer (MSP).\r
-\r
- \param [in] topOfMainStack Main Stack Pointer value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
-{\r
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Priority Mask\r
- \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
- \return Priority Mask value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Priority Mask\r
- \details Assigns the given value to the Priority Mask Register.\r
- \param [in] priMask Priority Mask\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
-{\r
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
-}\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U)\r
-\r
-/**\r
- \brief Enable FIQ\r
- \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsie f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Disable FIQ\r
- \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
- Can only be executed in Privileged modes.\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
-{\r
- __ASM volatile ("cpsid f" : : : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Base Priority\r
- \details Returns the current value of the Base Priority register.\r
- \return Base Priority register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority\r
- \details Assigns the given value to the Base Priority register.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Set Base Priority with condition\r
- \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
- or the new value increases the BASEPRI priority level.\r
- \param [in] basePri Base Priority value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
-{\r
- __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Get Fault Mask\r
- \details Returns the current value of the Fault Mask register.\r
- \return Fault Mask register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Set Fault Mask\r
- \details Assigns the given value to the Fault Mask register.\r
- \param [in] faultMask Fault Mask value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
-{\r
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) */\r
-\r
-\r
-#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
-\r
-/**\r
- \brief Get FPSCR\r
- \details Returns the current value of the Floating Point Status/Control register.\r
- \return Floating Point Status/Control register value\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- uint32_t result;\r
-\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
- __ASM volatile ("");\r
- return(result);\r
-#else\r
- return(0);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Set FPSCR\r
- \details Assigns the given value to the Floating Point Status/Control register.\r
- \param [in] fpscr Floating Point Status/Control value to set\r
- */\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
-{\r
-#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
- /* Empty asm statement works as a scheduling barrier */\r
- __ASM volatile ("");\r
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
- __ASM volatile ("");\r
-#endif\r
-}\r
-\r
-#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
-\r
-\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/* Define macros for porting to both thumb1 and thumb2.\r
- * For thumb1, use low register (r0-r7), specified by constraint "l"\r
- * Otherwise, use general registers, specified by constraint "r" */\r
-#if defined (__thumb__) && !defined (__thumb2__)\r
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
-#else\r
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
-#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
-#endif\r
-\r
-/**\r
- \brief No Operation\r
- \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
-{\r
- __ASM volatile ("nop");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Interrupt\r
- \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
-{\r
- __ASM volatile ("wfi");\r
-}\r
-\r
-\r
-/**\r
- \brief Wait For Event\r
- \details Wait For Event is a hint instruction that permits the processor to enter\r
- a low-power state until one of a number of events occurs.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
-{\r
- __ASM volatile ("wfe");\r
-}\r
-\r
-\r
-/**\r
- \brief Send Event\r
- \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
-{\r
- __ASM volatile ("sev");\r
-}\r
-\r
-\r
-/**\r
- \brief Instruction Synchronization Barrier\r
- \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
- so that all instructions following the ISB are fetched from cache or memory,\r
- after the instruction has been completed.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
-{\r
- __ASM volatile ("isb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Synchronization Barrier\r
- \details Acts as a special kind of Data Memory Barrier.\r
- It completes when all explicit memory accesses before this instruction complete.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
-{\r
- __ASM volatile ("dsb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Data Memory Barrier\r
- \details Ensures the apparent order of the explicit memory operations before\r
- and after the instruction, without ensuring their completion.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
-{\r
- __ASM volatile ("dmb 0xF":::"memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (32 bit)\r
- \details Reverses the byte order in integer value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
- return __builtin_bswap32(value);\r
-#else\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order (16 bit)\r
- \details Reverses the byte order in two unsigned short values.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Reverse byte order in signed short value\r
- \details Reverses the byte order in a signed short value with sign extension to integer.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
-{\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- return (short)__builtin_bswap16(value);\r
-#else\r
- int32_t result;\r
-\r
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-#endif\r
-}\r
-\r
-\r
-/**\r
- \brief Rotate Right in unsigned value (32 bit)\r
- \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
- \param [in] value Value to rotate\r
- \param [in] value Number of Bits to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
-{\r
- return (op1 >> op2) | (op1 << (32U - op2));\r
-}\r
-\r
-\r
-/**\r
- \brief Breakpoint\r
- \details Causes the processor to enter Debug state.\r
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
- \param [in] value is ignored by the processor.\r
- If required, a debugger can use it to store additional information about the breakpoint.\r
- */\r
-#define __BKPT(value) __ASM volatile ("bkpt "#value)\r
-\r
-\r
-/**\r
- \brief Reverse bit order of value\r
- \details Reverses the bit order of the given value.\r
- \param [in] value Value to reverse\r
- \return Reversed value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
-#else\r
- int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
-\r
- result = value; /* r will be reversed bits of v; first get LSB of v */\r
- for (value >>= 1U; value; value >>= 1U)\r
- {\r
- result <<= 1U;\r
- result |= value & 1U;\r
- s--;\r
- }\r
- result <<= s; /* shift when v's highest bits are zero */\r
-#endif\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Count leading zeros\r
- \details Counts the number of leading zeros of a data value.\r
- \param [in] value Value to count the leading zeros\r
- \return number of leading zeros in value\r
- */\r
-#define __CLZ __builtin_clz\r
-\r
-\r
-#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
-\r
-/**\r
- \brief LDR Exclusive (8 bit)\r
- \details Executes a exclusive LDR instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (16 bit)\r
- \details Executes a exclusive LDR instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDR Exclusive (32 bit)\r
- \details Executes a exclusive LDR instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (8 bit)\r
- \details Executes a exclusive STR instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (16 bit)\r
- \details Executes a exclusive STR instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STR Exclusive (32 bit)\r
- \details Executes a exclusive STR instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- \return 0 Function succeeded\r
- \return 1 Function failed\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief Remove the exclusive lock\r
- \details Removes the exclusive lock which is created by LDREX.\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
-{\r
- __ASM volatile ("clrex" ::: "memory");\r
-}\r
-\r
-\r
-/**\r
- \brief Signed Saturate\r
- \details Saturates a signed value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (1..32)\r
- \return Saturated value\r
- */\r
-#define __SSAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Unsigned Saturate\r
- \details Saturates an unsigned value.\r
- \param [in] value Value to be saturated\r
- \param [in] sat Bit position to saturate to (0..31)\r
- \return Saturated value\r
- */\r
-#define __USAT(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-\r
-/**\r
- \brief Rotate Right with Extend (32 bit)\r
- \details Moves each bit of a bitstring right by one bit.\r
- The carry input is shifted in at the left end of the bitstring.\r
- \param [in] value Value to rotate\r
- \return Rotated value\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint8_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint8_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint16_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
-{\r
- uint32_t result;\r
-\r
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
- __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
-#else\r
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
- accepted by assembler. So has to use following less efficient pattern.\r
- */\r
- __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
-#endif\r
- return ((uint16_t) result); /* Add explicit type cast here */\r
-}\r
-\r
-\r
-/**\r
- \brief LDRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
- \param [in] ptr Pointer to data\r
- \return value of type uint32_t at (*ptr)\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
- return(result);\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (8 bit)\r
- \details Executes a Unprivileged STRT instruction for 8 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
-{\r
- __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (16 bit)\r
- \details Executes a Unprivileged STRT instruction for 16 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
-{\r
- __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
-}\r
-\r
-\r
-/**\r
- \brief STRT Unprivileged (32 bit)\r
- \details Executes a Unprivileged STRT instruction for 32 bit values.\r
- \param [in] value Value to store\r
- \param [in] ptr Pointer to location\r
- */\r
-__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
-{\r
- __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#define __SSAT16(ARG1,ARG2) \\r
-({ \\r
- int32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-#define __USAT16(ARG1,ARG2) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1); \\r
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
-{\r
- union llreg_u{\r
- uint32_t w32[2];\r
- uint64_t w64;\r
- } llr;\r
- llr.w64 = acc;\r
-\r
-#ifndef __ARMEB__ /* Little endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
-#else /* Big endian */\r
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
-#endif\r
-\r
- return(llr.w64);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)\r
-{\r
- uint32_t result;\r
-\r
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
- return(result);\r
-}\r
-\r
-#define __PKHBT(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-#define __PKHTB(ARG1,ARG2,ARG3) \\r
-({ \\r
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
- if (ARG3 == 0) \\r
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \\r
- else \\r
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \\r
- __RES; \\r
- })\r
-\r
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
-{\r
- int32_t result;\r
-\r
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );\r
- return(result);\r
-}\r
-\r
-#endif /* (__CORTEX_M >= 0x04) */\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#if defined ( __GNUC__ )\r
-#pragma GCC diagnostic pop\r
-#endif\r
-\r
-#endif /* __CMSIS_GCC_H */\r
+++ /dev/null
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V4.30
- * @date 20. October 2015
- ******************************************************************************/
-/* Copyright (c) 2009 - 2015 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header /* treat file as system include file */
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-#include <stdint.h>
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/**
- \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/**
- \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x04U) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x1EU) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04U) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __CSMC__ )
- #define __packed
- #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
- #define __INLINE inline /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
- #define __STATIC_INLINE static inline
-
-#else
- #error Unknown compiler
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not.
- For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
- #if defined __ARM_PCS_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1U
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#elif defined ( __CSMC__ )
- #if ( __CSMC__ & 0x400U)
- #if (__FPU_PRESENT == 1U)
- #define __FPU_USED 1U
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0U
- #endif
- #else
- #define __FPU_USED 0U
- #endif
-
-#endif
-
-#include "core_cmInstr.h" /* Core Instruction Access */
-#include "core_cmFunc.h" /* Core Function Access */
-#include "core_cmSimd.h" /* Compiler specific SIMD Intrinsics */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000U
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0U
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0U
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4U
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0U
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/* following defines should be used for structure members */
-#define __IM volatile const /*! Defines 'read only' structure member permissions */
-#define __OM volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/**
- \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/**
- \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-/* APSR Register Definitions */
-#define APSR_N_Pos 31U /*!< APSR: N Position */
-#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
-
-#define APSR_Z_Pos 30U /*!< APSR: Z Position */
-#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
-
-#define APSR_C_Pos 29U /*!< APSR: C Position */
-#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
-
-#define APSR_V_Pos 28U /*!< APSR: V Position */
-#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
-
-#define APSR_Q_Pos 27U /*!< APSR: Q Position */
-#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
-
-#define APSR_GE_Pos 16U /*!< APSR: GE Position */
-#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
-
-
-/**
- \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-/* IPSR Register Definitions */
-#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
-#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-/* xPSR Register Definitions */
-#define xPSR_N_Pos 31U /*!< xPSR: N Position */
-#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
-
-#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
-#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
-
-#define xPSR_C_Pos 29U /*!< xPSR: C Position */
-#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
-
-#define xPSR_V_Pos 28U /*!< xPSR: V Position */
-#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
-
-#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
-#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
-
-#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
-#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
-
-#define xPSR_T_Pos 24U /*!< xPSR: T Position */
-#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
-
-#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
-#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
-
-#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
-#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
-
-
-/**
- \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/* CONTROL Register Definitions */
-#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
-#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
-
-#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
-#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
-
-#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
-#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
-
-/*@} end of group CMSIS_CORE */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/**
- \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24U];
- __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24U];
- __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24U];
- __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24U];
- __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56U];
- __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644U];
- __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/**
- \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5U];
- __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Register Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Register Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/**
- \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/**
- \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/**
- \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __OM union
- {
- __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864U];
- __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15U];
- __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15U];
- __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29U];
- __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43U];
- __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6U];
- __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/**
- \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1U];
- __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1U];
- __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1U];
- __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/**
- \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2U];
- __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55U];
- __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131U];
- __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759U];
- __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1U];
- __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39U];
- __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8U];
- __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/**
- \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register Definitions */
-#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register Definitions */
-#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register Definitions */
-#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register Definitions */
-#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register Definitions */
-#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1U)
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/**
- \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1U];
- __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register Definitions */
-#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register Definitions */
-#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register Definitions */
-#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 Definitions */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 Definitions */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/**
- \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register Definitions */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register Definitions */
-#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register Definitions */
-#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_bitfield Core register bit field macros
- \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
- @{
- */
-
-/**
- \brief Mask and shift a bit field value for use in a register bit range.
- \param[in] field Name of the register bit field.
- \param[in] value Value of the bit field.
- \return Masked and shifted value.
-*/
-#define _VAL2FLD(field, value) ((value << field ## _Pos) & field ## _Msk)
-
-/**
- \brief Mask and shift a register value to extract a bit filed value.
- \param[in] field Name of the register bit field.
- \param[in] value Value of register.
- \return Masked and shifted bit field value.
-*/
-#define _FLD2VAL(field, value) ((value & field ## _Msk) >> field ## _Pos)
-
-/*@} end of group CMSIS_core_bitfield */
-
-
-/**
- \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1U)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1U)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/**
- \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/**
- \brief Set Priority Grouping
- \details Sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/**
- \brief Get Priority Grouping
- \details Reads the priority grouping field from the NVIC Interrupt Controller.
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
-}
-
-
-/**
- \brief Enable External Interrupt
- \details Enables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Disable External Interrupt
- \details Disables a device-specific interrupt in the NVIC interrupt controller.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Pending Interrupt
- \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Pending Interrupt
- \details Sets the pending bit of an external interrupt.
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Clear Pending Interrupt
- \details Clears the pending bit of an external interrupt.
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
-}
-
-
-/**
- \brief Get Active Interrupt
- \details Reads the active register in NVIC and returns the active bit.
- \param [in] IRQn Interrupt number.
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
-}
-
-
-/**
- \brief Set Interrupt Priority
- \details Sets the priority of an interrupt.
- \note The priority cannot be set for every core interrupt.
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if ((int32_t)(IRQn) < 0)
- {
- SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
- else
- {
- NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
- }
-}
-
-
-/**
- \brief Get Interrupt Priority
- \details Reads the priority of an interrupt.
- The interrupt number can be positive to specify an external (device specific) interrupt,
- or negative to specify an internal (core) interrupt.
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority.
- Value is aligned automatically to the implemented priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if ((int32_t)(IRQn) < 0)
- {
- return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
- }
- else
- {
- return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
- }
-}
-
-
-/**
- \brief Encode Priority
- \details Encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- return (
- ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
- ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
- );
-}
-
-
-/**
- \brief Decode Priority
- \details Decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
- SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
- *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
-}
-
-
-/**
- \brief System Reset
- \details Initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
-
- for(;;) /* wait until reset */
- {
- __NOP();
- }
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0U)
-
-/**
- \brief System Tick Configuration
- \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
- \param [in] ticks Number of ticks between two interrupts.
- \return 0 Function succeeded.
- \return 1 Function failed.
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- {
- return (1UL); /* Reload value impossible */
- }
-
- SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0UL); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/**
- \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/**
- \brief ITM Send Character
- \details Transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
- \param [in] ch Character to transmit.
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
- ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0U].u32 == 0UL)
- {
- __NOP();
- }
- ITM->PORT[0U].u8 = (uint8_t)ch;
- }
- return (ch);
-}
-
-
-/**
- \brief ITM Receive Character
- \details Inputs a character via the external variable \ref ITM_RxBuffer.
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void)
-{
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
- {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/**
- \brief ITM Check Character
- \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void)
-{
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
- {
- return (0); /* no character available */
- }
- else
- {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
\ No newline at end of file
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmFunc.h\r
- * @brief CMSIS Cortex-M Core Function Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMFUNC_H\r
-#define __CORE_CMFUNC_H\r
-\r
-\r
-/* ########################### Core Function Access ########################### */\r
-/** \ingroup CMSIS_Core_FunctionInterface\r
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of CMSIS_Core_RegAccFunctions */\r
-\r
-#endif /* __CORE_CMFUNC_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmInstr.h\r
- * @brief CMSIS Cortex-M Core Instruction Access Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMINSTR_H\r
-#define __CORE_CMINSTR_H\r
-\r
-\r
-/* ########################## Core Instruction Access ######################### */\r
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
- Access to dedicated instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
-\r
-#endif /* __CORE_CMINSTR_H */\r
+++ /dev/null
-/**************************************************************************//**\r
- * @file core_cmSimd.h\r
- * @brief CMSIS Cortex-M SIMD Header File\r
- * @version V4.30\r
- * @date 20. October 2015\r
- ******************************************************************************/\r
-/* Copyright (c) 2009 - 2015 ARM LIMITED\r
-\r
- All rights reserved.\r
- Redistribution and use in source and binary forms, with or without\r
- modification, are permitted provided that the following conditions are met:\r
- - Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- - Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in the\r
- documentation and/or other materials provided with the distribution.\r
- - Neither the name of ARM nor the names of its contributors may be used\r
- to endorse or promote products derived from this software without\r
- specific prior written permission.\r
- *\r
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
- POSSIBILITY OF SUCH DAMAGE.\r
- ---------------------------------------------------------------------------*/\r
-\r
-\r
-#if defined ( __ICCARM__ )\r
- #pragma system_include /* treat file as system include file for MISRA check */\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #pragma clang system_header /* treat file as system include file */\r
-#endif\r
-\r
-#ifndef __CORE_CMSIMD_H\r
-#define __CORE_CMSIMD_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif\r
-\r
-\r
-/* ################### Compiler specific Intrinsics ########################### */\r
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
- Access to dedicated SIMD instructions\r
- @{\r
-*/\r
-\r
-/*------------------ RealView Compiler -----------------*/\r
-#if defined ( __CC_ARM )\r
- #include "cmsis_armcc.h"\r
-\r
-/*------------------ ARM Compiler V6 -------------------*/\r
-#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
- #include "cmsis_armcc_V6.h"\r
-\r
-/*------------------ GNU Compiler ----------------------*/\r
-#elif defined ( __GNUC__ )\r
- #include "cmsis_gcc.h"\r
-\r
-/*------------------ ICC Compiler ----------------------*/\r
-#elif defined ( __ICCARM__ )\r
- #include <cmsis_iar.h>\r
-\r
-/*------------------ TI CCS Compiler -------------------*/\r
-#elif defined ( __TMS470__ )\r
- #include <cmsis_ccs.h>\r
-\r
-/*------------------ TASKING Compiler ------------------*/\r
-#elif defined ( __TASKING__ )\r
- /*\r
- * The CMSIS functions have been implemented as intrinsics in the compiler.\r
- * Please use "carm -?i" to get an up to date list of all intrinsics,\r
- * Including the CMSIS ones.\r
- */\r
-\r
-/*------------------ COSMIC Compiler -------------------*/\r
-#elif defined ( __CSMC__ )\r
- #include <cmsis_csm.h>\r
-\r
-#endif\r
-\r
-/*@} end of group CMSIS_SIMD_intrinsics */\r
-\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif\r
-\r
-#endif /* __CORE_CMSIMD_H */\r
+++ /dev/null
-/**\r
- ******************************************************************************\r
- * @file stm32f4xx.h\r
- * @author MCD Application Team\r
- * @version V1.2.0RC2 - edited by Keil\r
- * @date 20-February-2013\r
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File. \r
- * This file contains all the peripheral register's definitions, bits \r
- * definitions and memory mapping for STM32F4xx devices. \r
- * \r
- * The file is the unique include file that the application programmer\r
- * is using in the C source code, usually in main.c. This file contains:\r
- * - Configuration section that allows to select:\r
- * - The device used in the target application\r
- * - To use or not the peripheral�s drivers in application code(i.e. \r
- * code will be based on direct access to peripheral�s registers \r
- * rather than drivers API), this option is controlled by \r
- * "#define USE_STDPERIPH_DRIVER"\r
- * - To change few application-specific parameters such as the HSE \r
- * crystal frequency\r
- * - Data structures and the address mapping for all peripherals\r
- * - Peripheral's registers declarations and bits definition\r
- * - Macros to access peripheral�s registers hardware\r
- * \r
- ******************************************************************************\r
- * @attention\r
- *\r
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>\r
- *\r
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
- * You may not use this file except in compliance with the License.\r
- * You may obtain a copy of the License at:\r
- *\r
- * http://www.st.com/software_license_agreement_liberty_v2\r
- *\r
- * Unless required by applicable law or agreed to in writing, software \r
- * distributed under the License is distributed on an "AS IS" BASIS, \r
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
- * See the License for the specific language governing permissions and\r
- * limitations under the License.\r
- *\r
- ****************************************************************************** \r
- */ \r
-\r
-/** @addtogroup CMSIS\r
- * @{\r
- */\r
-\r
-/** @addtogroup stm32f4xx\r
- * @{\r
- */\r
- \r
-#ifndef __STM32F4xx_H\r
-#define __STM32F4xx_H\r
-\r
-#ifdef __cplusplus\r
- extern "C" {\r
-#endif /* __cplusplus */\r
- \r
-/** @addtogroup Library_configuration_section\r
- * @{\r
- */\r
- \r
-/* Uncomment the line below according to the target STM32 device used in your\r
- application \r
- */\r
-\r
-#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X) \r
- #define STM32F40XX /*!< STM32F40xx/41xx Devices */\r
- /* #define STM32F427X */ /*!< STM32F427x/437x Devices */\r
- /* #define STM32F429X */ /*!< STM32F429x/439x Devices */\r
-#endif\r
-\r
-\r
-/* Tip: To avoid modifying this file each time you need to switch between these\r
- devices, you can define the device in your toolchain compiler preprocessor.\r
- */\r
-\r
-#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X)\r
- #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"\r
-#endif\r
-\r
-#if !defined (USE_STDPERIPH_DRIVER)\r
-/**\r
- * @brief Comment the line below if you will not use the peripherals drivers.\r
- In this case, these drivers will not be included and the application code will \r
- be based on direct access to peripherals registers \r
- */\r
- /*#define USE_STDPERIPH_DRIVER */\r
-#endif /* USE_STDPERIPH_DRIVER */\r
-\r
-/**\r
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
- used in your application \r
- \r
- Tip: To avoid modifying this file each time you need to use different HSE, you\r
- can define the HSE value in your toolchain compiler preprocessor.\r
- */ \r
-\r
-#if !defined (HSE_VALUE) \r
- #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
- \r
-#endif /* HSE_VALUE */\r
-\r
-/**\r
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
- Timeout value \r
- */\r
-#if !defined (HSE_STARTUP_TIMEOUT) \r
- #define HSE_STARTUP_TIMEOUT ((uint16_t)0x0600) /*!< Time out for HSE start up */\r
-#endif /* HSE_STARTUP_TIMEOUT */ \r
-\r
-#if !defined (HSI_VALUE) \r
- #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
-#endif /* HSI_VALUE */ \r
-\r
-/**\r
- * @brief STM32F4XX Standard Peripherals Library version number V1.2.0CR2\r
- */\r
-#define __STM32F4XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */ \r
-#define __STM32F4XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */\r
-#define __STM32F4XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */\r
-#define __STM32F4XX_STDPERIPH_VERSION_RC (0x02) /*!< [7:0] release candidate */ \r
-#define __STM32F4XX_STDPERIPH_VERSION ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\\r
- |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\\r
- |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\\r
- |(__STM32F4XX_STDPERIPH_VERSION_RC))\r
- \r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Configuration_section_for_CMSIS\r
- * @{\r
- */\r
-\r
-/**\r
- * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \r
- */\r
-#define __CM4_REV 0x0001 /*!< Core revision r0p1 */\r
-#define __MPU_PRESENT 1 /*!< STM32F4XX provides an MPU */\r
-#define __NVIC_PRIO_BITS 4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */\r
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */\r
-#define __FPU_PRESENT 1 /*!< FPU present */\r
-\r
-/**\r
- * @brief STM32F4XX Interrupt Number Definition, according to the selected device \r
- * in @ref Library_configuration_section \r
- */\r
-typedef enum IRQn\r
-{\r
-/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */\r
- MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */\r
- BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */\r
- UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */\r
- SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */\r
- DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */\r
- PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */\r
- SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */\r
-/****** STM32 specific Interrupt Numbers **********************************************************************/\r
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */\r
- PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */\r
- TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */\r
- RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */\r
- FLASH_IRQn = 4, /*!< FLASH global Interrupt */\r
- RCC_IRQn = 5, /*!< RCC global Interrupt */\r
- EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */\r
- EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */\r
- EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */\r
- EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */\r
- EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */\r
- DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */\r
- DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */\r
- DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */\r
- DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */\r
- DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */\r
- DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */\r
- DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */\r
- ADC_IRQn = 18, /*!< ADC1, ADC2 and ADC3 global Interrupts */\r
- CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */\r
- CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */\r
- CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */\r
- CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */\r
- EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */\r
- TIM1_BRK_TIM9_IRQn = 24, /*!< TIM1 Break interrupt and TIM9 global interrupt */\r
- TIM1_UP_TIM10_IRQn = 25, /*!< TIM1 Update Interrupt and TIM10 global interrupt */\r
- TIM1_TRG_COM_TIM11_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
- TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */\r
- TIM2_IRQn = 28, /*!< TIM2 global Interrupt */\r
- TIM3_IRQn = 29, /*!< TIM3 global Interrupt */\r
- TIM4_IRQn = 30, /*!< TIM4 global Interrupt */\r
- I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */\r
- I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */\r
- I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */\r
- I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ \r
- SPI1_IRQn = 35, /*!< SPI1 global Interrupt */\r
- SPI2_IRQn = 36, /*!< SPI2 global Interrupt */\r
- USART1_IRQn = 37, /*!< USART1 global Interrupt */\r
- USART2_IRQn = 38, /*!< USART2 global Interrupt */\r
- USART3_IRQn = 39, /*!< USART3 global Interrupt */\r
- EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */\r
- RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */\r
- OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS Wakeup through EXTI line interrupt */ \r
- TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */\r
- TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */\r
- TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
- TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */\r
- DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
- FSMC_IRQn = 48, /*!< FSMC global Interrupt */\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined(STM32F429X)\r
- FMC_IRQn = 48, /*!< FMC global Interrupt */\r
-#endif /* STM32F429X */ \r
-\r
- SDIO_IRQn = 49, /*!< SDIO global Interrupt */\r
- TIM5_IRQn = 50, /*!< TIM5 global Interrupt */\r
- SPI3_IRQn = 51, /*!< SPI3 global Interrupt */\r
- UART4_IRQn = 52, /*!< UART4 global Interrupt */\r
- UART5_IRQn = 53, /*!< UART5 global Interrupt */\r
- TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */\r
- TIM7_IRQn = 55, /*!< TIM7 global interrupt */\r
- DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */\r
- DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */\r
- DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */\r
- DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */\r
- DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */\r
- ETH_IRQn = 61, /*!< Ethernet global Interrupt */\r
- ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */\r
- CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */\r
- CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */\r
- CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */\r
- CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */\r
- OTG_FS_IRQn = 67, /*!< USB OTG FS global Interrupt */\r
- DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */\r
- DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */\r
- DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */\r
- USART6_IRQn = 71, /*!< USART6 global interrupt */\r
- I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */\r
- I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */\r
- OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */\r
- OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */\r
- OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */\r
- OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */\r
- DCMI_IRQn = 78, /*!< DCMI global interrupt */\r
- CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */\r
- HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */\r
-\r
-#if defined(STM32F40XX)\r
- FPU_IRQn = 81 /*!< FPU global interrupt */\r
-#endif /* STM32F40XX */\r
-\r
-#if defined (STM32F427X) \r
- FPU_IRQn = 81, /*!< FPU global interrupt */\r
- UART7_IRQn = 82, /*!< UART7 global interrupt */\r
- UART8_IRQn = 83, /*!< UART8 global interrupt */\r
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
- SPI6_IRQn = 86 /*!< SPI6 global Interrupt */\r
-#endif /* STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
- FPU_IRQn = 81, /*!< FPU global interrupt */\r
- UART7_IRQn = 82, /*!< UART7 global interrupt */\r
- UART8_IRQn = 83, /*!< UART8 global interrupt */\r
- SPI4_IRQn = 84, /*!< SPI4 global Interrupt */\r
- SPI5_IRQn = 85, /*!< SPI5 global Interrupt */\r
- SPI6_IRQn = 86, /*!< SPI6 global Interrupt */\r
- SAI1_IRQn = 87, /*!< SAI1 global Interrupt */\r
- LTDC_IRQn = 88, /*!< LTDC global Interrupt */\r
- LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */\r
- DMA2D_IRQn = 90 /*!< DMA2D global Interrupt */\r
-#endif /* STM32F429X */ \r
-} IRQn_Type;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */\r
-#include "system_stm32f4xx.h"\r
-#include <stdint.h>\r
-\r
-/** @addtogroup Exported_types\r
- * @{\r
- */ \r
-/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
-typedef int32_t s32;\r
-typedef int16_t s16;\r
-typedef int8_t s8;\r
-\r
-typedef const int32_t sc32; /*!< Read Only */\r
-typedef const int16_t sc16; /*!< Read Only */\r
-typedef const int8_t sc8; /*!< Read Only */\r
-\r
-typedef __IO int32_t vs32;\r
-typedef __IO int16_t vs16;\r
-typedef __IO int8_t vs8;\r
-\r
-typedef __I int32_t vsc32; /*!< Read Only */\r
-typedef __I int16_t vsc16; /*!< Read Only */\r
-typedef __I int8_t vsc8; /*!< Read Only */\r
-\r
-typedef uint32_t u32;\r
-typedef uint16_t u16;\r
-typedef uint8_t u8;\r
-\r
-typedef const uint32_t uc32; /*!< Read Only */\r
-typedef const uint16_t uc16; /*!< Read Only */\r
-typedef const uint8_t uc8; /*!< Read Only */\r
-\r
-typedef __IO uint32_t vu32;\r
-typedef __IO uint16_t vu16;\r
-typedef __IO uint8_t vu8;\r
-\r
-typedef __I uint32_t vuc32; /*!< Read Only */\r
-typedef __I uint16_t vuc16; /*!< Read Only */\r
-typedef __I uint8_t vuc8; /*!< Read Only */\r
-\r
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
-\r
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
-\r
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Peripheral_registers_structures\r
- * @{\r
- */ \r
-\r
-/** \r
- * @brief Analog to Digital Converter \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */\r
- __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */ \r
- __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */\r
- __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */\r
- __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */\r
- __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
- __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
- __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
- __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
- __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x24 */\r
- __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x28 */\r
- __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x2C */\r
- __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x30 */\r
- __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x34 */\r
- __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x38*/\r
- __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x3C */\r
- __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x40 */\r
- __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x44 */\r
- __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x48 */\r
- __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x4C */\r
-} ADC_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1 base address + 0x300 */\r
- __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */\r
- __IO uint32_t CDR; /*!< ADC common regular data register for dual\r
- AND triple modes, Address offset: ADC1 base address + 0x308 */\r
-} ADC_Common_TypeDef;\r
-\r
-\r
-/** \r
- * @brief Controller Area Network TxMailBox \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */\r
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
-} CAN_TxMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FIFOMailBox \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */\r
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
-} CAN_FIFOMailBox_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network FilterRegister \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
-} CAN_FilterRegister_TypeDef;\r
-\r
-/** \r
- * @brief Controller Area Network \r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */\r
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */\r
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */\r
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */\r
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */\r
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */\r
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */\r
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */\r
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */\r
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */\r
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */\r
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */\r
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */\r
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */\r
- uint32_t RESERVED2; /*!< Reserved, 0x208 */\r
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */\r
- uint32_t RESERVED3; /*!< Reserved, 0x210 */\r
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */\r
- uint32_t RESERVED4; /*!< Reserved, 0x218 */\r
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */\r
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */ \r
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */\r
-} CAN_TypeDef;\r
-\r
-/** \r
- * @brief CRC calculation unit \r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */\r
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */\r
- uint8_t RESERVED0; /*!< Reserved, 0x05 */\r
- uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */\r
-} CRC_TypeDef;\r
-\r
-/** \r
- * @brief Digital to Analog Converter\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */\r
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */\r
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */\r
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */\r
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */\r
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */\r
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */\r
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */\r
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */\r
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */\r
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */\r
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */\r
-} DAC_TypeDef;\r
-\r
-/** \r
- * @brief Debug MCU\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */\r
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */\r
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */\r
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */\r
-}DBGMCU_TypeDef;\r
-\r
-/** \r
- * @brief DCMI\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */\r
- __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */\r
- __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */\r
- __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */\r
- __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */\r
- __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */\r
- __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */\r
- __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
- __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */\r
- __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */\r
- __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */\r
-} DCMI_TypeDef;\r
-\r
-/** \r
- * @brief DMA Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< DMA stream x configuration register */\r
- __IO uint32_t NDTR; /*!< DMA stream x number of data register */\r
- __IO uint32_t PAR; /*!< DMA stream x peripheral address register */\r
- __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */\r
- __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */\r
- __IO uint32_t FCR; /*!< DMA stream x FIFO control register */\r
-} DMA_Stream_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */\r
- __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */\r
- __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */\r
- __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
-} DMA_TypeDef;\r
-\r
-#if defined (STM32F429X) \r
-/** \r
- * @brief DMA2D Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */\r
- __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */\r
- __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */\r
- __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */\r
- __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */\r
- __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */\r
- __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */\r
- __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */\r
- __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */\r
- __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */\r
- __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */\r
- __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */\r
- __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */\r
- __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */\r
- __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */\r
- __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */\r
- __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */\r
- __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */\r
- __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */\r
- __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */\r
- uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
- __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */\r
- __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */\r
-} DMA2D_TypeDef;\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief Ethernet MAC\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t MACCR;\r
- __IO uint32_t MACFFR;\r
- __IO uint32_t MACHTHR;\r
- __IO uint32_t MACHTLR;\r
- __IO uint32_t MACMIIAR;\r
- __IO uint32_t MACMIIDR;\r
- __IO uint32_t MACFCR;\r
- __IO uint32_t MACVLANTR; /* 8 */\r
- uint32_t RESERVED0[2];\r
- __IO uint32_t MACRWUFFR; /* 11 */\r
- __IO uint32_t MACPMTCSR;\r
- uint32_t RESERVED1[2];\r
- __IO uint32_t MACSR; /* 15 */\r
- __IO uint32_t MACIMR;\r
- __IO uint32_t MACA0HR;\r
- __IO uint32_t MACA0LR;\r
- __IO uint32_t MACA1HR;\r
- __IO uint32_t MACA1LR;\r
- __IO uint32_t MACA2HR;\r
- __IO uint32_t MACA2LR;\r
- __IO uint32_t MACA3HR;\r
- __IO uint32_t MACA3LR; /* 24 */\r
- uint32_t RESERVED2[40];\r
- __IO uint32_t MMCCR; /* 65 */\r
- __IO uint32_t MMCRIR;\r
- __IO uint32_t MMCTIR;\r
- __IO uint32_t MMCRIMR;\r
- __IO uint32_t MMCTIMR; /* 69 */\r
- uint32_t RESERVED3[14];\r
- __IO uint32_t MMCTGFSCCR; /* 84 */\r
- __IO uint32_t MMCTGFMSCCR;\r
- uint32_t RESERVED4[5];\r
- __IO uint32_t MMCTGFCR;\r
- uint32_t RESERVED5[10];\r
- __IO uint32_t MMCRFCECR;\r
- __IO uint32_t MMCRFAECR;\r
- uint32_t RESERVED6[10];\r
- __IO uint32_t MMCRGUFCR;\r
- uint32_t RESERVED7[334];\r
- __IO uint32_t PTPTSCR;\r
- __IO uint32_t PTPSSIR;\r
- __IO uint32_t PTPTSHR;\r
- __IO uint32_t PTPTSLR;\r
- __IO uint32_t PTPTSHUR;\r
- __IO uint32_t PTPTSLUR;\r
- __IO uint32_t PTPTSAR;\r
- __IO uint32_t PTPTTHR;\r
- __IO uint32_t PTPTTLR;\r
- __IO uint32_t RESERVED8;\r
- __IO uint32_t PTPTSSR;\r
- uint32_t RESERVED9[565];\r
- __IO uint32_t DMABMR;\r
- __IO uint32_t DMATPDR;\r
- __IO uint32_t DMARPDR;\r
- __IO uint32_t DMARDLAR;\r
- __IO uint32_t DMATDLAR;\r
- __IO uint32_t DMASR;\r
- __IO uint32_t DMAOMR;\r
- __IO uint32_t DMAIER;\r
- __IO uint32_t DMAMFBOCR;\r
- __IO uint32_t DMARSWTR;\r
- uint32_t RESERVED10[8];\r
- __IO uint32_t DMACHTDR;\r
- __IO uint32_t DMACHRDR;\r
- __IO uint32_t DMACHTBAR;\r
- __IO uint32_t DMACHRBAR;\r
-} ETH_TypeDef;\r
-\r
-/** \r
- * @brief External Interrupt/Event Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */\r
- __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */\r
- __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */\r
- __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
- __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */\r
- __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */\r
-} EXTI_TypeDef;\r
-\r
-/** \r
- * @brief FLASH Registers\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */\r
- __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */\r
- __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */\r
- __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */\r
- __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */\r
- __IO uint32_t OPTCR; /*!< FLASH option control register , Address offset: 0x14 */\r
- __IO uint32_t OPTCR1; /*!< FLASH option control register 1, Address offset: 0x18 */\r
-} FLASH_TypeDef;\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
-/** \r
- * @brief Flexible Static Memory Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
-} FSMC_Bank1_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank1E\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
-} FSMC_Bank1E_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank2\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
- uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
-} FSMC_Bank2_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank3\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
- uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
-} FSMC_Bank3_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Static Memory Controller Bank4\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r
-} FSMC_Bank4_TypeDef; \r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-/** \r
- * @brief Flexible Memory Controller\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ \r
-} FMC_Bank1_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Memory Controller Bank1E\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
-} FMC_Bank1E_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Memory Controller Bank2\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */\r
- __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */\r
- __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */\r
- __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
- uint32_t RESERVED0; /*!< Reserved, 0x70 */\r
- __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */\r
-} FMC_Bank2_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Memory Controller Bank3\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR3; /*!< NAND Flash control register 3, Address offset: 0x80 */\r
- __IO uint32_t SR3; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */\r
- __IO uint32_t PMEM3; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */\r
- __IO uint32_t PATT3; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
- uint32_t RESERVED0; /*!< Reserved, 0x90 */\r
- __IO uint32_t ECCR3; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */\r
-} FMC_Bank3_TypeDef;\r
-\r
-/** \r
- * @brief Flexible Memory Controller Bank4\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t PCR4; /*!< PC Card control register 4, Address offset: 0xA0 */\r
- __IO uint32_t SR4; /*!< PC Card FIFO status and interrupt register 4, Address offset: 0xA4 */\r
- __IO uint32_t PMEM4; /*!< PC Card Common memory space timing register 4, Address offset: 0xA8 */\r
- __IO uint32_t PATT4; /*!< PC Card Attribute memory space timing register 4, Address offset: 0xAC */\r
- __IO uint32_t PIO4; /*!< PC Card I/O space timing register 4, Address offset: 0xB0 */\r
-} FMC_Bank4_TypeDef; \r
-\r
-/** \r
- * @brief Flexible Memory Controller Bank5_6\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */\r
- __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */\r
- __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */\r
- __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */\r
- __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */\r
-} FMC_Bank5_6_TypeDef; \r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief General Purpose I/O\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */\r
- __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */\r
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */\r
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */\r
- __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */\r
- __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */\r
- __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low register, Address offset: 0x18 */\r
- __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high register, Address offset: 0x1A */\r
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */\r
- __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */\r
-} GPIO_TypeDef;\r
-\r
-/** \r
- * @brief System configuration controller\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */\r
- __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */\r
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
- uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */ \r
- __IO uint32_t CMPCR; /*!< SYSCFG Compensation cell control register, Address offset: 0x20 */\r
-} SYSCFG_TypeDef;\r
-\r
-/** \r
- * @brief Inter-integrated Circuit Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */\r
- uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
- __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */\r
- uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
- __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */\r
- uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
- __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */\r
- uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
- __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */\r
- uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
- __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */\r
- uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
- __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */\r
- uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
- __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */\r
- uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
- __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */\r
- uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
- __IO uint16_t FLTR; /*!< I2C FLTR register, Address offset: 0x24 */\r
- uint16_t RESERVED9; /*!< Reserved, 0x26 */\r
-} I2C_TypeDef;\r
-\r
-/** \r
- * @brief Independent WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */\r
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */\r
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */\r
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */\r
-} IWDG_TypeDef;\r
-\r
-#if defined (STM32F429X)\r
-/** \r
- * @brief LCD-TFT Display Controller\r
- */\r
- \r
-typedef struct\r
-{\r
- uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */\r
- __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */\r
- __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */\r
- __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */\r
- __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */\r
- __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */\r
- uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */\r
- __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */\r
- uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */\r
- __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */\r
- uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */\r
- __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */\r
- __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */\r
- __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */\r
- __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
- __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */\r
- __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */\r
-} LTDC_TypeDef; \r
-\r
-/** \r
- * @brief LCD-TFT Display layer x Controller\r
- */\r
- \r
-typedef struct\r
-{ \r
- __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */\r
- __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
- __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */\r
- __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */\r
- __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */\r
- __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */\r
- __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */\r
- __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */\r
- uint32_t RESERVED0[2]; /*!< Reserved */\r
- __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */\r
- __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */\r
- __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */\r
- uint32_t RESERVED1[3]; /*!< Reserved */\r
- __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */\r
-\r
-} LTDC_Layer_TypeDef;\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief Power Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */\r
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */\r
-} PWR_TypeDef;\r
-\r
-/** \r
- * @brief Reset and Clock Control\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */\r
- __IO uint32_t PLLCFGR; /*!< RCC PLL configuration register, Address offset: 0x04 */\r
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */\r
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x0C */\r
- __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x10 */\r
- __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x14 */\r
- __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x18 */\r
- uint32_t RESERVED0; /*!< Reserved, 0x1C */\r
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x20 */\r
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */\r
- uint32_t RESERVED1[2]; /*!< Reserved, 0x28-0x2C */\r
- __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x30 */\r
- __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x34 */\r
- __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x38 */\r
- uint32_t RESERVED2; /*!< Reserved, 0x3C */\r
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 */\r
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 */\r
- uint32_t RESERVED3[2]; /*!< Reserved, 0x48-0x4C */\r
- __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
- __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
- __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
- uint32_t RESERVED4; /*!< Reserved, 0x5C */\r
- __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
- __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
- uint32_t RESERVED5[2]; /*!< Reserved, 0x68-0x6C */\r
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x70 */\r
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */\r
- uint32_t RESERVED6[2]; /*!< Reserved, 0x78-0x7C */\r
- __IO uint32_t SSCGR; /*!< RCC spread spectrum clock generation register, Address offset: 0x80 */\r
- __IO uint32_t PLLI2SCFGR; /*!< RCC PLLI2S configuration register, Address offset: 0x84 */\r
-\r
-#if defined (STM32F427X) \r
- uint32_t RESERVED7; /*!< Reserved, 0x88 */\r
- __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */\r
-#endif /* STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
- __IO uint32_t PLLSAICFGR; /*!< RCC PLLSAI configuration register, Address offset: 0x88 */\r
- __IO uint32_t DCKCFGR; /*!< RCC Dedicated Clocks configuration register, Address offset: 0x8C */\r
-#endif /* STM32F429X */\r
-\r
-} RCC_TypeDef;\r
-\r
-/** \r
- * @brief Real-Time Clock\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */\r
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */\r
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */\r
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */\r
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */\r
- __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */\r
- __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */\r
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */\r
- __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */\r
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */\r
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */\r
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */\r
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */\r
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */\r
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */\r
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */\r
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
- __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register, Address offset: 0x44 */\r
- __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register, Address offset: 0x48 */\r
- uint32_t RESERVED7; /*!< Reserved, 0x4C */\r
- __IO uint32_t BKP0R; /*!< RTC backup register 1, Address offset: 0x50 */\r
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */\r
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */\r
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */\r
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */\r
- __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */\r
- __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */\r
- __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */\r
- __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */\r
- __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */\r
- __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */\r
- __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */\r
- __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */\r
- __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */\r
- __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */\r
- __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */\r
- __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */\r
- __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */\r
- __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */\r
- __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */\r
-} RTC_TypeDef;\r
-\r
-#if defined (STM32F429X)\r
-/** \r
- * @brief Serial Audio Interface\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */\r
-} SAI_TypeDef;\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */\r
- __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */\r
- __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
- __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */\r
- __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */\r
- __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */\r
- __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */\r
- __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */\r
-} SAI_Block_TypeDef;\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief SD host Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */\r
- __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */\r
- __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */\r
- __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */\r
- __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */\r
- __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */\r
- __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */\r
- __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */\r
- __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */\r
- __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */\r
- __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */\r
- __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */\r
- __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */\r
- __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */\r
- __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */\r
- __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */\r
- uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */\r
- __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */\r
- uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */\r
- __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */\r
-} SDIO_TypeDef;\r
-\r
-/** \r
- * @brief Serial Peripheral Interface\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */\r
- uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
- __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */\r
- uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
- __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */\r
- uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */\r
- uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
- uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
- __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */\r
- uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
- __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */\r
- uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */\r
- uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */\r
- uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
-} SPI_TypeDef;\r
-\r
-/** \r
- * @brief TIM\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */\r
- uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */\r
- uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
- __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */\r
- uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */\r
- uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */\r
- uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */\r
- uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
- uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
- uint16_t RESERVED7; /*!< Reserved, 0x1E */\r
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
- uint16_t RESERVED8; /*!< Reserved, 0x22 */\r
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */\r
- __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */\r
- uint16_t RESERVED9; /*!< Reserved, 0x2A */\r
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */\r
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */\r
- uint16_t RESERVED10; /*!< Reserved, 0x32 */\r
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */\r
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */\r
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */\r
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */\r
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */\r
- uint16_t RESERVED11; /*!< Reserved, 0x46 */\r
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */\r
- uint16_t RESERVED12; /*!< Reserved, 0x4A */\r
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */\r
- uint16_t RESERVED13; /*!< Reserved, 0x4E */\r
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */\r
- uint16_t RESERVED14; /*!< Reserved, 0x52 */\r
-} TIM_TypeDef;\r
-\r
-/** \r
- * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
- */\r
- \r
-typedef struct\r
-{\r
- __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */\r
- uint16_t RESERVED0; /*!< Reserved, 0x02 */\r
- __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */\r
- uint16_t RESERVED1; /*!< Reserved, 0x06 */\r
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */\r
- uint16_t RESERVED2; /*!< Reserved, 0x0A */\r
- __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */\r
- uint16_t RESERVED3; /*!< Reserved, 0x0E */\r
- __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */\r
- uint16_t RESERVED4; /*!< Reserved, 0x12 */\r
- __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */\r
- uint16_t RESERVED5; /*!< Reserved, 0x16 */\r
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
- uint16_t RESERVED6; /*!< Reserved, 0x1A */\r
-} USART_TypeDef;\r
-\r
-/** \r
- * @brief Window WATCHDOG\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */\r
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */\r
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */\r
-} WWDG_TypeDef;\r
-\r
-/** \r
- * @brief Crypto Processor\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */\r
- __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */\r
- __IO uint32_t DR; /*!< CRYP data input register, Address offset: 0x08 */\r
- __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */\r
- __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */\r
- __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */\r
- __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */\r
- __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */\r
- __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */\r
- __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */\r
- __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */\r
- __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */\r
- __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */\r
- __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */\r
- __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */\r
- __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */\r
- __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */\r
- __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */\r
- __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */\r
- __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */\r
- __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */\r
- __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */\r
- __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */\r
- __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */\r
- __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */\r
- __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */\r
- __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */\r
- __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */\r
- __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */\r
- __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */\r
- __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */\r
- __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */\r
- __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */\r
- __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */\r
- __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */\r
- __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */\r
-} CRYP_TypeDef;\r
-\r
-/** \r
- * @brief HASH\r
- */\r
- \r
-typedef struct \r
-{\r
- __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */\r
- __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */\r
- __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */\r
- __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */\r
- __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */\r
- __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */\r
- uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */\r
- __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */\r
-} HASH_TypeDef;\r
-\r
-/** \r
- * @brief HASH_DIGEST\r
- */\r
- \r
-typedef struct \r
-{\r
- __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ \r
-} HASH_DIGEST_TypeDef;\r
-\r
-/** \r
- * @brief RNG\r
- */\r
- \r
-typedef struct \r
-{\r
- __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */\r
- __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */\r
- __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */\r
-} RNG_TypeDef;\r
-\r
-/** \r
- * @brief USB OTG FS\r
- */\r
-#pragma anon_unions\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t GOTGCTL;\r
- __IO uint32_t GOTGINT;\r
- __IO uint32_t GAHBCFG;\r
- __IO uint32_t GUSBCFG;\r
- __IO uint32_t GRSTCTL;\r
- __IO uint32_t GINTSTS;\r
- __IO uint32_t GINTMSK;\r
- __IO uint32_t GRXSTSR;\r
- __IO uint32_t GRXSTSP;\r
- __IO uint32_t GRXFSIZ;\r
- union {\r
- __IO uint32_t HNPTXFSIZ;\r
- __IO uint32_t DIEPTXF0;\r
- };\r
- __IO uint32_t HNPTXSTS;\r
- __IO uint32_t GI2CCTL;\r
- uint32_t RESERVED0;\r
- __IO uint32_t GCCFG;\r
- __IO uint32_t CID;\r
- uint32_t RESERVED1[48];\r
- __IO uint32_t HPTXFSIZ;\r
- __IO uint32_t DIEPTXF1;\r
- __IO uint32_t DIEPTXF2;\r
- __IO uint32_t DIEPTXF3;\r
- __IO uint32_t DIEPTXF4;\r
- __IO uint32_t DIEPTXF5;\r
- __IO uint32_t DIEPTXF6;\r
- __IO uint32_t DIEPTXF7;\r
- __IO uint32_t DIEPTXF8;\r
- __IO uint32_t DIEPTXF9;\r
- __IO uint32_t DIEPTXF10;\r
- __IO uint32_t DIEPTXF11;\r
- __IO uint32_t DIEPTXF12;\r
- __IO uint32_t DIEPTXF13;\r
- __IO uint32_t DIEPTXF14;\r
- __IO uint32_t DIEPTXF15;\r
- uint32_t RESERVED2[176];\r
- __IO uint32_t HCFG;\r
- __IO uint32_t HFIR;\r
- __IO uint32_t HFNUM;\r
- uint32_t RESERVED3;\r
- __IO uint32_t HPTXSTS;\r
- __IO uint32_t HAINT;\r
- __IO uint32_t HAINTMSK;\r
- uint32_t RESERVED4[9];\r
- __IO uint32_t HPRT;\r
- uint32_t RESERVED5[47];\r
- __IO uint32_t HCCHAR0;\r
- uint32_t RESERVED6;\r
- __IO uint32_t HCINT0;\r
- __IO uint32_t HCINTMSK0;\r
- __IO uint32_t HCTSIZ0;\r
- uint32_t RESERVED7[3];\r
- __IO uint32_t HCCHAR1;\r
- uint32_t RESERVED8;\r
- __IO uint32_t HCINT1;\r
- __IO uint32_t HCINTMSK1;\r
- __IO uint32_t HCTSIZ1;\r
- uint32_t RESERVED9[3];\r
- __IO uint32_t HCCHAR2;\r
- uint32_t RESERVED10;\r
- __IO uint32_t HCINT2;\r
- __IO uint32_t HCINTMSK2;\r
- __IO uint32_t HCTSIZ2;\r
- uint32_t RESERVED11[3];\r
- __IO uint32_t HCCHR3;\r
- uint32_t RESERVED12;\r
- __IO uint32_t HCINT3;\r
- __IO uint32_t HCINTMSK3;\r
- __IO uint32_t HCTSIZ3;\r
- uint32_t RESERVED13[3];\r
- __IO uint32_t HCCHR4;\r
- uint32_t RESERVED14;\r
- __IO uint32_t HCINT4;\r
- __IO uint32_t HCINTMSK4;\r
- __IO uint32_t HCTSIZ4;\r
- uint32_t RESERVED15[3];\r
- __IO uint32_t HCCHR5;\r
- uint32_t RESERVED16;\r
- __IO uint32_t HCINT5;\r
- __IO uint32_t HCINTMSK5;\r
- __IO uint32_t HCTSIZ5;\r
- uint32_t RESERVED17[3];\r
- __IO uint32_t HCCHR6;\r
- uint32_t RESERVED18;\r
- __IO uint32_t HCINT6;\r
- __IO uint32_t HCINTMSK6;\r
- __IO uint32_t HCTSIZ6;\r
- uint32_t RESERVED19[3];\r
- __IO uint32_t HCCHR7;\r
- uint32_t RESERVED20;\r
- __IO uint32_t HCINT7;\r
- __IO uint32_t HCINTMSK7;\r
- __IO uint32_t HCTSIZ7;\r
- uint32_t RESERVED21[3];\r
- __IO uint32_t HCCHR8;\r
- uint32_t RESERVED22;\r
- __IO uint32_t HCINT8;\r
- __IO uint32_t HCINTMSK8;\r
- __IO uint32_t HCTSIZ8;\r
- uint32_t RESERVED23[3];\r
- __IO uint32_t HCCHR9;\r
- uint32_t RESERVED24;\r
- __IO uint32_t HCINT9;\r
- __IO uint32_t HCINTMSK9;\r
- __IO uint32_t HCTSIZ9;\r
- uint32_t RESERVED25[3];\r
- __IO uint32_t HCCHR10;\r
- uint32_t RESERVED26;\r
- __IO uint32_t HCINT10;\r
- __IO uint32_t HCINTMSK10;\r
- __IO uint32_t HCTSIZ10;\r
- uint32_t RESERVED27[3];\r
- __IO uint32_t HCCHR11;\r
- uint32_t RESERVED28;\r
- __IO uint32_t HCINT11;\r
- __IO uint32_t HCINTMSK11;\r
- __IO uint32_t HCTSIZ11;\r
- uint32_t RESERVED29[3];\r
- __IO uint32_t HCCHR12;\r
- uint32_t RESERVED30;\r
- __IO uint32_t HCINT12;\r
- __IO uint32_t HCINTMSK12;\r
- __IO uint32_t HCTSIZ12;\r
- uint32_t RESERVED31[3];\r
- __IO uint32_t HCCHR13;\r
- uint32_t RESERVED32;\r
- __IO uint32_t HCINT13;\r
- __IO uint32_t HCINTMSK13;\r
- __IO uint32_t HCTSIZ13;\r
- uint32_t RESERVED33[3];\r
- __IO uint32_t HCCHR14;\r
- uint32_t RESERVED34;\r
- __IO uint32_t HCINT14;\r
- __IO uint32_t HCINTMSK14;\r
- __IO uint32_t HCTSIZ14;\r
- uint32_t RESERVED35[3];\r
- __IO uint32_t HCCHR15;\r
- uint32_t RESERVED36;\r
- __IO uint32_t HCINT15;\r
- __IO uint32_t HCINTMSK15;\r
- __IO uint32_t HCTSIZ15;\r
- uint32_t RESERVED37[3];\r
- uint32_t RESERVED38[64];\r
- __IO uint32_t DCFG;\r
- __IO uint32_t DCTL;\r
- __IO uint32_t DSTS;\r
- uint32_t RESERVED39;\r
- __IO uint32_t DIEPMSK;\r
- __IO uint32_t DOEPMSK;\r
- __IO uint32_t DAINT;\r
- __IO uint32_t DAINTMSK;\r
- uint32_t RESERVED40[2];\r
- __IO uint32_t DVBUSDIS;\r
- __IO uint32_t DVBUSPULSE;\r
- uint32_t RESERVED41;\r
- __IO uint32_t DIEPEMPMSK;\r
- uint32_t RESERVED42[50];\r
- __IO uint32_t DIEPCTL0;\r
- uint32_t RESERVED43;\r
- __IO uint32_t DIEPINT0;\r
- uint32_t RESERVED44;\r
- __IO uint32_t DIEPTSIZ0;\r
- uint32_t RESERVED45;\r
- __IO uint32_t DTXFSTS0;\r
- uint32_t RESERVED46;\r
- __IO uint32_t DIEPCTL1;\r
- uint32_t RESERVED47;\r
- __IO uint32_t DIEPINT1;\r
- uint32_t RESERVED48;\r
- __IO uint32_t DIEPTSIZ1;\r
- uint32_t RESERVED49;\r
- __IO uint32_t DTXFSTS1;\r
- uint32_t RESERVED50;\r
- __IO uint32_t DIEPCTL2;\r
- uint32_t RESERVED51;\r
- __IO uint32_t DIEPINT2;\r
- uint32_t RESERVED52;\r
- __IO uint32_t DIEPTSIZ2;\r
- uint32_t RESERVED53;\r
- __IO uint32_t DTXFSTS2;\r
- uint32_t RESERVED54;\r
- __IO uint32_t DIEPCTL3;\r
- uint32_t RESERVED55;\r
- __IO uint32_t DIEPINT3;\r
- uint32_t RESERVED56;\r
- __IO uint32_t DIEPTSIZ3;\r
- uint32_t RESERVED57;\r
- __IO uint32_t DTXFSTS3;\r
- uint32_t RESERVED58;\r
- __IO uint32_t DIEPCTL4;\r
- uint32_t RESERVED59;\r
- __IO uint32_t DIEPINT4;\r
- uint32_t RESERVED60;\r
- __IO uint32_t DIEPTSIZ4;\r
- uint32_t RESERVED61;\r
- __IO uint32_t DTXFSTS4;\r
- uint32_t RESERVED62;\r
- __IO uint32_t DIEPCTL5;\r
- uint32_t RESERVED63;\r
- __IO uint32_t DIEPINT5;\r
- uint32_t RESERVED64;\r
- __IO uint32_t DIEPTSIZ5;\r
- uint32_t RESERVED65[3];\r
- __IO uint32_t DIEPCTL6;\r
- uint32_t RESERVED66;\r
- __IO uint32_t DIEPINT6;\r
- uint32_t RESERVED67;\r
- __IO uint32_t DIEPTSIZ6;\r
- uint32_t RESERVED68[3];\r
- __IO uint32_t DIEPCTL7;\r
- uint32_t RESERVED69;\r
- __IO uint32_t DIEPINT7;\r
- uint32_t RESERVED70;\r
- __IO uint32_t DIEPTSIZ7;\r
- uint32_t RESERVED71[3];\r
- __IO uint32_t DIEPCTL8;\r
- uint32_t RESERVED72;\r
- __IO uint32_t DIEPINT8;\r
- uint32_t RESERVED73;\r
- __IO uint32_t DIEPTSIZ8;\r
- uint32_t RESERVED74[3];\r
- __IO uint32_t DIEPCTL9;\r
- uint32_t RESERVED75;\r
- __IO uint32_t DIEPINT9;\r
- uint32_t RESERVED76;\r
- __IO uint32_t DIEPTSIZ9;\r
- uint32_t RESERVED77[3];\r
- __IO uint32_t DIEPCTL10;\r
- uint32_t RESERVED78;\r
- __IO uint32_t DIEPINT10;\r
- uint32_t RESERVED79;\r
- __IO uint32_t DIEPTSIZ10;\r
- uint32_t RESERVED80[3];\r
- __IO uint32_t DIEPCTL11;\r
- uint32_t RESERVED81;\r
- __IO uint32_t DIEPINT11;\r
- uint32_t RESERVED82;\r
- __IO uint32_t DIEPTSIZ11;\r
- uint32_t RESERVED83[3];\r
- __IO uint32_t DIEPCTL12;\r
- uint32_t RESERVED84;\r
- __IO uint32_t DIEPINT12;\r
- uint32_t RESERVED85;\r
- __IO uint32_t DIEPTSIZ86;\r
- uint32_t RESERVED86[3];\r
- __IO uint32_t DIEPCTL13;\r
- uint32_t RESERVED87;\r
- __IO uint32_t DIEPINT13;\r
- uint32_t RESERVED88;\r
- __IO uint32_t DIEPTSIZ13;\r
- uint32_t RESERVED89[3];\r
- __IO uint32_t DIEPCTL14;\r
- uint32_t RESERVED90;\r
- __IO uint32_t DIEPINT14;\r
- uint32_t RESERVED91;\r
- __IO uint32_t DIEPTSIZ14;\r
- uint32_t RESERVED92[3];\r
- __IO uint32_t DIEPCTL15;\r
- uint32_t RESERVED93;\r
- __IO uint32_t DIEPINT15;\r
- uint32_t RESERVED94;\r
- __IO uint32_t DIEPTSIZ15;\r
- uint32_t RESERVED95[3];\r
- __IO uint32_t DOEPCTL0;\r
- uint32_t RESERVED96;\r
- __IO uint32_t DOEPINT0;\r
- uint32_t RESERVED97;\r
- __IO uint32_t DOEPTSIZ0;\r
- uint32_t RESERVED98[3];\r
- __IO uint32_t DOEPCTL1;\r
- uint32_t RESERVED99;\r
- __IO uint32_t DOEPINT1;\r
- uint32_t RESERVED100;\r
- __IO uint32_t DOEPTSIZ1;\r
- uint32_t RESERVED101[3];\r
- __IO uint32_t DOEPCTL2;\r
- uint32_t RESERVED102;\r
- __IO uint32_t DOEPINT2;\r
- uint32_t RESERVED103;\r
- __IO uint32_t DOEPTSIZ2;\r
- uint32_t RESERVED104[3];\r
- __IO uint32_t DOEPCTL3;\r
- uint32_t RESERVED105;\r
- __IO uint32_t DOEPINT3;\r
- uint32_t RESERVED106;\r
- __IO uint32_t DOEPTSIZ3;\r
- uint32_t RESERVED107[3];\r
- __IO uint32_t DOEPCTL4;\r
- uint32_t RESERVED108;\r
- __IO uint32_t DOEPINT4;\r
- uint32_t RESERVED109;\r
- __IO uint32_t DOEPTSIZ4;\r
- uint32_t RESERVED110[3];\r
- __IO uint32_t DOEPCTL5;\r
- uint32_t RESERVED111;\r
- __IO uint32_t DOEPINT5;\r
- uint32_t RESERVED112;\r
- __IO uint32_t DOEPTSIZ5;\r
- uint32_t RESERVED113[3];\r
- __IO uint32_t DOEPCTL6;\r
- uint32_t RESERVED114;\r
- __IO uint32_t DOEPINT6;\r
- uint32_t RESERVED115;\r
- __IO uint32_t DOEPTSIZ6;\r
- uint32_t RESERVED116[3];\r
- __IO uint32_t DOEPCTL7;\r
- uint32_t RESERVED117;\r
- __IO uint32_t DOEPINT7;\r
- uint32_t RESERVED118;\r
- __IO uint32_t DOEPTSIZ7;\r
- uint32_t RESERVED119[3];\r
- __IO uint32_t DOEPCTL8;\r
- uint32_t RESERVED120;\r
- __IO uint32_t DOEPINT8;\r
- uint32_t RESERVED121;\r
- __IO uint32_t DOEPTSIZ8;\r
- uint32_t RESERVED122[3];\r
- __IO uint32_t DOEPCTL9;\r
- uint32_t RESERVED123;\r
- __IO uint32_t DOEPINT9;\r
- uint32_t RESERVED124;\r
- __IO uint32_t DOEPTSIZ9;\r
- uint32_t RESERVED125[3];\r
- __IO uint32_t DOEPCTL10;\r
- uint32_t RESERVED126;\r
- __IO uint32_t DOEPINT10;\r
- uint32_t RESERVED127;\r
- __IO uint32_t DOEPTSIZ10;\r
- uint32_t RESERVED128[3];\r
- __IO uint32_t DOEPCTL11;\r
- uint32_t RESERVED129;\r
- __IO uint32_t DOEPINT11;\r
- uint32_t RESERVED130;\r
- __IO uint32_t DOEPTSIZ11;\r
- uint32_t RESERVED131[3];\r
- __IO uint32_t DOEPCTL12;\r
- uint32_t RESERVED132;\r
- __IO uint32_t DOEPINT12;\r
- uint32_t RESERVED133;\r
- __IO uint32_t DOEPTSIZ12;\r
- uint32_t RESERVED134[3];\r
- __IO uint32_t DOEPCTL13;\r
- uint32_t RESERVED135;\r
- __IO uint32_t DOEPINT13;\r
- uint32_t RESERVED136;\r
- __IO uint32_t DOEPTSIZ13;\r
- uint32_t RESERVED137[3];\r
- __IO uint32_t DOEPCTL14;\r
- uint32_t RESERVED138;\r
- __IO uint32_t DOEPINT14;\r
- uint32_t RESERVED139;\r
- __IO uint32_t DOEPTSIZ14;\r
- uint32_t RESERVED140[3];\r
- __IO uint32_t DOEPCTL15;\r
- uint32_t RESERVED141;\r
- __IO uint32_t DOEPINT15;\r
- uint32_t RESERVED142;\r
- __IO uint32_t DOEPTSIZ15;\r
- uint32_t RESERVED143[3];\r
- uint32_t RESERVED144[64];\r
- __IO uint32_t PCGCCTL;\r
-} OTG_FS_TypeDef;\r
-\r
-/** \r
- * @brief USB OTG HS\r
- */\r
-\r
-typedef struct\r
-{\r
- __IO uint32_t GOTGCTL;\r
- __IO uint32_t GOTGINT;\r
- __IO uint32_t GAHBCFG;\r
- __IO uint32_t GUSBCFG;\r
- __IO uint32_t GRSTCTL;\r
- __IO uint32_t GINTSTS;\r
- __IO uint32_t GINTMSK;\r
- __IO uint32_t GRXSTSR;\r
- __IO uint32_t GRXSTSP;\r
- __IO uint32_t GRXFSIZ;\r
- union {\r
- __IO uint32_t GNPTXFSIZ;\r
- __IO uint32_t TX0FSIZ;\r
- };\r
- __IO uint32_t GNPTXSTS;\r
- __IO uint32_t GI2CCTL;\r
- uint32_t RESERVED0;\r
- __IO uint32_t GCCFG;\r
- __IO uint32_t CID;\r
- uint32_t RESERVED1[48];\r
- __IO uint32_t HPTXFSIZ;\r
- __IO uint32_t DIEPTXF1;\r
- __IO uint32_t DIEPTXF2;\r
- __IO uint32_t DIEPTXF3;\r
- __IO uint32_t DIEPTXF4;\r
- __IO uint32_t DIEPTXF5;\r
- __IO uint32_t DIEPTXF6;\r
- __IO uint32_t DIEPTXF7;\r
- __IO uint32_t DIEPTXF8;\r
- __IO uint32_t DIEPTXF9;\r
- __IO uint32_t DIEPTXF10;\r
- __IO uint32_t DIEPTXF11;\r
- __IO uint32_t DIEPTXF12;\r
- __IO uint32_t DIEPTXF13;\r
- __IO uint32_t DIEPTXF14;\r
- __IO uint32_t DIEPTXF15;\r
- uint32_t RESERVED2[176];\r
- __IO uint32_t HCFG;\r
- __IO uint32_t HFIR;\r
- __IO uint32_t HFNUM;\r
- uint32_t RESERVED3;\r
- __IO uint32_t HPTXSTS;\r
- __IO uint32_t HAINT;\r
- __IO uint32_t HAINTMSK;\r
- uint32_t RESERVED4[9];\r
- __IO uint32_t HPRT;\r
- uint32_t RESERVED5[47];\r
- __IO uint32_t HCCHAR0;\r
- __IO uint32_t HCSPLT0;\r
- __IO uint32_t HCINT0;\r
- __IO uint32_t HCINTMSK0;\r
- __IO uint32_t HCTSIZ0;\r
- __IO uint32_t HCDMA0;\r
- uint32_t RESERVED6[2];\r
- __IO uint32_t HCCHAR1;\r
- __IO uint32_t HCSPLT1;\r
- __IO uint32_t HCINT1;\r
- __IO uint32_t HCINTMSK1;\r
- __IO uint32_t HCTSIZ1;\r
- __IO uint32_t HCDMA1;\r
- uint32_t RESERVED7[2];\r
- __IO uint32_t HCCHAR2;\r
- __IO uint32_t HCSPLT2;\r
- __IO uint32_t HCINT2;\r
- __IO uint32_t HCINTMSK2;\r
- __IO uint32_t HCTSIZ2;\r
- __IO uint32_t HCDMA2;\r
- uint32_t RESERVED8[2];\r
- __IO uint32_t HCCHAR3;\r
- __IO uint32_t HCSPLT3;\r
- __IO uint32_t HCINT3;\r
- __IO uint32_t HCINTMSK3;\r
- __IO uint32_t HCTSIZ3;\r
- __IO uint32_t HCDMA3;\r
- uint32_t RESERVED9[2];\r
- __IO uint32_t HCCHAR4;\r
- __IO uint32_t HCSPLT4;\r
- __IO uint32_t HCINT4;\r
- __IO uint32_t HCINTMSK4;\r
- __IO uint32_t HCTSIZ4;\r
- __IO uint32_t HCDMA4;\r
- uint32_t RESERVED10[2];\r
- __IO uint32_t HCCHAR5;\r
- __IO uint32_t HCSPLT5;\r
- __IO uint32_t HCINT5;\r
- __IO uint32_t HCINTMSK5;\r
- __IO uint32_t HCTSIZ5;\r
- __IO uint32_t HCDMA5;\r
- uint32_t RESERVED11[2];\r
- __IO uint32_t HCCHAR6;\r
- __IO uint32_t HCSPLT6;\r
- __IO uint32_t HCINT6;\r
- __IO uint32_t HCINTMSK6;\r
- __IO uint32_t HCTSIZ6;\r
- __IO uint32_t HCDMA6;\r
- uint32_t RESERVED12[2];\r
- __IO uint32_t HCCHAR7;\r
- __IO uint32_t HCSPLT7;\r
- __IO uint32_t HCINT7;\r
- __IO uint32_t HCINTMSK7;\r
- __IO uint32_t HCTSIZ7;\r
- __IO uint32_t HCDMA7;\r
- uint32_t RESERVED13[2];\r
- __IO uint32_t HCCHAR8;\r
- __IO uint32_t HCSPLT8;\r
- __IO uint32_t HCINT8;\r
- __IO uint32_t HCINTMSK8;\r
- __IO uint32_t HCTSIZ8;\r
- __IO uint32_t HCDMA8;\r
- uint32_t RESERVED14[2];\r
- __IO uint32_t HCCHAR9;\r
- __IO uint32_t HCSPLT9;\r
- __IO uint32_t HCINT9;\r
- __IO uint32_t HCINTMSK9;\r
- __IO uint32_t HCTSIZ9;\r
- __IO uint32_t HCDMA9;\r
- uint32_t RESERVED15[2];\r
- __IO uint32_t HCCHAR10;\r
- __IO uint32_t HCSPLT10;\r
- __IO uint32_t HCINT10;\r
- __IO uint32_t HCINTMSK10;\r
- __IO uint32_t HCTSIZ10;\r
- __IO uint32_t HCDMA10;\r
- uint32_t RESERVED16[2];\r
- __IO uint32_t HCCHAR11;\r
- __IO uint32_t HCSPLT11;\r
- __IO uint32_t HCINT11;\r
- __IO uint32_t HCINTMSK11;\r
- __IO uint32_t HCTSIZ11;\r
- __IO uint32_t HCDMA11;\r
- uint32_t RESERVED17[2];\r
- __IO uint32_t HCCHAR12;\r
- __IO uint32_t HCSPLT12;\r
- __IO uint32_t HCINT12;\r
- __IO uint32_t HCINTMSK12;\r
- __IO uint32_t HCTSIZ12;\r
- __IO uint32_t HCDMA12;\r
- uint32_t RESERVED18[2];\r
- __IO uint32_t HCCHAR13;\r
- __IO uint32_t HCSPLT13;\r
- __IO uint32_t HCINT13;\r
- __IO uint32_t HCINTMSK13;\r
- __IO uint32_t HCTSIZ13;\r
- __IO uint32_t HCDMA13;\r
- uint32_t RESERVED19[2];\r
- __IO uint32_t HCCHAR14;\r
- __IO uint32_t HCSPLT14;\r
- __IO uint32_t HCINT14;\r
- __IO uint32_t HCINTMSK14;\r
- __IO uint32_t HCTSIZ14;\r
- __IO uint32_t HCDMA14;\r
- uint32_t RESERVED20[2];\r
- __IO uint32_t HCCHAR15;\r
- __IO uint32_t HCSPLT15;\r
- __IO uint32_t HCINT15;\r
- __IO uint32_t HCINTMSK15;\r
- __IO uint32_t HCTSIZ15;\r
- __IO uint32_t HCDMA15;\r
- uint32_t RESERVED21[2];\r
- uint32_t RESERVED22[64];\r
- __IO uint32_t DCFG;\r
- __IO uint32_t DCTL;\r
- __IO uint32_t DSTS;\r
- uint32_t RESERVED23;\r
- __IO uint32_t DIEPMSK;\r
- __IO uint32_t DOEPMSK;\r
- __IO uint32_t DAINT;\r
- __IO uint32_t DAINTMSK;\r
- uint32_t RESERVED24[2];\r
- __IO uint32_t DVBUSDIS;\r
- __IO uint32_t DVBUSPULSE;\r
- uint32_t RESERVED25;\r
- __IO uint32_t DIEPEMPMSK;\r
- __IO uint32_t EACHHINT;\r
- __IO uint32_t EACHHINTMSK;\r
- __IO uint32_t DIEPEACHMSK1;\r
- uint32_t RESERVED26[15];\r
- __IO uint32_t DOEPEACHMSK1;\r
- uint32_t RESERVED27[31];\r
- __IO uint32_t DIEPCTL0;\r
- uint32_t RESERVED28;\r
- __IO uint32_t DIEPINT0;\r
- uint32_t RESERVED29;\r
- __IO uint32_t DIEPTSIZ0;\r
- __IO uint32_t DIEPDMA0;\r
- __IO uint32_t DTXFSTS0;\r
- uint32_t RESERVED30;\r
- __IO uint32_t DIEPCTL1;\r
- uint32_t RESERVED31;\r
- __IO uint32_t DIEPINT1;\r
- uint32_t RESERVED32;\r
- __IO uint32_t DIEPTSIZ1;\r
- __IO uint32_t DIEPDMA1;\r
- __IO uint32_t DTXFSTS1;\r
- uint32_t RESERVED33;\r
- __IO uint32_t DIEPCTL2;\r
- uint32_t RESERVED34;\r
- __IO uint32_t DIEPINT2;\r
- uint32_t RESERVED35;\r
- __IO uint32_t DIEPTSIZ2;\r
- __IO uint32_t DIEPDMA2;\r
- __IO uint32_t DTXFSTS2;\r
- uint32_t RESERVED36;\r
- __IO uint32_t DIEPCTL3;\r
- uint32_t RESERVED37;\r
- __IO uint32_t DIEPINT3;\r
- uint32_t RESERVED38;\r
- __IO uint32_t DIEPTSIZ3;\r
- __IO uint32_t DIEPDMA3;\r
- __IO uint32_t DTXFSTS3;\r
- uint32_t RESERVED39;\r
- __IO uint32_t DIEPCTL4;\r
- uint32_t RESERVED40;\r
- __IO uint32_t DIEPINT4;\r
- uint32_t RESERVED41;\r
- __IO uint32_t DIEPTSIZ4;\r
- __IO uint32_t DIEPDMA4;\r
- __IO uint32_t DTXFSTS4;\r
- uint32_t RESERVED42;\r
- __IO uint32_t DIEPCTL5;\r
- uint32_t RESERVED43;\r
- __IO uint32_t DIEPINT5;\r
- uint32_t RESERVED44;\r
- __IO uint32_t DIEPTSIZ5;\r
- __IO uint32_t DIEPDMA5;\r
- __IO uint32_t DTXFSTS5;\r
- uint32_t RESERVED45;\r
- __IO uint32_t DIEPCTL6;\r
- uint32_t RESERVED46;\r
- __IO uint32_t DIEPINT6;\r
- uint32_t RESERVED47;\r
- __IO uint32_t DIEPTSIZ6;\r
- __IO uint32_t DIEPDMA6;\r
- __IO uint32_t DTXFSTS6;\r
- uint32_t RESERVED48;\r
- __IO uint32_t DIEPCTL7;\r
- uint32_t RESERVED49;\r
- __IO uint32_t DIEPINT7;\r
- uint32_t RESERVED50;\r
- __IO uint32_t DIEPTSIZ7;\r
- __IO uint32_t DIEPDMA7;\r
- __IO uint32_t DTXFSTS7;\r
- uint32_t RESERVED51;\r
- __IO uint32_t DIEPCTL8;\r
- uint32_t RESERVED52;\r
- __IO uint32_t DIEPINT8;\r
- uint32_t RESERVED53;\r
- __IO uint32_t DIEPTSIZ8;\r
- __IO uint32_t DIEPDMA8;\r
- __IO uint32_t DTXFSTS8;\r
- uint32_t RESERVED54;\r
- __IO uint32_t DIEPCTL9;\r
- uint32_t RESERVED55;\r
- __IO uint32_t DIEPINT9;\r
- uint32_t RESERVED56;\r
- __IO uint32_t DIEPTSIZ9;\r
- __IO uint32_t DIEPDMA9;\r
- __IO uint32_t DTXFSTS9;\r
- uint32_t RESERVED57;\r
- __IO uint32_t DIEPCTL10;\r
- uint32_t RESERVED58;\r
- __IO uint32_t DIEPINT10;\r
- uint32_t RESERVED59;\r
- __IO uint32_t DIEPTSIZ10;\r
- __IO uint32_t DIEPDMA10;\r
- __IO uint32_t DTXFSTS10;\r
- uint32_t RESERVED60;\r
- __IO uint32_t DIEPCTL11;\r
- uint32_t RESERVED61;\r
- __IO uint32_t DIEPINT11;\r
- uint32_t RESERVED62;\r
- __IO uint32_t DIEPTSIZ11;\r
- __IO uint32_t DIEPDMA11;\r
- __IO uint32_t DTXFSTS11;\r
- uint32_t RESERVED63;\r
- __IO uint32_t DIEPCTL12;\r
- uint32_t RESERVED64;\r
- __IO uint32_t DIEPINT12;\r
- uint32_t RESERVED65;\r
- __IO uint32_t DIEPTSIZ12;\r
- __IO uint32_t DIEPDMA12;\r
- __IO uint32_t DTXFSTS12;\r
- uint32_t RESERVED66;\r
- __IO uint32_t DIEPCTL13;\r
- uint32_t RESERVED67;\r
- __IO uint32_t DIEPINT13;\r
- uint32_t RESERVED68;\r
- __IO uint32_t DIEPTSIZ13;\r
- __IO uint32_t DIEPDMA13;\r
- __IO uint32_t DTXFSTS13;\r
- uint32_t RESERVED69;\r
- __IO uint32_t DIEPCTL14;\r
- uint32_t RESERVED70;\r
- __IO uint32_t DIEPINT14;\r
- uint32_t RESERVED71;\r
- __IO uint32_t DIEPTSIZ14;\r
- __IO uint32_t DIEPDMA14;\r
- __IO uint32_t DTXFSTS14;\r
- uint32_t RESERVED72;\r
- __IO uint32_t DIEPCTL15;\r
- uint32_t RESERVED73;\r
- __IO uint32_t DIEPINT15;\r
- uint32_t RESERVED74;\r
- __IO uint32_t DIEPTSIZ15;\r
- __IO uint32_t DIEPDMA15;\r
- __IO uint32_t DTXFSTS15;\r
- uint32_t RESERVED75;\r
- __IO uint32_t DOEPCTL0;\r
- uint32_t RESERVED76;\r
- __IO uint32_t DOEPINT0;\r
- uint32_t RESERVED77;\r
- __IO uint32_t DOEPTSIZ0;\r
- __IO uint32_t DOEPDMAB0;\r
- uint32_t RESERVED78[2];\r
- __IO uint32_t DOEPCTL1;\r
- uint32_t RESERVED79;\r
- __IO uint32_t DOEPINT1;\r
- uint32_t RESERVED80;\r
- __IO uint32_t DOEPTSIZ1;\r
- __IO uint32_t DOEPDMAB1;\r
- uint32_t RESERVED81[2];\r
- __IO uint32_t DOEPCTL2;\r
- uint32_t RESERVED82;\r
- __IO uint32_t DOEPINT2;\r
- uint32_t RESERVED83;\r
- __IO uint32_t DOEPTSIZ2;\r
- __IO uint32_t DOEPDMAB2;\r
- uint32_t RESERVED84[2];\r
- __IO uint32_t DOEPCTL3;\r
- uint32_t RESERVED85;\r
- __IO uint32_t DOEPINT3;\r
- uint32_t RESERVED86;\r
- __IO uint32_t DOEPTSIZ3;\r
- __IO uint32_t DOEPDMAB3;\r
- uint32_t RESERVED87[2];\r
- __IO uint32_t DOEPCTL4;\r
- uint32_t RESERVED88;\r
- __IO uint32_t DOEPINT4;\r
- uint32_t RESERVED89;\r
- __IO uint32_t DOEPTSIZ4;\r
- __IO uint32_t DOEPDMAB4;\r
- uint32_t RESERVED90[2];\r
- __IO uint32_t DOEPCTL5;\r
- uint32_t RESERVED91;\r
- __IO uint32_t DOEPINT5;\r
- uint32_t RESERVED92;\r
- __IO uint32_t DOEPTSIZ5;\r
- __IO uint32_t DOEPDMAB5;\r
- uint32_t RESERVED93[2];\r
- __IO uint32_t DOEPCTL6;\r
- uint32_t RESERVED94;\r
- __IO uint32_t DOEPINT6;\r
- uint32_t RESERVED95;\r
- __IO uint32_t DOEPTSIZ6;\r
- __IO uint32_t DOEPDMAB6;\r
- uint32_t RESERVED96[2];\r
- __IO uint32_t DOEPCTL7;\r
- uint32_t RESERVED97;\r
- __IO uint32_t DOEPINT7;\r
- uint32_t RESERVED98;\r
- __IO uint32_t DOEPTSIZ7;\r
- __IO uint32_t DOEPDMAB7;\r
- uint32_t RESERVED99[2];\r
- __IO uint32_t DOEPCTL8;\r
- uint32_t RESERVED100;\r
- __IO uint32_t DOEPINT8;\r
- uint32_t RESERVED101;\r
- __IO uint32_t DOEPTSIZ8;\r
- __IO uint32_t DOEPDMAB8;\r
- uint32_t RESERVED102[2];\r
- __IO uint32_t DOEPCTL9;\r
- uint32_t RESERVED103;\r
- __IO uint32_t DOEPINT9;\r
- uint32_t RESERVED104;\r
- __IO uint32_t DOEPTSIZ9;\r
- __IO uint32_t DOEPDMAB9;\r
- uint32_t RESERVED105[2];\r
- __IO uint32_t DOEPCTL10;\r
- uint32_t RESERVED106;\r
- __IO uint32_t DOEPINT10;\r
- uint32_t RESERVED107;\r
- __IO uint32_t DOEPTSIZ10;\r
- __IO uint32_t DOEPDMAB10;\r
- uint32_t RESERVED108[2];\r
- __IO uint32_t DOEPCTL11;\r
- uint32_t RESERVED109;\r
- __IO uint32_t DOEPINT11;\r
- uint32_t RESERVED110;\r
- __IO uint32_t DOEPTSIZ11;\r
- __IO uint32_t DOEPDMAB11;\r
- uint32_t RESERVED111[2];\r
- __IO uint32_t DOEPCTL12;\r
- uint32_t RESERVED112;\r
- __IO uint32_t DOEPINT12;\r
- uint32_t RESERVED113;\r
- __IO uint32_t DOEPTSIZ12;\r
- __IO uint32_t DOEPDMAB12;\r
- uint32_t RESERVED114[2];\r
- __IO uint32_t DOEPCTL13;\r
- uint32_t RESERVED115;\r
- __IO uint32_t DOEPINT13;\r
- uint32_t RESERVED116;\r
- __IO uint32_t DOEPTSIZ13;\r
- __IO uint32_t DOEPDMAB13;\r
- uint32_t RESERVED117[2];\r
- __IO uint32_t DOEPCTL14;\r
- uint32_t RESERVED118;\r
- __IO uint32_t DOEPINT14;\r
- uint32_t RESERVED119;\r
- __IO uint32_t DOEPTSIZ14;\r
- __IO uint32_t DOEPDMAB14;\r
- uint32_t RESERVED120[2];\r
- __IO uint32_t DOEPCTL15;\r
- uint32_t RESERVED121;\r
- __IO uint32_t DOEPINT15;\r
- uint32_t RESERVED122;\r
- __IO uint32_t DOEPTSIZ15;\r
- __IO uint32_t DOEPDMAB15;\r
- uint32_t RESERVED123[2];\r
- uint32_t RESERVED143[64];\r
- __IO uint32_t PCGCCTL;\r
-} OTG_HS_TypeDef;\r
-#pragma no_anon_unions\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_memory_map\r
- * @{\r
- */\r
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region */\r
-#define CCMDATARAM_BASE ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region */\r
-#define SRAM1_BASE ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region */\r
-#define SRAM2_BASE ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region */\r
-#define SRAM3_BASE ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region */\r
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */\r
-#define BKPSRAM_BASE ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region */\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
-#define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-#define FMC_R_BASE ((uint32_t)0xA0000000) /*!< FMC registers base address */\r
-#endif /* STM32F429X */\r
-\r
-#define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region */\r
-#define SRAM1_BB_BASE ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region */\r
-#define SRAM2_BB_BASE ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region */\r
-#define SRAM3_BB_BASE ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region */\r
-#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */\r
-#define BKPSRAM_BB_BASE ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region */\r
-\r
-/* Legacy defines */\r
-#define SRAM_BASE SRAM1_BASE\r
-#define SRAM_BB_BASE SRAM1_BB_BASE\r
-\r
-\r
-/*!< Peripheral memory map */\r
-#define APB1PERIPH_BASE PERIPH_BASE\r
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)\r
-#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)\r
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000)\r
-\r
-/*!< APB1 peripherals */\r
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)\r
-#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)\r
-#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)\r
-#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)\r
-#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)\r
-#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)\r
-#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)\r
-#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)\r
-#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)\r
-#define RTC_BASE (APB1PERIPH_BASE + 0x2800)\r
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)\r
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)\r
-#define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400)\r
-#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)\r
-#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)\r
-#define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000)\r
-#define USART2_BASE (APB1PERIPH_BASE + 0x4400)\r
-#define USART3_BASE (APB1PERIPH_BASE + 0x4800)\r
-#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)\r
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)\r
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)\r
-#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)\r
-#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00)\r
-#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)\r
-#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)\r
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)\r
-#define DAC_BASE (APB1PERIPH_BASE + 0x7400)\r
-#define UART7_BASE (APB1PERIPH_BASE + 0x7800)\r
-#define UART8_BASE (APB1PERIPH_BASE + 0x7C00)\r
-\r
-/*!< APB2 peripherals */\r
-#define TIM1_BASE (APB2PERIPH_BASE + 0x0000)\r
-#define TIM8_BASE (APB2PERIPH_BASE + 0x0400)\r
-#define USART1_BASE (APB2PERIPH_BASE + 0x1000)\r
-#define USART6_BASE (APB2PERIPH_BASE + 0x1400)\r
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2000)\r
-#define ADC2_BASE (APB2PERIPH_BASE + 0x2100)\r
-#define ADC3_BASE (APB2PERIPH_BASE + 0x2200)\r
-#define ADC_BASE (APB2PERIPH_BASE + 0x2300)\r
-#define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)\r
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)\r
-#define SPI4_BASE (APB2PERIPH_BASE + 0x3400)\r
-#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800)\r
-#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00)\r
-#define TIM9_BASE (APB2PERIPH_BASE + 0x4000)\r
-#define TIM10_BASE (APB2PERIPH_BASE + 0x4400)\r
-#define TIM11_BASE (APB2PERIPH_BASE + 0x4800)\r
-#define SPI5_BASE (APB2PERIPH_BASE + 0x5000)\r
-#define SPI6_BASE (APB2PERIPH_BASE + 0x5400)\r
-\r
-#if defined (STM32F429X)\r
-#define SAI1_BASE (APB2PERIPH_BASE + 0x5800)\r
-#define SAI1_Block_A_BASE (SAI1_BASE + 0x004)\r
-#define SAI1_Block_B_BASE (SAI1_BASE + 0x024)\r
-#define LTDC_BASE (APB2PERIPH_BASE + 0x6800)\r
-#define LTDC_Layer1_BASE (LTDC_BASE + 0x84)\r
-#define LTDC_Layer2_BASE (LTDC_BASE + 0x104) \r
-#endif /* STM32F429X */\r
-\r
-/*!< AHB1 peripherals */\r
-#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000)\r
-#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400)\r
-#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800)\r
-#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00)\r
-#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000)\r
-#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400)\r
-#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800)\r
-#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00)\r
-#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000)\r
-\r
-#if defined (STM32F429X)\r
-#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400)\r
-#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800)\r
-#endif /* STM32F429X */\r
-\r
-#define CRC_BASE (AHB1PERIPH_BASE + 0x3000)\r
-#define RCC_BASE (AHB1PERIPH_BASE + 0x3800)\r
-#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00)\r
-#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000)\r
-#define DMA1_Stream0_BASE (DMA1_BASE + 0x010)\r
-#define DMA1_Stream1_BASE (DMA1_BASE + 0x028)\r
-#define DMA1_Stream2_BASE (DMA1_BASE + 0x040)\r
-#define DMA1_Stream3_BASE (DMA1_BASE + 0x058)\r
-#define DMA1_Stream4_BASE (DMA1_BASE + 0x070)\r
-#define DMA1_Stream5_BASE (DMA1_BASE + 0x088)\r
-#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0)\r
-#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8)\r
-#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400)\r
-#define DMA2_Stream0_BASE (DMA2_BASE + 0x010)\r
-#define DMA2_Stream1_BASE (DMA2_BASE + 0x028)\r
-#define DMA2_Stream2_BASE (DMA2_BASE + 0x040)\r
-#define DMA2_Stream3_BASE (DMA2_BASE + 0x058)\r
-#define DMA2_Stream4_BASE (DMA2_BASE + 0x070)\r
-#define DMA2_Stream5_BASE (DMA2_BASE + 0x088)\r
-#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0)\r
-#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8)\r
-#define ETH_BASE (AHB1PERIPH_BASE + 0x8000)\r
-#define ETH_MAC_BASE (ETH_BASE)\r
-#define ETH_MMC_BASE (ETH_BASE + 0x0100)\r
-#define ETH_PTP_BASE (ETH_BASE + 0x0700)\r
-#define ETH_DMA_BASE (ETH_BASE + 0x1000)\r
-#define OTG_HS_BASE (AHB1PERIPH_BASE + 0x20000)\r
-#define OTG_HS_DFIFO0_BASE (OTG_HS_BASE + 0x01000)\r
-#define OTG_HS_DFIFO1_BASE (OTG_HS_BASE + 0x02000)\r
-#define OTG_HS_DFIFO2_BASE (OTG_HS_BASE + 0x03000)\r
-#define OTG_HS_DFIFO3_BASE (OTG_HS_BASE + 0x04000)\r
-#define OTG_HS_DFIFO4_BASE (OTG_HS_BASE + 0x05000)\r
-#define OTG_HS_DFIFO5_BASE (OTG_HS_BASE + 0x06000)\r
-#define OTG_HS_DFIFO6_BASE (OTG_HS_BASE + 0x07000)\r
-#define OTG_HS_DFIFO7_BASE (OTG_HS_BASE + 0x08000)\r
-#define OTG_HS_DFIFO8_BASE (OTG_HS_BASE + 0x09000)\r
-#define OTG_HS_DFIFO9_BASE (OTG_HS_BASE + 0x0A000)\r
-#define OTG_HS_DFIFO10_BASE (OTG_HS_BASE + 0x0B000)\r
-#define OTG_HS_DFIFO11_BASE (OTG_HS_BASE + 0x0C000)\r
-#define OTG_HS_DFIFO12_BASE (OTG_HS_BASE + 0x0D000)\r
-#define OTG_HS_DFIFO13_BASE (OTG_HS_BASE + 0x0E000)\r
-#define OTG_HS_DFIFO14_BASE (OTG_HS_BASE + 0x0F000)\r
-#define OTG_HS_DFIFO15_BASE (OTG_HS_BASE + 0x10000)\r
-\r
-#if defined (STM32F429X)\r
-#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000)\r
-#endif /* STM32F429X */\r
-\r
-/*!< AHB2 peripherals */\r
-#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x00000)\r
-#define OTG_FS_DFIFO0_BASE (OTG_FS_BASE + 0x01000)\r
-#define OTG_FS_DFIFO1_BASE (OTG_FS_BASE + 0x02000)\r
-#define OTG_FS_DFIFO2_BASE (OTG_FS_BASE + 0x03000)\r
-#define OTG_FS_DFIFO3_BASE (OTG_FS_BASE + 0x04000)\r
-#define OTG_FS_DFIFO4_BASE (OTG_FS_BASE + 0x05000)\r
-#define OTG_FS_DFIFO5_BASE (OTG_FS_BASE + 0x06000)\r
-#define OTG_FS_DFIFO6_BASE (OTG_FS_BASE + 0x07000)\r
-#define OTG_FS_DFIFO7_BASE (OTG_FS_BASE + 0x08000)\r
-#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000)\r
-#define CRYP_BASE (AHB2PERIPH_BASE + 0x60000)\r
-#define HASH_BASE (AHB2PERIPH_BASE + 0x60400)\r
-#define HASH_DIGEST_BASE (AHB2PERIPH_BASE + 0x60710)\r
-#define RNG_BASE (AHB2PERIPH_BASE + 0x60800)\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
-/*!< FSMC Bankx registers base address */\r
-#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)\r
-#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)\r
-#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)\r
-#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)\r
-#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-/*!< FMC Bankx registers base address */\r
-#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)\r
-#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)\r
-#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)\r
-#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)\r
-#define FMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)\r
-#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)\r
-#endif /* STM32F429X */\r
-\r
-/* Debug MCU registers base address */\r
-#define DBGMCU_BASE ((uint32_t )0xE0042000)\r
-\r
-/**\r
- * @}\r
- */\r
- \r
-/** @addtogroup Peripheral_declaration\r
- * @{\r
- */ \r
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)\r
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)\r
-#define TIM4 ((TIM_TypeDef *) TIM4_BASE)\r
-#define TIM5 ((TIM_TypeDef *) TIM5_BASE)\r
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)\r
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)\r
-#define TIM12 ((TIM_TypeDef *) TIM12_BASE)\r
-#define TIM13 ((TIM_TypeDef *) TIM13_BASE)\r
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)\r
-#define RTC ((RTC_TypeDef *) RTC_BASE)\r
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)\r
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)\r
-#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)\r
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)\r
-#define SPI3 ((SPI_TypeDef *) SPI3_BASE)\r
-#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)\r
-#define USART2 ((USART_TypeDef *) USART2_BASE)\r
-#define USART3 ((USART_TypeDef *) USART3_BASE)\r
-#define UART4 ((USART_TypeDef *) UART4_BASE)\r
-#define UART5 ((USART_TypeDef *) UART5_BASE)\r
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)\r
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)\r
-#define I2C3 ((I2C_TypeDef *) I2C3_BASE)\r
-#define CAN1 ((CAN_TypeDef *) CAN1_BASE)\r
-#define CAN2 ((CAN_TypeDef *) CAN2_BASE)\r
-#define PWR ((PWR_TypeDef *) PWR_BASE)\r
-#define DAC ((DAC_TypeDef *) DAC_BASE)\r
-#define UART7 ((USART_TypeDef *) UART7_BASE)\r
-#define UART8 ((USART_TypeDef *) UART8_BASE)\r
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)\r
-#define TIM8 ((TIM_TypeDef *) TIM8_BASE)\r
-#define USART1 ((USART_TypeDef *) USART1_BASE)\r
-#define USART6 ((USART_TypeDef *) USART6_BASE)\r
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)\r
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)\r
-#define ADC2 ((ADC_TypeDef *) ADC2_BASE)\r
-#define ADC3 ((ADC_TypeDef *) ADC3_BASE)\r
-#define SDIO ((SDIO_TypeDef *) SDIO_BASE)\r
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE) \r
-#define SPI4 ((SPI_TypeDef *) SPI4_BASE)\r
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)\r
-#define TIM9 ((TIM_TypeDef *) TIM9_BASE)\r
-#define TIM10 ((TIM_TypeDef *) TIM10_BASE)\r
-#define TIM11 ((TIM_TypeDef *) TIM11_BASE)\r
-#define SPI5 ((SPI_TypeDef *) SPI5_BASE)\r
-#define SPI6 ((SPI_TypeDef *) SPI6_BASE)\r
-\r
-#if defined (STM32F429X)\r
-#define SAI1 ((SAI_TypeDef *) SAI1_BASE)\r
-#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
-#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
-#define LTDC ((LTDC_TypeDef *)LTDC_BASE)\r
-#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
-#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
-#endif /* STM32F429X */\r
-\r
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)\r
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)\r
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)\r
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)\r
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)\r
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)\r
-#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)\r
-#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)\r
-#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)\r
-\r
-#if defined (STM32F429X)\r
-#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)\r
-#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)\r
-#endif /* STM32F429X */\r
-\r
-#define CRC ((CRC_TypeDef *) CRC_BASE)\r
-#define RCC ((RCC_TypeDef *) RCC_BASE)\r
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)\r
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)\r
-#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
-#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
-#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
-#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
-#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
-#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
-#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
-#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
-#define DMA2 ((DMA_TypeDef *) DMA2_BASE)\r
-#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
-#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
-#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
-#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
-#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
-#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
-#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
-#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
-#define ETH ((ETH_TypeDef *) ETH_BASE) \r
-#define OTG_HS ((OTG_HS_TypeDef *) OTG_HS_BASE) \r
-#define OTG_HS_DFIFO0 (((uint32_t *) OTG_HS_DFIFO0_BASE) )\r
-#define OTG_HS_DFIFO1 (((uint32_t *) OTG_HS_DFIFO1_BASE) )\r
-#define OTG_HS_DFIFO2 (((uint32_t *) OTG_HS_DFIFO2_BASE) )\r
-#define OTG_HS_DFIFO3 (((uint32_t *) OTG_HS_DFIFO3_BASE) )\r
-#define OTG_HS_DFIFO4 (((uint32_t *) OTG_HS_DFIFO4_BASE) )\r
-#define OTG_HS_DFIFO5 (((uint32_t *) OTG_HS_DFIFO5_BASE) )\r
-#define OTG_HS_DFIFO6 (((uint32_t *) OTG_HS_DFIFO6_BASE) )\r
-#define OTG_HS_DFIFO7 (((uint32_t *) OTG_HS_DFIFO7_BASE) )\r
-#define OTG_HS_DFIFO8 (((uint32_t *) OTG_HS_DFIFO8_BASE) )\r
-#define OTG_HS_DFIFO9 (((uint32_t *) OTG_HS_DFIFO9_BASE) )\r
-#define OTG_HS_DFIFO10 (((uint32_t *) OTG_HS_DFIFO10_BASE) )\r
-#define OTG_HS_DFIFO11 (((uint32_t *) OTG_HS_DFIFO11_BASE) )\r
-#define OTG_HS_DFIFO12 (((uint32_t *) OTG_HS_DFIFO12_BASE) )\r
-#define OTG_HS_DFIFO13 (((uint32_t *) OTG_HS_DFIFO13_BASE) )\r
-#define OTG_HS_DFIFO14 (((uint32_t *) OTG_HS_DFIFO14_BASE) )\r
-#define OTG_HS_DFIFO15 (((uint32_t *) OTG_HS_DFIFO15_BASE) )\r
-#define OTG_FS ((OTG_FS_TypeDef *) OTG_FS_BASE) \r
-#define OTG_FS_DFIFO0 (((uint32_t *) OTG_FS_DFIFO0_BASE) )\r
-#define OTG_FS_DFIFO1 (((uint32_t *) OTG_FS_DFIFO1_BASE) )\r
-#define OTG_FS_DFIFO2 (((uint32_t *) OTG_FS_DFIFO2_BASE) )\r
-#define OTG_FS_DFIFO3 (((uint32_t *) OTG_FS_DFIFO3_BASE) )\r
-#define OTG_FS_DFIFO4 (((uint32_t *) OTG_FS_DFIFO4_BASE) )\r
-#define OTG_FS_DFIFO5 (((uint32_t *) OTG_FS_DFIFO5_BASE) )\r
-#define OTG_FS_DFIFO6 (((uint32_t *) OTG_FS_DFIFO6_BASE) )\r
-#define OTG_FS_DFIFO7 (((uint32_t *) OTG_FS_DFIFO7_BASE) )\r
-\r
-#if defined (STM32F429X)\r
-#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)\r
-#endif /* STM32F429X */\r
-\r
-#define DCMI ((DCMI_TypeDef *) DCMI_BASE)\r
-#define CRYP ((CRYP_TypeDef *) CRYP_BASE)\r
-#define HASH ((HASH_TypeDef *) HASH_BASE)\r
-#define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r
-#define RNG ((RNG_TypeDef *) RNG_BASE)\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
-#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
-#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
-#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
-#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
-#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
-#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
-#define FMC_Bank2 ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r
-#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
-#define FMC_Bank4 ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)\r
-#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
-#endif /* STM32F429X */\r
-\r
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-/** @addtogroup Exported_constants\r
- * @{\r
- */\r
- \r
- /** @addtogroup Peripheral_Registers_Bits_Definition\r
- * @{\r
- */\r
- \r
-/******************************************************************************/\r
-/* Peripheral Registers_Bits_Definition */\r
-/******************************************************************************/\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Analog to Digital Converter */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for ADC_SR register ********************/\r
-#define ADC_SR_AWD ((uint8_t)0x01) /*!<Analog watchdog flag */\r
-#define ADC_SR_EOC ((uint8_t)0x02) /*!<End of conversion */\r
-#define ADC_SR_JEOC ((uint8_t)0x04) /*!<Injected channel end of conversion */\r
-#define ADC_SR_JSTRT ((uint8_t)0x08) /*!<Injected channel Start flag */\r
-#define ADC_SR_STRT ((uint8_t)0x10) /*!<Regular channel Start flag */\r
-#define ADC_SR_OVR ((uint8_t)0x20) /*!<Overrun flag */\r
-\r
-/******************* Bit definition for ADC_CR1 register ********************/\r
-#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
-#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!<Interrupt enable for EOC */\r
-#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!<AAnalog Watchdog interrupt enable */\r
-#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!<Interrupt enable for injected channels */\r
-#define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!<Scan mode */\r
-#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!<Enable the watchdog on a single channel in scan mode */\r
-#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!<Automatic injected group conversion */\r
-#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!<Discontinuous mode on regular channels */\r
-#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!<Discontinuous mode on injected channels */\r
-#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
-#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!<Analog watchdog enable on injected channels */\r
-#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!<Analog watchdog enable on regular channels */\r
-#define ADC_CR1_RES ((uint32_t)0x03000000) /*!<RES[2:0] bits (Resolution) */\r
-#define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!<overrun interrupt enable */\r
- \r
-/******************* Bit definition for ADC_CR2 register ********************/\r
-#define ADC_CR2_ADON ((uint32_t)0x00000001) /*!<A/D Converter ON / OFF */\r
-#define ADC_CR2_CONT ((uint32_t)0x00000002) /*!<Continuous Conversion */\r
-#define ADC_CR2_DMA ((uint32_t)0x00000100) /*!<Direct Memory access mode */\r
-#define ADC_CR2_DDS ((uint32_t)0x00000200) /*!<DMA disable selection (Single ADC) */\r
-#define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!<End of conversion selection */\r
-#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!<Data Alignment */\r
-#define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
-#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
-#define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!<Start Conversion of injected channels */\r
-#define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
-#define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
-#define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-#define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!<Start Conversion of regular channels */\r
-\r
-/****************** Bit definition for ADC_SMPR1 register *******************/\r
-#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
-#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
-#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
-#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
-#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
-#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
-#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
-#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
-#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
-#define ADC_SMPR1_SMP18 ((uint32_t)0x07000000) /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
-#define ADC_SMPR1_SMP18_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define ADC_SMPR1_SMP18_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define ADC_SMPR1_SMP18_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for ADC_SMPR2 register *******************/\r
-#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
-#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
-#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
-#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
-#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
-#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
-#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
-#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
-#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
-#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
-#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /*!<Bit 0 */\r
-#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /*!<Bit 1 */\r
-#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for ADC_JOFR1 register *******************/\r
-#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 1 */\r
-\r
-/****************** Bit definition for ADC_JOFR2 register *******************/\r
-#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 2 */\r
-\r
-/****************** Bit definition for ADC_JOFR3 register *******************/\r
-#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 3 */\r
-\r
-/****************** Bit definition for ADC_JOFR4 register *******************/\r
-#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /*!<Data offset for injected channel 4 */\r
-\r
-/******************* Bit definition for ADC_HTR register ********************/\r
-#define ADC_HTR_HT ((uint16_t)0x0FFF) /*!<Analog watchdog high threshold */\r
-\r
-/******************* Bit definition for ADC_LTR register ********************/\r
-#define ADC_LTR_LT ((uint16_t)0x0FFF) /*!<Analog watchdog low threshold */\r
-\r
-/******************* Bit definition for ADC_SQR1 register *******************/\r
-#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
-#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-#define ADC_SQR1_L ((uint32_t)0x00F00000) /*!<L[3:0] bits (Regular channel sequence length) */\r
-#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for ADC_SQR2 register *******************/\r
-#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
-#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
-#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
-#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
-#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
-#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
-#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for ADC_SQR3 register *******************/\r
-#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
-#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
-#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
-#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /*!<Bit 4 */\r
-#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
-#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /*!<Bit 0 */\r
-#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /*!<Bit 1 */\r
-#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /*!<Bit 2 */\r
-#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /*!<Bit 3 */\r
-#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for ADC_JSQR register *******************/\r
-#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */ \r
-#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!<Bit 4 */\r
-#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!<Bit 4 */\r
-#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
-#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!<Bit 0 */\r
-#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!<Bit 1 */\r
-#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!<Bit 2 */\r
-#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!<Bit 3 */\r
-#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!<Bit 4 */\r
-#define ADC_JSQR_JL ((uint32_t)0x00300000) /*!<JL[1:0] bits (Injected Sequence length) */\r
-#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for ADC_JDR1 register *******************/\r
-#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR2 register *******************/\r
-#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR3 register *******************/\r
-#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************* Bit definition for ADC_JDR4 register *******************/\r
-#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /*!<Injected data */\r
-\r
-/******************** Bit definition for ADC_DR register ********************/\r
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!<Regular data */\r
-#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /*!<ADC2 data */\r
-\r
-/******************* Bit definition for ADC_CSR register ********************/\r
-#define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!<ADC1 Analog watchdog flag */\r
-#define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!<ADC1 End of conversion */\r
-#define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!<ADC1 Injected channel end of conversion */\r
-#define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!<ADC1 Injected channel Start flag */\r
-#define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!<ADC1 Regular channel Start flag */\r
-#define ADC_CSR_DOVR1 ((uint32_t)0x00000020) /*!<ADC1 DMA overrun flag */\r
-#define ADC_CSR_AWD2 ((uint32_t)0x00000100) /*!<ADC2 Analog watchdog flag */\r
-#define ADC_CSR_EOC2 ((uint32_t)0x00000200) /*!<ADC2 End of conversion */\r
-#define ADC_CSR_JEOC2 ((uint32_t)0x00000400) /*!<ADC2 Injected channel end of conversion */\r
-#define ADC_CSR_JSTRT2 ((uint32_t)0x00000800) /*!<ADC2 Injected channel Start flag */\r
-#define ADC_CSR_STRT2 ((uint32_t)0x00001000) /*!<ADC2 Regular channel Start flag */\r
-#define ADC_CSR_DOVR2 ((uint32_t)0x00002000) /*!<ADC2 DMA overrun flag */\r
-#define ADC_CSR_AWD3 ((uint32_t)0x00010000) /*!<ADC3 Analog watchdog flag */\r
-#define ADC_CSR_EOC3 ((uint32_t)0x00020000) /*!<ADC3 End of conversion */\r
-#define ADC_CSR_JEOC3 ((uint32_t)0x00040000) /*!<ADC3 Injected channel end of conversion */\r
-#define ADC_CSR_JSTRT3 ((uint32_t)0x00080000) /*!<ADC3 Injected channel Start flag */\r
-#define ADC_CSR_STRT3 ((uint32_t)0x00100000) /*!<ADC3 Regular channel Start flag */\r
-#define ADC_CSR_DOVR3 ((uint32_t)0x00200000) /*!<ADC3 DMA overrun flag */\r
-\r
-/******************* Bit definition for ADC_CCR register ********************/\r
-#define ADC_CCR_MULTI ((uint32_t)0x0000001F) /*!<MULTI[4:0] bits (Multi-ADC mode selection) */ \r
-#define ADC_CCR_MULTI_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define ADC_CCR_MULTI_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define ADC_CCR_MULTI_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define ADC_CCR_MULTI_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define ADC_CCR_MULTI_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define ADC_CCR_DELAY ((uint32_t)0x00000F00) /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */ \r
-#define ADC_CCR_DELAY_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define ADC_CCR_DELAY_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define ADC_CCR_DELAY_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define ADC_CCR_DELAY_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define ADC_CCR_DDS ((uint32_t)0x00002000) /*!<DMA disable selection (Multi-ADC mode) */\r
-#define ADC_CCR_DMA ((uint32_t)0x0000C000) /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */ \r
-#define ADC_CCR_DMA_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
-#define ADC_CCR_DMA_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
-#define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!<ADCPRE[1:0] bits (ADC prescaler) */ \r
-#define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define ADC_CCR_VBATE ((uint32_t)0x00400000) /*!<VBAT Enable */\r
-#define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!<Temperature Sensor and VREFINT Enable */\r
-\r
-/******************* Bit definition for ADC_CDR register ********************/\r
-#define ADC_CDR_DATA1 ((uint32_t)0x0000FFFF) /*!<1st data of a pair of regular conversions */\r
-#define ADC_CDR_DATA2 ((uint32_t)0xFFFF0000) /*!<2nd data of a pair of regular conversions */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Controller Area Network */\r
-/* */\r
-/******************************************************************************/\r
-/*!<CAN control and status registers */\r
-/******************* Bit definition for CAN_MCR register ********************/\r
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */\r
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */\r
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */\r
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */\r
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */\r
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */\r
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */\r
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */\r
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */\r
-\r
-/******************* Bit definition for CAN_MSR register ********************/\r
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */\r
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */\r
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */\r
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */\r
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */\r
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */\r
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */\r
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */\r
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */\r
-\r
-/******************* Bit definition for CAN_TSR register ********************/\r
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */\r
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */\r
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */\r
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */\r
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */\r
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */\r
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */\r
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */\r
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */\r
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */\r
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */\r
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */\r
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */\r
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */\r
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */\r
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */\r
-\r
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */\r
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */\r
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */\r
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */\r
-\r
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */\r
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */\r
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */\r
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */\r
-\r
-/******************* Bit definition for CAN_RF0R register *******************/\r
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */\r
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */\r
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */\r
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */\r
-\r
-/******************* Bit definition for CAN_RF1R register *******************/\r
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */\r
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */\r
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */\r
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */\r
-\r
-/******************** Bit definition for CAN_IER register *******************/\r
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */\r
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */\r
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */\r
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */\r
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */\r
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */\r
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */\r
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */\r
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */\r
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */\r
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */\r
-\r
-/******************** Bit definition for CAN_ESR register *******************/\r
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */\r
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */\r
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */\r
-\r
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */\r
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-\r
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */\r
-\r
-/******************* Bit definition for CAN_BTR register ********************/\r
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */\r
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */\r
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */\r
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */\r
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */\r
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */\r
-\r
-/*!<Mailbox registers */\r
-/****************** Bit definition for CAN_TI0R register ********************/\r
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/****************** Bit definition for CAN_TDT0R register *******************/\r
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/****************** Bit definition for CAN_TDL0R register *******************/\r
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/****************** Bit definition for CAN_TDH0R register *******************/\r
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI1R register *******************/\r
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT1R register ******************/\r
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL1R register ******************/\r
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH1R register ******************/\r
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_TI2R register *******************/\r
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */\r
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_TDT2R register ******************/ \r
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */\r
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_TDL2R register ******************/\r
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_TDH2R register ******************/\r
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI0R register *******************/\r
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */\r
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT0R register ******************/\r
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL0R register ******************/\r
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH0R register ******************/\r
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/******************* Bit definition for CAN_RI1R register *******************/\r
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */\r
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */\r
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */\r
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */\r
-\r
-/******************* Bit definition for CAN_RDT1R register ******************/\r
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */\r
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */\r
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */\r
-\r
-/******************* Bit definition for CAN_RDL1R register ******************/\r
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */\r
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */\r
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */\r
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */\r
-\r
-/******************* Bit definition for CAN_RDH1R register ******************/\r
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */\r
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */\r
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */\r
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */\r
-\r
-/*!<CAN filter registers */\r
-/******************* Bit definition for CAN_FMR register ********************/\r
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */\r
-\r
-/******************* Bit definition for CAN_FM1R register *******************/\r
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */\r
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */\r
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */\r
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */\r
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */\r
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */\r
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */\r
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */\r
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */\r
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */\r
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */\r
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */\r
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */\r
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */\r
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */\r
-\r
-/******************* Bit definition for CAN_FS1R register *******************/\r
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */\r
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */\r
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */\r
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */\r
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */\r
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */\r
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */\r
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */\r
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */\r
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */\r
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */\r
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */\r
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */\r
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */\r
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */\r
-\r
-/****************** Bit definition for CAN_FFA1R register *******************/\r
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */\r
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */\r
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */\r
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */\r
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */\r
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */\r
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */\r
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */\r
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */\r
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */\r
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */\r
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */\r
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */\r
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */\r
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */\r
-\r
-/******************* Bit definition for CAN_FA1R register *******************/\r
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */\r
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */\r
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */\r
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */\r
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */\r
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */\r
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */\r
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */\r
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */\r
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */\r
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */\r
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */\r
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */\r
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */\r
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */\r
-\r
-/******************* Bit definition for CAN_F0R1 register *******************/\r
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R1 register *******************/\r
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R1 register *******************/\r
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R1 register *******************/\r
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R1 register *******************/\r
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R1 register *******************/\r
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R1 register *******************/\r
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R1 register *******************/\r
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R1 register *******************/\r
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R1 register *******************/\r
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R1 register ******************/\r
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R1 register ******************/\r
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R1 register ******************/\r
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R1 register ******************/\r
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F0R2 register *******************/\r
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F1R2 register *******************/\r
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F2R2 register *******************/\r
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F3R2 register *******************/\r
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F4R2 register *******************/\r
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F5R2 register *******************/\r
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F6R2 register *******************/\r
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F7R2 register *******************/\r
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F8R2 register *******************/\r
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F9R2 register *******************/\r
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F10R2 register ******************/\r
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F11R2 register ******************/\r
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F12R2 register ******************/\r
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************* Bit definition for CAN_F13R2 register ******************/\r
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */\r
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */\r
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */\r
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */\r
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */\r
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */\r
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */\r
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */\r
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */\r
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */\r
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */\r
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */\r
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */\r
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */\r
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */\r
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */\r
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */\r
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */\r
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */\r
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */\r
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */\r
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */\r
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */\r
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */\r
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */\r
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */\r
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */\r
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */\r
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */\r
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */\r
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */\r
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* CRC calculation unit */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for CRC_DR register *********************/\r
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
-\r
-\r
-/******************* Bit definition for CRC_IDR register ********************/\r
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */\r
-\r
-\r
-/******************** Bit definition for CRC_CR register ********************/\r
-#define CRC_CR_RESET ((uint8_t)0x01) /*!< RESET bit */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Crypto Processor */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bits definition for CRYP_CR register ********************/\r
-#define CRYP_CR_ALGODIR ((uint32_t)0x00000004)\r
-\r
-#define CRYP_CR_ALGOMODE ((uint32_t)0x00080038)\r
-#define CRYP_CR_ALGOMODE_0 ((uint32_t)0x00000008)\r
-#define CRYP_CR_ALGOMODE_1 ((uint32_t)0x00000010)\r
-#define CRYP_CR_ALGOMODE_2 ((uint32_t)0x00000020)\r
-#define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)\r
-#define CRYP_CR_ALGOMODE_TDES_CBC ((uint32_t)0x00000008)\r
-#define CRYP_CR_ALGOMODE_DES_ECB ((uint32_t)0x00000010)\r
-#define CRYP_CR_ALGOMODE_DES_CBC ((uint32_t)0x00000018)\r
-#define CRYP_CR_ALGOMODE_AES_ECB ((uint32_t)0x00000020)\r
-#define CRYP_CR_ALGOMODE_AES_CBC ((uint32_t)0x00000028)\r
-#define CRYP_CR_ALGOMODE_AES_CTR ((uint32_t)0x00000030)\r
-#define CRYP_CR_ALGOMODE_AES_KEY ((uint32_t)0x00000038)\r
-\r
-#define CRYP_CR_DATATYPE ((uint32_t)0x000000C0)\r
-#define CRYP_CR_DATATYPE_0 ((uint32_t)0x00000040)\r
-#define CRYP_CR_DATATYPE_1 ((uint32_t)0x00000080)\r
-#define CRYP_CR_KEYSIZE ((uint32_t)0x00000300)\r
-#define CRYP_CR_KEYSIZE_0 ((uint32_t)0x00000100)\r
-#define CRYP_CR_KEYSIZE_1 ((uint32_t)0x00000200)\r
-#define CRYP_CR_FFLUSH ((uint32_t)0x00004000)\r
-#define CRYP_CR_CRYPEN ((uint32_t)0x00008000)\r
-\r
-#define CRYP_CR_GCM_CCMPH ((uint32_t)0x00030000)\r
-#define CRYP_CR_GCM_CCMPH_0 ((uint32_t)0x00010000)\r
-#define CRYP_CR_GCM_CCMPH_1 ((uint32_t)0x00020000)\r
-#define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000) \r
-\r
-/****************** Bits definition for CRYP_SR register *********************/\r
-#define CRYP_SR_IFEM ((uint32_t)0x00000001)\r
-#define CRYP_SR_IFNF ((uint32_t)0x00000002)\r
-#define CRYP_SR_OFNE ((uint32_t)0x00000004)\r
-#define CRYP_SR_OFFU ((uint32_t)0x00000008)\r
-#define CRYP_SR_BUSY ((uint32_t)0x00000010)\r
-/****************** Bits definition for CRYP_DMACR register ******************/\r
-#define CRYP_DMACR_DIEN ((uint32_t)0x00000001)\r
-#define CRYP_DMACR_DOEN ((uint32_t)0x00000002)\r
-/***************** Bits definition for CRYP_IMSCR register ******************/\r
-#define CRYP_IMSCR_INIM ((uint32_t)0x00000001)\r
-#define CRYP_IMSCR_OUTIM ((uint32_t)0x00000002)\r
-/****************** Bits definition for CRYP_RISR register *******************/\r
-#define CRYP_RISR_OUTRIS ((uint32_t)0x00000001)\r
-#define CRYP_RISR_INRIS ((uint32_t)0x00000002)\r
-/****************** Bits definition for CRYP_MISR register *******************/\r
-#define CRYP_MISR_INMIS ((uint32_t)0x00000001)\r
-#define CRYP_MISR_OUTMIS ((uint32_t)0x00000002)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Digital to Analog Converter */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for DAC_CR register ********************/\r
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */\r
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */\r
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */\r
-\r
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */\r
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */\r
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */\r
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */\r
-\r
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
-\r
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */\r
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */\r
-\r
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */\r
-\r
-/***************** Bit definition for DAC_SWTRIGR register ******************/\r
-#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */\r
-#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */\r
-\r
-/***************** Bit definition for DAC_DHR12R1 register ******************/\r
-#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L1 register ******************/\r
-#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R1 register ******************/\r
-#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12R2 register ******************/\r
-#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12L2 register ******************/\r
-#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8R2 register ******************/\r
-#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12RD register ******************/\r
-#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */\r
-#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */\r
-\r
-/***************** Bit definition for DAC_DHR12LD register ******************/\r
-#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */\r
-#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */\r
-\r
-/****************** Bit definition for DAC_DHR8RD register ******************/\r
-#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */\r
-#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */\r
-\r
-/******************* Bit definition for DAC_DOR1 register *******************/\r
-#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */\r
-\r
-/******************* Bit definition for DAC_DOR2 register *******************/\r
-#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */\r
-\r
-/******************** Bit definition for DAC_SR register ********************/\r
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */\r
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Debug MCU */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DCMI */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bits definition for DCMI_CR register ******************/\r
-#define DCMI_CR_CAPTURE ((uint32_t)0x00000001)\r
-#define DCMI_CR_CM ((uint32_t)0x00000002)\r
-#define DCMI_CR_CROP ((uint32_t)0x00000004)\r
-#define DCMI_CR_JPEG ((uint32_t)0x00000008)\r
-#define DCMI_CR_ESS ((uint32_t)0x00000010)\r
-#define DCMI_CR_PCKPOL ((uint32_t)0x00000020)\r
-#define DCMI_CR_HSPOL ((uint32_t)0x00000040)\r
-#define DCMI_CR_VSPOL ((uint32_t)0x00000080)\r
-#define DCMI_CR_FCRC_0 ((uint32_t)0x00000100)\r
-#define DCMI_CR_FCRC_1 ((uint32_t)0x00000200)\r
-#define DCMI_CR_EDM_0 ((uint32_t)0x00000400)\r
-#define DCMI_CR_EDM_1 ((uint32_t)0x00000800)\r
-#define DCMI_CR_CRE ((uint32_t)0x00001000)\r
-#define DCMI_CR_ENABLE ((uint32_t)0x00004000)\r
-\r
-/******************** Bits definition for DCMI_SR register ******************/\r
-#define DCMI_SR_HSYNC ((uint32_t)0x00000001)\r
-#define DCMI_SR_VSYNC ((uint32_t)0x00000002)\r
-#define DCMI_SR_FNE ((uint32_t)0x00000004)\r
-\r
-/******************** Bits definition for DCMI_RISR register ****************/\r
-#define DCMI_RISR_FRAME_RIS ((uint32_t)0x00000001)\r
-#define DCMI_RISR_OVF_RIS ((uint32_t)0x00000002)\r
-#define DCMI_RISR_ERR_RIS ((uint32_t)0x00000004)\r
-#define DCMI_RISR_VSYNC_RIS ((uint32_t)0x00000008)\r
-#define DCMI_RISR_LINE_RIS ((uint32_t)0x00000010)\r
-\r
-/******************** Bits definition for DCMI_IER register *****************/\r
-#define DCMI_IER_FRAME_IE ((uint32_t)0x00000001)\r
-#define DCMI_IER_OVF_IE ((uint32_t)0x00000002)\r
-#define DCMI_IER_ERR_IE ((uint32_t)0x00000004)\r
-#define DCMI_IER_VSYNC_IE ((uint32_t)0x00000008)\r
-#define DCMI_IER_LINE_IE ((uint32_t)0x00000010)\r
-\r
-/******************** Bits definition for DCMI_MISR register ****************/\r
-#define DCMI_MISR_FRAME_MIS ((uint32_t)0x00000001)\r
-#define DCMI_MISR_OVF_MIS ((uint32_t)0x00000002)\r
-#define DCMI_MISR_ERR_MIS ((uint32_t)0x00000004)\r
-#define DCMI_MISR_VSYNC_MIS ((uint32_t)0x00000008)\r
-#define DCMI_MISR_LINE_MIS ((uint32_t)0x00000010)\r
-\r
-/******************** Bits definition for DCMI_ICR register *****************/\r
-#define DCMI_ICR_FRAME_ISC ((uint32_t)0x00000001)\r
-#define DCMI_ICR_OVF_ISC ((uint32_t)0x00000002)\r
-#define DCMI_ICR_ERR_ISC ((uint32_t)0x00000004)\r
-#define DCMI_ICR_VSYNC_ISC ((uint32_t)0x00000008)\r
-#define DCMI_ICR_LINE_ISC ((uint32_t)0x00000010)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DMA Controller */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bits definition for DMA_SxCR register *****************/ \r
-#define DMA_SxCR_CHSEL ((uint32_t)0x0E000000)\r
-#define DMA_SxCR_CHSEL_0 ((uint32_t)0x02000000)\r
-#define DMA_SxCR_CHSEL_1 ((uint32_t)0x04000000)\r
-#define DMA_SxCR_CHSEL_2 ((uint32_t)0x08000000) \r
-#define DMA_SxCR_MBURST ((uint32_t)0x01800000)\r
-#define DMA_SxCR_MBURST_0 ((uint32_t)0x00800000)\r
-#define DMA_SxCR_MBURST_1 ((uint32_t)0x01000000)\r
-#define DMA_SxCR_PBURST ((uint32_t)0x00600000)\r
-#define DMA_SxCR_PBURST_0 ((uint32_t)0x00200000)\r
-#define DMA_SxCR_PBURST_1 ((uint32_t)0x00400000)\r
-#define DMA_SxCR_ACK ((uint32_t)0x00100000)\r
-#define DMA_SxCR_CT ((uint32_t)0x00080000) \r
-#define DMA_SxCR_DBM ((uint32_t)0x00040000)\r
-#define DMA_SxCR_PL ((uint32_t)0x00030000)\r
-#define DMA_SxCR_PL_0 ((uint32_t)0x00010000)\r
-#define DMA_SxCR_PL_1 ((uint32_t)0x00020000)\r
-#define DMA_SxCR_PINCOS ((uint32_t)0x00008000)\r
-#define DMA_SxCR_MSIZE ((uint32_t)0x00006000)\r
-#define DMA_SxCR_MSIZE_0 ((uint32_t)0x00002000)\r
-#define DMA_SxCR_MSIZE_1 ((uint32_t)0x00004000)\r
-#define DMA_SxCR_PSIZE ((uint32_t)0x00001800)\r
-#define DMA_SxCR_PSIZE_0 ((uint32_t)0x00000800)\r
-#define DMA_SxCR_PSIZE_1 ((uint32_t)0x00001000)\r
-#define DMA_SxCR_MINC ((uint32_t)0x00000400)\r
-#define DMA_SxCR_PINC ((uint32_t)0x00000200)\r
-#define DMA_SxCR_CIRC ((uint32_t)0x00000100)\r
-#define DMA_SxCR_DIR ((uint32_t)0x000000C0)\r
-#define DMA_SxCR_DIR_0 ((uint32_t)0x00000040)\r
-#define DMA_SxCR_DIR_1 ((uint32_t)0x00000080)\r
-#define DMA_SxCR_PFCTRL ((uint32_t)0x00000020)\r
-#define DMA_SxCR_TCIE ((uint32_t)0x00000010)\r
-#define DMA_SxCR_HTIE ((uint32_t)0x00000008)\r
-#define DMA_SxCR_TEIE ((uint32_t)0x00000004)\r
-#define DMA_SxCR_DMEIE ((uint32_t)0x00000002)\r
-#define DMA_SxCR_EN ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for DMA_SxCNDTR register **************/\r
-#define DMA_SxNDT ((uint32_t)0x0000FFFF)\r
-#define DMA_SxNDT_0 ((uint32_t)0x00000001)\r
-#define DMA_SxNDT_1 ((uint32_t)0x00000002)\r
-#define DMA_SxNDT_2 ((uint32_t)0x00000004)\r
-#define DMA_SxNDT_3 ((uint32_t)0x00000008)\r
-#define DMA_SxNDT_4 ((uint32_t)0x00000010)\r
-#define DMA_SxNDT_5 ((uint32_t)0x00000020)\r
-#define DMA_SxNDT_6 ((uint32_t)0x00000040)\r
-#define DMA_SxNDT_7 ((uint32_t)0x00000080)\r
-#define DMA_SxNDT_8 ((uint32_t)0x00000100)\r
-#define DMA_SxNDT_9 ((uint32_t)0x00000200)\r
-#define DMA_SxNDT_10 ((uint32_t)0x00000400)\r
-#define DMA_SxNDT_11 ((uint32_t)0x00000800)\r
-#define DMA_SxNDT_12 ((uint32_t)0x00001000)\r
-#define DMA_SxNDT_13 ((uint32_t)0x00002000)\r
-#define DMA_SxNDT_14 ((uint32_t)0x00004000)\r
-#define DMA_SxNDT_15 ((uint32_t)0x00008000)\r
-\r
-/******************** Bits definition for DMA_SxFCR register ****************/ \r
-#define DMA_SxFCR_FEIE ((uint32_t)0x00000080)\r
-#define DMA_SxFCR_FS ((uint32_t)0x00000038)\r
-#define DMA_SxFCR_FS_0 ((uint32_t)0x00000008)\r
-#define DMA_SxFCR_FS_1 ((uint32_t)0x00000010)\r
-#define DMA_SxFCR_FS_2 ((uint32_t)0x00000020)\r
-#define DMA_SxFCR_DMDIS ((uint32_t)0x00000004)\r
-#define DMA_SxFCR_FTH ((uint32_t)0x00000003)\r
-#define DMA_SxFCR_FTH_0 ((uint32_t)0x00000001)\r
-#define DMA_SxFCR_FTH_1 ((uint32_t)0x00000002)\r
-\r
-/******************** Bits definition for DMA_LISR register *****************/ \r
-#define DMA_LISR_TCIF3 ((uint32_t)0x08000000)\r
-#define DMA_LISR_HTIF3 ((uint32_t)0x04000000)\r
-#define DMA_LISR_TEIF3 ((uint32_t)0x02000000)\r
-#define DMA_LISR_DMEIF3 ((uint32_t)0x01000000)\r
-#define DMA_LISR_FEIF3 ((uint32_t)0x00400000)\r
-#define DMA_LISR_TCIF2 ((uint32_t)0x00200000)\r
-#define DMA_LISR_HTIF2 ((uint32_t)0x00100000)\r
-#define DMA_LISR_TEIF2 ((uint32_t)0x00080000)\r
-#define DMA_LISR_DMEIF2 ((uint32_t)0x00040000)\r
-#define DMA_LISR_FEIF2 ((uint32_t)0x00010000)\r
-#define DMA_LISR_TCIF1 ((uint32_t)0x00000800)\r
-#define DMA_LISR_HTIF1 ((uint32_t)0x00000400)\r
-#define DMA_LISR_TEIF1 ((uint32_t)0x00000200)\r
-#define DMA_LISR_DMEIF1 ((uint32_t)0x00000100)\r
-#define DMA_LISR_FEIF1 ((uint32_t)0x00000040)\r
-#define DMA_LISR_TCIF0 ((uint32_t)0x00000020)\r
-#define DMA_LISR_HTIF0 ((uint32_t)0x00000010)\r
-#define DMA_LISR_TEIF0 ((uint32_t)0x00000008)\r
-#define DMA_LISR_DMEIF0 ((uint32_t)0x00000004)\r
-#define DMA_LISR_FEIF0 ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for DMA_HISR register *****************/ \r
-#define DMA_HISR_TCIF7 ((uint32_t)0x08000000)\r
-#define DMA_HISR_HTIF7 ((uint32_t)0x04000000)\r
-#define DMA_HISR_TEIF7 ((uint32_t)0x02000000)\r
-#define DMA_HISR_DMEIF7 ((uint32_t)0x01000000)\r
-#define DMA_HISR_FEIF7 ((uint32_t)0x00400000)\r
-#define DMA_HISR_TCIF6 ((uint32_t)0x00200000)\r
-#define DMA_HISR_HTIF6 ((uint32_t)0x00100000)\r
-#define DMA_HISR_TEIF6 ((uint32_t)0x00080000)\r
-#define DMA_HISR_DMEIF6 ((uint32_t)0x00040000)\r
-#define DMA_HISR_FEIF6 ((uint32_t)0x00010000)\r
-#define DMA_HISR_TCIF5 ((uint32_t)0x00000800)\r
-#define DMA_HISR_HTIF5 ((uint32_t)0x00000400)\r
-#define DMA_HISR_TEIF5 ((uint32_t)0x00000200)\r
-#define DMA_HISR_DMEIF5 ((uint32_t)0x00000100)\r
-#define DMA_HISR_FEIF5 ((uint32_t)0x00000040)\r
-#define DMA_HISR_TCIF4 ((uint32_t)0x00000020)\r
-#define DMA_HISR_HTIF4 ((uint32_t)0x00000010)\r
-#define DMA_HISR_TEIF4 ((uint32_t)0x00000008)\r
-#define DMA_HISR_DMEIF4 ((uint32_t)0x00000004)\r
-#define DMA_HISR_FEIF4 ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for DMA_LIFCR register ****************/ \r
-#define DMA_LIFCR_CTCIF3 ((uint32_t)0x08000000)\r
-#define DMA_LIFCR_CHTIF3 ((uint32_t)0x04000000)\r
-#define DMA_LIFCR_CTEIF3 ((uint32_t)0x02000000)\r
-#define DMA_LIFCR_CDMEIF3 ((uint32_t)0x01000000)\r
-#define DMA_LIFCR_CFEIF3 ((uint32_t)0x00400000)\r
-#define DMA_LIFCR_CTCIF2 ((uint32_t)0x00200000)\r
-#define DMA_LIFCR_CHTIF2 ((uint32_t)0x00100000)\r
-#define DMA_LIFCR_CTEIF2 ((uint32_t)0x00080000)\r
-#define DMA_LIFCR_CDMEIF2 ((uint32_t)0x00040000)\r
-#define DMA_LIFCR_CFEIF2 ((uint32_t)0x00010000)\r
-#define DMA_LIFCR_CTCIF1 ((uint32_t)0x00000800)\r
-#define DMA_LIFCR_CHTIF1 ((uint32_t)0x00000400)\r
-#define DMA_LIFCR_CTEIF1 ((uint32_t)0x00000200)\r
-#define DMA_LIFCR_CDMEIF1 ((uint32_t)0x00000100)\r
-#define DMA_LIFCR_CFEIF1 ((uint32_t)0x00000040)\r
-#define DMA_LIFCR_CTCIF0 ((uint32_t)0x00000020)\r
-#define DMA_LIFCR_CHTIF0 ((uint32_t)0x00000010)\r
-#define DMA_LIFCR_CTEIF0 ((uint32_t)0x00000008)\r
-#define DMA_LIFCR_CDMEIF0 ((uint32_t)0x00000004)\r
-#define DMA_LIFCR_CFEIF0 ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for DMA_HIFCR register ****************/ \r
-#define DMA_HIFCR_CTCIF7 ((uint32_t)0x08000000)\r
-#define DMA_HIFCR_CHTIF7 ((uint32_t)0x04000000)\r
-#define DMA_HIFCR_CTEIF7 ((uint32_t)0x02000000)\r
-#define DMA_HIFCR_CDMEIF7 ((uint32_t)0x01000000)\r
-#define DMA_HIFCR_CFEIF7 ((uint32_t)0x00400000)\r
-#define DMA_HIFCR_CTCIF6 ((uint32_t)0x00200000)\r
-#define DMA_HIFCR_CHTIF6 ((uint32_t)0x00100000)\r
-#define DMA_HIFCR_CTEIF6 ((uint32_t)0x00080000)\r
-#define DMA_HIFCR_CDMEIF6 ((uint32_t)0x00040000)\r
-#define DMA_HIFCR_CFEIF6 ((uint32_t)0x00010000)\r
-#define DMA_HIFCR_CTCIF5 ((uint32_t)0x00000800)\r
-#define DMA_HIFCR_CHTIF5 ((uint32_t)0x00000400)\r
-#define DMA_HIFCR_CTEIF5 ((uint32_t)0x00000200)\r
-#define DMA_HIFCR_CDMEIF5 ((uint32_t)0x00000100)\r
-#define DMA_HIFCR_CFEIF5 ((uint32_t)0x00000040)\r
-#define DMA_HIFCR_CTCIF4 ((uint32_t)0x00000020)\r
-#define DMA_HIFCR_CHTIF4 ((uint32_t)0x00000010)\r
-#define DMA_HIFCR_CTEIF4 ((uint32_t)0x00000008)\r
-#define DMA_HIFCR_CDMEIF4 ((uint32_t)0x00000004)\r
-#define DMA_HIFCR_CFEIF4 ((uint32_t)0x00000001)\r
-\r
-#if defined (STM32F429X)\r
-/******************************************************************************/\r
-/* */\r
-/* AHB Master DMA2D Controller (DMA2D) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for DMA2D_CR register ******************/\r
-\r
-#define DMA2D_CR_START ((uint32_t)0x00000001) /*!< Start transfer */\r
-#define DMA2D_CR_SUSP ((uint32_t)0x00000002) /*!< Suspend transfer */\r
-#define DMA2D_CR_ABORT ((uint32_t)0x00000004) /*!< Abort transfer */\r
-#define DMA2D_CR_TEIE ((uint32_t)0x00000100) /*!< Transfer Error Interrupt Enable */\r
-#define DMA2D_CR_TCIE ((uint32_t)0x00000200) /*!< Transfer Complete Interrupt Enable */\r
-#define DMA2D_CR_TWIE ((uint32_t)0x00000400) /*!< Transfer Watermark Interrupt Enable */\r
-#define DMA2D_CR_CAEIE ((uint32_t)0x00000800) /*!< CLUT Access Error Interrupt Enable */\r
-#define DMA2D_CR_CTCIE ((uint32_t)0x00001000) /*!< CLUT Transfer Complete Interrupt Enable */\r
-#define DMA2D_CR_CEIE ((uint32_t)0x00002000) /*!< Configuration Error Interrupt Enable */\r
-#define DMA2D_CR_MODE ((uint32_t)0x00030000) /*!< DMA2D Mode */\r
-\r
-/******************** Bit definition for DMA2D_ISR register *****************/\r
-\r
-#define DMA2D_ISR_TEIF ((uint32_t)0x00000001) /*!< Transfer Error Interrupt Flag */\r
-#define DMA2D_ISR_TCIF ((uint32_t)0x00000002) /*!< Transfer Complete Interrupt Flag */\r
-#define DMA2D_ISR_TWIF ((uint32_t)0x00000004) /*!< Transfer Watermark Interrupt Flag */\r
-#define DMA2D_ISR_CAEIF ((uint32_t)0x00000008) /*!< CLUT Access Error Interrupt Flag */\r
-#define DMA2D_ISR_CTCIF ((uint32_t)0x00000010) /*!< CLUT Transfer Complete Interrupt Flag */\r
-#define DMA2D_ISR_CEIF ((uint32_t)0x00000020) /*!< Configuration Error Interrupt Flag */\r
-\r
-/******************** Bit definition for DMA2D_IFSR register ****************/\r
-\r
-#define DMA2D_IFSR_CTEIF ((uint32_t)0x00000001) /*!< Clears Transfer Error Interrupt Flag */\r
-#define DMA2D_IFSR_CTCIF ((uint32_t)0x00000002) /*!< Clears Transfer Complete Interrupt Flag */\r
-#define DMA2D_IFSR_CTWIF ((uint32_t)0x00000004) /*!< Clears Transfer Watermark Interrupt Flag */\r
-#define DMA2D_IFSR_CCAEIF ((uint32_t)0x00000008) /*!< Clears CLUT Access Error Interrupt Flag */\r
-#define DMA2D_IFSR_CCTCIF ((uint32_t)0x00000010) /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
-#define DMA2D_IFSR_CCEIF ((uint32_t)0x00000020) /*!< Clears Configuration Error Interrupt Flag */\r
-\r
-/******************** Bit definition for DMA2D_FGMAR register ***************/\r
-\r
-#define DMA2D_FGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************** Bit definition for DMA2D_FGOR register ****************/\r
-\r
-#define DMA2D_FGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
-\r
-/******************** Bit definition for DMA2D_BGMAR register ***************/\r
-\r
-#define DMA2D_BGMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************** Bit definition for DMA2D_BGOR register ****************/\r
-\r
-#define DMA2D_BGOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
-\r
-/******************** Bit definition for DMA2D_FGPFCCR register *************/\r
-\r
-#define DMA2D_FGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
-#define DMA2D_FGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
-#define DMA2D_FGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
-#define DMA2D_FGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
-#define DMA2D_FGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha mode */\r
-#define DMA2D_FGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
-\r
-/******************** Bit definition for DMA2D_FGCOLR register **************/\r
-\r
-#define DMA2D_FGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
-#define DMA2D_FGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
-#define DMA2D_FGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */ \r
-\r
-/******************** Bit definition for DMA2D_BGPFCCR register *************/\r
-\r
-#define DMA2D_BGPFCCR_CM ((uint32_t)0x0000000F) /*!< Color mode */\r
-#define DMA2D_BGPFCCR_CCM ((uint32_t)0x00000010) /*!< CLUT Color mode */\r
-#define DMA2D_BGPFCCR_START ((uint32_t)0x00000020) /*!< Start */\r
-#define DMA2D_BGPFCCR_CS ((uint32_t)0x0000FF00) /*!< CLUT size */\r
-#define DMA2D_BGPFCCR_AM ((uint32_t)0x00030000) /*!< Alpha Mode */\r
-#define DMA2D_BGPFCCR_ALPHA ((uint32_t)0xFF000000) /*!< Alpha value */\r
-\r
-/******************** Bit definition for DMA2D_BGCOLR register **************/\r
-\r
-#define DMA2D_BGCOLR_BLUE ((uint32_t)0x000000FF) /*!< Blue Value */\r
-#define DMA2D_BGCOLR_GREEN ((uint32_t)0x0000FF00) /*!< Green Value */\r
-#define DMA2D_BGCOLR_RED ((uint32_t)0x00FF0000) /*!< Red Value */\r
-\r
-/******************** Bit definition for DMA2D_FGCMAR register **************/\r
-\r
-#define DMA2D_FGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************** Bit definition for DMA2D_BGCMAR register **************/\r
-\r
-#define DMA2D_BGCMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************** Bit definition for DMA2D_OPFCCR register **************/\r
-\r
-#define DMA2D_OPFCCR_CM ((uint32_t)0x00000007) /*!< Color mode */\r
-\r
-/******************** Bit definition for DMA2D_OCOLR register ***************/\r
-\r
-/*!<Mode_ARGB8888/RGB888 */\r
-\r
-#define DMA2D_OCOLR_BLUE_1 ((uint32_t)0x000000FF) /*!< BLUE Value */\r
-#define DMA2D_OCOLR_GREEN_1 ((uint32_t)0x0000FF00) /*!< GREEN Value */\r
-#define DMA2D_OCOLR_RED_1 ((uint32_t)0x00FF0000) /*!< Red Value */\r
-#define DMA2D_OCOLR_ALPHA_1 ((uint32_t)0xFF000000) /*!< Alpha Channel Value */\r
-\r
-/*!<Mode_RGB565 */\r
-#define DMA2D_OCOLR_BLUE_2 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
-#define DMA2D_OCOLR_GREEN_2 ((uint32_t)0x000007E0) /*!< GREEN Value */\r
-#define DMA2D_OCOLR_RED_2 ((uint32_t)0x0000F800) /*!< Red Value */\r
-\r
-/*!<Mode_ARGB1555 */\r
-#define DMA2D_OCOLR_BLUE_3 ((uint32_t)0x0000001F) /*!< BLUE Value */\r
-#define DMA2D_OCOLR_GREEN_3 ((uint32_t)0x000003E0) /*!< GREEN Value */\r
-#define DMA2D_OCOLR_RED_3 ((uint32_t)0x00007C00) /*!< Red Value */\r
-#define DMA2D_OCOLR_ALPHA_3 ((uint32_t)0x00008000) /*!< Alpha Channel Value */\r
-\r
-/*!<Mode_ARGB4444 */\r
-#define DMA2D_OCOLR_BLUE_4 ((uint32_t)0x0000000F) /*!< BLUE Value */\r
-#define DMA2D_OCOLR_GREEN_4 ((uint32_t)0x000000F0) /*!< GREEN Value */\r
-#define DMA2D_OCOLR_RED_4 ((uint32_t)0x00000F00) /*!< Red Value */\r
-#define DMA2D_OCOLR_ALPHA_4 ((uint32_t)0x0000F000) /*!< Alpha Channel Value */\r
-\r
-/******************** Bit definition for DMA2D_OMAR register ****************/\r
-\r
-#define DMA2D_OMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */\r
-\r
-/******************** Bit definition for DMA2D_OOR register *****************/\r
-\r
-#define DMA2D_OOR_LO ((uint32_t)0x00003FFF) /*!< Line Offset */\r
-\r
-/******************** Bit definition for DMA2D_NLR register *****************/\r
-\r
-#define DMA2D_NLR_NL ((uint32_t)0x0000FFFF) /*!< Number of Lines */\r
-#define DMA2D_NLR_PL ((uint32_t)0x3FFF0000) /*!< Pixel per Lines */\r
-\r
-/******************** Bit definition for DMA2D_LWR register *****************/\r
-\r
-#define DMA2D_LWR_LW ((uint32_t)0x0000FFFF) /*!< Line Watermark */\r
-\r
-/******************** Bit definition for DMA2D_AMTCR register ***************/\r
-\r
-#define DMA2D_AMTCR_EN ((uint32_t)0x00000001) /*!< Enable */\r
-#define DMA2D_AMTCR_DT ((uint32_t)0x0000FF00) /*!< Dead Time */\r
-\r
-\r
-\r
-/******************** Bit definition for DMA2D_FGCLUT register **************/\r
- \r
-/******************** Bit definition for DMA2D_BGCLUT register **************/\r
-#endif /* STM32F429X */\r
-\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* External Interrupt/Event Controller */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for EXTI_IMR register *******************/\r
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */\r
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */\r
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */\r
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */\r
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */\r
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */\r
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */\r
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */\r
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */\r
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */\r
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */\r
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */\r
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */\r
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */\r
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */\r
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */\r
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */\r
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */\r
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */\r
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */\r
-\r
-/******************* Bit definition for EXTI_EMR register *******************/\r
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */\r
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */\r
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */\r
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */\r
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */\r
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */\r
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */\r
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */\r
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */\r
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */\r
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */\r
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */\r
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */\r
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */\r
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */\r
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */\r
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */\r
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */\r
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */\r
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */\r
-\r
-/****************** Bit definition for EXTI_RTSR register *******************/\r
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */\r
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */\r
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */\r
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */\r
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */\r
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */\r
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */\r
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */\r
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */\r
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */\r
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */\r
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */\r
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */\r
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */\r
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */\r
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */\r
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */\r
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */\r
-#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */\r
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */\r
-\r
-/****************** Bit definition for EXTI_FTSR register *******************/\r
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */\r
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */\r
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */\r
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */\r
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */\r
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */\r
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */\r
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */\r
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */\r
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */\r
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */\r
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */\r
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */\r
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */\r
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */\r
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */\r
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */\r
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */\r
-#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */\r
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */\r
-\r
-/****************** Bit definition for EXTI_SWIER register ******************/\r
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */\r
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */\r
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */\r
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */\r
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */\r
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */\r
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */\r
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */\r
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */\r
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */\r
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */\r
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */\r
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */\r
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */\r
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */\r
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */\r
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */\r
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */\r
-#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */\r
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */\r
-\r
-/******************* Bit definition for EXTI_PR register ********************/\r
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */\r
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */\r
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */\r
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */\r
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */\r
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */\r
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */\r
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */\r
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */\r
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */\r
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */\r
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */\r
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */\r
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */\r
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */\r
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */\r
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */\r
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */\r
-#define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */\r
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* FLASH */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bits definition for FLASH_ACR register *****************/\r
-#define FLASH_ACR_LATENCY ((uint32_t)0x0000000F)\r
-#define FLASH_ACR_LATENCY_0WS ((uint32_t)0x00000000)\r
-#define FLASH_ACR_LATENCY_1WS ((uint32_t)0x00000001)\r
-#define FLASH_ACR_LATENCY_2WS ((uint32_t)0x00000002)\r
-#define FLASH_ACR_LATENCY_3WS ((uint32_t)0x00000003)\r
-#define FLASH_ACR_LATENCY_4WS ((uint32_t)0x00000004)\r
-#define FLASH_ACR_LATENCY_5WS ((uint32_t)0x00000005)\r
-#define FLASH_ACR_LATENCY_6WS ((uint32_t)0x00000006)\r
-#define FLASH_ACR_LATENCY_7WS ((uint32_t)0x00000007)\r
-\r
-#if defined (STM32F429X)\r
-#define FLASH_ACR_LATENCY_8WS ((uint32_t)0x00000008)\r
-#define FLASH_ACR_LATENCY_9WS ((uint32_t)0x00000009)\r
-#define FLASH_ACR_LATENCY_10WS ((uint32_t)0x0000000A)\r
-#define FLASH_ACR_LATENCY_11WS ((uint32_t)0x0000000B)\r
-#define FLASH_ACR_LATENCY_12WS ((uint32_t)0x0000000C)\r
-#define FLASH_ACR_LATENCY_13WS ((uint32_t)0x0000000D)\r
-#define FLASH_ACR_LATENCY_14WS ((uint32_t)0x0000000E)\r
-#define FLASH_ACR_LATENCY_15WS ((uint32_t)0x0000000F)\r
-#endif /* STM32F429X */\r
-\r
-#define FLASH_ACR_PRFTEN ((uint32_t)0x00000100)\r
-#define FLASH_ACR_ICEN ((uint32_t)0x00000200)\r
-#define FLASH_ACR_DCEN ((uint32_t)0x00000400)\r
-#define FLASH_ACR_ICRST ((uint32_t)0x00000800)\r
-#define FLASH_ACR_DCRST ((uint32_t)0x00001000)\r
-#define FLASH_ACR_BYTE0_ADDRESS ((uint32_t)0x40023C00)\r
-#define FLASH_ACR_BYTE2_ADDRESS ((uint32_t)0x40023C03)\r
-\r
-/******************* Bits definition for FLASH_SR register ******************/\r
-#define FLASH_SR_EOP ((uint32_t)0x00000001)\r
-#define FLASH_SR_SOP ((uint32_t)0x00000002)\r
-#define FLASH_SR_WRPERR ((uint32_t)0x00000010)\r
-#define FLASH_SR_PGAERR ((uint32_t)0x00000020)\r
-#define FLASH_SR_PGPERR ((uint32_t)0x00000040)\r
-#define FLASH_SR_PGSERR ((uint32_t)0x00000080)\r
-#define FLASH_SR_BSY ((uint32_t)0x00010000)\r
-\r
-/******************* Bits definition for FLASH_CR register ******************/\r
-#define FLASH_CR_PG ((uint32_t)0x00000001)\r
-#define FLASH_CR_SER ((uint32_t)0x00000002)\r
-#define FLASH_CR_MER ((uint32_t)0x00000004)\r
-#define FLASH_CR_MER1 FLASH_CR_MER\r
-#define FLASH_CR_SNB ((uint32_t)0x000000F8)\r
-#define FLASH_CR_SNB_0 ((uint32_t)0x00000008)\r
-#define FLASH_CR_SNB_1 ((uint32_t)0x00000010)\r
-#define FLASH_CR_SNB_2 ((uint32_t)0x00000020)\r
-#define FLASH_CR_SNB_3 ((uint32_t)0x00000040)\r
-#define FLASH_CR_SNB_4 ((uint32_t)0x00000040)\r
-#define FLASH_CR_PSIZE ((uint32_t)0x00000300)\r
-#define FLASH_CR_PSIZE_0 ((uint32_t)0x00000100)\r
-#define FLASH_CR_PSIZE_1 ((uint32_t)0x00000200)\r
-#define FLASH_CR_MER2 ((uint32_t)0x00008000)\r
-#define FLASH_CR_STRT ((uint32_t)0x00010000)\r
-#define FLASH_CR_EOPIE ((uint32_t)0x01000000)\r
-#define FLASH_CR_LOCK ((uint32_t)0x80000000)\r
-\r
-/******************* Bits definition for FLASH_OPTCR register ***************/\r
-#define FLASH_OPTCR_OPTLOCK ((uint32_t)0x00000001)\r
-#define FLASH_OPTCR_OPTSTRT ((uint32_t)0x00000002)\r
-#define FLASH_OPTCR_BOR_LEV_0 ((uint32_t)0x00000004)\r
-#define FLASH_OPTCR_BOR_LEV_1 ((uint32_t)0x00000008)\r
-#define FLASH_OPTCR_BOR_LEV ((uint32_t)0x0000000C)\r
-\r
-#if defined (STM32F429X)\r
-#define FLASH_OPTCR_BFB2 ((uint32_t)0x00000010)\r
-#endif /* STM32F429X */\r
-\r
-#define FLASH_OPTCR_WDG_SW ((uint32_t)0x00000020)\r
-#define FLASH_OPTCR_nRST_STOP ((uint32_t)0x00000040)\r
-#define FLASH_OPTCR_nRST_STDBY ((uint32_t)0x00000080)\r
-#define FLASH_OPTCR_RDP ((uint32_t)0x0000FF00)\r
-#define FLASH_OPTCR_RDP_0 ((uint32_t)0x00000100)\r
-#define FLASH_OPTCR_RDP_1 ((uint32_t)0x00000200)\r
-#define FLASH_OPTCR_RDP_2 ((uint32_t)0x00000400)\r
-#define FLASH_OPTCR_RDP_3 ((uint32_t)0x00000800)\r
-#define FLASH_OPTCR_RDP_4 ((uint32_t)0x00001000)\r
-#define FLASH_OPTCR_RDP_5 ((uint32_t)0x00002000)\r
-#define FLASH_OPTCR_RDP_6 ((uint32_t)0x00004000)\r
-#define FLASH_OPTCR_RDP_7 ((uint32_t)0x00008000)\r
-#define FLASH_OPTCR_nWRP ((uint32_t)0x0FFF0000)\r
-#define FLASH_OPTCR_nWRP_0 ((uint32_t)0x00010000)\r
-#define FLASH_OPTCR_nWRP_1 ((uint32_t)0x00020000)\r
-#define FLASH_OPTCR_nWRP_2 ((uint32_t)0x00040000)\r
-#define FLASH_OPTCR_nWRP_3 ((uint32_t)0x00080000)\r
-#define FLASH_OPTCR_nWRP_4 ((uint32_t)0x00100000)\r
-#define FLASH_OPTCR_nWRP_5 ((uint32_t)0x00200000)\r
-#define FLASH_OPTCR_nWRP_6 ((uint32_t)0x00400000)\r
-#define FLASH_OPTCR_nWRP_7 ((uint32_t)0x00800000)\r
-#define FLASH_OPTCR_nWRP_8 ((uint32_t)0x01000000)\r
-#define FLASH_OPTCR_nWRP_9 ((uint32_t)0x02000000)\r
-#define FLASH_OPTCR_nWRP_10 ((uint32_t)0x04000000)\r
-#define FLASH_OPTCR_nWRP_11 ((uint32_t)0x08000000)\r
-\r
-#if defined (STM32F429X)\r
-#define FLASH_OPTCR_DB1M ((uint32_t)0x40000000) \r
-#define FLASH_OPTCR_SPRMOD ((uint32_t)0x80000000) \r
-#endif /* STM32F429X */\r
- \r
-/****************** Bits definition for FLASH_OPTCR1 register ***************/\r
-#define FLASH_OPTCR1_nWRP ((uint32_t)0x0FFF0000)\r
-#define FLASH_OPTCR1_nWRP_0 ((uint32_t)0x00010000)\r
-#define FLASH_OPTCR1_nWRP_1 ((uint32_t)0x00020000)\r
-#define FLASH_OPTCR1_nWRP_2 ((uint32_t)0x00040000)\r
-#define FLASH_OPTCR1_nWRP_3 ((uint32_t)0x00080000)\r
-#define FLASH_OPTCR1_nWRP_4 ((uint32_t)0x00100000)\r
-#define FLASH_OPTCR1_nWRP_5 ((uint32_t)0x00200000)\r
-#define FLASH_OPTCR1_nWRP_6 ((uint32_t)0x00400000)\r
-#define FLASH_OPTCR1_nWRP_7 ((uint32_t)0x00800000)\r
-#define FLASH_OPTCR1_nWRP_8 ((uint32_t)0x01000000)\r
-#define FLASH_OPTCR1_nWRP_9 ((uint32_t)0x02000000)\r
-#define FLASH_OPTCR1_nWRP_10 ((uint32_t)0x04000000)\r
-#define FLASH_OPTCR1_nWRP_11 ((uint32_t)0x08000000)\r
-\r
-#if defined (STM32F40XX) || defined (STM32F427X)\r
-/******************************************************************************/\r
-/* */\r
-/* Flexible Static Memory Controller */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bit definition for FSMC_BCR1 register *******************/\r
-#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR2 register *******************/\r
-#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR3 register *******************/\r
-#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BCR4 register *******************/\r
-#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FSMC_BTR1 register ******************/\r
-#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BTR2 register *******************/\r
-#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for FSMC_BTR3 register *******************/\r
-#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BTR4 register *******************/\r
-#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR1 register ******************/\r
-#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR2 register ******************/\r
-#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
-#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR3 register ******************/\r
-#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_BWTR4 register ******************/\r
-#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FSMC_PCR2 register *******************/\r
-#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
-#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FSMC_PCR3 register *******************/\r
-#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FSMC_PCR4 register *******************/\r
-#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/******************* Bit definition for FSMC_SR2 register *******************/\r
-#define FSMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FSMC_SR3 register *******************/\r
-#define FSMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FSMC_SR4 register *******************/\r
-#define FSMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FSMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FSMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FSMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FSMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FSMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FSMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/****************** Bit definition for FSMC_PMEM2 register ******************/\r
-#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
-#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
-#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
-#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
-#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PMEM3 register ******************/\r
-#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
-#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
-#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
-#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
-#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PMEM4 register ******************/\r
-#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
-#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
-#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
-#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
-#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT2 register ******************/\r
-#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
-#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
-#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
-#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
-#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT3 register ******************/\r
-#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
-#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
-#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
-#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
-#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PATT4 register ******************/\r
-#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
-#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
-#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
-#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
-#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_PIO4 register *******************/\r
-#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
-#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
-#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
-#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
-#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FSMC_ECCR2 register ******************/\r
-#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-\r
-/****************** Bit definition for FSMC_ECCR3 register ******************/\r
-#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-/******************************************************************************/\r
-/* */\r
-/* Flexible Memory Controller */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bit definition for FMC_BCR1 register *******************/\r
-#define FMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_BCR1_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FMC_BCR1_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-#define FMC_BCR1_CCLKEN ((uint32_t)0x00100000) /*!<Continous clock enable */\r
-\r
-/****************** Bit definition for FMC_BCR2 register *******************/\r
-#define FMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_BCR2_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FMC_BCR2_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FMC_BCR3 register *******************/\r
-#define FMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_BCR3_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FMC_BCR3_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FMC_BCR4 register *******************/\r
-#define FMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!<Memory bank enable bit */\r
-#define FMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!<Address/data multiplexing enable bit */\r
-\r
-#define FMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!<MTYP[1:0] bits (Memory type) */\r
-#define FMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_BCR4_MWID ((uint32_t)0x00000030) /*!<MWID[1:0] bits (Memory data bus width) */\r
-#define FMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!<Flash access enable */\r
-#define FMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!<Burst enable bit */\r
-#define FMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!<Wait signal polarity bit */\r
-#define FMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!<Wrapped burst mode support */\r
-#define FMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!<Wait timing configuration */\r
-#define FMC_BCR4_WREN ((uint32_t)0x00001000) /*!<Write enable bit */\r
-#define FMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!<Wait enable bit */\r
-#define FMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!<Extended mode enable */\r
-#define FMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!<Asynchronous wait */\r
-#define FMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!<Write burst enable */\r
-\r
-/****************** Bit definition for FMC_BTR1 register ******************/\r
-#define FMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BTR2 register *******************/\r
-#define FMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for FMC_BTR3 register *******************/\r
-#define FMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BTR4 register *******************/\r
-#define FMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
-#define FMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BWTR1 register ******************/\r
-#define FMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BWTR1_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BWTR1_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BWTR1_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BWTR1_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BWTR2 register ******************/\r
-#define FMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BWTR2_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BWTR2_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BWTR2_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BWTR2_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1*/\r
-#define FMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BWTR3 register ******************/\r
-#define FMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BWTR3_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BWTR3_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BWTR3_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BWTR3_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_BWTR4 register ******************/\r
-#define FMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
-#define FMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
-#define FMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!<DATAST [3:0] bits (Data-phase duration) */\r
-#define FMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_BWTR4_DATAST_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_BWTR4_DATAST_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_BWTR4_DATAST_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_BWTR4_DATAST_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
-#define FMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-#define FMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!<DATLA[3:0] bits (Data latency) */\r
-#define FMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-\r
-#define FMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!<ACCMOD[1:0] bits (Access mode) */\r
-#define FMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!<Bit 0 */\r
-#define FMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_PCR2 register *******************/\r
-#define FMC_PCR2_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FMC_PCR2_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FMC_PCR2_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FMC_PCR2_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FMC_PCR2_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_PCR2_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_PCR2_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FMC_PCR2_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR2_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FMC_PCR2_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FMC_PCR2_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FMC_PCR2_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FMC_PCR2_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR2_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[1:0] bits (ECC page size) */\r
-#define FMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FMC_PCR3 register *******************/\r
-#define FMC_PCR3_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FMC_PCR3_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FMC_PCR3_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FMC_PCR3_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FMC_PCR3_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_PCR3_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_PCR3_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FMC_PCR3_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR3_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FMC_PCR3_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FMC_PCR3_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FMC_PCR3_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FMC_PCR3_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR3_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FMC_PCR4 register *******************/\r
-#define FMC_PCR4_PWAITEN ((uint32_t)0x00000002) /*!<Wait feature enable bit */\r
-#define FMC_PCR4_PBKEN ((uint32_t)0x00000004) /*!<PC Card/NAND Flash memory bank enable bit */\r
-#define FMC_PCR4_PTYP ((uint32_t)0x00000008) /*!<Memory type */\r
-\r
-#define FMC_PCR4_PWID ((uint32_t)0x00000030) /*!<PWID[1:0] bits (NAND Flash databus width) */\r
-#define FMC_PCR4_PWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_PCR4_PWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_PCR4_ECCEN ((uint32_t)0x00000040) /*!<ECC computation logic enable bit */\r
-\r
-#define FMC_PCR4_TCLR ((uint32_t)0x00001E00) /*!<TCLR[3:0] bits (CLE to RE delay) */\r
-#define FMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /*!<Bit 0 */\r
-#define FMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /*!<Bit 1 */\r
-#define FMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /*!<Bit 2 */\r
-#define FMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR4_TAR ((uint32_t)0x0001E000) /*!<TAR[3:0] bits (ALE to RE delay) */\r
-#define FMC_PCR4_TAR_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FMC_PCR4_TAR_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-#define FMC_PCR4_TAR_2 ((uint32_t)0x00008000) /*!<Bit 2 */\r
-#define FMC_PCR4_TAR_3 ((uint32_t)0x00010000) /*!<Bit 3 */\r
-\r
-#define FMC_PCR4_ECCPS ((uint32_t)0x000E0000) /*!<ECCPS[2:0] bits (ECC page size) */\r
-#define FMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /*!<Bit 0 */\r
-#define FMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /*!<Bit 1 */\r
-#define FMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /*!<Bit 2 */\r
-\r
-/******************* Bit definition for FMC_SR2 register *******************/\r
-#define FMC_SR2_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FMC_SR2_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FMC_SR2_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FMC_SR2_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FMC_SR2_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FMC_SR2_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FMC_SR2_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FMC_SR3 register *******************/\r
-#define FMC_SR3_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FMC_SR3_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FMC_SR3_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FMC_SR3_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FMC_SR3_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FMC_SR3_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FMC_SR3_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/******************* Bit definition for FMC_SR4 register *******************/\r
-#define FMC_SR4_IRS ((uint8_t)0x01) /*!<Interrupt Rising Edge status */\r
-#define FMC_SR4_ILS ((uint8_t)0x02) /*!<Interrupt Level status */\r
-#define FMC_SR4_IFS ((uint8_t)0x04) /*!<Interrupt Falling Edge status */\r
-#define FMC_SR4_IREN ((uint8_t)0x08) /*!<Interrupt Rising Edge detection Enable bit */\r
-#define FMC_SR4_ILEN ((uint8_t)0x10) /*!<Interrupt Level detection Enable bit */\r
-#define FMC_SR4_IFEN ((uint8_t)0x20) /*!<Interrupt Falling Edge detection Enable bit */\r
-#define FMC_SR4_FEMPT ((uint8_t)0x40) /*!<FIFO empty */\r
-\r
-/****************** Bit definition for FMC_PMEM2 register ******************/\r
-#define FMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
-#define FMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
-#define FMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
-#define FMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
-#define FMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PMEM3 register ******************/\r
-#define FMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
-#define FMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
-#define FMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
-#define FMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
-#define FMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PMEM4 register ******************/\r
-#define FMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
-#define FMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
-#define FMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
-#define FMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
-#define FMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PATT2 register ******************/\r
-#define FMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
-#define FMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
-#define FMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
-#define FMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
-#define FMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PATT3 register ******************/\r
-#define FMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
-#define FMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
-#define FMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
-#define FMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
-#define FMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PATT4 register ******************/\r
-#define FMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
-#define FMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
-#define FMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
-#define FMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
-#define FMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_PIO4 register *******************/\r
-#define FMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
-#define FMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define FMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define FMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define FMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define FMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define FMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
-#define FMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define FMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define FMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define FMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-#define FMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /*!<Bit 7 */\r
-\r
-#define FMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
-#define FMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-#define FMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /*!<Bit 3 */\r
-#define FMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /*!<Bit 4 */\r
-#define FMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /*!<Bit 5 */\r
-#define FMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /*!<Bit 6 */\r
-#define FMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /*!<Bit 7 */\r
-\r
-#define FMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
-#define FMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-#define FMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /*!<Bit 3 */\r
-#define FMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /*!<Bit 4 */\r
-#define FMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /*!<Bit 5 */\r
-#define FMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /*!<Bit 6 */\r
-#define FMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /*!<Bit 7 */\r
-\r
-/****************** Bit definition for FMC_ECCR2 register ******************/\r
-#define FMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-\r
-/****************** Bit definition for FMC_ECCR3 register ******************/\r
-#define FMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /*!<ECC result */\r
-\r
-/****************** Bit definition for FMC_SDCR1 register ******************/\r
-#define FMC_SDCR1_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
-#define FMC_SDCR1_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_SDCR1_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR1_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
-#define FMC_SDCR1_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_SDCR1_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR1_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
-#define FMC_SDCR1_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_SDCR1_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR1_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
-\r
-#define FMC_SDCR1_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
-#define FMC_SDCR1_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
-#define FMC_SDCR1_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR1_WP ((uint32_t)0x00000200) /*!<Write protection */\r
-\r
-#define FMC_SDCR1_SDCLK ((uint32_t)0x00000C00) /*!<SDRAM clock configuration */\r
-#define FMC_SDCR1_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define FMC_SDCR1_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR1_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
-\r
-#define FMC_SDCR1_RPIPE ((uint32_t)0x00006000) /*!<Write protection */\r
-#define FMC_SDCR1_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FMC_SDCR1_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_SDCR2 register ******************/\r
-#define FMC_SDCR2_NC ((uint32_t)0x00000003) /*!<NC[1:0] bits (Number of column bits) */\r
-#define FMC_SDCR2_NC_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_SDCR2_NC_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR2_NR ((uint32_t)0x0000000C) /*!<NR[1:0] bits (Number of row bits) */\r
-#define FMC_SDCR2_NR_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define FMC_SDCR2_NR_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR2_MWID ((uint32_t)0x00000030) /*!<NR[1:0] bits (Number of row bits) */\r
-#define FMC_SDCR2_MWID_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_SDCR2_MWID_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR2_NB ((uint32_t)0x00000040) /*!<Number of internal bank */\r
-\r
-#define FMC_SDCR2_CAS ((uint32_t)0x00000180) /*!<CAS[1:0] bits (CAS latency) */\r
-#define FMC_SDCR2_CAS_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
-#define FMC_SDCR2_CAS_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR2_WP ((uint32_t)0x00000200) /*!<Write protection */\r
-\r
-#define FMC_SDCR2_SDCLK ((uint32_t)0x00000C00) /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
-#define FMC_SDCR2_SDCLK_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define FMC_SDCR2_SDCLK_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-\r
-#define FMC_SDCR2_RBURST ((uint32_t)0x00001000) /*!<Read burst */\r
-\r
-#define FMC_SDCR2_RPIPE ((uint32_t)0x00006000) /*!<RPIPE[1:0](Read pipe) */\r
-#define FMC_SDCR2_RPIPE_0 ((uint32_t)0x00002000) /*!<Bit 0 */\r
-#define FMC_SDCR2_RPIPE_1 ((uint32_t)0x00004000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for FMC_SDTR1 register ******************/\r
-#define FMC_SDTR1_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
-#define FMC_SDTR1_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_SDTR1_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_SDTR1_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_SDTR1_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
- \r
-#define FMC_SDTR1_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
-#define FMC_SDTR1_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_SDTR1_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_SDTR1_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_SDTR1_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_SDTR1_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
-#define FMC_SDTR1_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_SDTR1_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_SDTR1_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_SDTR1_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FMC_SDTR1_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
-#define FMC_SDTR1_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define FMC_SDTR1_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define FMC_SDTR1_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR1_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
-#define FMC_SDTR1_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_SDTR1_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_SDTR1_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR1_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
-#define FMC_SDTR1_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_SDTR1_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_SDTR1_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR1_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
-#define FMC_SDTR1_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_SDTR1_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_SDTR1_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FMC_SDTR2 register ******************/\r
-#define FMC_SDTR2_TMRD ((uint32_t)0x0000000F) /*!<TMRD[3:0] bits (Load mode register to active) */\r
-#define FMC_SDTR2_TMRD_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_SDTR2_TMRD_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_SDTR2_TMRD_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define FMC_SDTR2_TMRD_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
- \r
-#define FMC_SDTR2_TXSR ((uint32_t)0x000000F0) /*!<TXSR[3:0] bits (Exit self refresh) */\r
-#define FMC_SDTR2_TXSR_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define FMC_SDTR2_TXSR_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-#define FMC_SDTR2_TXSR_2 ((uint32_t)0x00000040) /*!<Bit 2 */\r
-#define FMC_SDTR2_TXSR_3 ((uint32_t)0x00000080) /*!<Bit 3 */\r
-\r
-#define FMC_SDTR2_TRAS ((uint32_t)0x00000F00) /*!<TRAS[3:0] bits (Self refresh time) */\r
-#define FMC_SDTR2_TRAS_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define FMC_SDTR2_TRAS_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define FMC_SDTR2_TRAS_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define FMC_SDTR2_TRAS_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define FMC_SDTR2_TRC ((uint32_t)0x0000F000) /*!<TRC[2:0] bits (Row cycle delay) */\r
-#define FMC_SDTR2_TRC_0 ((uint32_t)0x00001000) /*!<Bit 0 */\r
-#define FMC_SDTR2_TRC_1 ((uint32_t)0x00002000) /*!<Bit 1 */\r
-#define FMC_SDTR2_TRC_2 ((uint32_t)0x00004000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR2_TWR ((uint32_t)0x000F0000) /*!<TRC[2:0] bits (Write recovery delay) */\r
-#define FMC_SDTR2_TWR_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define FMC_SDTR2_TWR_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define FMC_SDTR2_TWR_2 ((uint32_t)0x00040000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR2_TRP ((uint32_t)0x00F00000) /*!<TRP[2:0] bits (Row precharge delay) */\r
-#define FMC_SDTR2_TRP_0 ((uint32_t)0x00100000) /*!<Bit 0 */\r
-#define FMC_SDTR2_TRP_1 ((uint32_t)0x00200000) /*!<Bit 1 */\r
-#define FMC_SDTR2_TRP_2 ((uint32_t)0x00400000) /*!<Bit 2 */\r
-\r
-#define FMC_SDTR2_TRCD ((uint32_t)0x0F000000) /*!<TRP[2:0] bits (Row to column delay) */\r
-#define FMC_SDTR2_TRCD_0 ((uint32_t)0x01000000) /*!<Bit 0 */\r
-#define FMC_SDTR2_TRCD_1 ((uint32_t)0x02000000) /*!<Bit 1 */\r
-#define FMC_SDTR2_TRCD_2 ((uint32_t)0x04000000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for FMC_SDCMR register ******************/\r
-#define FMC_SDCMR_MODE ((uint32_t)0x00000007) /*!<MODE[2:0] bits (Command mode) */\r
-#define FMC_SDCMR_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define FMC_SDCMR_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define FMC_SDCMR_MODE_2 ((uint32_t)0x00000003) /*!<Bit 2 */\r
- \r
-#define FMC_SDCMR_CTB2 ((uint32_t)0x00000008) /*!<Command target 2 */\r
-\r
-#define FMC_SDCMR_CTB1 ((uint32_t)0x00000010) /*!<Command target 1 */\r
-\r
-#define FMC_SDCMR_NRFS ((uint32_t)0x000001E0) /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
-#define FMC_SDCMR_NRFS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define FMC_SDCMR_NRFS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define FMC_SDCMR_NRFS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-#define FMC_SDCMR_NRFS_3 ((uint32_t)0x00000100) /*!<Bit 3 */\r
-\r
-#define FMC_SDCMR_MRD ((uint32_t)0x003FFE00) /*!<MRD[12:0] bits (Mode register definition) */\r
-\r
-/****************** Bit definition for FMC_SDRTR register ******************/\r
-#define FMC_SDRTR_CRE ((uint32_t)0x00000001) /*!<Clear refresh error flag */\r
-\r
-#define FMC_SDRTR_COUNT ((uint32_t)0x00003FFE) /*!<COUNT[12:0] bits (Refresh timer count) */\r
-\r
-#define FMC_SDRTR_REIE ((uint32_t)0x00004000) /*!<RES interupt enable */\r
-\r
-/****************** Bit definition for FMC_SDSR register ******************/\r
-#define FMC_SDSR_RE ((uint32_t)0x00000001) /*!<Refresh error flag */\r
-\r
-#define FMC_SDSR_MODES1 ((uint32_t)0x00000006) /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
-#define FMC_SDSR_MODES1_0 ((uint32_t)0x00000002) /*!<Bit 0 */\r
-#define FMC_SDSR_MODES1_1 ((uint32_t)0x00000004) /*!<Bit 1 */\r
-\r
-#define FMC_SDSR_MODES2 ((uint32_t)0x00000018) /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
-#define FMC_SDSR_MODES2_0 ((uint32_t)0x00000008) /*!<Bit 0 */\r
-#define FMC_SDSR_MODES2_1 ((uint32_t)0x00000010) /*!<Bit 1 */\r
-\r
-#define FMC_SDSR_BUSY ((uint32_t)0x00000020) /*!<Busy status */\r
-\r
-#endif /* STM32F429X */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* General Purpose I/O */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bits definition for GPIO_MODER register *****************/\r
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)\r
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)\r
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)\r
-\r
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)\r
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)\r
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)\r
-\r
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)\r
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)\r
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)\r
-\r
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)\r
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)\r
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)\r
-\r
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)\r
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)\r
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)\r
-\r
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)\r
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)\r
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)\r
-\r
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)\r
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)\r
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)\r
-\r
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)\r
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)\r
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)\r
-\r
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)\r
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)\r
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)\r
-\r
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)\r
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)\r
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)\r
-\r
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)\r
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)\r
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)\r
-\r
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)\r
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)\r
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)\r
-\r
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)\r
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)\r
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)\r
-\r
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)\r
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)\r
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)\r
-\r
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)\r
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)\r
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)\r
-\r
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)\r
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)\r
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)\r
-\r
-/****************** Bits definition for GPIO_OTYPER register ****************/\r
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)\r
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)\r
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)\r
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)\r
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)\r
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)\r
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)\r
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)\r
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)\r
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)\r
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)\r
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)\r
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)\r
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)\r
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)\r
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)\r
-\r
-/****************** Bits definition for GPIO_OSPEEDR register ***************/\r
-#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)\r
-#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)\r
-#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)\r
-#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)\r
-#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)\r
-#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)\r
-#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)\r
-#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)\r
-#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)\r
-#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)\r
-#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)\r
-#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)\r
-#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)\r
-#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)\r
-#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)\r
-#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)\r
-#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)\r
-#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)\r
-#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)\r
-#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)\r
-#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)\r
-#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)\r
-#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)\r
-#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)\r
-#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)\r
-#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)\r
-#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)\r
-#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)\r
-#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)\r
-#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)\r
-#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)\r
-\r
-#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)\r
-#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)\r
-#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)\r
-\r
-/****************** Bits definition for GPIO_PUPDR register *****************/\r
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)\r
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)\r
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)\r
-\r
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)\r
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)\r
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)\r
-\r
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)\r
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)\r
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)\r
-\r
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)\r
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)\r
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)\r
-\r
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)\r
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)\r
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)\r
-\r
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)\r
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)\r
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)\r
-\r
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)\r
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)\r
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)\r
-\r
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)\r
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)\r
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)\r
-\r
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)\r
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)\r
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)\r
-\r
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)\r
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)\r
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)\r
-\r
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)\r
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)\r
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)\r
-\r
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)\r
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)\r
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)\r
-\r
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)\r
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)\r
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)\r
-\r
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)\r
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)\r
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)\r
-\r
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)\r
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)\r
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)\r
-\r
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)\r
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)\r
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)\r
-\r
-/****************** Bits definition for GPIO_IDR register *******************/\r
-#define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)\r
-#define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)\r
-#define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)\r
-#define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)\r
-#define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)\r
-#define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)\r
-#define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)\r
-#define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)\r
-#define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)\r
-#define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)\r
-#define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)\r
-#define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)\r
-#define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)\r
-#define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)\r
-#define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)\r
-#define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)\r
-/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
-#define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0\r
-#define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1\r
-#define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2\r
-#define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3\r
-#define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4\r
-#define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5\r
-#define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6\r
-#define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7\r
-#define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8\r
-#define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9\r
-#define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10\r
-#define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11\r
-#define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12\r
-#define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13\r
-#define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14\r
-#define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15\r
-\r
-/****************** Bits definition for GPIO_ODR register *******************/\r
-#define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)\r
-#define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)\r
-#define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)\r
-#define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)\r
-#define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)\r
-#define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)\r
-#define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)\r
-#define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)\r
-#define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)\r
-#define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)\r
-#define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)\r
-#define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)\r
-#define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)\r
-#define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)\r
-#define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)\r
-#define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)\r
-/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
-#define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0\r
-#define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1\r
-#define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2\r
-#define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3\r
-#define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4\r
-#define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5\r
-#define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6\r
-#define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7\r
-#define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8\r
-#define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9\r
-#define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10\r
-#define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11\r
-#define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12\r
-#define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13\r
-#define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14\r
-#define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15\r
-\r
-/****************** Bits definition for GPIO_BSRR register ******************/\r
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)\r
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)\r
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)\r
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)\r
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)\r
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)\r
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)\r
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)\r
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)\r
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)\r
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)\r
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)\r
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)\r
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)\r
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)\r
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)\r
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)\r
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)\r
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)\r
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)\r
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)\r
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)\r
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)\r
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)\r
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)\r
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)\r
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)\r
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)\r
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)\r
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)\r
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)\r
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* HASH */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bits definition for HASH_CR register ********************/\r
-#define HASH_CR_INIT ((uint32_t)0x00000004)\r
-#define HASH_CR_DMAE ((uint32_t)0x00000008)\r
-#define HASH_CR_DATATYPE ((uint32_t)0x00000030)\r
-#define HASH_CR_DATATYPE_0 ((uint32_t)0x00000010)\r
-#define HASH_CR_DATATYPE_1 ((uint32_t)0x00000020)\r
-#define HASH_CR_MODE ((uint32_t)0x00000040)\r
-#define HASH_CR_ALGO ((uint32_t)0x00040080)\r
-#define HASH_CR_ALGO_0 ((uint32_t)0x00000080)\r
-#define HASH_CR_ALGO_1 ((uint32_t)0x00040000)\r
-#define HASH_CR_NBW ((uint32_t)0x00000F00)\r
-#define HASH_CR_NBW_0 ((uint32_t)0x00000100)\r
-#define HASH_CR_NBW_1 ((uint32_t)0x00000200)\r
-#define HASH_CR_NBW_2 ((uint32_t)0x00000400)\r
-#define HASH_CR_NBW_3 ((uint32_t)0x00000800)\r
-#define HASH_CR_DINNE ((uint32_t)0x00001000)\r
-#define HASH_CR_MDMAT ((uint32_t)0x00002000)\r
-#define HASH_CR_LKEY ((uint32_t)0x00010000)\r
-\r
-/****************** Bits definition for HASH_STR register *******************/\r
-#define HASH_STR_NBW ((uint32_t)0x0000001F)\r
-#define HASH_STR_NBW_0 ((uint32_t)0x00000001)\r
-#define HASH_STR_NBW_1 ((uint32_t)0x00000002)\r
-#define HASH_STR_NBW_2 ((uint32_t)0x00000004)\r
-#define HASH_STR_NBW_3 ((uint32_t)0x00000008)\r
-#define HASH_STR_NBW_4 ((uint32_t)0x00000010)\r
-#define HASH_STR_DCAL ((uint32_t)0x00000100)\r
-\r
-/****************** Bits definition for HASH_IMR register *******************/\r
-#define HASH_IMR_DINIM ((uint32_t)0x00000001)\r
-#define HASH_IMR_DCIM ((uint32_t)0x00000002)\r
-\r
-/****************** Bits definition for HASH_SR register ********************/\r
-#define HASH_SR_DINIS ((uint32_t)0x00000001)\r
-#define HASH_SR_DCIS ((uint32_t)0x00000002)\r
-#define HASH_SR_DMAS ((uint32_t)0x00000004)\r
-#define HASH_SR_BUSY ((uint32_t)0x00000008)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Inter-integrated Circuit Interface */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for I2C_CR1 register ********************/\r
-#define I2C_CR1_PE ((uint16_t)0x0001) /*!<Peripheral Enable */\r
-#define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!<SMBus Mode */\r
-#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!<SMBus Type */\r
-#define I2C_CR1_ENARP ((uint16_t)0x0010) /*!<ARP Enable */\r
-#define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!<PEC Enable */\r
-#define I2C_CR1_ENGC ((uint16_t)0x0040) /*!<General Call Enable */\r
-#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!<Clock Stretching Disable (Slave mode) */\r
-#define I2C_CR1_START ((uint16_t)0x0100) /*!<Start Generation */\r
-#define I2C_CR1_STOP ((uint16_t)0x0200) /*!<Stop Generation */\r
-#define I2C_CR1_ACK ((uint16_t)0x0400) /*!<Acknowledge Enable */\r
-#define I2C_CR1_POS ((uint16_t)0x0800) /*!<Acknowledge/PEC Position (for data reception) */\r
-#define I2C_CR1_PEC ((uint16_t)0x1000) /*!<Packet Error Checking */\r
-#define I2C_CR1_ALERT ((uint16_t)0x2000) /*!<SMBus Alert */\r
-#define I2C_CR1_SWRST ((uint16_t)0x8000) /*!<Software Reset */\r
-\r
-/******************* Bit definition for I2C_CR2 register ********************/\r
-#define I2C_CR2_FREQ ((uint16_t)0x003F) /*!<FREQ[5:0] bits (Peripheral Clock Frequency) */\r
-#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-\r
-#define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!<Error Interrupt Enable */\r
-#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!<Event Interrupt Enable */\r
-#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!<Buffer Interrupt Enable */\r
-#define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!<DMA Requests Enable */\r
-#define I2C_CR2_LAST ((uint16_t)0x1000) /*!<DMA Last Transfer */\r
-\r
-/******************* Bit definition for I2C_OAR1 register *******************/\r
-#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!<Interface Address */\r
-#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!<Interface Address */\r
-\r
-#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!<Bit 8 */\r
-#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!<Bit 9 */\r
-\r
-#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!<Addressing Mode (Slave mode) */\r
-\r
-/******************* Bit definition for I2C_OAR2 register *******************/\r
-#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!<Dual addressing mode enable */\r
-#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!<Interface address */\r
-\r
-/******************** Bit definition for I2C_DR register ********************/\r
-#define I2C_DR_DR ((uint8_t)0xFF) /*!<8-bit Data Register */\r
-\r
-/******************* Bit definition for I2C_SR1 register ********************/\r
-#define I2C_SR1_SB ((uint16_t)0x0001) /*!<Start Bit (Master mode) */\r
-#define I2C_SR1_ADDR ((uint16_t)0x0002) /*!<Address sent (master mode)/matched (slave mode) */\r
-#define I2C_SR1_BTF ((uint16_t)0x0004) /*!<Byte Transfer Finished */\r
-#define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!<10-bit header sent (Master mode) */\r
-#define I2C_SR1_STOPF ((uint16_t)0x0010) /*!<Stop detection (Slave mode) */\r
-#define I2C_SR1_RXNE ((uint16_t)0x0040) /*!<Data Register not Empty (receivers) */\r
-#define I2C_SR1_TXE ((uint16_t)0x0080) /*!<Data Register Empty (transmitters) */\r
-#define I2C_SR1_BERR ((uint16_t)0x0100) /*!<Bus Error */\r
-#define I2C_SR1_ARLO ((uint16_t)0x0200) /*!<Arbitration Lost (master mode) */\r
-#define I2C_SR1_AF ((uint16_t)0x0400) /*!<Acknowledge Failure */\r
-#define I2C_SR1_OVR ((uint16_t)0x0800) /*!<Overrun/Underrun */\r
-#define I2C_SR1_PECERR ((uint16_t)0x1000) /*!<PEC Error in reception */\r
-#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!<Timeout or Tlow Error */\r
-#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!<SMBus Alert */\r
-\r
-/******************* Bit definition for I2C_SR2 register ********************/\r
-#define I2C_SR2_MSL ((uint16_t)0x0001) /*!<Master/Slave */\r
-#define I2C_SR2_BUSY ((uint16_t)0x0002) /*!<Bus Busy */\r
-#define I2C_SR2_TRA ((uint16_t)0x0004) /*!<Transmitter/Receiver */\r
-#define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!<General Call Address (Slave mode) */\r
-#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!<SMBus Device Default Address (Slave mode) */\r
-#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!<SMBus Host Header (Slave mode) */\r
-#define I2C_SR2_DUALF ((uint16_t)0x0080) /*!<Dual Flag (Slave mode) */\r
-#define I2C_SR2_PEC ((uint16_t)0xFF00) /*!<Packet Error Checking Register */\r
-\r
-/******************* Bit definition for I2C_CCR register ********************/\r
-#define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
-#define I2C_CCR_DUTY ((uint16_t)0x4000) /*!<Fast Mode Duty Cycle */\r
-#define I2C_CCR_FS ((uint16_t)0x8000) /*!<I2C Master Mode Selection */\r
-\r
-/****************** Bit definition for I2C_TRISE register *******************/\r
-#define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
-\r
-/****************** Bit definition for I2C_FLTR register *******************/\r
-#define I2C_FLTR_DNF ((uint8_t)0x0F) /*!<Digital Noise Filter */\r
-#define I2C_FLTR_ANOFF ((uint8_t)0x10) /*!<Analog Noise Filter OFF */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Independent WATCHDOG */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for IWDG_KR register ********************/\r
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!<Key value (write only, read 0000h) */\r
-\r
-/******************* Bit definition for IWDG_PR register ********************/\r
-#define IWDG_PR_PR ((uint8_t)0x07) /*!<PR[2:0] (Prescaler divider) */\r
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!<Bit 2 */\r
-\r
-/******************* Bit definition for IWDG_RLR register *******************/\r
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!<Watchdog counter reload value */\r
-\r
-/******************* Bit definition for IWDG_SR register ********************/\r
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!<Watchdog prescaler value update */\r
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!<Watchdog counter reload value update */\r
-\r
-#if defined (STM32F429X)\r
-/******************************************************************************/\r
-/* */\r
-/* LCD-TFT Display Controller (LTDC) */\r
-/* */\r
-/******************************************************************************/\r
-\r
-/******************** Bit definition for LTDC_SSCR register *****************/\r
-\r
-#define LTDC_SSCR_VSH ((uint32_t)0x000007FF) /*!< Vertical Synchronization Height */\r
-#define LTDC_SSCR_HSW ((uint32_t)0x0FFF0000) /*!< Horizontal Synchronization Width */\r
-\r
-/******************** Bit definition for LTDC_BPCR register *****************/\r
-\r
-#define LTDC_BPCR_AVBP ((uint32_t)0x000007FF) /*!< Accumulated Vertical Back Porch */\r
-#define LTDC_BPCR_AHBP ((uint32_t)0x0FFF0000) /*!< Accumulated Horizontal Back Porch */\r
-\r
-/******************** Bit definition for LTDC_AWCR register *****************/\r
-\r
-#define LTDC_AWCR_AAH ((uint32_t)0x000007FF) /*!< Accumulated Active heigh */\r
-#define LTDC_AWCR_AAW ((uint32_t)0x0FFF0000) /*!< Accumulated Active Width */\r
-\r
-/******************** Bit definition for LTDC_TWCR register *****************/\r
-\r
-#define LTDC_TWCR_TOTALH ((uint32_t)0x000007FF) /*!< Total Heigh */\r
-#define LTDC_TWCR_TOTALW ((uint32_t)0x0FFF0000) /*!< Total Width */\r
-\r
-/******************** Bit definition for LTDC_GCR register ******************/\r
-\r
-#define LTDC_GCR_LTDCEN ((uint32_t)0x00000001) /*!< LCD-TFT controller enable bit */\r
-#define LTDC_GCR_DBW ((uint32_t)0x00000070) /*!< Dither Blue Width */\r
-#define LTDC_GCR_DGW ((uint32_t)0x00000700) /*!< Dither Green Width */\r
-#define LTDC_GCR_DRW ((uint32_t)0x00007000) /*!< Dither Red Width */\r
-#define LTDC_GCR_DTEN ((uint32_t)0x00010000) /*!< Dither Enable */\r
-#define LTDC_GCR_PCPOL ((uint32_t)0x10000000) /*!< Pixel Clock Polarity */\r
-#define LTDC_GCR_DEPOL ((uint32_t)0x20000000) /*!< Data Enable Polarity */\r
-#define LTDC_GCR_VSPOL ((uint32_t)0x40000000) /*!< Vertical Synchronization Polarity */\r
-#define LTDC_GCR_HSPOL ((uint32_t)0x80000000) /*!< Horizontal Synchronization Polarity */\r
-\r
-/******************** Bit definition for LTDC_SRCR register *****************/\r
-\r
-#define LTDC_SRCR_IMR ((uint32_t)0x00000001) /*!< Immediate Reload */\r
-#define LTDC_SRCR_VBR ((uint32_t)0x00000002) /*!< Vertical Blanking Reload */\r
-\r
-/******************** Bit definition for LTDC_BCCR register *****************/\r
-\r
-#define LTDC_BCCR_BCBLUE ((uint32_t)0x000000FF) /*!< Background Blue value */\r
-#define LTDC_BCCR_BCGREEN ((uint32_t)0x0000FF00) /*!< Background Green value */\r
-#define LTDC_BCCR_BCRED ((uint32_t)0x00FF0000) /*!< Background Red value */\r
-\r
-/******************** Bit definition for LTDC_IER register ******************/\r
-\r
-#define LTDC_IER_LIE ((uint32_t)0x00000001) /*!< Line Interrupt Enable */\r
-#define LTDC_IER_FUIE ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Enable */\r
-#define LTDC_IER_TERRIE ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Enable */\r
-#define LTDC_IER_RRIE ((uint32_t)0x00000008) /*!< Register Reload interrupt enable */\r
-\r
-/******************** Bit definition for LTDC_ISR register ******************/\r
-\r
-#define LTDC_ISR_LIF ((uint32_t)0x00000001) /*!< Line Interrupt Flag */\r
-#define LTDC_ISR_FUIF ((uint32_t)0x00000002) /*!< FIFO Underrun Interrupt Flag */\r
-#define LTDC_ISR_TERRIF ((uint32_t)0x00000004) /*!< Transfer Error Interrupt Flag */\r
-#define LTDC_ISR_RRIF ((uint32_t)0x00000008) /*!< Register Reload interrupt Flag */\r
-\r
-/******************** Bit definition for LTDC_ICR register ******************/\r
-\r
-#define LTDC_ICR_CLIF ((uint32_t)0x00000001) /*!< Clears the Line Interrupt Flag */\r
-#define LTDC_ICR_CFUIF ((uint32_t)0x00000002) /*!< Clears the FIFO Underrun Interrupt Flag */\r
-#define LTDC_ICR_CTERRIF ((uint32_t)0x00000004) /*!< Clears the Transfer Error Interrupt Flag */\r
-#define LTDC_ICR_CRRIF ((uint32_t)0x00000008) /*!< Clears Register Reload interrupt Flag */\r
-\r
-/******************** Bit definition for LTDC_LIPCR register ****************/\r
-\r
-#define LTDC_LIPCR_LIPOS ((uint32_t)0x000007FF) /*!< Line Interrupt Position */\r
-\r
-/******************** Bit definition for LTDC_CPSR register *****************/\r
-\r
-#define LTDC_CPSR_CYPOS ((uint32_t)0x0000FFFF) /*!< Current Y Position */\r
-#define LTDC_CPSR_CXPOS ((uint32_t)0xFFFF0000) /*!< Current X Position */\r
-\r
-/******************** Bit definition for LTDC_CDSR register *****************/\r
-\r
-#define LTDC_CDSR_VDES ((uint32_t)0x00000001) /*!< Vertical Data Enable Status */\r
-#define LTDC_CDSR_HDES ((uint32_t)0x00000002) /*!< Horizontal Data Enable Status */\r
-#define LTDC_CDSR_VSYNCS ((uint32_t)0x00000004) /*!< Vertical Synchronization Status */\r
-#define LTDC_CDSR_HSYNCS ((uint32_t)0x00000008) /*!< Horizontal Synchronization Status */\r
-\r
-/******************** Bit definition for LTDC_LxCR register *****************/\r
-\r
-#define LTDC_LxCR_LEN ((uint32_t)0x00000001) /*!< Layer Enable */\r
-#define LTDC_LxCR_COLKEN ((uint32_t)0x00000002) /*!< Color Keying Enable */\r
-#define LTDC_LxCR_CLUTEN ((uint32_t)0x00000010) /*!< Color Lockup Table Enable */\r
-\r
-/******************** Bit definition for LTDC_LxWHPCR register **************/\r
-\r
-#define LTDC_LxWHPCR_WHSTPOS ((uint32_t)0x00000FFF) /*!< Window Horizontal Start Position */\r
-#define LTDC_LxWHPCR_WHSPPOS ((uint32_t)0xFFFF0000) /*!< Window Horizontal Stop Position */\r
-\r
-/******************** Bit definition for LTDC_LxWVPCR register **************/\r
-\r
-#define LTDC_LxWVPCR_WVSTPOS ((uint32_t)0x00000FFF) /*!< Window Vertical Start Position */\r
-#define LTDC_LxWVPCR_WVSPPOS ((uint32_t)0xFFFF0000) /*!< Window Vertical Stop Position */\r
-\r
-/******************** Bit definition for LTDC_LxCKCR register ***************/\r
-\r
-#define LTDC_LxCKCR_CKBLUE ((uint32_t)0x000000FF) /*!< Color Key Blue value */\r
-#define LTDC_LxCKCR_CKGREEN ((uint32_t)0x0000FF00) /*!< Color Key Green value */\r
-#define LTDC_LxCKCR_CKRED ((uint32_t)0x00FF0000) /*!< Color Key Red value */\r
-\r
-/******************** Bit definition for LTDC_LxPFCR register ***************/\r
-\r
-#define LTDC_LxPFCR_PF ((uint32_t)0x00000007) /*!< Pixel Format */\r
-\r
-/******************** Bit definition for LTDC_LxCACR register ***************/\r
-\r
-#define LTDC_LxCACR_CONSTA ((uint32_t)0x000000FF) /*!< Constant Alpha */\r
-\r
-/******************** Bit definition for LTDC_LxDCCR register ***************/\r
-\r
-#define LTDC_LxDCCR_DCBLUE ((uint32_t)0x000000FF) /*!< Default Color Blue */\r
-#define LTDC_LxDCCR_DCGREEN ((uint32_t)0x0000FF00) /*!< Default Color Green */\r
-#define LTDC_LxDCCR_DCRED ((uint32_t)0x00FF0000) /*!< Default Color Red */\r
-#define LTDC_LxDCCR_DCALPHA ((uint32_t)0xFF000000) /*!< Default Color Alpha */\r
- \r
-/******************** Bit definition for LTDC_LxBFCR register ***************/\r
-\r
-#define LTDC_LxBFCR_BF2 ((uint32_t)0x00000007) /*!< Blending Factor 2 */\r
-#define LTDC_LxBFCR_BF1 ((uint32_t)0x00000700) /*!< Blending Factor 1 */\r
-\r
-/******************** Bit definition for LTDC_LxCFBAR register **************/\r
-\r
-#define LTDC_LxCFBAR_CFBADD ((uint32_t)0xFFFFFFFF) /*!< Color Frame Buffer Start Address */\r
-\r
-/******************** Bit definition for LTDC_LxCFBLR register **************/\r
-\r
-#define LTDC_LxCFBLR_CFBLL ((uint32_t)0x00001FFF) /*!< Color Frame Buffer Line Length */\r
-#define LTDC_LxCFBLR_CFBP ((uint32_t)0x1FFF0000) /*!< Color Frame Buffer Pitch in bytes */\r
-\r
-/******************** Bit definition for LTDC_LxCFBLNR register *************/\r
-\r
-#define LTDC_LxCFBLNR_CFBLNBR ((uint32_t)0x000007FF) /*!< Frame Buffer Line Number */\r
-\r
-/******************** Bit definition for LTDC_LxCLUTWR register *************/\r
-\r
-#define LTDC_LxCLUTWR_BLUE ((uint32_t)0x000000FF) /*!< Blue value */\r
-#define LTDC_LxCLUTWR_GREEN ((uint32_t)0x0000FF00) /*!< Green value */\r
-#define LTDC_LxCLUTWR_RED ((uint32_t)0x00FF0000) /*!< Red value */\r
-#define LTDC_LxCLUTWR_CLUTADD ((uint32_t)0xFF000000) /*!< CLUT address */\r
-#endif /* STM32F429X */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Power Control */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for PWR_CR register ********************/\r
-#define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-Power Deepsleep */\r
-#define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */\r
-#define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */\r
-#define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */\r
-#define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */\r
-\r
-#define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */\r
-#define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */\r
-#define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */\r
-#define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */\r
-\r
-/*!< PVD level configuration */\r
-#define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */\r
-#define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */\r
-#define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */\r
-#define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */\r
-#define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */\r
-#define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */\r
-#define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */\r
-#define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */\r
-\r
-#define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */\r
-#define PWR_CR_FPDS ((uint32_t)0x00000200) /*!< Flash power down in Stop mode */\r
-\r
-#if defined (STM32F429X)\r
-#define PWR_CR_LPLVDS ((uint32_t)0x00000400) /*!< Low-Power Regulator Low Voltage Scaling in Stop mode */\r
-#define PWR_CR_MRLVDS ((uint32_t)0x00000800) /*!< Main regulator Low Voltage Scaling in Stop mode */\r
-#endif /* STM32F429X */\r
-\r
-#define PWR_CR_ADCDC1 ((uint32_t)0x00002000) /*!< Refer to AN4073 on how to use this bit */ \r
-\r
-#define PWR_CR_VOS ((uint32_t)0x0000C000) /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
-#define PWR_CR_VOS_0 ((uint32_t)0x00004000) /*!< Bit 0 */\r
-#define PWR_CR_VOS_1 ((uint32_t)0x00008000) /*!< Bit 1 */\r
-\r
-#if defined (STM32F429X)\r
-#define PWR_CR_ODEN ((uint32_t)0x00010000) /*!< Over Drive enable */\r
-#define PWR_CR_ODSWEN ((uint32_t)0x00020000) /*!< Over Drive switch enabled */\r
-#define PWR_CR_UDEN ((uint32_t)0x000C0000) /*!< Under Drive enable in stop mode */\r
-#define PWR_CR_UDEN_0 ((uint32_t)0x00040000) /*!< Bit 0 */\r
-#define PWR_CR_UDEN_1 ((uint32_t)0x00080000) /*!< Bit 1 */\r
-#endif /* STM32F429X */\r
-\r
-/* Legacy define */\r
-#define PWR_CR_PMODE PWR_CR_VOS\r
-\r
-/******************* Bit definition for PWR_CSR register ********************/\r
-#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */\r
-#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */\r
-#define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */\r
-#define PWR_CSR_BRR ((uint32_t)0x00000008) /*!< Backup regulator ready */\r
-#define PWR_CSR_EWUP ((uint32_t)0x00000100) /*!< Enable WKUP pin */\r
-#define PWR_CSR_BRE ((uint32_t)0x00000200) /*!< Backup regulator enable */\r
-#define PWR_CSR_VOSRDY ((uint32_t)0x00004000) /*!< Regulator voltage scaling output selection ready */\r
-\r
-#if defined (STM32F429X)\r
-#define PWR_CSR_ODRDY ((uint32_t)0x00010000) /*!< Over Drive generator ready */\r
-#define PWR_CSR_ODSWRDY ((uint32_t)0x00020000) /*!< Over Drive Switch ready */\r
-#define PWR_CSR_UDSWRDY ((uint32_t)0x000C0000) /*!< Under Drive ready */\r
-#endif /* STM32F429X */\r
-/* Legacy define */\r
-#define PWR_CSR_REGRDY PWR_CSR_VOSRDY\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Reset and Clock Control */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for RCC_CR register ********************/\r
-#define RCC_CR_HSION ((uint32_t)0x00000001)\r
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002)\r
-\r
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)\r
-#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */\r
-#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */\r
-#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */\r
-#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */\r
-#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */\r
-\r
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)\r
-#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */\r
-#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */\r
-#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */\r
-#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */\r
-#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */\r
-#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */\r
-#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */\r
-#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */\r
-\r
-#define RCC_CR_HSEON ((uint32_t)0x00010000)\r
-#define RCC_CR_HSERDY ((uint32_t)0x00020000)\r
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000)\r
-#define RCC_CR_CSSON ((uint32_t)0x00080000)\r
-#define RCC_CR_PLLON ((uint32_t)0x01000000)\r
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000)\r
-#define RCC_CR_PLLI2SON ((uint32_t)0x04000000)\r
-#define RCC_CR_PLLI2SRDY ((uint32_t)0x08000000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_CR_PLLSAION ((uint32_t)0x10000000)\r
-#define RCC_CR_PLLSAIRDY ((uint32_t)0x20000000)\r
-#endif /* STM32F429X */\r
-\r
-/******************** Bit definition for RCC_PLLCFGR register ***************/\r
-#define RCC_PLLCFGR_PLLM ((uint32_t)0x0000003F)\r
-#define RCC_PLLCFGR_PLLM_0 ((uint32_t)0x00000001)\r
-#define RCC_PLLCFGR_PLLM_1 ((uint32_t)0x00000002)\r
-#define RCC_PLLCFGR_PLLM_2 ((uint32_t)0x00000004)\r
-#define RCC_PLLCFGR_PLLM_3 ((uint32_t)0x00000008)\r
-#define RCC_PLLCFGR_PLLM_4 ((uint32_t)0x00000010)\r
-#define RCC_PLLCFGR_PLLM_5 ((uint32_t)0x00000020)\r
-\r
-#define RCC_PLLCFGR_PLLN ((uint32_t)0x00007FC0)\r
-#define RCC_PLLCFGR_PLLN_0 ((uint32_t)0x00000040)\r
-#define RCC_PLLCFGR_PLLN_1 ((uint32_t)0x00000080)\r
-#define RCC_PLLCFGR_PLLN_2 ((uint32_t)0x00000100)\r
-#define RCC_PLLCFGR_PLLN_3 ((uint32_t)0x00000200)\r
-#define RCC_PLLCFGR_PLLN_4 ((uint32_t)0x00000400)\r
-#define RCC_PLLCFGR_PLLN_5 ((uint32_t)0x00000800)\r
-#define RCC_PLLCFGR_PLLN_6 ((uint32_t)0x00001000)\r
-#define RCC_PLLCFGR_PLLN_7 ((uint32_t)0x00002000)\r
-#define RCC_PLLCFGR_PLLN_8 ((uint32_t)0x00004000)\r
-\r
-#define RCC_PLLCFGR_PLLP ((uint32_t)0x00030000)\r
-#define RCC_PLLCFGR_PLLP_0 ((uint32_t)0x00010000)\r
-#define RCC_PLLCFGR_PLLP_1 ((uint32_t)0x00020000)\r
-\r
-#define RCC_PLLCFGR_PLLSRC ((uint32_t)0x00400000)\r
-#define RCC_PLLCFGR_PLLSRC_HSE ((uint32_t)0x00400000)\r
-#define RCC_PLLCFGR_PLLSRC_HSI ((uint32_t)0x00000000)\r
-\r
-#define RCC_PLLCFGR_PLLQ ((uint32_t)0x0F000000)\r
-#define RCC_PLLCFGR_PLLQ_0 ((uint32_t)0x01000000)\r
-#define RCC_PLLCFGR_PLLQ_1 ((uint32_t)0x02000000)\r
-#define RCC_PLLCFGR_PLLQ_2 ((uint32_t)0x04000000)\r
-#define RCC_PLLCFGR_PLLQ_3 ((uint32_t)0x08000000)\r
-\r
-/******************** Bit definition for RCC_CFGR register ******************/\r
-/*!< SW configuration */\r
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */\r
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */\r
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */\r
-\r
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */\r
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */\r
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */\r
-\r
-/*!< SWS configuration */\r
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */\r
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */\r
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */\r
-\r
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */\r
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */\r
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */\r
-\r
-/*!< HPRE configuration */\r
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */\r
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */\r
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */\r
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */\r
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */\r
-\r
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */\r
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */\r
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */\r
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */\r
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */\r
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */\r
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */\r
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */\r
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */\r
-\r
-/*!< PPRE1 configuration */\r
-#define RCC_CFGR_PPRE1 ((uint32_t)0x00001C00) /*!< PRE1[2:0] bits (APB1 prescaler) */\r
-#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000400) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000800) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00001000) /*!< Bit 2 */\r
-\r
-#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00001000) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00001400) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00001800) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00001C00) /*!< HCLK divided by 16 */\r
-\r
-/*!< PPRE2 configuration */\r
-#define RCC_CFGR_PPRE2 ((uint32_t)0x0000E000) /*!< PRE2[2:0] bits (APB2 prescaler) */\r
-#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00002000) /*!< Bit 0 */\r
-#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00004000) /*!< Bit 1 */\r
-#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00008000) /*!< Bit 2 */\r
-\r
-#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */\r
-#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00008000) /*!< HCLK divided by 2 */\r
-#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x0000A000) /*!< HCLK divided by 4 */\r
-#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x0000C000) /*!< HCLK divided by 8 */\r
-#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x0000E000) /*!< HCLK divided by 16 */\r
-\r
-/*!< RTCPRE configuration */\r
-#define RCC_CFGR_RTCPRE ((uint32_t)0x001F0000)\r
-#define RCC_CFGR_RTCPRE_0 ((uint32_t)0x00010000)\r
-#define RCC_CFGR_RTCPRE_1 ((uint32_t)0x00020000)\r
-#define RCC_CFGR_RTCPRE_2 ((uint32_t)0x00040000)\r
-#define RCC_CFGR_RTCPRE_3 ((uint32_t)0x00080000)\r
-#define RCC_CFGR_RTCPRE_4 ((uint32_t)0x00100000)\r
-\r
-/*!< MCO1 configuration */\r
-#define RCC_CFGR_MCO1 ((uint32_t)0x00600000)\r
-#define RCC_CFGR_MCO1_0 ((uint32_t)0x00200000)\r
-#define RCC_CFGR_MCO1_1 ((uint32_t)0x00400000)\r
-\r
-#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000)\r
-\r
-#define RCC_CFGR_MCO1PRE ((uint32_t)0x07000000)\r
-#define RCC_CFGR_MCO1PRE_0 ((uint32_t)0x01000000)\r
-#define RCC_CFGR_MCO1PRE_1 ((uint32_t)0x02000000)\r
-#define RCC_CFGR_MCO1PRE_2 ((uint32_t)0x04000000)\r
-\r
-#define RCC_CFGR_MCO2PRE ((uint32_t)0x38000000)\r
-#define RCC_CFGR_MCO2PRE_0 ((uint32_t)0x08000000)\r
-#define RCC_CFGR_MCO2PRE_1 ((uint32_t)0x10000000)\r
-#define RCC_CFGR_MCO2PRE_2 ((uint32_t)0x20000000)\r
-\r
-#define RCC_CFGR_MCO2 ((uint32_t)0xC0000000)\r
-#define RCC_CFGR_MCO2_0 ((uint32_t)0x40000000)\r
-#define RCC_CFGR_MCO2_1 ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_CIR register *******************/\r
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001)\r
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002)\r
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004)\r
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008)\r
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010)\r
-#define RCC_CIR_PLLI2SRDYF ((uint32_t)0x00000020)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_CIR_PLLSAIRDYF ((uint32_t)0x00000040)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_CIR_CSSF ((uint32_t)0x00000080)\r
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100)\r
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200)\r
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400)\r
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800)\r
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000)\r
-#define RCC_CIR_PLLI2SRDYIE ((uint32_t)0x00002000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_CIR_PLLSAIRDYIE ((uint32_t)0x00004000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000)\r
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000)\r
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000)\r
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000)\r
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000)\r
-#define RCC_CIR_PLLI2SRDYC ((uint32_t)0x00200000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_CIR_PLLSAIRDYC ((uint32_t)0x00400000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_CIR_CSSC ((uint32_t)0x00800000)\r
-\r
-/******************** Bit definition for RCC_AHB1RSTR register **************/\r
-#define RCC_AHB1RSTR_GPIOARST ((uint32_t)0x00000001)\r
-#define RCC_AHB1RSTR_GPIOBRST ((uint32_t)0x00000002)\r
-#define RCC_AHB1RSTR_GPIOCRST ((uint32_t)0x00000004)\r
-#define RCC_AHB1RSTR_GPIODRST ((uint32_t)0x00000008)\r
-#define RCC_AHB1RSTR_GPIOERST ((uint32_t)0x00000010)\r
-#define RCC_AHB1RSTR_GPIOFRST ((uint32_t)0x00000020)\r
-#define RCC_AHB1RSTR_GPIOGRST ((uint32_t)0x00000040)\r
-#define RCC_AHB1RSTR_GPIOHRST ((uint32_t)0x00000080)\r
-#define RCC_AHB1RSTR_GPIOIRST ((uint32_t)0x00000100)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1RSTR_GPIOJRST ((uint32_t)0x00000200)\r
-#define RCC_AHB1RSTR_GPIOKRST ((uint32_t)0x00000400)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1RSTR_CRCRST ((uint32_t)0x00001000)\r
-#define RCC_AHB1RSTR_DMA1RST ((uint32_t)0x00200000)\r
-#define RCC_AHB1RSTR_DMA2RST ((uint32_t)0x00400000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1RSTR_DMA2DRST ((uint32_t)0x00800000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1RSTR_ETHMACRST ((uint32_t)0x02000000)\r
-#define RCC_AHB1RSTR_OTGHRST ((uint32_t)0x10000000)\r
-\r
-/******************** Bit definition for RCC_AHB2RSTR register **************/\r
-#define RCC_AHB2RSTR_DCMIRST ((uint32_t)0x00000001)\r
-#define RCC_AHB2RSTR_CRYPRST ((uint32_t)0x00000010)\r
-#define RCC_AHB2RSTR_HASHRST ((uint32_t)0x00000020)\r
- /* maintained for legacy purpose */\r
- #define RCC_AHB2RSTR_HSAHRST RCC_AHB2RSTR_HASHRST\r
-#define RCC_AHB2RSTR_RNGRST ((uint32_t)0x00000040)\r
-#define RCC_AHB2RSTR_OTGFSRST ((uint32_t)0x00000080)\r
-\r
-/******************** Bit definition for RCC_AHB3RSTR register **************/\r
-#if defined(STM32F40XX) || defined(STM32F427X)\r
-#define RCC_AHB3RSTR_FSMCRST ((uint32_t)0x00000001)\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB3RSTR_FMCRST ((uint32_t)0x00000001)\r
-#endif /* STM32F429X */\r
-/******************** Bit definition for RCC_APB1RSTR register **************/\r
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001)\r
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002)\r
-#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004)\r
-#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008)\r
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010)\r
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020)\r
-#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040)\r
-#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080)\r
-#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100)\r
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800)\r
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000)\r
-#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000)\r
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000)\r
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000)\r
-#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000)\r
-#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000)\r
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000)\r
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000)\r
-#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x00800000)\r
-#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000)\r
-#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000)\r
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000)\r
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000)\r
-#define RCC_APB1RSTR_UART7RST ((uint32_t)0x40000000)\r
-#define RCC_APB1RSTR_UART8RST ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_APB2RSTR register **************/\r
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000001)\r
-#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000002)\r
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00000010)\r
-#define RCC_APB2RSTR_USART6RST ((uint32_t)0x00000020)\r
-#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000100)\r
-#define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800)\r
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000)\r
-#define RCC_APB2RSTR_SPI4RST ((uint32_t)0x00002000)\r
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00004000)\r
-#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00010000)\r
-#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00020000)\r
-#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00040000)\r
-#define RCC_APB2RSTR_SPI5RST ((uint32_t)0x00100000)\r
-#define RCC_APB2RSTR_SPI6RST ((uint32_t)0x00200000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_APB2RSTR_SAI1RST ((uint32_t)0x00400000)\r
-#define RCC_APB2RSTR_LTDCRST ((uint32_t)0x04000000)\r
-#endif /* STM32F429X */\r
-\r
-/* Old SPI1RST bit definition, maintained for legacy purpose */\r
-#define RCC_APB2RSTR_SPI1 RCC_APB2RSTR_SPI1RST\r
-\r
-/******************** Bit definition for RCC_AHB1ENR register ***************/\r
-#define RCC_AHB1ENR_GPIOAEN ((uint32_t)0x00000001)\r
-#define RCC_AHB1ENR_GPIOBEN ((uint32_t)0x00000002)\r
-#define RCC_AHB1ENR_GPIOCEN ((uint32_t)0x00000004)\r
-#define RCC_AHB1ENR_GPIODEN ((uint32_t)0x00000008)\r
-#define RCC_AHB1ENR_GPIOEEN ((uint32_t)0x00000010)\r
-#define RCC_AHB1ENR_GPIOFEN ((uint32_t)0x00000020)\r
-#define RCC_AHB1ENR_GPIOGEN ((uint32_t)0x00000040)\r
-#define RCC_AHB1ENR_GPIOHEN ((uint32_t)0x00000080)\r
-#define RCC_AHB1ENR_GPIOIEN ((uint32_t)0x00000100)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1ENR_GPIOJEN ((uint32_t)0x00000200)\r
-#define RCC_AHB1ENR_GPIOKEN ((uint32_t)0x00000400)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1ENR_CRCEN ((uint32_t)0x00001000)\r
-#define RCC_AHB1ENR_BKPSRAMEN ((uint32_t)0x00040000)\r
-#define RCC_AHB1ENR_CCMDATARAMEN ((uint32_t)0x00100000)\r
-#define RCC_AHB1ENR_DMA1EN ((uint32_t)0x00200000)\r
-#define RCC_AHB1ENR_DMA2EN ((uint32_t)0x00400000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1ENR_DMA2DEN ((uint32_t)0x00800000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1ENR_ETHMACEN ((uint32_t)0x02000000)\r
-#define RCC_AHB1ENR_ETHMACTXEN ((uint32_t)0x04000000)\r
-#define RCC_AHB1ENR_ETHMACRXEN ((uint32_t)0x08000000)\r
-#define RCC_AHB1ENR_ETHMACPTPEN ((uint32_t)0x10000000)\r
-#define RCC_AHB1ENR_OTGHSEN ((uint32_t)0x20000000)\r
-#define RCC_AHB1ENR_OTGHSULPIEN ((uint32_t)0x40000000)\r
-\r
-/******************** Bit definition for RCC_AHB2ENR register ***************/\r
-#define RCC_AHB2ENR_DCMIEN ((uint32_t)0x00000001)\r
-#define RCC_AHB2ENR_CRYPEN ((uint32_t)0x00000010)\r
-#define RCC_AHB2ENR_HASHEN ((uint32_t)0x00000020)\r
-#define RCC_AHB2ENR_RNGEN ((uint32_t)0x00000040)\r
-#define RCC_AHB2ENR_OTGFSEN ((uint32_t)0x00000080)\r
-\r
-/******************** Bit definition for RCC_AHB3ENR register ***************/\r
-\r
-#if defined(STM32F40XX) || defined(STM32F427X)\r
-#define RCC_AHB3ENR_FSMCEN ((uint32_t)0x00000001)\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB3ENR_FMCEN ((uint32_t)0x00000001)\r
-#endif /* STM32F429X */\r
-\r
-/******************** Bit definition for RCC_APB1ENR register ***************/\r
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001)\r
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002)\r
-#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004)\r
-#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008)\r
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010)\r
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020)\r
-#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040)\r
-#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080)\r
-#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100)\r
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800)\r
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000)\r
-#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000)\r
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000)\r
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000)\r
-#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000)\r
-#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000)\r
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000)\r
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000)\r
-#define RCC_APB1ENR_I2C3EN ((uint32_t)0x00800000)\r
-#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000)\r
-#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000)\r
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000)\r
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000)\r
-#define RCC_APB1ENR_UART7EN ((uint32_t)0x40000000)\r
-#define RCC_APB1ENR_UART8EN ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_APB2ENR register ***************/\r
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000001)\r
-#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00000002)\r
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00000010)\r
-#define RCC_APB2ENR_USART6EN ((uint32_t)0x00000020)\r
-#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000100)\r
-#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000200)\r
-#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00000400)\r
-#define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800)\r
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000)\r
-#define RCC_APB2ENR_SPI4EN ((uint32_t)0x00002000)\r
-#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00004000)\r
-#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00010000)\r
-#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00020000)\r
-#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00040000)\r
-#define RCC_APB2ENR_SPI5EN ((uint32_t)0x00100000)\r
-#define RCC_APB2ENR_SPI6EN ((uint32_t)0x00200000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_APB2ENR_SAI1EN ((uint32_t)0x00400000)\r
-#define RCC_APB2ENR_LTDCEN ((uint32_t)0x04000000)\r
-#endif /* STM32F429X */\r
-\r
-/******************** Bit definition for RCC_AHB1LPENR register *************/\r
-#define RCC_AHB1LPENR_GPIOALPEN ((uint32_t)0x00000001)\r
-#define RCC_AHB1LPENR_GPIOBLPEN ((uint32_t)0x00000002)\r
-#define RCC_AHB1LPENR_GPIOCLPEN ((uint32_t)0x00000004)\r
-#define RCC_AHB1LPENR_GPIODLPEN ((uint32_t)0x00000008)\r
-#define RCC_AHB1LPENR_GPIOELPEN ((uint32_t)0x00000010)\r
-#define RCC_AHB1LPENR_GPIOFLPEN ((uint32_t)0x00000020)\r
-#define RCC_AHB1LPENR_GPIOGLPEN ((uint32_t)0x00000040)\r
-#define RCC_AHB1LPENR_GPIOHLPEN ((uint32_t)0x00000080)\r
-#define RCC_AHB1LPENR_GPIOILPEN ((uint32_t)0x00000100)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1LPENR_GPIOJLPEN ((uint32_t)0x00000200)\r
-#define RCC_AHB1LPENR_GPIOKLPEN ((uint32_t)0x00000400)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1LPENR_CRCLPEN ((uint32_t)0x00001000)\r
-#define RCC_AHB1LPENR_FLITFLPEN ((uint32_t)0x00008000)\r
-#define RCC_AHB1LPENR_SRAM1LPEN ((uint32_t)0x00010000)\r
-#define RCC_AHB1LPENR_SRAM2LPEN ((uint32_t)0x00020000)\r
-#define RCC_AHB1LPENR_BKPSRAMLPEN ((uint32_t)0x00040000)\r
-#define RCC_AHB1LPENR_SRAM3LPEN ((uint32_t)0x00080000)\r
-#define RCC_AHB1LPENR_DMA1LPEN ((uint32_t)0x00200000)\r
-#define RCC_AHB1LPENR_DMA2LPEN ((uint32_t)0x00400000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB1LPENR_DMA2DLPEN ((uint32_t)0x00800000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_AHB1LPENR_ETHMACLPEN ((uint32_t)0x02000000)\r
-#define RCC_AHB1LPENR_ETHMACTXLPEN ((uint32_t)0x04000000)\r
-#define RCC_AHB1LPENR_ETHMACRXLPEN ((uint32_t)0x08000000)\r
-#define RCC_AHB1LPENR_ETHMACPTPLPEN ((uint32_t)0x10000000)\r
-#define RCC_AHB1LPENR_OTGHSLPEN ((uint32_t)0x20000000)\r
-#define RCC_AHB1LPENR_OTGHSULPILPEN ((uint32_t)0x40000000)\r
-\r
-/******************** Bit definition for RCC_AHB2LPENR register *************/\r
-#define RCC_AHB2LPENR_DCMILPEN ((uint32_t)0x00000001)\r
-#define RCC_AHB2LPENR_CRYPLPEN ((uint32_t)0x00000010)\r
-#define RCC_AHB2LPENR_HASHLPEN ((uint32_t)0x00000020)\r
-#define RCC_AHB2LPENR_RNGLPEN ((uint32_t)0x00000040)\r
-#define RCC_AHB2LPENR_OTGFSLPEN ((uint32_t)0x00000080)\r
-\r
-/******************** Bit definition for RCC_AHB3LPENR register *************/\r
-#if defined(STM32F40XX) || defined(STM32F427X)\r
-#define RCC_AHB3LPENR_FSMCLPEN ((uint32_t)0x00000001)\r
-#endif /* STM32F40XX || STM32F427X */\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_AHB3LPENR_FMCLPEN ((uint32_t)0x00000001)\r
-#endif /* STM32F429X */\r
-\r
-/******************** Bit definition for RCC_APB1LPENR register *************/\r
-#define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001)\r
-#define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002)\r
-#define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004)\r
-#define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008)\r
-#define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010)\r
-#define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020)\r
-#define RCC_APB1LPENR_TIM12LPEN ((uint32_t)0x00000040)\r
-#define RCC_APB1LPENR_TIM13LPEN ((uint32_t)0x00000080)\r
-#define RCC_APB1LPENR_TIM14LPEN ((uint32_t)0x00000100)\r
-#define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800)\r
-#define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000)\r
-#define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000)\r
-#define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000)\r
-#define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000)\r
-#define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000)\r
-#define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000)\r
-#define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000)\r
-#define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000)\r
-#define RCC_APB1LPENR_I2C3LPEN ((uint32_t)0x00800000)\r
-#define RCC_APB1LPENR_CAN1LPEN ((uint32_t)0x02000000)\r
-#define RCC_APB1LPENR_CAN2LPEN ((uint32_t)0x04000000)\r
-#define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000)\r
-#define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000)\r
-#define RCC_APB1LPENR_UART7LPEN ((uint32_t)0x40000000)\r
-#define RCC_APB1LPENR_UART8LPEN ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_APB2LPENR register *************/\r
-#define RCC_APB2LPENR_TIM1LPEN ((uint32_t)0x00000001)\r
-#define RCC_APB2LPENR_TIM8LPEN ((uint32_t)0x00000002)\r
-#define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00000010)\r
-#define RCC_APB2LPENR_USART6LPEN ((uint32_t)0x00000020)\r
-#define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000100)\r
-#define RCC_APB2LPENR_ADC2PEN ((uint32_t)0x00000200)\r
-#define RCC_APB2LPENR_ADC3LPEN ((uint32_t)0x00000400)\r
-#define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800)\r
-#define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000)\r
-#define RCC_APB2LPENR_SPI4LPEN ((uint32_t)0x00002000)\r
-#define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00004000)\r
-#define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00010000)\r
-#define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00020000)\r
-#define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00040000)\r
-#define RCC_APB2LPENR_SPI5LPEN ((uint32_t)0x00100000)\r
-#define RCC_APB2LPENR_SPI6LPEN ((uint32_t)0x00200000)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_APB2LPENR_SAI1LPEN ((uint32_t)0x00400000)\r
-#define RCC_APB2LPENR_LTDCLPEN ((uint32_t)0x04000000)\r
-#endif /* STM32F429X */\r
-\r
-/******************** Bit definition for RCC_BDCR register ******************/\r
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001)\r
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002)\r
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004)\r
-\r
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300)\r
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100)\r
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200)\r
-\r
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000)\r
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000)\r
-\r
-/******************** Bit definition for RCC_CSR register *******************/\r
-#define RCC_CSR_LSION ((uint32_t)0x00000001)\r
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002)\r
-#define RCC_CSR_RMVF ((uint32_t)0x01000000)\r
-#define RCC_CSR_BORRSTF ((uint32_t)0x02000000)\r
-#define RCC_CSR_PADRSTF ((uint32_t)0x04000000)\r
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000)\r
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000)\r
-#define RCC_CSR_WDGRSTF ((uint32_t)0x20000000)\r
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000)\r
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_SSCGR register *****************/\r
-#define RCC_SSCGR_MODPER ((uint32_t)0x00001FFF)\r
-#define RCC_SSCGR_INCSTEP ((uint32_t)0x0FFFE000)\r
-#define RCC_SSCGR_SPREADSEL ((uint32_t)0x40000000)\r
-#define RCC_SSCGR_SSCGEN ((uint32_t)0x80000000)\r
-\r
-/******************** Bit definition for RCC_PLLI2SCFGR register ************/\r
-#define RCC_PLLI2SCFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
-\r
-#if defined (STM32F429X)\r
-#define RCC_PLLI2SCFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
-#endif /* STM32F429X */\r
-\r
-#define RCC_PLLI2SCFGR_PLLI2SR ((uint32_t)0x70000000)\r
-\r
-#if defined (STM32F429X)\r
-/******************** Bit definition for RCC_PLLSAICFGR register ************/\r
-#define RCC_PLLSAICFGR_PLLI2SN ((uint32_t)0x00007FC0)\r
-#define RCC_PLLSAICFGR_PLLI2SQ ((uint32_t)0x0F000000)\r
-#define RCC_PLLSAICFGR_PLLI2SR ((uint32_t)0x70000000)\r
-\r
-/******************** Bit definition for RCC_DCKCFGR register ***************/\r
-#define RCC_DCKCFGR_PLLI2SDIVQ ((uint32_t)0x0000001F)\r
-#define RCC_DCKCFGR_PLLSAIDIVQ ((uint32_t)0x00001F00)\r
-#define RCC_DCKCFGR_PLLSAIDIVR ((uint32_t)0x00030000)\r
-#define RCC_DCKCFGR_SAI1ASRC ((uint32_t)0x00300000)\r
-#define RCC_DCKCFGR_SAI1BSRC ((uint32_t)0x00C00000)\r
-#endif /* STM32F429X */\r
-#define RCC_DCKCFGR_TIMPRE ((uint32_t)0x01000000)\r
-\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* RNG */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bits definition for RNG_CR register *******************/\r
-#define RNG_CR_RNGEN ((uint32_t)0x00000004)\r
-#define RNG_CR_IE ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RNG_SR register *******************/\r
-#define RNG_SR_DRDY ((uint32_t)0x00000001)\r
-#define RNG_SR_CECS ((uint32_t)0x00000002)\r
-#define RNG_SR_SECS ((uint32_t)0x00000004)\r
-#define RNG_SR_CEIS ((uint32_t)0x00000020)\r
-#define RNG_SR_SEIS ((uint32_t)0x00000040)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Real-Time Clock (RTC) */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bits definition for RTC_TR register *******************/\r
-#define RTC_TR_PM ((uint32_t)0x00400000)\r
-#define RTC_TR_HT ((uint32_t)0x00300000)\r
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_TR_HU ((uint32_t)0x000F0000)\r
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_TR_MNT ((uint32_t)0x00007000)\r
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_TR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_TR_ST ((uint32_t)0x00000070)\r
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_TR_SU ((uint32_t)0x0000000F)\r
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_DR register *******************/\r
-#define RTC_DR_YT ((uint32_t)0x00F00000)\r
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)\r
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)\r
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)\r
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)\r
-#define RTC_DR_YU ((uint32_t)0x000F0000)\r
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)\r
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)\r
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)\r
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)\r
-#define RTC_DR_WDU ((uint32_t)0x0000E000)\r
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)\r
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)\r
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)\r
-#define RTC_DR_MT ((uint32_t)0x00001000)\r
-#define RTC_DR_MU ((uint32_t)0x00000F00)\r
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)\r
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)\r
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)\r
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)\r
-#define RTC_DR_DT ((uint32_t)0x00000030)\r
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)\r
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)\r
-#define RTC_DR_DU ((uint32_t)0x0000000F)\r
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)\r
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)\r
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)\r
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_CR register *******************/\r
-#define RTC_CR_COE ((uint32_t)0x00800000)\r
-#define RTC_CR_OSEL ((uint32_t)0x00600000)\r
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)\r
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)\r
-#define RTC_CR_POL ((uint32_t)0x00100000)\r
-#define RTC_CR_COSEL ((uint32_t)0x00080000)\r
-#define RTC_CR_BCK ((uint32_t)0x00040000)\r
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)\r
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)\r
-#define RTC_CR_TSIE ((uint32_t)0x00008000)\r
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)\r
-#define RTC_CR_ALRBIE ((uint32_t)0x00002000)\r
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)\r
-#define RTC_CR_TSE ((uint32_t)0x00000800)\r
-#define RTC_CR_WUTE ((uint32_t)0x00000400)\r
-#define RTC_CR_ALRBE ((uint32_t)0x00000200)\r
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)\r
-#define RTC_CR_DCE ((uint32_t)0x00000080)\r
-#define RTC_CR_FMT ((uint32_t)0x00000040)\r
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)\r
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)\r
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)\r
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)\r
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)\r
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)\r
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)\r
-\r
-/******************** Bits definition for RTC_ISR register ******************/\r
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000)\r
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)\r
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)\r
-#define RTC_ISR_TSF ((uint32_t)0x00000800)\r
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)\r
-#define RTC_ISR_ALRBF ((uint32_t)0x00000200)\r
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)\r
-#define RTC_ISR_INIT ((uint32_t)0x00000080)\r
-#define RTC_ISR_INITF ((uint32_t)0x00000040)\r
-#define RTC_ISR_RSF ((uint32_t)0x00000020)\r
-#define RTC_ISR_INITS ((uint32_t)0x00000010)\r
-#define RTC_ISR_SHPF ((uint32_t)0x00000008)\r
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)\r
-#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)\r
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for RTC_PRER register *****************/\r
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)\r
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00001FFF)\r
-\r
-/******************** Bits definition for RTC_WUTR register *****************/\r
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)\r
-\r
-/******************** Bits definition for RTC_CALIBR register ***************/\r
-#define RTC_CALIBR_DCS ((uint32_t)0x00000080)\r
-#define RTC_CALIBR_DC ((uint32_t)0x0000001F)\r
-\r
-/******************** Bits definition for RTC_ALRMAR register ***************/\r
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)\r
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)\r
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)\r
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)\r
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)\r
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)\r
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)\r
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)\r
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)\r
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)\r
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)\r
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)\r
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)\r
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)\r
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)\r
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_ALRMBR register ***************/\r
-#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)\r
-#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)\r
-#define RTC_ALRMBR_DT ((uint32_t)0x30000000)\r
-#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)\r
-#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)\r
-#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)\r
-#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)\r
-#define RTC_ALRMBR_PM ((uint32_t)0x00400000)\r
-#define RTC_ALRMBR_HT ((uint32_t)0x00300000)\r
-#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)\r
-#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)\r
-#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)\r
-#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)\r
-#define RTC_ALRMBR_ST ((uint32_t)0x00000070)\r
-#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)\r
-#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_WPR register ******************/\r
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)\r
-\r
-/******************** Bits definition for RTC_SSR register ******************/\r
-#define RTC_SSR_SS ((uint32_t)0x0000FFFF)\r
-\r
-/******************** Bits definition for RTC_SHIFTR register ***************/\r
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)\r
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)\r
-\r
-/******************** Bits definition for RTC_TSTR register *****************/\r
-#define RTC_TSTR_PM ((uint32_t)0x00400000)\r
-#define RTC_TSTR_HT ((uint32_t)0x00300000)\r
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)\r
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)\r
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)\r
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)\r
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)\r
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)\r
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)\r
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)\r
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)\r
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)\r
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)\r
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)\r
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)\r
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)\r
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)\r
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)\r
-#define RTC_TSTR_ST ((uint32_t)0x00000070)\r
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)\r
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)\r
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)\r
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)\r
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)\r
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)\r
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)\r
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_TSDR register *****************/\r
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)\r
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)\r
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)\r
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)\r
-#define RTC_TSDR_MT ((uint32_t)0x00001000)\r
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)\r
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)\r
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)\r
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)\r
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)\r
-#define RTC_TSDR_DT ((uint32_t)0x00000030)\r
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)\r
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)\r
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)\r
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)\r
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)\r
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)\r
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)\r
-\r
-/******************** Bits definition for RTC_TSSSR register ****************/\r
-#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)\r
-\r
-/******************** Bits definition for RTC_CAL register *****************/\r
-#define RTC_CALR_CALP ((uint32_t)0x00008000)\r
-#define RTC_CALR_CALW8 ((uint32_t)0x00004000)\r
-#define RTC_CALR_CALW16 ((uint32_t)0x00002000)\r
-#define RTC_CALR_CALM ((uint32_t)0x000001FF)\r
-#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)\r
-#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)\r
-#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)\r
-#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)\r
-#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)\r
-#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)\r
-#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)\r
-#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)\r
-#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)\r
-\r
-/******************** Bits definition for RTC_TAFCR register ****************/\r
-#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)\r
-#define RTC_TAFCR_TSINSEL ((uint32_t)0x00020000)\r
-#define RTC_TAFCR_TAMPINSEL ((uint32_t)0x00010000)\r
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)\r
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)\r
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)\r
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)\r
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)\r
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)\r
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)\r
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)\r
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)\r
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)\r
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)\r
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)\r
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)\r
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)\r
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)\r
-\r
-/******************** Bits definition for RTC_ALRMASSR register *************/\r
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)\r
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)\r
-\r
-/******************** Bits definition for RTC_ALRMBSSR register *************/\r
-#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)\r
-#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)\r
-#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)\r
-#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)\r
-#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)\r
-#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)\r
-\r
-/******************** Bits definition for RTC_BKP0R register ****************/\r
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP1R register ****************/\r
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP2R register ****************/\r
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP3R register ****************/\r
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP4R register ****************/\r
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP5R register ****************/\r
-#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP6R register ****************/\r
-#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP7R register ****************/\r
-#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP8R register ****************/\r
-#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP9R register ****************/\r
-#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP10R register ***************/\r
-#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP11R register ***************/\r
-#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP12R register ***************/\r
-#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP13R register ***************/\r
-#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP14R register ***************/\r
-#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP15R register ***************/\r
-#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP16R register ***************/\r
-#define RTC_BKP16R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP17R register ***************/\r
-#define RTC_BKP17R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP18R register ***************/\r
-#define RTC_BKP18R ((uint32_t)0xFFFFFFFF)\r
-\r
-/******************** Bits definition for RTC_BKP19R register ***************/\r
-#define RTC_BKP19R ((uint32_t)0xFFFFFFFF)\r
-\r
-#if defined (STM32F429X)\r
-/******************************************************************************/\r
-/* */\r
-/* Serial Audio Interface */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for SAI_GCR register *******************/\r
-#define SAI_GCR_SYNCIN ((uint32_t)0x00000003) /*!<SYNCIN[1:0] bits (Synchronization Inputs) */\r
-#define SAI_GCR_SYNCIN_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define SAI_GCR_SYNCIN_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-\r
-#define SAI_GCR_SYNCOUT ((uint32_t)0x00000030) /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
-#define SAI_GCR_SYNCOUT_0 ((uint32_t)0x00000010) /*!<Bit 0 */\r
-#define SAI_GCR_SYNCOUT_1 ((uint32_t)0x00000020) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for SAI_xCR1 register *******************/\r
-#define SAI_xCR1_MODE ((uint32_t)0x00000003) /*!<MODE[1:0] bits (Audio Block Mode) */\r
-#define SAI_xCR1_MODE_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define SAI_xCR1_MODE_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-\r
-#define SAI_xCR1_PRTCFG ((uint32_t)0x0000000C) /*!<PRTCFG[1:0] bits (Protocol Configuration) */\r
-#define SAI_xCR1_PRTCFG_0 ((uint32_t)0x00000004) /*!<Bit 0 */\r
-#define SAI_xCR1_PRTCFG_1 ((uint32_t)0x00000008) /*!<Bit 1 */\r
-\r
-#define SAI_xCR1_DS ((uint32_t)0x000000E0) /*!<DS[1:0] bits (Data Size) */\r
-#define SAI_xCR1_DS_0 ((uint32_t)0x00000020) /*!<Bit 0 */\r
-#define SAI_xCR1_DS_1 ((uint32_t)0x00000040) /*!<Bit 1 */\r
-#define SAI_xCR1_DS_2 ((uint32_t)0x00000080) /*!<Bit 2 */\r
-\r
-#define SAI_xCR1_LSBFIRST ((uint32_t)0x00000100) /*!<LSB First Configuration */\r
-#define SAI_xCR1_CKSTR ((uint32_t)0x00000200) /*!<ClocK STRobing edge */\r
-\r
-#define SAI_xCR1_SYNCEN ((uint32_t)0x00000C00) /*!<SYNCEN[1:0](SYNChronization ENable) */\r
-#define SAI_xCR1_SYNCEN_0 ((uint32_t)0x00000400) /*!<Bit 0 */\r
-#define SAI_xCR1_SYNCEN_1 ((uint32_t)0x00000800) /*!<Bit 1 */\r
-\r
-#define SAI_xCR1_MONO ((uint32_t)0x00001000) /*!<Mono mode */\r
-#define SAI_xCR1_OUTDRIV ((uint32_t)0x00002000) /*!<Output Drive */\r
-#define SAI_xCR1_SAIEN ((uint32_t)0x00010000) /*!<Audio Block enable */\r
-#define SAI_xCR1_DMAEN ((uint32_t)0x00020000) /*!<DMA enable */\r
-#define SAI_xCR1_NODIV ((uint32_t)0x00080000) /*!<No Divider Configuration */\r
-\r
-#define SAI_xCR1_MCKDIV ((uint32_t)0x00780000) /*!<MCKDIV[3:0] (Master ClocK Divider) */\r
-#define SAI_xCR1_MCKDIV_0 ((uint32_t)0x00080000) /*!<Bit 0 */\r
-#define SAI_xCR1_MCKDIV_1 ((uint32_t)0x00100000) /*!<Bit 1 */\r
-#define SAI_xCR1_MCKDIV_2 ((uint32_t)0x00200000) /*!<Bit 2 */\r
-#define SAI_xCR1_MCKDIV_3 ((uint32_t)0x00400000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for SAI_xCR2 register *******************/\r
-#define SAI_xCR2_FTH ((uint32_t)0x00000003) /*!<FTH[1:0](Fifo THreshold) */\r
-#define SAI_xCR2_FTH_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define SAI_xCR2_FTH_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-\r
-#define SAI_xCR2_FFLUSH ((uint32_t)0x00000008) /*!<Fifo FLUSH */\r
-#define SAI_xCR2_TRIS ((uint32_t)0x00000010) /*!<TRIState Management on data line */\r
-#define SAI_xCR2_MUTE ((uint32_t)0x00000020) /*!<Mute mode */\r
-#define SAI_xCR2_MUTEVAL ((uint32_t)0x00000040) /*!<Muate value */\r
-\r
-#define SAI_xCR2_MUTECNT ((uint32_t)0x00001F80) /*!<MUTECNT[5:0] (MUTE counter) */\r
-#define SAI_xCR2_MUTECNT_0 ((uint32_t)0x00000080) /*!<Bit 0 */\r
-#define SAI_xCR2_MUTECNT_1 ((uint32_t)0x00000100) /*!<Bit 1 */\r
-#define SAI_xCR2_MUTECNT_2 ((uint32_t)0x00000200) /*!<Bit 2 */\r
-#define SAI_xCR2_MUTECNT_3 ((uint32_t)0x00000400) /*!<Bit 3 */\r
-#define SAI_xCR2_MUTECNT_4 ((uint32_t)0x00000800) /*!<Bit 4 */\r
-#define SAI_xCR2_MUTECNT_5 ((uint32_t)0x00001000) /*!<Bit 5 */\r
-\r
-#define SAI_xCR2_CPL ((uint32_t)0x00080000) /*!< Complement Bit */\r
-\r
-#define SAI_xCR2_COMP ((uint32_t)0x0000C000) /*!<COMP[1:0] (Companding mode) */\r
-#define SAI_xCR2_COMP_0 ((uint32_t)0x00004000) /*!<Bit 0 */\r
-#define SAI_xCR2_COMP_1 ((uint32_t)0x00008000) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for SAI_xFRCR register *******************/\r
-#define SAI_xFRCR_FRL ((uint32_t)0x000000FF) /*!<FRL[1:0](Frame length) */\r
-#define SAI_xFRCR_FRL_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define SAI_xFRCR_FRL_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define SAI_xFRCR_FRL_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define SAI_xFRCR_FRL_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define SAI_xFRCR_FRL_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
-#define SAI_xFRCR_FRL_5 ((uint32_t)0x00000020) /*!<Bit 5 */\r
-#define SAI_xFRCR_FRL_6 ((uint32_t)0x00000040) /*!<Bit 6 */\r
-#define SAI_xFRCR_FRL_7 ((uint32_t)0x00000080) /*!<Bit 7 */\r
-\r
-#define SAI_xFRCR_FSALL ((uint32_t)0x00007F00) /*!<FRL[1:0] (Frame synchronization active level length) */\r
-#define SAI_xFRCR_FSALL_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define SAI_xFRCR_FSALL_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define SAI_xFRCR_FSALL_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define SAI_xFRCR_FSALL_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-#define SAI_xFRCR_FSALL_4 ((uint32_t)0x00001000) /*!<Bit 4 */\r
-#define SAI_xFRCR_FSALL_5 ((uint32_t)0x00002000) /*!<Bit 5 */\r
-#define SAI_xFRCR_FSALL_6 ((uint32_t)0x00004000) /*!<Bit 6 */\r
-\r
-#define SAI_xFRCR_FSDEF ((uint32_t)0x00010000) /*!< Frame Synchronization Definition */\r
-#define SAI_xFRCR_FSPO ((uint32_t)0x00020000) /*!<Frame Synchronization POLarity */\r
-#define SAI_xFRCR_FSOFF ((uint32_t)0x00040000) /*!<Frame Synchronization OFFset */\r
-\r
-/****************** Bit definition for SAI_xSLOTR register *******************/\r
-#define SAI_xSLOTR_FBOFF ((uint32_t)0x0000001F) /*!<FRL[4:0](First Bit Offset) */\r
-#define SAI_xSLOTR_FBOFF_0 ((uint32_t)0x00000001) /*!<Bit 0 */\r
-#define SAI_xSLOTR_FBOFF_1 ((uint32_t)0x00000002) /*!<Bit 1 */\r
-#define SAI_xSLOTR_FBOFF_2 ((uint32_t)0x00000004) /*!<Bit 2 */\r
-#define SAI_xSLOTR_FBOFF_3 ((uint32_t)0x00000008) /*!<Bit 3 */\r
-#define SAI_xSLOTR_FBOFF_4 ((uint32_t)0x00000010) /*!<Bit 4 */\r
- \r
-#define SAI_xSLOTR_SLOTSZ ((uint32_t)0x000000C0) /*!<SLOTSZ[1:0] (Slot size) */\r
-#define SAI_xSLOTR_SLOTSZ_0 ((uint32_t)0x00000040) /*!<Bit 0 */\r
-#define SAI_xSLOTR_SLOTSZ_1 ((uint32_t)0x00000080) /*!<Bit 1 */\r
-\r
-#define SAI_xSLOTR_NBSLOT ((uint32_t)0x00000F00) /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */\r
-#define SAI_xSLOTR_NBSLOT_0 ((uint32_t)0x00000100) /*!<Bit 0 */\r
-#define SAI_xSLOTR_NBSLOT_1 ((uint32_t)0x00000200) /*!<Bit 1 */\r
-#define SAI_xSLOTR_NBSLOT_2 ((uint32_t)0x00000400) /*!<Bit 2 */\r
-#define SAI_xSLOTR_NBSLOT_3 ((uint32_t)0x00000800) /*!<Bit 3 */\r
-\r
-#define SAI_xSLOTR_SLOTEN ((uint32_t)0xFFFF0000) /*!<SLOTEN[15:0] (Slot Enable) */\r
-\r
-/******************* Bit definition for SAI_xIMR register *******************/\r
-#define SAI_xIMR_OVRUDRIE ((uint32_t)0x00000001) /*!<Overrun underrun interrupt enable */\r
-#define SAI_xIMR_MUTEDETIE ((uint32_t)0x00000002) /*!<Mute detection interrupt enable */\r
-#define SAI_xIMR_WCKCFGIE ((uint32_t)0x00000004) /*!<Wrong Clock Configuration interrupt enable */\r
-#define SAI_xIMR_FREQIE ((uint32_t)0x00000008) /*!<FIFO request interrupt enable */\r
-#define SAI_xIMR_CNRDYIE ((uint32_t)0x00000010) /*!<Codec not ready interrupt enable */\r
-#define SAI_xIMR_AFSDETIE ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection interrupt enable */\r
-#define SAI_xIMR_LFSDETIE ((uint32_t)0x00000040) /*!<Late frame synchronization detection interrupt enable */\r
-\r
-/******************** Bit definition for SAI_xSR register *******************/\r
-#define SAI_xSR_OVRUDR ((uint32_t)0x00000001) /*!<Overrun underrun */\r
-#define SAI_xSR_MUTEDET ((uint32_t)0x00000002) /*!<Mute detection */\r
-#define SAI_xSR_WCKCFG ((uint32_t)0x00000004) /*!<Wrong Clock Configuration */\r
-#define SAI_xSR_FREQ ((uint32_t)0x00000008) /*!<FIFO request */\r
-#define SAI_xSR_CNRDY ((uint32_t)0x00000010) /*!<Codec not ready */\r
-#define SAI_xSR_AFSDET ((uint32_t)0x00000020) /*!<Anticipated frame synchronization detection */\r
-#define SAI_xSR_LFSDET ((uint32_t)0x00000040) /*!<Late frame synchronization detection */\r
-\r
-#define SAI_xSR_FLVL ((uint32_t)0x00070000) /*!<FLVL[2:0] (FIFO Level Threshold) */\r
-#define SAI_xSR_FLVL_0 ((uint32_t)0x00010000) /*!<Bit 0 */\r
-#define SAI_xSR_FLVL_1 ((uint32_t)0x00020000) /*!<Bit 1 */\r
-#define SAI_xSR_FLVL_2 ((uint32_t)0x00030000) /*!<Bit 2 */\r
-\r
-/****************** Bit definition for SAI_xCLRFR register ******************/\r
-#define SAI_xCLRFR_COVRUDR ((uint32_t)0x00000001) /*!<Clear Overrun underrun */\r
-#define SAI_xCLRFR_CMUTEDET ((uint32_t)0x00000002) /*!<Clear Mute detection */\r
-#define SAI_xCLRFR_CWCKCFG ((uint32_t)0x00000004) /*!<Clear Wrong Clock Configuration */\r
-#define SAI_xCLRFR_CFREQ ((uint32_t)0x00000008) /*!<Clear FIFO request */\r
-#define SAI_xCLRFR_CCNRDY ((uint32_t)0x00000010) /*!<Clear Codec not ready */\r
-#define SAI_xCLRFR_CAFSDET ((uint32_t)0x00000020) /*!<Clear Anticipated frame synchronization detection */\r
-#define SAI_xCLRFR_CLFSDET ((uint32_t)0x00000040) /*!<Clear Late frame synchronization detection */\r
-\r
-/****************** Bit definition for SAI_xDR register ******************/\r
-#define SAI_xDR_DATA ((uint32_t)0xFFFFFFFF) \r
-#endif /* STM32F429X */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SD host Interface */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bit definition for SDIO_POWER register ******************/\r
-#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
-#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!<Bit 1 */\r
-\r
-/****************** Bit definition for SDIO_CLKCR register ******************/\r
-#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!<Clock divide factor */\r
-#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!<Clock enable bit */\r
-#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!<Power saving configuration bit */\r
-#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!<Clock divider bypass enable bit */\r
-\r
-#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
-#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!<Bit 0 */\r
-#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!<Bit 1 */\r
-\r
-#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!<SDIO_CK dephasing selection bit */\r
-#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!<HW Flow Control enable */\r
-\r
-/******************* Bit definition for SDIO_ARG register *******************/\r
-#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!<Command argument */\r
-\r
-/******************* Bit definition for SDIO_CMD register *******************/\r
-#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!<Command Index */\r
-\r
-#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
-#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */\r
-#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */\r
-\r
-#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!<CPSM Waits for Interrupt Request */\r
-#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
-#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!<Command path state machine (CPSM) Enable bit */\r
-#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!<SD I/O suspend command */\r
-#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!<Enable CMD completion */\r
-#define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!<Not Interrupt Enable */\r
-#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!<CE-ATA command */\r
-\r
-/***************** Bit definition for SDIO_RESPCMD register *****************/\r
-#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!<Response command index */\r
-\r
-/****************** Bit definition for SDIO_RESP0 register ******************/\r
-#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP1 register ******************/\r
-#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP2 register ******************/\r
-#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP3 register ******************/\r
-#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_RESP4 register ******************/\r
-#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!<Card Status */\r
-\r
-/****************** Bit definition for SDIO_DTIMER register *****************/\r
-#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!<Data timeout period. */\r
-\r
-/****************** Bit definition for SDIO_DLEN register *******************/\r
-#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!<Data length value */\r
-\r
-/****************** Bit definition for SDIO_DCTRL register ******************/\r
-#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!<Data transfer enabled bit */\r
-#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!<Data transfer direction selection */\r
-#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!<Data transfer mode selection */\r
-#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!<DMA enabled bit */\r
-\r
-#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
-#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!<Read wait start */\r
-#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!<Read wait stop */\r
-#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!<Read wait mode */\r
-#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!<SD I/O enable functions */\r
-\r
-/****************** Bit definition for SDIO_DCOUNT register *****************/\r
-#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!<Data count value */\r
-\r
-/****************** Bit definition for SDIO_STA register ********************/\r
-#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!<Command response received (CRC check failed) */\r
-#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!<Data block sent/received (CRC check failed) */\r
-#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!<Command response timeout */\r
-#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!<Data timeout */\r
-#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!<Transmit FIFO underrun error */\r
-#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!<Received FIFO overrun error */\r
-#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!<Command response received (CRC check passed) */\r
-#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!<Command sent (no response required) */\r
-#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!<Data end (data counter, SDIDCOUNT, is zero) */\r
-#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!<Start bit not detected on all data signals in wide bus mode */\r
-#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!<Data block sent/received (CRC check passed) */\r
-#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!<Command transfer in progress */\r
-#define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!<Data transmit in progress */\r
-#define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!<Data receive in progress */\r
-#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
-#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
-#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!<Transmit FIFO full */\r
-#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!<Receive FIFO full */\r
-#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!<Transmit FIFO empty */\r
-#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!<Receive FIFO empty */\r
-#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!<Data available in transmit FIFO */\r
-#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!<Data available in receive FIFO */\r
-#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!<SDIO interrupt received */\r
-#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received for CMD61 */\r
-\r
-/******************* Bit definition for SDIO_ICR register *******************/\r
-#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!<CCRCFAIL flag clear bit */\r
-#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!<DCRCFAIL flag clear bit */\r
-#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!<CTIMEOUT flag clear bit */\r
-#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!<DTIMEOUT flag clear bit */\r
-#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!<TXUNDERR flag clear bit */\r
-#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!<RXOVERR flag clear bit */\r
-#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!<CMDREND flag clear bit */\r
-#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!<CMDSENT flag clear bit */\r
-#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!<DATAEND flag clear bit */\r
-#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!<STBITERR flag clear bit */\r
-#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!<DBCKEND flag clear bit */\r
-#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!<SDIOIT flag clear bit */\r
-#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!<CEATAEND flag clear bit */\r
-\r
-/****************** Bit definition for SDIO_MASK register *******************/\r
-#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!<Command CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!<Data CRC Fail Interrupt Enable */\r
-#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!<Command TimeOut Interrupt Enable */\r
-#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!<Data TimeOut Interrupt Enable */\r
-#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!<Tx FIFO UnderRun Error Interrupt Enable */\r
-#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!<Rx FIFO OverRun Error Interrupt Enable */\r
-#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!<Command Response Received Interrupt Enable */\r
-#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!<Command Sent Interrupt Enable */\r
-#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!<Data End Interrupt Enable */\r
-#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!<Start Bit Error Interrupt Enable */\r
-#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!<Data Block End Interrupt Enable */\r
-#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!<CCommand Acting Interrupt Enable */\r
-#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!<Data Transmit Acting Interrupt Enable */\r
-#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!<Data receive acting interrupt enabled */\r
-#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!<Tx FIFO Half Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!<Rx FIFO Half Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!<Tx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!<Rx FIFO Full interrupt Enable */\r
-#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!<Tx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!<Rx FIFO Empty interrupt Enable */\r
-#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!<Data available in Tx FIFO interrupt Enable */\r
-#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!<Data available in Rx FIFO interrupt Enable */\r
-#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!<SDIO Mode Interrupt Received interrupt Enable */\r
-#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!<CE-ATA command completion signal received Interrupt Enable */\r
-\r
-/***************** Bit definition for SDIO_FIFOCNT register *****************/\r
-#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!<Remaining number of words to be written to or read from the FIFO */\r
-\r
-/****************** Bit definition for SDIO_FIFO register *******************/\r
-#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!<Receive and transmit FIFO data */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Serial Peripheral Interface */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for SPI_CR1 register ********************/\r
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!<Clock Phase */\r
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!<Clock Polarity */\r
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!<Master Selection */\r
-\r
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!<BR[2:0] bits (Baud Rate Control) */\r
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!<Bit 0 */\r
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!<Bit 1 */\r
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!<Bit 2 */\r
-\r
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!<SPI Enable */\r
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!<Frame Format */\r
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!<Internal slave select */\r
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!<Software slave management */\r
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!<Receive only */\r
-#define SPI_CR1_DFF ((uint16_t)0x0800) /*!<Data Frame Format */\r
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!<Transmit CRC next */\r
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!<Hardware CRC calculation enable */\r
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!<Output enable in bidirectional mode */\r
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!<Bidirectional data mode enable */\r
-\r
-/******************* Bit definition for SPI_CR2 register ********************/\r
-#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!<Rx Buffer DMA Enable */\r
-#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!<Tx Buffer DMA Enable */\r
-#define SPI_CR2_SSOE ((uint8_t)0x04) /*!<SS Output Enable */\r
-#define SPI_CR2_ERRIE ((uint8_t)0x20) /*!<Error Interrupt Enable */\r
-#define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!<RX buffer Not Empty Interrupt Enable */\r
-#define SPI_CR2_TXEIE ((uint8_t)0x80) /*!<Tx buffer Empty Interrupt Enable */\r
-\r
-/******************** Bit definition for SPI_SR register ********************/\r
-#define SPI_SR_RXNE ((uint8_t)0x01) /*!<Receive buffer Not Empty */\r
-#define SPI_SR_TXE ((uint8_t)0x02) /*!<Transmit buffer Empty */\r
-#define SPI_SR_CHSIDE ((uint8_t)0x04) /*!<Channel side */\r
-#define SPI_SR_UDR ((uint8_t)0x08) /*!<Underrun flag */\r
-#define SPI_SR_CRCERR ((uint8_t)0x10) /*!<CRC Error flag */\r
-#define SPI_SR_MODF ((uint8_t)0x20) /*!<Mode fault */\r
-#define SPI_SR_OVR ((uint8_t)0x40) /*!<Overrun flag */\r
-#define SPI_SR_BSY ((uint8_t)0x80) /*!<Busy flag */\r
-\r
-/******************** Bit definition for SPI_DR register ********************/\r
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!<Data Register */\r
-\r
-/******************* Bit definition for SPI_CRCPR register ******************/\r
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!<CRC polynomial register */\r
-\r
-/****************** Bit definition for SPI_RXCRCR register ******************/\r
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!<Rx CRC Register */\r
-\r
-/****************** Bit definition for SPI_TXCRCR register ******************/\r
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!<Tx CRC Register */\r
-\r
-/****************** Bit definition for SPI_I2SCFGR register *****************/\r
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */\r
-\r
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */\r
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */\r
-\r
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */\r
-\r
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */\r
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */\r
-\r
-/****************** Bit definition for SPI_I2SPR register *******************/\r
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */\r
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */\r
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* SYSCFG */\r
-/* */\r
-/******************************************************************************/\r
-/****************** Bit definition for SYSCFG_MEMRMP register ***************/ \r
-#define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */\r
-#define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001)\r
-#define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002)\r
-#define SYSCFG_MEMRMP_MEM_MODE_2 ((uint32_t)0x00000004)\r
-\r
-#define SYSCFG_MEMRMP_UFB_MODE ((uint32_t)0x00000100) /*!< User Flash Bank mode */\r
-\r
-/****************** Bit definition for SYSCFG_PMC register ******************/\r
-#define SYSCFG_PMC_ADCxDC2 ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit */\r
-#define SYSCFG_PMC_ADC1DC2 ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit */\r
-#define SYSCFG_PMC_ADC2DC2 ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit */\r
-#define SYSCFG_PMC_ADC3DC2 ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit */\r
-\r
-#define SYSCFG_PMC_MII_RMII_SEL ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
-/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\r
-#define SYSCFG_PMC_MII_RMII SYSCFG_PMC_MII_RMII_SEL\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/\r
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!<EXTI 0 configuration */\r
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!<EXTI 1 configuration */\r
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!<EXTI 2 configuration */\r
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!<EXTI 3 configuration */\r
-/** \r
- * @brief EXTI0 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!<PA[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!<PB[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!<PC[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!<PD[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!<PE[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!<PF[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /*!<PG[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0007) /*!<PH[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PI ((uint16_t)0x0008) /*!<PI[0] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR1_EXTI0_PJ ((uint16_t)0x0009) /*!<PJ[0] pin */\r
-#define SYSCFG_EXTICR1_EXTI0_PK ((uint16_t)0x000A) /*!<PK[0] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI1 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!<PA[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!<PB[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!<PC[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!<PD[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!<PE[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!<PF[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /*!<PG[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0070) /*!<PH[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PI ((uint16_t)0x0080) /*!<PI[1] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR1_EXTI1_PJ ((uint16_t)0x0090) /*!<PJ[1] pin */\r
-#define SYSCFG_EXTICR1_EXTI1_PK ((uint16_t)0x00A0) /*!<PK[1] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI2 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!<PA[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!<PB[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!<PC[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!<PD[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!<PE[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!<PF[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /*!<PG[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0700) /*!<PH[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PI ((uint16_t)0x0800) /*!<PI[2] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR1_EXTI2_PJ ((uint16_t)0x0900) /*!<PJ[2] pin */\r
-#define SYSCFG_EXTICR1_EXTI2_PK ((uint16_t)0x0A00) /*!<PK[2] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI3 configuration \r
- */ \r
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!<PA[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!<PB[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!<PC[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!<PD[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!<PE[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!<PF[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /*!<PG[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PH ((uint16_t)0x7000) /*!<PH[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PI ((uint16_t)0x8000) /*!<PI[3] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR1_EXTI3_PJ ((uint16_t)0x9000) /*!<PJ[3] pin */\r
-#define SYSCFG_EXTICR1_EXTI3_PK ((uint16_t)0xA000) /*!<PK[3] pin */\r
-#endif /* STM32F429X */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR2 register ***************/\r
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!<EXTI 4 configuration */\r
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!<EXTI 5 configuration */\r
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!<EXTI 6 configuration */\r
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!<EXTI 7 configuration */\r
-/** \r
- * @brief EXTI4 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!<PA[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!<PB[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!<PC[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!<PD[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!<PE[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!<PF[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /*!<PG[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PH ((uint16_t)0x0007) /*!<PH[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PI ((uint16_t)0x0008) /*!<PI[4] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR2_EXTI4_PJ ((uint16_t)0x0009) /*!<PJ[4] pin */\r
-#define SYSCFG_EXTICR2_EXTI4_PK ((uint16_t)0x000A) /*!<PK[4] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI5 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!<PA[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!<PB[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!<PC[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!<PD[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!<PE[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!<PF[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /*!<PG[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PH ((uint16_t)0x0070) /*!<PH[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PI ((uint16_t)0x0080) /*!<PI[5] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR2_EXTI5_PJ ((uint16_t)0x0090) /*!<PJ[5] pin */\r
-#define SYSCFG_EXTICR2_EXTI5_PK ((uint16_t)0x00A0) /*!<PK[5] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI6 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!<PA[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!<PB[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!<PC[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!<PD[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!<PE[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!<PF[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /*!<PG[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PH ((uint16_t)0x0700) /*!<PH[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PI ((uint16_t)0x0800) /*!<PI[6] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR2_EXTI6_PJ ((uint16_t)0x0900) /*!<PJ[6] pin */\r
-#define SYSCFG_EXTICR2_EXTI6_PK ((uint16_t)0x0A00) /*!<PK[6] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI7 configuration \r
- */ \r
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!<PA[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!<PB[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!<PC[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!<PD[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!<PE[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!<PF[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /*!<PG[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PH ((uint16_t)0x7000) /*!<PH[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PI ((uint16_t)0x8000) /*!<PI[7] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR2_EXTI7_PJ ((uint16_t)0x9000) /*!<PJ[7] pin */\r
-#define SYSCFG_EXTICR2_EXTI7_PK ((uint16_t)0xA000) /*!<PK[7] pin */\r
-#endif /* STM32F429X */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR3 register ***************/\r
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!<EXTI 8 configuration */\r
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!<EXTI 9 configuration */\r
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!<EXTI 10 configuration */\r
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!<EXTI 11 configuration */\r
- \r
-/** \r
- * @brief EXTI8 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!<PA[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!<PB[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!<PC[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!<PD[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!<PE[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!<PF[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /*!<PG[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PH ((uint16_t)0x0007) /*!<PH[8] pin */\r
-#define SYSCFG_EXTICR3_EXTI8_PI ((uint16_t)0x0008) /*!<PI[8] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR3_EXTI8_PJ ((uint16_t)0x0009) /*!<PJ[8] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI9 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!<PA[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!<PB[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!<PC[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!<PD[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!<PE[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!<PF[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /*!<PG[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PH ((uint16_t)0x0070) /*!<PH[9] pin */\r
-#define SYSCFG_EXTICR3_EXTI9_PI ((uint16_t)0x0080) /*!<PI[9] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR3_EXTI9_PJ ((uint16_t)0x0090) /*!<PJ[9] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI10 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!<PA[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!<PB[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!<PC[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!<PD[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!<PE[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!<PF[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /*!<PG[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PH ((uint16_t)0x0700) /*!<PH[10] pin */\r
-#define SYSCFG_EXTICR3_EXTI10_PI ((uint16_t)0x0800) /*!<PI[10] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR3_EXTI10_PJ ((uint16_t)0x0900) /*!<PJ[10] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI11 configuration \r
- */ \r
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!<PA[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!<PB[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!<PC[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!<PD[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!<PE[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!<PF[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /*!<PG[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PH ((uint16_t)0x7000) /*!<PH[11] pin */\r
-#define SYSCFG_EXTICR3_EXTI11_PI ((uint16_t)0x8000) /*!<PI[11] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR3_EXTI11_PJ ((uint16_t)0x9000) /*!<PJ[11] pin */\r
-#endif /* STM32F429X */\r
-\r
-/***************** Bit definition for SYSCFG_EXTICR4 register ***************/\r
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!<EXTI 12 configuration */\r
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!<EXTI 13 configuration */\r
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!<EXTI 14 configuration */\r
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!<EXTI 15 configuration */\r
-/** \r
- * @brief EXTI12 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!<PA[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!<PB[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!<PC[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!<PD[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!<PE[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!<PF[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /*!<PG[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PH ((uint16_t)0x0007) /*!<PH[12] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR4_EXTI12_PI ((uint16_t)0x0008) /*!<PI[12] pin */\r
-#define SYSCFG_EXTICR4_EXTI12_PJ ((uint16_t)0x0009) /*!<PJ[12] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI13 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!<PA[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!<PB[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!<PC[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!<PD[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!<PE[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!<PF[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /*!<PG[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PH ((uint16_t)0x0070) /*!<PH[13] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR4_EXTI13_PI ((uint16_t)0x0008) /*!<PI[13] pin */\r
-#define SYSCFG_EXTICR4_EXTI13_PJ ((uint16_t)0x0009) /*!<PJ[13] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI14 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!<PA[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!<PB[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!<PC[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!<PD[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!<PE[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!<PF[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /*!<PG[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PH ((uint16_t)0x0700) /*!<PH[14] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR4_EXTI14_PI ((uint16_t)0x0800) /*!<PI[14] pin */\r
-#define SYSCFG_EXTICR4_EXTI14_PJ ((uint16_t)0x0900) /*!<PJ[14] pin */\r
-#endif /* STM32F429X */\r
-\r
-/** \r
- * @brief EXTI15 configuration \r
- */ \r
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!<PA[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!<PB[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!<PC[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!<PD[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!<PE[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!<PF[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /*!<PG[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PH ((uint16_t)0x7000) /*!<PH[15] pin */\r
-\r
-#if defined (STM32F429X)\r
-#define SYSCFG_EXTICR4_EXTI15_PI ((uint16_t)0x8000) /*!<PI[15] pin */\r
-#define SYSCFG_EXTICR4_EXTI15_PJ ((uint16_t)0x9000) /*!<PJ[15] pin */\r
-#endif /* STM32F429X */\r
-\r
-/****************** Bit definition for SYSCFG_CMPCR register ****************/ \r
-#define SYSCFG_CMPCR_CMP_PD ((uint32_t)0x00000001) /*!<Compensation cell ready flag */\r
-#define SYSCFG_CMPCR_READY ((uint32_t)0x00000100) /*!<Compensation cell power-down */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* TIM */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for TIM_CR1 register ********************/\r
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */\r
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */\r
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */\r
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */\r
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */\r
-\r
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */\r
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */\r
-\r
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */\r
-\r
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */\r
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-/******************* Bit definition for TIM_CR2 register ********************/\r
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */\r
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */\r
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */\r
-\r
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */\r
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */\r
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */\r
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */\r
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */\r
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */\r
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */\r
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */\r
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */\r
-\r
-/******************* Bit definition for TIM_SMCR register *******************/\r
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */\r
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */\r
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */\r
-\r
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */\r
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-\r
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */\r
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */\r
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */\r
-\r
-/******************* Bit definition for TIM_DIER register *******************/\r
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */\r
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */\r
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */\r
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */\r
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */\r
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */\r
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */\r
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */\r
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */\r
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */\r
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */\r
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */\r
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */\r
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */\r
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */\r
-\r
-/******************** Bit definition for TIM_SR register ********************/\r
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */\r
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */\r
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */\r
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */\r
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */\r
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */\r
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */\r
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */\r
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */\r
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */\r
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */\r
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */\r
-\r
-/******************* Bit definition for TIM_EGR register ********************/\r
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */\r
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */\r
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */\r
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */\r
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */\r
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */\r
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */\r
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */\r
-\r
-/****************** Bit definition for TIM_CCMR1 register *******************/\r
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */\r
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */\r
-\r
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */\r
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */\r
-\r
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */\r
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */\r
-\r
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */\r
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */\r
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */\r
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */\r
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/****************** Bit definition for TIM_CCMR2 register *******************/\r
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */\r
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */\r
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */\r
-\r
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */\r
-\r
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */\r
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */\r
-\r
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-\r
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */\r
-\r
-/*----------------------------------------------------------------------------*/\r
-\r
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */\r
-\r
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */\r
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */\r
-\r
-/******************* Bit definition for TIM_CCER register *******************/\r
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */\r
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */\r
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */\r
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */\r
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */\r
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */\r
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */\r
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */\r
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */\r
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */\r
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */\r
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */\r
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */\r
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */\r
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */\r
-\r
-/******************* Bit definition for TIM_CNT register ********************/\r
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */\r
-\r
-/******************* Bit definition for TIM_PSC register ********************/\r
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */\r
-\r
-/******************* Bit definition for TIM_ARR register ********************/\r
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */\r
-\r
-/******************* Bit definition for TIM_RCR register ********************/\r
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */\r
-\r
-/******************* Bit definition for TIM_CCR1 register *******************/\r
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */\r
-\r
-/******************* Bit definition for TIM_CCR2 register *******************/\r
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */\r
-\r
-/******************* Bit definition for TIM_CCR3 register *******************/\r
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */\r
-\r
-/******************* Bit definition for TIM_CCR4 register *******************/\r
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */\r
-\r
-/******************* Bit definition for TIM_BDTR register *******************/\r
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-\r
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */\r
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-\r
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */\r
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */\r
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */\r
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */\r
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */\r
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */\r
-\r
-/******************* Bit definition for TIM_DCR register ********************/\r
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */\r
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-\r
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */\r
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */\r
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */\r
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */\r
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */\r
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */\r
-\r
-/******************* Bit definition for TIM_DMAR register *******************/\r
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */\r
-\r
-/******************* Bit definition for TIM_OR register *********************/\r
-#define TIM_OR_TI4_RMP ((uint16_t)0x00C0) /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) */\r
-#define TIM_OR_TI4_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */\r
-#define TIM_OR_TI4_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */\r
-#define TIM_OR_ITR1_RMP ((uint16_t)0x0C00) /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
-#define TIM_OR_ITR1_RMP_0 ((uint16_t)0x0400) /*!<Bit 0 */\r
-#define TIM_OR_ITR1_RMP_1 ((uint16_t)0x0800) /*!<Bit 1 */\r
-\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Universal Synchronous Asynchronous Receiver Transmitter */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for USART_SR register *******************/\r
-#define USART_SR_PE ((uint16_t)0x0001) /*!<Parity Error */\r
-#define USART_SR_FE ((uint16_t)0x0002) /*!<Framing Error */\r
-#define USART_SR_NE ((uint16_t)0x0004) /*!<Noise Error Flag */\r
-#define USART_SR_ORE ((uint16_t)0x0008) /*!<OverRun Error */\r
-#define USART_SR_IDLE ((uint16_t)0x0010) /*!<IDLE line detected */\r
-#define USART_SR_RXNE ((uint16_t)0x0020) /*!<Read Data Register Not Empty */\r
-#define USART_SR_TC ((uint16_t)0x0040) /*!<Transmission Complete */\r
-#define USART_SR_TXE ((uint16_t)0x0080) /*!<Transmit Data Register Empty */\r
-#define USART_SR_LBD ((uint16_t)0x0100) /*!<LIN Break Detection Flag */\r
-#define USART_SR_CTS ((uint16_t)0x0200) /*!<CTS Flag */\r
-\r
-/******************* Bit definition for USART_DR register *******************/\r
-#define USART_DR_DR ((uint16_t)0x01FF) /*!<Data value */\r
-\r
-/****************** Bit definition for USART_BRR register *******************/\r
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /*!<Fraction of USARTDIV */\r
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /*!<Mantissa of USARTDIV */\r
-\r
-/****************** Bit definition for USART_CR1 register *******************/\r
-#define USART_CR1_SBK ((uint16_t)0x0001) /*!<Send Break */\r
-#define USART_CR1_RWU ((uint16_t)0x0002) /*!<Receiver wakeup */\r
-#define USART_CR1_RE ((uint16_t)0x0004) /*!<Receiver Enable */\r
-#define USART_CR1_TE ((uint16_t)0x0008) /*!<Transmitter Enable */\r
-#define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!<IDLE Interrupt Enable */\r
-#define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!<RXNE Interrupt Enable */\r
-#define USART_CR1_TCIE ((uint16_t)0x0040) /*!<Transmission Complete Interrupt Enable */\r
-#define USART_CR1_TXEIE ((uint16_t)0x0080) /*!<PE Interrupt Enable */\r
-#define USART_CR1_PEIE ((uint16_t)0x0100) /*!<PE Interrupt Enable */\r
-#define USART_CR1_PS ((uint16_t)0x0200) /*!<Parity Selection */\r
-#define USART_CR1_PCE ((uint16_t)0x0400) /*!<Parity Control Enable */\r
-#define USART_CR1_WAKE ((uint16_t)0x0800) /*!<Wakeup method */\r
-#define USART_CR1_M ((uint16_t)0x1000) /*!<Word length */\r
-#define USART_CR1_UE ((uint16_t)0x2000) /*!<USART Enable */\r
-#define USART_CR1_OVER8 ((uint16_t)0x8000) /*!<USART Oversampling by 8 enable */\r
-\r
-/****************** Bit definition for USART_CR2 register *******************/\r
-#define USART_CR2_ADD ((uint16_t)0x000F) /*!<Address of the USART node */\r
-#define USART_CR2_LBDL ((uint16_t)0x0020) /*!<LIN Break Detection Length */\r
-#define USART_CR2_LBDIE ((uint16_t)0x0040) /*!<LIN Break Detection Interrupt Enable */\r
-#define USART_CR2_LBCL ((uint16_t)0x0100) /*!<Last Bit Clock pulse */\r
-#define USART_CR2_CPHA ((uint16_t)0x0200) /*!<Clock Phase */\r
-#define USART_CR2_CPOL ((uint16_t)0x0400) /*!<Clock Polarity */\r
-#define USART_CR2_CLKEN ((uint16_t)0x0800) /*!<Clock Enable */\r
-\r
-#define USART_CR2_STOP ((uint16_t)0x3000) /*!<STOP[1:0] bits (STOP bits) */\r
-#define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!<Bit 0 */\r
-#define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!<Bit 1 */\r
-\r
-#define USART_CR2_LINEN ((uint16_t)0x4000) /*!<LIN mode enable */\r
-\r
-/****************** Bit definition for USART_CR3 register *******************/\r
-#define USART_CR3_EIE ((uint16_t)0x0001) /*!<Error Interrupt Enable */\r
-#define USART_CR3_IREN ((uint16_t)0x0002) /*!<IrDA mode Enable */\r
-#define USART_CR3_IRLP ((uint16_t)0x0004) /*!<IrDA Low-Power */\r
-#define USART_CR3_HDSEL ((uint16_t)0x0008) /*!<Half-Duplex Selection */\r
-#define USART_CR3_NACK ((uint16_t)0x0010) /*!<Smartcard NACK enable */\r
-#define USART_CR3_SCEN ((uint16_t)0x0020) /*!<Smartcard mode enable */\r
-#define USART_CR3_DMAR ((uint16_t)0x0040) /*!<DMA Enable Receiver */\r
-#define USART_CR3_DMAT ((uint16_t)0x0080) /*!<DMA Enable Transmitter */\r
-#define USART_CR3_RTSE ((uint16_t)0x0100) /*!<RTS Enable */\r
-#define USART_CR3_CTSE ((uint16_t)0x0200) /*!<CTS Enable */\r
-#define USART_CR3_CTSIE ((uint16_t)0x0400) /*!<CTS Interrupt Enable */\r
-#define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!<USART One bit method enable */\r
-\r
-/****************** Bit definition for USART_GTPR register ******************/\r
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!<PSC[7:0] bits (Prescaler value) */\r
-#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!<Bit 7 */\r
-\r
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!<Guard time value */\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Window WATCHDOG */\r
-/* */\r
-/******************************************************************************/\r
-/******************* Bit definition for WWDG_CR register ********************/\r
-#define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */\r
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */\r
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */\r
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */\r
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */\r
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */\r
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */\r
-\r
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */\r
-\r
-/******************* Bit definition for WWDG_CFR register *******************/\r
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */\r
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */\r
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */\r
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */\r
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */\r
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */\r
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */\r
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */\r
-\r
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */\r
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */\r
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */\r
-\r
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */\r
-\r
-/******************* Bit definition for WWDG_SR register ********************/\r
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */\r
-\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* DBG */\r
-/* */\r
-/******************************************************************************/\r
-/******************** Bit definition for DBGMCU_IDCODE register *************/\r
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)\r
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)\r
-\r
-/******************** Bit definition for DBGMCU_CR register *****************/\r
-#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)\r
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)\r
-#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)\r
-\r
-#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)\r
-#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */\r
-#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */\r
-\r
-/******************** Bit definition for DBGMCU_APB1_FZ register ************/\r
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)\r
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)\r
-#define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008)\r
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)\r
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)\r
-#define DBGMCU_APB1_FZ_DBG_TIM12_STOP ((uint32_t)0x00000040)\r
-#define DBGMCU_APB1_FZ_DBG_TIM13_STOP ((uint32_t)0x00000080)\r
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100)\r
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)\r
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)\r
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)\r
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)\r
-#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)\r
-#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)\r
-#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)\r
-#define DBGMCU_APB1_FZ_DBG_CAN2_STOP ((uint32_t)0x04000000)\r
-/* Old IWDGSTOP bit definition, maintained for legacy purpose */\r
-#define DBGMCU_APB1_FZ_DBG_IWDEG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP\r
-\r
-/******************** Bit definition for DBGMCU_APB2_FZ register ************/\r
-#define DBGMCU_APB1_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)\r
-#define DBGMCU_APB1_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)\r
-#define DBGMCU_APB1_FZ_DBG_TIM9_STOP ((uint32_t)0x00010000)\r
-#define DBGMCU_APB1_FZ_DBG_TIM10_STOP ((uint32_t)0x00020000)\r
-#define DBGMCU_APB1_FZ_DBG_TIM11_STOP ((uint32_t)0x00040000)\r
-\r
-/******************************************************************************/\r
-/* */\r
-/* Ethernet MAC Registers bits definitions */\r
-/* */\r
-/******************************************************************************/\r
-/* Bit definition for Ethernet MAC Control Register register */\r
-#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */\r
-#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */\r
-#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */\r
-#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */\r
- #define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */\r
- #define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */\r
- #define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */\r
- #define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ \r
- #define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */\r
- #define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */\r
- #define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ \r
-#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */\r
-#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */\r
-#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */\r
-#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */\r
-#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */\r
-#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */\r
-#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */\r
-#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */\r
-#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
- a transmission attempt during retries after a collision: 0 =< r <2^k */\r
- #define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */\r
- #define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */\r
- #define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */\r
- #define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */ \r
-#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */\r
-#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */\r
-#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */\r
-\r
-/* Bit definition for Ethernet MAC Frame Filter Register */\r
-#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */ \r
-#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */ \r
-#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */ \r
-#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */ \r
-#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */\r
- #define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */\r
- #define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */\r
- #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ \r
-#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */ \r
-#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */ \r
-#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */ \r
-#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */ \r
-#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */\r
-#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */\r
-\r
-/* Bit definition for Ethernet MAC Hash Table High Register */\r
-#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */\r
-\r
-/* Bit definition for Ethernet MAC Hash Table Low Register */\r
-#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */\r
-\r
-/* Bit definition for Ethernet MAC MII Address Register */\r
-#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */ \r
-#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */ \r
-#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */ \r
- #define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
- #define ETH_MACMIIAR_CR_Div62 ((uint32_t)0x00000004) /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
- #define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
- #define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
- #define ETH_MACMIIAR_CR_Div102 ((uint32_t)0x00000010) /* HCLK:150-168 MHz; MDC clock= HCLK/102 */ \r
-#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */ \r
-#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */ \r
- \r
-/* Bit definition for Ethernet MAC MII Data Register */\r
-#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */\r
-\r
-/* Bit definition for Ethernet MAC Flow Control Register */\r
-#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */\r
-#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */\r
-#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */\r
- #define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */\r
- #define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */\r
- #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */\r
- #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ \r
-#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */\r
-#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */\r
-#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */\r
-#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */\r
-\r
-/* Bit definition for Ethernet MAC VLAN Tag Register */\r
-#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */\r
-#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */\r
-\r
-/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
-#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */\r
-/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
- Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
-/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
- Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
- Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
- Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
- Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
- RSVD - Filter1 Command - RSVD - Filter0 Command\r
- Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
- Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
- Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
-\r
-/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
-#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */\r
-#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */\r
-#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */\r
-#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */\r
-#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */\r
-#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */\r
-#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */\r
-\r
-/* Bit definition for Ethernet MAC Status Register */\r
-#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */\r
-#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */\r
-#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */\r
-#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */\r
-#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */\r
-\r
-/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
-#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */\r
-#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */\r
-\r
-/* Bit definition for Ethernet MAC Address0 High Register */\r
-#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */\r
-\r
-/* Bit definition for Ethernet MAC Address0 Low Register */\r
-#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */\r
-\r
-/* Bit definition for Ethernet MAC Address1 High Register */\r
-#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
- #define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */ \r
-#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
-\r
-/* Bit definition for Ethernet MAC Address1 Low Register */\r
-#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */\r
-\r
-/* Bit definition for Ethernet MAC Address2 High Register */\r
-#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
- #define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
-#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */\r
-\r
-/* Bit definition for Ethernet MAC Address2 Low Register */\r
-#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */\r
-\r
-/* Bit definition for Ethernet MAC Address3 High Register */\r
-#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */\r
-#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */\r
-#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */\r
- #define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */\r
- #define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */\r
- #define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */\r
- #define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */\r
- #define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */\r
- #define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */\r
-#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */\r
-\r
-/* Bit definition for Ethernet MAC Address3 Low Register */\r
-#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */\r
-\r
-/******************************************************************************/\r
-/* Ethernet MMC Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet MMC Contol Register */\r
-#define ETH_MMCCR_MCFHP ((uint32_t)0x00000020) /* MMC counter Full-Half preset */\r
-#define ETH_MMCCR_MCP ((uint32_t)0x00000010) /* MMC counter preset */\r
-#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */\r
-#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */\r
-#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */\r
-#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */\r
-\r
-/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
-#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */\r
-#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */\r
-#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
-#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */\r
-#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */\r
-#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
-#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
-#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
-#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
-#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
-#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
-#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
-#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
-#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
-\r
-/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
-#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */\r
-\r
-/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
-#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */\r
-\r
-/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
-#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */\r
-\r
-/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
-#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */\r
-\r
-/******************************************************************************/\r
-/* Ethernet PTP Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
-#define ETH_PTPTSCR_TSCNT ((uint32_t)0x00030000) /* Time stamp clock node type */\r
-#define ETH_PTPTSSR_TSSMRME ((uint32_t)0x00008000) /* Time stamp snapshot for message relevant to master enable */\r
-#define ETH_PTPTSSR_TSSEME ((uint32_t)0x00004000) /* Time stamp snapshot for event message enable */\r
-#define ETH_PTPTSSR_TSSIPV4FE ((uint32_t)0x00002000) /* Time stamp snapshot for IPv4 frames enable */\r
-#define ETH_PTPTSSR_TSSIPV6FE ((uint32_t)0x00001000) /* Time stamp snapshot for IPv6 frames enable */\r
-#define ETH_PTPTSSR_TSSPTPOEFE ((uint32_t)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */\r
-#define ETH_PTPTSSR_TSPTPPSV2E ((uint32_t)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */\r
-#define ETH_PTPTSSR_TSSSR ((uint32_t)0x00000200) /* Time stamp Sub-seconds rollover */\r
-#define ETH_PTPTSSR_TSSARFE ((uint32_t)0x00000100) /* Time stamp snapshot for all received frames enable */\r
-\r
-#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */\r
-#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */\r
-#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */\r
-#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */\r
-#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */\r
-#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */\r
-\r
-/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
-#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp High Register */\r
-#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
-#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */\r
-#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
-#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
-#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */\r
-#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
-#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */\r
-\r
-/* Bit definition for Ethernet PTP Target Time High Register */\r
-#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */\r
-\r
-/* Bit definition for Ethernet PTP Target Time Low Register */\r
-#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */\r
-\r
-/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
-#define ETH_PTPTSSR_TSTTR ((uint32_t)0x00000020) /* Time stamp target time reached */\r
-#define ETH_PTPTSSR_TSSO ((uint32_t)0x00000010) /* Time stamp seconds overflow */\r
-\r
-/******************************************************************************/\r
-/* Ethernet DMA Registers bits definition */\r
-/******************************************************************************/\r
-\r
-/* Bit definition for Ethernet DMA Bus Mode Register */\r
-#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */\r
-#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */\r
-#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */\r
-#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */\r
- #define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
- #define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
- #define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
- #define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
- #define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
- #define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ \r
- #define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
- #define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
- #define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
- #define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
- #define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
- #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ \r
-#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */\r
-#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */\r
- #define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */ \r
-#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */\r
- #define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
- #define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
- #define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
- #define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
- #define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
- #define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ \r
- #define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
- #define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
- #define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
- #define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
- #define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
- #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
-#define ETH_DMABMR_EDE ((uint32_t)0x00000080) /* Enhanced Descriptor Enable */\r
-#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */\r
-#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */\r
-#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */\r
-\r
-/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
-#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */\r
-\r
-/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
-#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */\r
-\r
-/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
-#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */\r
-\r
-/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
-#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */\r
-\r
-/* Bit definition for Ethernet DMA Status Register */\r
-#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */\r
-#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */\r
-#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */\r
-#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */\r
- /* combination with EBS[2:0] for GetFlagStatus function */\r
- #define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */\r
- #define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */\r
- #define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */\r
-#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */\r
- #define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */\r
- #define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */\r
- #define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */\r
- #define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */\r
- #define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */\r
- #define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */\r
-#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */\r
- #define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */\r
- #define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */\r
- #define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */\r
- #define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */\r
- #define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */\r
- #define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */\r
-#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */\r
-#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */\r
-#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */\r
-#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */\r
-#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */\r
-#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */\r
-#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */\r
-#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */\r
-#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */\r
-#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */\r
-#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */\r
-#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */\r
-#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */\r
-#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */\r
-#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */\r
-\r
-/* Bit definition for Ethernet DMA Operation Mode Register */\r
-#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */\r
-#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */\r
-#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */\r
-#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */\r
-#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */\r
-#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */\r
- #define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
- #define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
- #define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
- #define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
- #define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
- #define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
- #define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
- #define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
-#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */\r
-#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */\r
-#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */\r
-#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */\r
- #define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
- #define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
- #define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
- #define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
-#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */\r
-#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */\r
-\r
-/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
-#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */\r
-#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */\r
-#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */\r
-#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */\r
-#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */\r
-#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */\r
-#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */\r
-#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */\r
-#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */\r
-#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */\r
-#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */\r
-#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */\r
-#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */\r
-#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */\r
-#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */\r
-\r
-/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
-#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */\r
-#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */\r
-#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */\r
-#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
-#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
-#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
-#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */\r
-\r
-/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
-#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */\r
-\r
-/**\r
- *\r
- */\r
-\r
- /**\r
- * @}\r
- */ \r
-\r
-#ifdef USE_STDPERIPH_DRIVER\r
- #include "stm32f4xx_conf.h"\r
-#endif /* USE_STDPERIPH_DRIVER */\r
-\r
-/** @addtogroup Exported_macro\r
- * @{\r
- */\r
-\r
-#define SET_BIT(REG, BIT) ((REG) |= (BIT))\r
-\r
-#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))\r
-\r
-#define READ_BIT(REG, BIT) ((REG) & (BIT))\r
-\r
-#define CLEAR_REG(REG) ((REG) = (0x0))\r
-\r
-#define WRITE_REG(REG, VAL) ((REG) = (VAL))\r
-\r
-#define READ_REG(REG) ((REG))\r
-\r
-#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
-\r
-/**\r
- * @}\r
- */\r
-\r
-#ifdef __cplusplus\r
-}\r
-#endif /* __cplusplus */\r
-\r
-#endif /* __STM32F4xx_H */\r
-\r
-/**\r
- * @}\r
- */\r
-\r
- /**\r
- * @}\r
- */\r
-\r
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r
+++ /dev/null
-/**
- ******************************************************************************
- * @file system_stm32f4xx.h
- * @author MCD Application Team
- * @version V1.6.1
- * @date 21-October-2015
- * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f4xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F4XX_H
-#define __SYSTEM_STM32F4XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F4xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F4xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F4xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F4XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+++ /dev/null
-/* Label for the program's entry point */
-ENTRY(reset_handler)
-
-/* the end of the stack */
-_estack = 0x20018000;
-
-/* Set minimum size for stack and dynamic memory. */
-/* (The linker will generate an error if there is
- * less than this much RAM leftover.) */
-/* (1KB) */
-_Min_Leftover_RAM = 0x400;
-
-
-MEMORY
-{
- FLASH (rx): ORIGIN = 0x08000000, LENGTH = 512K
- RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
-}
-
-SECTIONS
-{
- /* The vector table goes at the start of flash. */
- .vector_table :
- {
- . = ALIGN(4);
- KEEP (*(.vector_table))
- . = ALIGN(4);
- } >FLASH
- /* The 'text' section contains the main program code. */
- .text :
- {
- . = ALIGN(4);
- *(.text)
- *(.text*)
- . = ALIGN(4);
- } >FLASH
- /* The 'rodata' section contains read-only data,
- * constants, strings, information that won't change. */
- .rodata :
- {
- . = ALIGN(4);
- *(.rodata)
- *(.rodata*)
- . = ALIGN(4);
- } >FLASH
- /* The 'data' section is space set aside in RAM for
- * things like variables, which can change. */
- _sidata = .;
- .data : AT(_sidata)
- {
- . = ALIGN(4);
- /* Mark start/end locations for the 'data' section. */
- _sdata = .;
- *(.data)
- *(.data*)
- _edata = .;
- . = ALIGN(4);
- } >RAM
- /* The 'bss' section is similar to the 'data' section,
- * but its space is initialized to all 0s at the
- * start of the program. */
- .bss :
- {
- . = ALIGN(4);
- /* Also mark the start/end of the BSS section. */
- _sbss = .;
- *(.bss)
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- _ebss = .;
- } >RAM
- /* Space set aside for the application's heap/stack. */
- .dynamic_allocations :
- {
- . = ALIGN(4);
- _ssystem_ram = .;
- . = . + _Min_Leftover_RAM;
- . = ALIGN(4);
- _esystem_ram = .;
- } >RAM
-}
+++ /dev/null
-#include "main.h"
-
-/**
- * Main program.
- */
-int main(void) {
- // Enable the GPIOa and GPIOC peripheral in RCC.
- RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN ;
- RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN ;
-
- // Initialize the GPIOC pins.
- // C15 should be set to 'input' mode with pull-up.
- GPIOC->MODER &= ~(0x3 << (BUTTON_PIN*2));
- GPIOC->PUPDR &= ~(0x3 << (BUTTON_PIN*2));
- GPIOC->PUPDR |= (0x1 << (BUTTON_PIN*2));
-
- // A5 is connected to an LED on the 'Nucleo' board.
- // It should be set to push-pull low-speed output.
- GPIOA->MODER &= ~(0x3 << (LED_PIN*2));
- GPIOA->MODER |= (0x1 << (LED_PIN*2));
- GPIOA->OTYPER &= ~(1 << LED_PIN);
-
- // Main loop
- while (1){
- // Invert the IDR register since '0' means 'pressed'.
- uint32_t idr_val = ~GPIOC->IDR;
- if (idr_val & (1 << BUTTON_PIN)) {
- GPIOA->ODR = (1 << LED_PIN);
- }
- else {
- GPIOA->ODR = (0 << LED_PIN);
- }
- }
-}
\ No newline at end of file
+++ /dev/null
-#ifndef _VVC_MAIN_H
-#define _VVC_MAIN_H
-#include <stdint.h>
-#include "device/stm32f4xx.h"
-// Define GPIOB pin mappings for our LED and button.
-#define BUTTON_PIN (13) //C13
-#define LED_PIN (5) //A5
-#endif
\ No newline at end of file
+++ /dev/null
-// These instructions define attributes of our chip and
-// the assembly language we'll use:
-.syntax unified
-.cpu cortex-m4
-.fpu softvfp
-.thumb
-
-// Global memory locations.
-.global vtable
-.global Default_Handler
-
-/*
- * The actual vector table.
- */
-.type vtable, %object
-.section .vector_table,"a",%progbits
-vtable:
- .word _estack
- .word reset_handler
- .word NMI_Handler
- .word HardFault_Handler
- .word MemManage_Handler
- .word BusFault_Handler
- .word UsageFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word DebugMon_Handler
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
- /* External Interrupts */
- .word WWDG_IRQHandler /* Window WatchDog */
- .word PVD_IRQHandler /* PVD through EXTI Line detection */
- .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
- .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
- .word FLASH_IRQHandler /* FLASH */
- .word RCC_IRQHandler /* RCC */
- .word EXTI0_IRQHandler /* EXTI Line0 */
- .word EXTI1_IRQHandler /* EXTI Line1 */
- .word EXTI2_IRQHandler /* EXTI Line2 */
- .word EXTI3_IRQHandler /* EXTI Line3 */
- .word EXTI4_IRQHandler /* EXTI Line4 */
- .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
- .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
- .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
- .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
- .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
- .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
- .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
- .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word EXTI9_5_IRQHandler /* External Line[9:5]s */
- .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
- .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
- .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
- .word TIM2_IRQHandler /* TIM2 */
- .word TIM3_IRQHandler /* TIM3 */
- .word TIM4_IRQHandler /* TIM4 */
- .word I2C1_EV_IRQHandler /* I2C1 Event */
- .word I2C1_ER_IRQHandler /* I2C1 Error */
- .word I2C2_EV_IRQHandler /* I2C2 Event */
- .word I2C2_ER_IRQHandler /* I2C2 Error */
- .word SPI1_IRQHandler /* SPI1 */
- .word SPI2_IRQHandler /* SPI2 */
- .word USART1_IRQHandler /* USART1 */
- .word USART2_IRQHandler /* USART2 */
- .word 0 /* Reserved */
- .word EXTI15_10_IRQHandler /* External Line[15:10]s */
- .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
- .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
- .word 0 /* Reserved */
- .word SDIO_IRQHandler /* SDIO */
- .word TIM5_IRQHandler /* TIM5 */
- .word SPI3_IRQHandler /* SPI3 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
- .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
- .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
- .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
- .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word OTG_FS_IRQHandler /* USB OTG FS */
- .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
- .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
- .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
- .word USART6_IRQHandler /* USART6 */
- .word I2C3_EV_IRQHandler /* I2C3 event */
- .word I2C3_ER_IRQHandler /* I2C3 error */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word FPU_IRQHandler /* FPU */
- .word 0 /* Reserved */
- .word 0 /* Reserved */
- .word SPI4_IRQHandler /* SPI4 */
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak MemManage_Handler
- .thumb_set MemManage_Handler,Default_Handler
-
- .weak BusFault_Handler
- .thumb_set BusFault_Handler,Default_Handler
-
- .weak UsageFault_Handler
- .thumb_set UsageFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak DebugMon_Handler
- .thumb_set DebugMon_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak TAMP_STAMP_IRQHandler
- .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
-
- .weak RTC_WKUP_IRQHandler
- .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_IRQHandler
- .thumb_set EXTI0_IRQHandler,Default_Handler
-
- .weak EXTI1_IRQHandler
- .thumb_set EXTI1_IRQHandler,Default_Handler
-
- .weak EXTI2_IRQHandler
- .thumb_set EXTI2_IRQHandler,Default_Handler
-
- .weak EXTI3_IRQHandler
- .thumb_set EXTI3_IRQHandler,Default_Handler
-
- .weak EXTI4_IRQHandler
- .thumb_set EXTI4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream0_IRQHandler
- .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
-
- .weak DMA1_Stream1_IRQHandler
- .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
-
- .weak DMA1_Stream2_IRQHandler
- .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
-
- .weak DMA1_Stream3_IRQHandler
- .thumb_set DMA1_Stream3_IRQHandler,Default_Handler
-
- .weak DMA1_Stream4_IRQHandler
- .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
-
- .weak DMA1_Stream5_IRQHandler
- .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
-
- .weak DMA1_Stream6_IRQHandler
- .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
-
- .weak ADC_IRQHandler
- .thumb_set ADC_IRQHandler,Default_Handler
-
- .weak EXTI9_5_IRQHandler
- .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_TIM9_IRQHandler
- .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
-
- .weak TIM1_UP_TIM10_IRQHandler
- .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
-
- .weak TIM1_TRG_COM_TIM11_IRQHandler
- .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM4_IRQHandler
- .thumb_set TIM4_IRQHandler,Default_Handler
-
- .weak I2C1_EV_IRQHandler
- .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
- .weak I2C1_ER_IRQHandler
- .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
- .weak I2C2_EV_IRQHandler
- .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
- .weak I2C2_ER_IRQHandler
- .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak EXTI15_10_IRQHandler
- .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
- .weak RTC_Alarm_IRQHandler
- .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
- .weak OTG_FS_WKUP_IRQHandler
- .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
-
- .weak DMA1_Stream7_IRQHandler
- .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
-
- .weak SDIO_IRQHandler
- .thumb_set SDIO_IRQHandler,Default_Handler
-
- .weak TIM5_IRQHandler
- .thumb_set TIM5_IRQHandler,Default_Handler
-
- .weak SPI3_IRQHandler
- .thumb_set SPI3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream0_IRQHandler
- .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
-
- .weak DMA2_Stream1_IRQHandler
- .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
-
- .weak DMA2_Stream2_IRQHandler
- .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
-
- .weak DMA2_Stream3_IRQHandler
- .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
-
- .weak DMA2_Stream4_IRQHandler
- .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
-
- .weak OTG_FS_IRQHandler
- .thumb_set OTG_FS_IRQHandler,Default_Handler
-
- .weak DMA2_Stream5_IRQHandler
- .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
-
- .weak DMA2_Stream6_IRQHandler
- .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
-
- .weak DMA2_Stream7_IRQHandler
- .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
-
- .weak USART6_IRQHandler
- .thumb_set USART6_IRQHandler,Default_Handler
-
- .weak I2C3_EV_IRQHandler
- .thumb_set I2C3_EV_IRQHandler,Default_Handler
-
- .weak I2C3_ER_IRQHandler
- .thumb_set I2C3_ER_IRQHandler,Default_Handler
-
- .weak FPU_IRQHandler
- .thumb_set FPU_IRQHandler,Default_Handler
-
- .weak SPI4_IRQHandler
- .thumb_set SPI4_IRQHandler,Default_Handler
-
-.size vtable, .-vtable
-
-/*
- * A 'Default' interrupt handler. This is where interrupts
- * which are not otherwise configured will go.
- * It is an infinite loop, because...well, we weren't
- * expecting the interrupt, so what can we do?
- */
-.section .text.Default_Handler,"ax",%progbits
-Default_Handler:
- default_interrupt_loop:
- B default_interrupt_loop
-.size Default_Handler, .-Default_Handler
projects / numworks-zeta-os.git / commitdiff