added a button/led script

diff --git a/Makefile b/Makefile
index 5c8a98d7e12837b7e147427a12f6828723502b2a..6e1a6e4616c1c42412dd7f0f8949d8f175cd3f5f 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -50,6 +50,9 @@ VECT_TBL = $(SRC_DIR)/vector_table.S
 AS_SRC   = $(SRC_DIR)/core.S
 C_SRC    = $(SRC_DIR)/main.c
 
+INCLUDE  =  -I./
+INCLUDE  += -I./device
+
 OBJS =  $(BUILD_DIR)/$(notdir $(VECT_TBL:.S=.o))
 OBJS += $(BUILD_DIR)/$(notdir $(AS_SRC:.S=.o))
 OBJS += $(BUILD_DIR)/$(notdir $(C_SRC:.c=.o))

diff --git a/build/main.bin b/build/main.bin
index 21b570c32879e01d9580dfac098f7465dec07e94..43776ead1e200df51cd538904e62cda2f7602c8f 100755 (executable)
Binary files a/build/main.bin and b/build/main.bin differ

diff --git a/build/main.elf b/build/main.elf
index 907ea0b13f401ce36186d78226c39461c7d898f4..bcf1fbc4d91725acbd7198f7683ddfc9957ccc2d 100755 (executable)
Binary files a/build/main.elf and b/build/main.elf differ

diff --git a/build/main.o b/build/main.o
index 1870a0e4132be74a2f6571441c3f202952398b1f..50ce62e8cbaeceb494581020f0a1eae51299dd84 100644 (file)
Binary files a/build/main.o and b/build/main.o differ

diff --git a/src/device/cmsis_gcc.h b/src/device/cmsis_gcc.h
new file mode 100644 (file)
index 0000000..d868f2e
--- /dev/null
+++ b/src/device/cmsis_gcc.h
@@ -0,0 +1,1373 @@
+/**************************************************************************//**\r
+ * @file     cmsis_gcc.h\r
+ * @brief    CMSIS Cortex-M Core Function/Instruction Header File\r
+ * @version  V4.30\r
+ * @date     20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+   All rights reserved.\r
+   Redistribution and use in source and binary forms, with or without\r
+   modification, are permitted provided that the following conditions are met:\r
+   - Redistributions of source code must retain the above copyright\r
+     notice, this list of conditions and the following disclaimer.\r
+   - Redistributions in binary form must reproduce the above copyright\r
+     notice, this list of conditions and the following disclaimer in the\r
+     documentation and/or other materials provided with the distribution.\r
+   - Neither the name of ARM nor the names of its contributors may be used\r
+     to endorse or promote products derived from this software without\r
+     specific prior written permission.\r
+   *\r
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+   POSSIBILITY OF SUCH DAMAGE.\r
+   ---------------------------------------------------------------------------*/\r
+\r
+\r
+#ifndef __CMSIS_GCC_H\r
+#define __CMSIS_GCC_H\r
+\r
+/* ignore some GCC warnings */\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic push\r
+#pragma GCC diagnostic ignored "-Wsign-conversion"\r
+#pragma GCC diagnostic ignored "-Wconversion"\r
+#pragma GCC diagnostic ignored "-Wunused-parameter"\r
+#endif\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+/** \ingroup  CMSIS_Core_FunctionInterface\r
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+  @{\r
+ */\r
+\r
+/**\r
+  \brief   Enable IRQ Interrupts\r
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)\r
+{\r
+  __ASM volatile ("cpsie i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable IRQ Interrupts\r
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.\r
+  Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)\r
+{\r
+  __ASM volatile ("cpsid i" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Control Register\r
+  \details Returns the content of the Control Register.\r
+  \return               Control Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, control" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Control Register\r
+  \details Writes the given value to the Control Register.\r
+  \param [in]    control  Control Register value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)\r
+{\r
+  __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get IPSR Register\r
+  \details Returns the content of the IPSR Register.\r
+  \return               IPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get APSR Register\r
+  \details Returns the content of the APSR Register.\r
+  \return               APSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get xPSR Register\r
+  \details Returns the content of the xPSR Register.\r
+\r
+    \return               xPSR Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Process Stack Pointer\r
+  \details Returns the current value of the Process Stack Pointer (PSP).\r
+  \return               PSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)\r
+{\r
+  register uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Process Stack Pointer\r
+  \details Assigns the given value to the Process Stack Pointer (PSP).\r
+  \param [in]    topOfProcStack  Process Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)\r
+{\r
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Main Stack Pointer\r
+  \details Returns the current value of the Main Stack Pointer (MSP).\r
+  \return               MSP Register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)\r
+{\r
+  register uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Main Stack Pointer\r
+  \details Assigns the given value to the Main Stack Pointer (MSP).\r
+\r
+    \param [in]    topOfMainStack  Main Stack Pointer value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)\r
+{\r
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Priority Mask\r
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.\r
+  \return               Priority Mask value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Priority Mask\r
+  \details Assigns the given value to the Priority Mask Register.\r
+  \param [in]    priMask  Priority Mask\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)\r
+{\r
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");\r
+}\r
+\r
+\r
+#if       (__CORTEX_M >= 0x03U)\r
+\r
+/**\r
+  \brief   Enable FIQ\r
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)\r
+{\r
+  __ASM volatile ("cpsie f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Disable FIQ\r
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.\r
+           Can only be executed in Privileged modes.\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)\r
+{\r
+  __ASM volatile ("cpsid f" : : : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Base Priority\r
+  \details Returns the current value of the Base Priority register.\r
+  \return               Base Priority register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, basepri" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority\r
+  \details Assigns the given value to the Base Priority register.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)\r
+{\r
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Base Priority with condition\r
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,\r
+           or the new value increases the BASEPRI priority level.\r
+  \param [in]    basePri  Base Priority value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)\r
+{\r
+  __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Get Fault Mask\r
+  \details Returns the current value of the Fault Mask register.\r
+  \return               Fault Mask register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set Fault Mask\r
+  \details Assigns the given value to the Fault Mask register.\r
+  \param [in]    faultMask  Fault Mask value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)\r
+{\r
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) */\r
+\r
+\r
+#if       (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)\r
+\r
+/**\r
+  \brief   Get FPSCR\r
+  \details Returns the current value of the Floating Point Status/Control register.\r
+  \return               Floating Point Status/Control register value\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+  uint32_t result;\r
+\r
+  /* Empty asm statement works as a scheduling barrier */\r
+  __ASM volatile ("");\r
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );\r
+  __ASM volatile ("");\r
+  return(result);\r
+#else\r
+   return(0);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Set FPSCR\r
+  \details Assigns the given value to the Floating Point Status/Control register.\r
+  \param [in]    fpscr  Floating Point Status/Control value to set\r
+ */\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)\r
+{\r
+#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)\r
+  /* Empty asm statement works as a scheduling barrier */\r
+  __ASM volatile ("");\r
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");\r
+  __ASM volatile ("");\r
+#endif\r
+}\r
+\r
+#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */\r
+\r
+\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+  Access to dedicated instructions\r
+  @{\r
+*/\r
+\r
+/* Define macros for porting to both thumb1 and thumb2.\r
+ * For thumb1, use low register (r0-r7), specified by constraint "l"\r
+ * Otherwise, use general registers, specified by constraint "r" */\r
+#if defined (__thumb__) && !defined (__thumb2__)\r
+#define __CMSIS_GCC_OUT_REG(r) "=l" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "l" (r)\r
+#else\r
+#define __CMSIS_GCC_OUT_REG(r) "=r" (r)\r
+#define __CMSIS_GCC_USE_REG(r) "r" (r)\r
+#endif\r
+\r
+/**\r
+  \brief   No Operation\r
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)\r
+{\r
+  __ASM volatile ("nop");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Wait For Interrupt\r
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)\r
+{\r
+  __ASM volatile ("wfi");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Wait For Event\r
+  \details Wait For Event is a hint instruction that permits the processor to enter\r
+    a low-power state until one of a number of events occurs.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)\r
+{\r
+  __ASM volatile ("wfe");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Send Event\r
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)\r
+{\r
+  __ASM volatile ("sev");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Instruction Synchronization Barrier\r
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,\r
+           so that all instructions following the ISB are fetched from cache or memory,\r
+           after the instruction has been completed.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __ISB(void)\r
+{\r
+  __ASM volatile ("isb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Data Synchronization Barrier\r
+  \details Acts as a special kind of Data Memory Barrier.\r
+           It completes when all explicit memory accesses before this instruction complete.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DSB(void)\r
+{\r
+  __ASM volatile ("dsb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Data Memory Barrier\r
+  \details Ensures the apparent order of the explicit memory operations before\r
+           and after the instruction, without ensuring their completion.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __DMB(void)\r
+{\r
+  __ASM volatile ("dmb 0xF":::"memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (32 bit)\r
+  \details Reverses the byte order in integer value.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)\r
+  return __builtin_bswap32(value);\r
+#else\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order (16 bit)\r
+  \details Reverses the byte order in two unsigned short values.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Reverse byte order in signed short value\r
+  \details Reverses the byte order in a signed short value with sign extension to integer.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value)\r
+{\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+  return (short)__builtin_bswap16(value);\r
+#else\r
+  int32_t result;\r
+\r
+  __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+#endif\r
+}\r
+\r
+\r
+/**\r
+  \brief   Rotate Right in unsigned value (32 bit)\r
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.\r
+  \param [in]    value  Value to rotate\r
+  \param [in]    value  Number of Bits to rotate\r
+  \return               Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)\r
+{\r
+  return (op1 >> op2) | (op1 << (32U - op2));\r
+}\r
+\r
+\r
+/**\r
+  \brief   Breakpoint\r
+  \details Causes the processor to enter Debug state.\r
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.\r
+  \param [in]    value  is ignored by the processor.\r
+                 If required, a debugger can use it to store additional information about the breakpoint.\r
+ */\r
+#define __BKPT(value)                       __ASM volatile ("bkpt "#value)\r
+\r
+\r
+/**\r
+  \brief   Reverse bit order of value\r
+  \details Reverses the bit order of the given value.\r
+  \param [in]    value  Value to reverse\r
+  \return               Reversed value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );\r
+#else\r
+  int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */\r
+\r
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */\r
+  for (value >>= 1U; value; value >>= 1U)\r
+  {\r
+    result <<= 1U;\r
+    result |= value & 1U;\r
+    s--;\r
+  }\r
+  result <<= s;                        /* shift when v's highest bits are zero */\r
+#endif\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Count leading zeros\r
+  \details Counts the number of leading zeros of a data value.\r
+  \param [in]  value  Value to count the leading zeros\r
+  \return             number of leading zeros in value\r
+ */\r
+#define __CLZ             __builtin_clz\r
+\r
+\r
+#if       (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)\r
+\r
+/**\r
+  \brief   LDR Exclusive (8 bit)\r
+  \details Executes a exclusive LDR instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint8_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (16 bit)\r
+  \details Executes a exclusive LDR instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint16_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDR Exclusive (32 bit)\r
+  \details Executes a exclusive LDR instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (8 bit)\r
+  \details Executes a exclusive STR instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (16 bit)\r
+  \details Executes a exclusive STR instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STR Exclusive (32 bit)\r
+  \details Executes a exclusive STR instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+  \return          0  Function succeeded\r
+  \return          1  Function failed\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)\r
+{\r
+   uint32_t result;\r
+\r
+   __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   Remove the exclusive lock\r
+  \details Removes the exclusive lock which is created by LDREX.\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)\r
+{\r
+  __ASM volatile ("clrex" ::: "memory");\r
+}\r
+\r
+\r
+/**\r
+  \brief   Signed Saturate\r
+  \details Saturates a signed value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (1..32)\r
+  \return             Saturated value\r
+ */\r
+#define __SSAT(ARG1,ARG2) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+\r
+/**\r
+  \brief   Unsigned Saturate\r
+  \details Saturates an unsigned value.\r
+  \param [in]  value  Value to be saturated\r
+  \param [in]    sat  Bit position to saturate to (0..31)\r
+  \return             Saturated value\r
+ */\r
+#define __USAT(ARG1,ARG2) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+\r
+/**\r
+  \brief   Rotate Right with Extend (32 bit)\r
+  \details Moves each bit of a bitstring right by one bit.\r
+           The carry input is shifted in at the left end of the bitstring.\r
+  \param [in]    value  Value to rotate\r
+  \return               Rotated value\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );\r
+  return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.\r
+  \param [in]    ptr  Pointer to data\r
+  \return             value of type uint8_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint8_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint16_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)\r
+   __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*addr) );\r
+#else\r
+    /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not\r
+       accepted by assembler. So has to use following less efficient pattern.\r
+    */\r
+   __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );\r
+#endif\r
+   return ((uint16_t) result);    /* Add explicit type cast here */\r
+}\r
+\r
+\r
+/**\r
+  \brief   LDRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.\r
+  \param [in]    ptr  Pointer to data\r
+  \return        value of type uint32_t at (*ptr)\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *addr)\r
+{\r
+    uint32_t result;\r
+\r
+   __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*addr) );\r
+   return(result);\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (8 bit)\r
+  \details Executes a Unprivileged STRT instruction for 8 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *addr)\r
+{\r
+   __ASM volatile ("strbt %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (16 bit)\r
+  \details Executes a Unprivileged STRT instruction for 16 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *addr)\r
+{\r
+   __ASM volatile ("strht %1, %0" : "=Q" (*addr) : "r" ((uint32_t)value) );\r
+}\r
+\r
+\r
+/**\r
+  \brief   STRT Unprivileged (32 bit)\r
+  \details Executes a Unprivileged STRT instruction for 32 bit values.\r
+  \param [in]  value  Value to store\r
+  \param [in]    ptr  Pointer to location\r
+ */\r
+__attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *addr)\r
+{\r
+   __ASM volatile ("strt %1, %0" : "=Q" (*addr) : "r" (value) );\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+  Access to dedicated SIMD instructions\r
+  @{\r
+*/\r
+\r
+#if (__CORTEX_M >= 0x04U)  /* only for Cortex-M4 and above */\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+#define __SSAT16(ARG1,ARG2) \\r
+({                          \\r
+  int32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __USAT16(ARG1,ARG2) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1); \\r
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \\r
+  __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)\r
+{\r
+  union llreg_u{\r
+    uint32_t w32[2];\r
+    uint64_t w64;\r
+  } llr;\r
+  llr.w64 = acc;\r
+\r
+#ifndef __ARMEB__   /* Little endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );\r
+#else               /* Big endian */\r
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );\r
+#endif\r
+\r
+  return(llr.w64);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)\r
+{\r
+  uint32_t result;\r
+\r
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QADD( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE  int32_t __QSUB( int32_t op1,  int32_t op2)\r
+{\r
+  int32_t result;\r
+\r
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );\r
+  return(result);\r
+}\r
+\r
+#define __PKHBT(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+\r
+#define __PKHTB(ARG1,ARG2,ARG3) \\r
+({                          \\r
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \\r
+  if (ARG3 == 0) \\r
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \\r
+  else \\r
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \\r
+  __RES; \\r
+ })\r
+\r
+__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)\r
+{\r
+ int32_t result;\r
+\r
+ __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r"  (op1), "r" (op2), "r" (op3) );\r
+ return(result);\r
+}\r
+\r
+#endif /* (__CORTEX_M >= 0x04) */\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#if defined ( __GNUC__ )\r
+#pragma GCC diagnostic pop\r
+#endif\r
+\r
+#endif /* __CMSIS_GCC_H */\r

diff --git a/src/device/core_cm4.h b/src/device/core_cm4.h
new file mode 100644 (file)
index 0000000..873eec9
--- /dev/null
+++ b/src/device/core_cm4.h
@@ -0,0 +1,1937 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V4.30
+ * @date     20. October 2015
+ ******************************************************************************/
+/* Copyright (c) 2009 - 2015 ARM LIMITED
+
+   All rights reserved.
+   Redistribution and use in source and binary forms, with or without
+   modification, are permitted provided that the following conditions are met:
+   - Redistributions of source code must retain the above copyright
+     notice, this list of conditions and the following disclaimer.
+   - Redistributions in binary form must reproduce the above copyright
+     notice, this list of conditions and the following disclaimer in the
+     documentation and/or other materials provided with the distribution.
+   - Neither the name of ARM nor the names of its contributors may be used
+     to endorse or promote products derived from this software without
+     specific prior written permission.
+   *
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+   POSSIBILITY OF SUCH DAMAGE.
+   ---------------------------------------------------------------------------*/
+
+
+#if   defined ( __ICCARM__ )
+ #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/**
+  \page CMSIS_MISRA_Exceptions  MISRA-C:2004 Compliance Exceptions
+  CMSIS violates the following MISRA-C:2004 rules:
+
+   \li Required Rule 8.5, object/function definition in header file.<br>
+     Function definitions in header files are used to allow 'inlining'.
+
+   \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
+     Unions are used for effective representation of core registers.
+
+   \li Advisory Rule 19.7, Function-like macro defined.<br>
+     Function-like macros are used to allow more efficient code.
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/**
+  \ingroup Cortex_M4
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x04U)                                      /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x1EU)                                      /*!< [15:0]  CMSIS HAL sub version */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16U) | \
+                                    __CM4_CMSIS_VERSION_SUB           )        /*!< CMSIS HAL version number */
+
+#define __CORTEX_M                (0x04U)                                      /*!< Cortex-M Core */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler */
+  #define __STATIC_INLINE  static __inline
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __ICCARM__ )
+  #define __ASM            __asm                                      /*!< asm keyword for IAR Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TMS470__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TI CCS Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler */
+  #define __STATIC_INLINE  static inline
+
+#elif defined ( __CSMC__ )
+  #define __packed
+  #define __ASM            _asm                                      /*!< asm keyword for COSMIC Compiler */
+  #define __INLINE         inline                                    /*!< inline keyword for COSMIC Compiler. Use -pc99 on compile line */
+  #define __STATIC_INLINE  static inline
+
+#else
+  #error Unknown compiler
+#endif
+
+/** __FPU_USED indicates whether an FPU is used or not.
+    For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
+*/
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
+  #if defined __ARM_PCS_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1U
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TMS470__ )
+  #if defined __TI_VFP_SUPPORT__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __TASKING__ )
+  #if defined __FPU_VFP__
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#elif defined ( __CSMC__ )
+  #if ( __CSMC__ & 0x400U)
+    #if (__FPU_PRESENT == 1U)
+      #define __FPU_USED       1U
+    #else
+      #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0U
+    #endif
+  #else
+    #define __FPU_USED         0U
+  #endif
+
+#endif
+
+#include "core_cmInstr.h"                /* Core Instruction Access */
+#include "core_cmFunc.h"                 /* Core Function Access */
+#include "core_cmSimd.h"                 /* Compiler specific SIMD Intrinsics */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000U
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0U
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0U
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4U
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0U
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+/**
+    \defgroup CMSIS_glob_defs CMSIS Global Defines
+
+    <strong>IO Type Qualifiers</strong> are used
+    \li to specify the access to peripheral variables.
+    \li for automatic generation of peripheral register debug information.
+*/
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< Defines 'read only' permissions */
+#else
+  #define   __I     volatile const       /*!< Defines 'read only' permissions */
+#endif
+#define     __O     volatile             /*!< Defines 'write only' permissions */
+#define     __IO    volatile             /*!< Defines 'read / write' permissions */
+
+/* following defines should be used for structure members */
+#define     __IM     volatile const      /*! Defines 'read only' structure member permissions */
+#define     __OM     volatile            /*! Defines 'write only' structure member permissions */
+#define     __IOM    volatile            /*! Defines 'read / write' structure member permissions */
+
+/*@} end of group Cortex_M4 */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_core_register Defines and Type Definitions
+  \brief Type definitions and defines for Cortex-M processor based devices.
+*/
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_CORE  Status and Control Registers
+  \brief      Core Register type definitions.
+  @{
+ */
+
+/**
+  \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} APSR_Type;
+
+/* APSR Register Definitions */
+#define APSR_N_Pos                         31U                                            /*!< APSR: N Position */
+#define APSR_N_Msk                         (1UL << APSR_N_Pos)                            /*!< APSR: N Mask */
+
+#define APSR_Z_Pos                         30U                                            /*!< APSR: Z Position */
+#define APSR_Z_Msk                         (1UL << APSR_Z_Pos)                            /*!< APSR: Z Mask */
+
+#define APSR_C_Pos                         29U                                            /*!< APSR: C Position */
+#define APSR_C_Msk                         (1UL << APSR_C_Pos)                            /*!< APSR: C Mask */
+
+#define APSR_V_Pos                         28U                                            /*!< APSR: V Position */
+#define APSR_V_Msk                         (1UL << APSR_V_Pos)                            /*!< APSR: V Mask */
+
+#define APSR_Q_Pos                         27U                                            /*!< APSR: Q Position */
+#define APSR_Q_Msk                         (1UL << APSR_Q_Pos)                            /*!< APSR: Q Mask */
+
+#define APSR_GE_Pos                        16U                                            /*!< APSR: GE Position */
+#define APSR_GE_Msk                        (0xFUL << APSR_GE_Pos)                         /*!< APSR: GE Mask */
+
+
+/**
+  \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} IPSR_Type;
+
+/* IPSR Register Definitions */
+#define IPSR_ISR_Pos                        0U                                            /*!< IPSR: ISR Position */
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number */
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved */
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0) */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0) */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} xPSR_Type;
+
+/* xPSR Register Definitions */
+#define xPSR_N_Pos                         31U                                            /*!< xPSR: N Position */
+#define xPSR_N_Msk                         (1UL << xPSR_N_Pos)                            /*!< xPSR: N Mask */
+
+#define xPSR_Z_Pos                         30U                                            /*!< xPSR: Z Position */
+#define xPSR_Z_Msk                         (1UL << xPSR_Z_Pos)                            /*!< xPSR: Z Mask */
+
+#define xPSR_C_Pos                         29U                                            /*!< xPSR: C Position */
+#define xPSR_C_Msk                         (1UL << xPSR_C_Pos)                            /*!< xPSR: C Mask */
+
+#define xPSR_V_Pos                         28U                                            /*!< xPSR: V Position */
+#define xPSR_V_Msk                         (1UL << xPSR_V_Pos)                            /*!< xPSR: V Mask */
+
+#define xPSR_Q_Pos                         27U                                            /*!< xPSR: Q Position */
+#define xPSR_Q_Msk                         (1UL << xPSR_Q_Pos)                            /*!< xPSR: Q Mask */
+
+#define xPSR_IT_Pos                        25U                                            /*!< xPSR: IT Position */
+#define xPSR_IT_Msk                        (3UL << xPSR_IT_Pos)                           /*!< xPSR: IT Mask */
+
+#define xPSR_T_Pos                         24U                                            /*!< xPSR: T Position */
+#define xPSR_T_Msk                         (1UL << xPSR_T_Pos)                            /*!< xPSR: T Mask */
+
+#define xPSR_GE_Pos                        16U                                            /*!< xPSR: GE Position */
+#define xPSR_GE_Msk                        (0xFUL << xPSR_GE_Pos)                         /*!< xPSR: GE Mask */
+
+#define xPSR_ISR_Pos                        0U                                            /*!< xPSR: ISR Position */
+#define xPSR_ISR_Msk                       (0x1FFUL /*<< xPSR_ISR_Pos*/)                  /*!< xPSR: ISR Mask */
+
+
+/**
+  \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved */
+  } b;                                   /*!< Structure used for bit  access */
+  uint32_t w;                            /*!< Type      used for word access */
+} CONTROL_Type;
+
+/* CONTROL Register Definitions */
+#define CONTROL_FPCA_Pos                    2U                                            /*!< CONTROL: FPCA Position */
+#define CONTROL_FPCA_Msk                   (1UL << CONTROL_FPCA_Pos)                      /*!< CONTROL: FPCA Mask */
+
+#define CONTROL_SPSEL_Pos                   1U                                            /*!< CONTROL: SPSEL Position */
+#define CONTROL_SPSEL_Msk                  (1UL << CONTROL_SPSEL_Pos)                     /*!< CONTROL: SPSEL Mask */
+
+#define CONTROL_nPRIV_Pos                   0U                                            /*!< CONTROL: nPRIV Position */
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+
+/*@} end of group CMSIS_CORE */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_NVIC  Nested Vectored Interrupt Controller (NVIC)
+  \brief      Type definitions for the NVIC Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IOM uint32_t ISER[8U];               /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register */
+        uint32_t RESERVED0[24U];
+  __IOM uint32_t ICER[8U];               /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register */
+        uint32_t RSERVED1[24U];
+  __IOM uint32_t ISPR[8U];               /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register */
+        uint32_t RESERVED2[24U];
+  __IOM uint32_t ICPR[8U];               /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register */
+        uint32_t RESERVED3[24U];
+  __IOM uint32_t IABR[8U];               /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register */
+        uint32_t RESERVED4[56U];
+  __IOM uint8_t  IP[240U];               /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+        uint32_t RESERVED5[644U];
+  __OM  uint32_t STIR;                   /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0U                                         /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/)        /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCB     System Control Block (SCB)
+  \brief    Type definitions for the System Control Block Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __IM  uint32_t CPUID;                  /*!< Offset: 0x000 (R/ )  CPUID Base Register */
+  __IOM uint32_t ICSR;                   /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register */
+  __IOM uint32_t VTOR;                   /*!< Offset: 0x008 (R/W)  Vector Table Offset Register */
+  __IOM uint32_t AIRCR;                  /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register */
+  __IOM uint32_t SCR;                    /*!< Offset: 0x010 (R/W)  System Control Register */
+  __IOM uint32_t CCR;                    /*!< Offset: 0x014 (R/W)  Configuration Control Register */
+  __IOM uint8_t  SHP[12U];               /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IOM uint32_t SHCSR;                  /*!< Offset: 0x024 (R/W)  System Handler Control and State Register */
+  __IOM uint32_t CFSR;                   /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register */
+  __IOM uint32_t HFSR;                   /*!< Offset: 0x02C (R/W)  HardFault Status Register */
+  __IOM uint32_t DFSR;                   /*!< Offset: 0x030 (R/W)  Debug Fault Status Register */
+  __IOM uint32_t MMFAR;                  /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register */
+  __IOM uint32_t BFAR;                   /*!< Offset: 0x038 (R/W)  BusFault Address Register */
+  __IOM uint32_t AFSR;                   /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register */
+  __IM  uint32_t PFR[2U];                /*!< Offset: 0x040 (R/ )  Processor Feature Register */
+  __IM  uint32_t DFR;                    /*!< Offset: 0x048 (R/ )  Debug Feature Register */
+  __IM  uint32_t ADR;                    /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register */
+  __IM  uint32_t MMFR[4U];               /*!< Offset: 0x050 (R/ )  Memory Model Feature Register */
+  __IM  uint32_t ISAR[5U];               /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register */
+        uint32_t RESERVED0[5U];
+  __IOM uint32_t CPACR;                  /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24U                                            /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20U                                            /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16U                                            /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4U                                            /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0U                                            /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL /*<< SCB_CPUID_REVISION_Pos*/)          /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31U                                            /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28U                                            /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27U                                            /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26U                                            /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25U                                            /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23U                                            /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22U                                            /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12U                                            /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11U                                            /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0U                                            /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/)       /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7U                                            /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16U                                            /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16U                                            /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15U                                            /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8U                                            /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2U                                            /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1U                                            /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0U                                            /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/)           /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4U                                            /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2U                                            /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1U                                            /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9U                                            /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8U                                            /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4U                                            /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3U                                            /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1U                                            /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0U                                            /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/)        /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18U                                            /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17U                                            /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16U                                            /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15U                                            /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14U                                            /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13U                                            /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12U                                            /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11U                                            /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10U                                            /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8U                                            /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7U                                            /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3U                                            /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1U                                            /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0U                                            /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/)         /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Register Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16U                                            /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8U                                            /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0U                                            /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/)        /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Register Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31U                                            /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30U                                            /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1U                                            /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4U                                            /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3U                                            /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2U                                            /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1U                                            /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0U                                            /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL /*<< SCB_DFSR_HALTED_Pos*/)               /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
+  \brief    Type definitions for the System Control and ID Register not in the SCB
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IM  uint32_t ICTR;                   /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register */
+  __IOM uint32_t ACTLR;                  /*!< Offset: 0x008 (R/W)  Auxiliary Control Register */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0U                                         /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/)  /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9U                                         /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8U                                         /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2U                                         /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1U                                         /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0U                                         /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/)    /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_SysTick     System Tick Timer (SysTick)
+  \brief    Type definitions for the System Timer Registers.
+  @{
+ */
+
+/**
+  \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IOM uint32_t LOAD;                   /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register */
+  __IOM uint32_t VAL;                    /*!< Offset: 0x008 (R/W)  SysTick Current Value Register */
+  __IM  uint32_t CALIB;                  /*!< Offset: 0x00C (R/ )  SysTick Calibration Register */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16U                                            /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2U                                            /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1U                                            /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0U                                            /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL /*<< SysTick_CTRL_ENABLE_Pos*/)           /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0U                                            /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/)    /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0U                                            /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/)    /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31U                                            /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30U                                            /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0U                                            /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/)    /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_ITM     Instrumentation Trace Macrocell (ITM)
+  \brief    Type definitions for the Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __OM  union
+  {
+    __OM  uint8_t    u8;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit */
+    __OM  uint16_t   u16;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit */
+    __OM  uint32_t   u32;                /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit */
+  }  PORT [32U];                         /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers */
+        uint32_t RESERVED0[864U];
+  __IOM uint32_t TER;                    /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register */
+        uint32_t RESERVED1[15U];
+  __IOM uint32_t TPR;                    /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register */
+        uint32_t RESERVED2[15U];
+  __IOM uint32_t TCR;                    /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register */
+        uint32_t RESERVED3[29U];
+  __OM  uint32_t IWR;                    /*!< Offset: 0xEF8 ( /W)  ITM Integration Write Register */
+  __IM  uint32_t IRR;                    /*!< Offset: 0xEFC (R/ )  ITM Integration Read Register */
+  __IOM uint32_t IMCR;                   /*!< Offset: 0xF00 (R/W)  ITM Integration Mode Control Register */
+        uint32_t RESERVED4[43U];
+  __OM  uint32_t LAR;                    /*!< Offset: 0xFB0 ( /W)  ITM Lock Access Register */
+  __IM  uint32_t LSR;                    /*!< Offset: 0xFB4 (R/ )  ITM Lock Status Register */
+        uint32_t RESERVED5[6U];
+  __IM  uint32_t PID4;                   /*!< Offset: 0xFD0 (R/ )  ITM Peripheral Identification Register #4 */
+  __IM  uint32_t PID5;                   /*!< Offset: 0xFD4 (R/ )  ITM Peripheral Identification Register #5 */
+  __IM  uint32_t PID6;                   /*!< Offset: 0xFD8 (R/ )  ITM Peripheral Identification Register #6 */
+  __IM  uint32_t PID7;                   /*!< Offset: 0xFDC (R/ )  ITM Peripheral Identification Register #7 */
+  __IM  uint32_t PID0;                   /*!< Offset: 0xFE0 (R/ )  ITM Peripheral Identification Register #0 */
+  __IM  uint32_t PID1;                   /*!< Offset: 0xFE4 (R/ )  ITM Peripheral Identification Register #1 */
+  __IM  uint32_t PID2;                   /*!< Offset: 0xFE8 (R/ )  ITM Peripheral Identification Register #2 */
+  __IM  uint32_t PID3;                   /*!< Offset: 0xFEC (R/ )  ITM Peripheral Identification Register #3 */
+  __IM  uint32_t CID0;                   /*!< Offset: 0xFF0 (R/ )  ITM Component  Identification Register #0 */
+  __IM  uint32_t CID1;                   /*!< Offset: 0xFF4 (R/ )  ITM Component  Identification Register #1 */
+  __IM  uint32_t CID2;                   /*!< Offset: 0xFF8 (R/ )  ITM Component  Identification Register #2 */
+  __IM  uint32_t CID3;                   /*!< Offset: 0xFFC (R/ )  ITM Component  Identification Register #3 */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0U                                            /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/)            /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23U                                            /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                      /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16U                                            /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)             /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10U                                            /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                   /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8U                                            /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)                /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4U                                            /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                    /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_DWTENA_Pos                  3U                                            /*!< ITM TCR: DWTENA Position */
+#define ITM_TCR_DWTENA_Msk                 (1UL << ITM_TCR_DWTENA_Pos)                    /*!< ITM TCR: DWTENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2U                                            /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                   /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1U                                            /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                     /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0U                                            /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL /*<< ITM_TCR_ITMENA_Pos*/)                /*!< ITM TCR: ITM Enable bit Mask */
+
+/* ITM Integration Write Register Definitions */
+#define ITM_IWR_ATVALIDM_Pos                0U                                            /*!< ITM IWR: ATVALIDM Position */
+#define ITM_IWR_ATVALIDM_Msk               (1UL /*<< ITM_IWR_ATVALIDM_Pos*/)              /*!< ITM IWR: ATVALIDM Mask */
+
+/* ITM Integration Read Register Definitions */
+#define ITM_IRR_ATREADYM_Pos                0U                                            /*!< ITM IRR: ATREADYM Position */
+#define ITM_IRR_ATREADYM_Msk               (1UL /*<< ITM_IRR_ATREADYM_Pos*/)              /*!< ITM IRR: ATREADYM Mask */
+
+/* ITM Integration Mode Control Register Definitions */
+#define ITM_IMCR_INTEGRATION_Pos            0U                                            /*!< ITM IMCR: INTEGRATION Position */
+#define ITM_IMCR_INTEGRATION_Msk           (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/)          /*!< ITM IMCR: INTEGRATION Mask */
+
+/* ITM Lock Status Register Definitions */
+#define ITM_LSR_ByteAcc_Pos                 2U                                            /*!< ITM LSR: ByteAcc Position */
+#define ITM_LSR_ByteAcc_Msk                (1UL << ITM_LSR_ByteAcc_Pos)                   /*!< ITM LSR: ByteAcc Mask */
+
+#define ITM_LSR_Access_Pos                  1U                                            /*!< ITM LSR: Access Position */
+#define ITM_LSR_Access_Msk                 (1UL << ITM_LSR_Access_Pos)                    /*!< ITM LSR: Access Mask */
+
+#define ITM_LSR_Present_Pos                 0U                                            /*!< ITM LSR: Present Position */
+#define ITM_LSR_Present_Msk                (1UL /*<< ITM_LSR_Present_Pos*/)               /*!< ITM LSR: Present Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_DWT     Data Watchpoint and Trace (DWT)
+  \brief    Type definitions for the Data Watchpoint and Trace (DWT)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Data Watchpoint and Trace Register (DWT).
+ */
+typedef struct
+{
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x000 (R/W)  Control Register */
+  __IOM uint32_t CYCCNT;                 /*!< Offset: 0x004 (R/W)  Cycle Count Register */
+  __IOM uint32_t CPICNT;                 /*!< Offset: 0x008 (R/W)  CPI Count Register */
+  __IOM uint32_t EXCCNT;                 /*!< Offset: 0x00C (R/W)  Exception Overhead Count Register */
+  __IOM uint32_t SLEEPCNT;               /*!< Offset: 0x010 (R/W)  Sleep Count Register */
+  __IOM uint32_t LSUCNT;                 /*!< Offset: 0x014 (R/W)  LSU Count Register */
+  __IOM uint32_t FOLDCNT;                /*!< Offset: 0x018 (R/W)  Folded-instruction Count Register */
+  __IM  uint32_t PCSR;                   /*!< Offset: 0x01C (R/ )  Program Counter Sample Register */
+  __IOM uint32_t COMP0;                  /*!< Offset: 0x020 (R/W)  Comparator Register 0 */
+  __IOM uint32_t MASK0;                  /*!< Offset: 0x024 (R/W)  Mask Register 0 */
+  __IOM uint32_t FUNCTION0;              /*!< Offset: 0x028 (R/W)  Function Register 0 */
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t COMP1;                  /*!< Offset: 0x030 (R/W)  Comparator Register 1 */
+  __IOM uint32_t MASK1;                  /*!< Offset: 0x034 (R/W)  Mask Register 1 */
+  __IOM uint32_t FUNCTION1;              /*!< Offset: 0x038 (R/W)  Function Register 1 */
+        uint32_t RESERVED1[1U];
+  __IOM uint32_t COMP2;                  /*!< Offset: 0x040 (R/W)  Comparator Register 2 */
+  __IOM uint32_t MASK2;                  /*!< Offset: 0x044 (R/W)  Mask Register 2 */
+  __IOM uint32_t FUNCTION2;              /*!< Offset: 0x048 (R/W)  Function Register 2 */
+        uint32_t RESERVED2[1U];
+  __IOM uint32_t COMP3;                  /*!< Offset: 0x050 (R/W)  Comparator Register 3 */
+  __IOM uint32_t MASK3;                  /*!< Offset: 0x054 (R/W)  Mask Register 3 */
+  __IOM uint32_t FUNCTION3;              /*!< Offset: 0x058 (R/W)  Function Register 3 */
+} DWT_Type;
+
+/* DWT Control Register Definitions */
+#define DWT_CTRL_NUMCOMP_Pos               28U                                         /*!< DWT CTRL: NUMCOMP Position */
+#define DWT_CTRL_NUMCOMP_Msk               (0xFUL << DWT_CTRL_NUMCOMP_Pos)             /*!< DWT CTRL: NUMCOMP Mask */
+
+#define DWT_CTRL_NOTRCPKT_Pos              27U                                         /*!< DWT CTRL: NOTRCPKT Position */
+#define DWT_CTRL_NOTRCPKT_Msk              (0x1UL << DWT_CTRL_NOTRCPKT_Pos)            /*!< DWT CTRL: NOTRCPKT Mask */
+
+#define DWT_CTRL_NOEXTTRIG_Pos             26U                                         /*!< DWT CTRL: NOEXTTRIG Position */
+#define DWT_CTRL_NOEXTTRIG_Msk             (0x1UL << DWT_CTRL_NOEXTTRIG_Pos)           /*!< DWT CTRL: NOEXTTRIG Mask */
+
+#define DWT_CTRL_NOCYCCNT_Pos              25U                                         /*!< DWT CTRL: NOCYCCNT Position */
+#define DWT_CTRL_NOCYCCNT_Msk              (0x1UL << DWT_CTRL_NOCYCCNT_Pos)            /*!< DWT CTRL: NOCYCCNT Mask */
+
+#define DWT_CTRL_NOPRFCNT_Pos              24U                                         /*!< DWT CTRL: NOPRFCNT Position */
+#define DWT_CTRL_NOPRFCNT_Msk              (0x1UL << DWT_CTRL_NOPRFCNT_Pos)            /*!< DWT CTRL: NOPRFCNT Mask */
+
+#define DWT_CTRL_CYCEVTENA_Pos             22U                                         /*!< DWT CTRL: CYCEVTENA Position */
+#define DWT_CTRL_CYCEVTENA_Msk             (0x1UL << DWT_CTRL_CYCEVTENA_Pos)           /*!< DWT CTRL: CYCEVTENA Mask */
+
+#define DWT_CTRL_FOLDEVTENA_Pos            21U                                         /*!< DWT CTRL: FOLDEVTENA Position */
+#define DWT_CTRL_FOLDEVTENA_Msk            (0x1UL << DWT_CTRL_FOLDEVTENA_Pos)          /*!< DWT CTRL: FOLDEVTENA Mask */
+
+#define DWT_CTRL_LSUEVTENA_Pos             20U                                         /*!< DWT CTRL: LSUEVTENA Position */
+#define DWT_CTRL_LSUEVTENA_Msk             (0x1UL << DWT_CTRL_LSUEVTENA_Pos)           /*!< DWT CTRL: LSUEVTENA Mask */
+
+#define DWT_CTRL_SLEEPEVTENA_Pos           19U                                         /*!< DWT CTRL: SLEEPEVTENA Position */
+#define DWT_CTRL_SLEEPEVTENA_Msk           (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos)         /*!< DWT CTRL: SLEEPEVTENA Mask */
+
+#define DWT_CTRL_EXCEVTENA_Pos             18U                                         /*!< DWT CTRL: EXCEVTENA Position */
+#define DWT_CTRL_EXCEVTENA_Msk             (0x1UL << DWT_CTRL_EXCEVTENA_Pos)           /*!< DWT CTRL: EXCEVTENA Mask */
+
+#define DWT_CTRL_CPIEVTENA_Pos             17U                                         /*!< DWT CTRL: CPIEVTENA Position */
+#define DWT_CTRL_CPIEVTENA_Msk             (0x1UL << DWT_CTRL_CPIEVTENA_Pos)           /*!< DWT CTRL: CPIEVTENA Mask */
+
+#define DWT_CTRL_EXCTRCENA_Pos             16U                                         /*!< DWT CTRL: EXCTRCENA Position */
+#define DWT_CTRL_EXCTRCENA_Msk             (0x1UL << DWT_CTRL_EXCTRCENA_Pos)           /*!< DWT CTRL: EXCTRCENA Mask */
+
+#define DWT_CTRL_PCSAMPLENA_Pos            12U                                         /*!< DWT CTRL: PCSAMPLENA Position */
+#define DWT_CTRL_PCSAMPLENA_Msk            (0x1UL << DWT_CTRL_PCSAMPLENA_Pos)          /*!< DWT CTRL: PCSAMPLENA Mask */
+
+#define DWT_CTRL_SYNCTAP_Pos               10U                                         /*!< DWT CTRL: SYNCTAP Position */
+#define DWT_CTRL_SYNCTAP_Msk               (0x3UL << DWT_CTRL_SYNCTAP_Pos)             /*!< DWT CTRL: SYNCTAP Mask */
+
+#define DWT_CTRL_CYCTAP_Pos                 9U                                         /*!< DWT CTRL: CYCTAP Position */
+#define DWT_CTRL_CYCTAP_Msk                (0x1UL << DWT_CTRL_CYCTAP_Pos)              /*!< DWT CTRL: CYCTAP Mask */
+
+#define DWT_CTRL_POSTINIT_Pos               5U                                         /*!< DWT CTRL: POSTINIT Position */
+#define DWT_CTRL_POSTINIT_Msk              (0xFUL << DWT_CTRL_POSTINIT_Pos)            /*!< DWT CTRL: POSTINIT Mask */
+
+#define DWT_CTRL_POSTPRESET_Pos             1U                                         /*!< DWT CTRL: POSTPRESET Position */
+#define DWT_CTRL_POSTPRESET_Msk            (0xFUL << DWT_CTRL_POSTPRESET_Pos)          /*!< DWT CTRL: POSTPRESET Mask */
+
+#define DWT_CTRL_CYCCNTENA_Pos              0U                                         /*!< DWT CTRL: CYCCNTENA Position */
+#define DWT_CTRL_CYCCNTENA_Msk             (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/)       /*!< DWT CTRL: CYCCNTENA Mask */
+
+/* DWT CPI Count Register Definitions */
+#define DWT_CPICNT_CPICNT_Pos               0U                                         /*!< DWT CPICNT: CPICNT Position */
+#define DWT_CPICNT_CPICNT_Msk              (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/)       /*!< DWT CPICNT: CPICNT Mask */
+
+/* DWT Exception Overhead Count Register Definitions */
+#define DWT_EXCCNT_EXCCNT_Pos               0U                                         /*!< DWT EXCCNT: EXCCNT Position */
+#define DWT_EXCCNT_EXCCNT_Msk              (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/)       /*!< DWT EXCCNT: EXCCNT Mask */
+
+/* DWT Sleep Count Register Definitions */
+#define DWT_SLEEPCNT_SLEEPCNT_Pos           0U                                         /*!< DWT SLEEPCNT: SLEEPCNT Position */
+#define DWT_SLEEPCNT_SLEEPCNT_Msk          (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/)   /*!< DWT SLEEPCNT: SLEEPCNT Mask */
+
+/* DWT LSU Count Register Definitions */
+#define DWT_LSUCNT_LSUCNT_Pos               0U                                         /*!< DWT LSUCNT: LSUCNT Position */
+#define DWT_LSUCNT_LSUCNT_Msk              (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/)       /*!< DWT LSUCNT: LSUCNT Mask */
+
+/* DWT Folded-instruction Count Register Definitions */
+#define DWT_FOLDCNT_FOLDCNT_Pos             0U                                         /*!< DWT FOLDCNT: FOLDCNT Position */
+#define DWT_FOLDCNT_FOLDCNT_Msk            (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/)     /*!< DWT FOLDCNT: FOLDCNT Mask */
+
+/* DWT Comparator Mask Register Definitions */
+#define DWT_MASK_MASK_Pos                   0U                                         /*!< DWT MASK: MASK Position */
+#define DWT_MASK_MASK_Msk                  (0x1FUL /*<< DWT_MASK_MASK_Pos*/)           /*!< DWT MASK: MASK Mask */
+
+/* DWT Comparator Function Register Definitions */
+#define DWT_FUNCTION_MATCHED_Pos           24U                                         /*!< DWT FUNCTION: MATCHED Position */
+#define DWT_FUNCTION_MATCHED_Msk           (0x1UL << DWT_FUNCTION_MATCHED_Pos)         /*!< DWT FUNCTION: MATCHED Mask */
+
+#define DWT_FUNCTION_DATAVADDR1_Pos        16U                                         /*!< DWT FUNCTION: DATAVADDR1 Position */
+#define DWT_FUNCTION_DATAVADDR1_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos)      /*!< DWT FUNCTION: DATAVADDR1 Mask */
+
+#define DWT_FUNCTION_DATAVADDR0_Pos        12U                                         /*!< DWT FUNCTION: DATAVADDR0 Position */
+#define DWT_FUNCTION_DATAVADDR0_Msk        (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos)      /*!< DWT FUNCTION: DATAVADDR0 Mask */
+
+#define DWT_FUNCTION_DATAVSIZE_Pos         10U                                         /*!< DWT FUNCTION: DATAVSIZE Position */
+#define DWT_FUNCTION_DATAVSIZE_Msk         (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos)       /*!< DWT FUNCTION: DATAVSIZE Mask */
+
+#define DWT_FUNCTION_LNK1ENA_Pos            9U                                         /*!< DWT FUNCTION: LNK1ENA Position */
+#define DWT_FUNCTION_LNK1ENA_Msk           (0x1UL << DWT_FUNCTION_LNK1ENA_Pos)         /*!< DWT FUNCTION: LNK1ENA Mask */
+
+#define DWT_FUNCTION_DATAVMATCH_Pos         8U                                         /*!< DWT FUNCTION: DATAVMATCH Position */
+#define DWT_FUNCTION_DATAVMATCH_Msk        (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos)      /*!< DWT FUNCTION: DATAVMATCH Mask */
+
+#define DWT_FUNCTION_CYCMATCH_Pos           7U                                         /*!< DWT FUNCTION: CYCMATCH Position */
+#define DWT_FUNCTION_CYCMATCH_Msk          (0x1UL << DWT_FUNCTION_CYCMATCH_Pos)        /*!< DWT FUNCTION: CYCMATCH Mask */
+
+#define DWT_FUNCTION_EMITRANGE_Pos          5U                                         /*!< DWT FUNCTION: EMITRANGE Position */
+#define DWT_FUNCTION_EMITRANGE_Msk         (0x1UL << DWT_FUNCTION_EMITRANGE_Pos)       /*!< DWT FUNCTION: EMITRANGE Mask */
+
+#define DWT_FUNCTION_FUNCTION_Pos           0U                                         /*!< DWT FUNCTION: FUNCTION Position */
+#define DWT_FUNCTION_FUNCTION_Msk          (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/)    /*!< DWT FUNCTION: FUNCTION Mask */
+
+/*@}*/ /* end of group CMSIS_DWT */
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_TPI     Trace Port Interface (TPI)
+  \brief    Type definitions for the Trace Port Interface (TPI)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Trace Port Interface Register (TPI).
+ */
+typedef struct
+{
+  __IOM uint32_t SSPSR;                  /*!< Offset: 0x000 (R/ )  Supported Parallel Port Size Register */
+  __IOM uint32_t CSPSR;                  /*!< Offset: 0x004 (R/W)  Current Parallel Port Size Register */
+        uint32_t RESERVED0[2U];
+  __IOM uint32_t ACPR;                   /*!< Offset: 0x010 (R/W)  Asynchronous Clock Prescaler Register */
+        uint32_t RESERVED1[55U];
+  __IOM uint32_t SPPR;                   /*!< Offset: 0x0F0 (R/W)  Selected Pin Protocol Register */
+        uint32_t RESERVED2[131U];
+  __IM  uint32_t FFSR;                   /*!< Offset: 0x300 (R/ )  Formatter and Flush Status Register */
+  __IOM uint32_t FFCR;                   /*!< Offset: 0x304 (R/W)  Formatter and Flush Control Register */
+  __IM  uint32_t FSCR;                   /*!< Offset: 0x308 (R/ )  Formatter Synchronization Counter Register */
+        uint32_t RESERVED3[759U];
+  __IM  uint32_t TRIGGER;                /*!< Offset: 0xEE8 (R/ )  TRIGGER */
+  __IM  uint32_t FIFO0;                  /*!< Offset: 0xEEC (R/ )  Integration ETM Data */
+  __IM  uint32_t ITATBCTR2;              /*!< Offset: 0xEF0 (R/ )  ITATBCTR2 */
+        uint32_t RESERVED4[1U];
+  __IM  uint32_t ITATBCTR0;              /*!< Offset: 0xEF8 (R/ )  ITATBCTR0 */
+  __IM  uint32_t FIFO1;                  /*!< Offset: 0xEFC (R/ )  Integration ITM Data */
+  __IOM uint32_t ITCTRL;                 /*!< Offset: 0xF00 (R/W)  Integration Mode Control */
+        uint32_t RESERVED5[39U];
+  __IOM uint32_t CLAIMSET;               /*!< Offset: 0xFA0 (R/W)  Claim tag set */
+  __IOM uint32_t CLAIMCLR;               /*!< Offset: 0xFA4 (R/W)  Claim tag clear */
+        uint32_t RESERVED7[8U];
+  __IM  uint32_t DEVID;                  /*!< Offset: 0xFC8 (R/ )  TPIU_DEVID */
+  __IM  uint32_t DEVTYPE;                /*!< Offset: 0xFCC (R/ )  TPIU_DEVTYPE */
+} TPI_Type;
+
+/* TPI Asynchronous Clock Prescaler Register Definitions */
+#define TPI_ACPR_PRESCALER_Pos              0U                                         /*!< TPI ACPR: PRESCALER Position */
+#define TPI_ACPR_PRESCALER_Msk             (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)    /*!< TPI ACPR: PRESCALER Mask */
+
+/* TPI Selected Pin Protocol Register Definitions */
+#define TPI_SPPR_TXMODE_Pos                 0U                                         /*!< TPI SPPR: TXMODE Position */
+#define TPI_SPPR_TXMODE_Msk                (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)          /*!< TPI SPPR: TXMODE Mask */
+
+/* TPI Formatter and Flush Status Register Definitions */
+#define TPI_FFSR_FtNonStop_Pos              3U                                         /*!< TPI FFSR: FtNonStop Position */
+#define TPI_FFSR_FtNonStop_Msk             (0x1UL << TPI_FFSR_FtNonStop_Pos)           /*!< TPI FFSR: FtNonStop Mask */
+
+#define TPI_FFSR_TCPresent_Pos              2U                                         /*!< TPI FFSR: TCPresent Position */
+#define TPI_FFSR_TCPresent_Msk             (0x1UL << TPI_FFSR_TCPresent_Pos)           /*!< TPI FFSR: TCPresent Mask */
+
+#define TPI_FFSR_FtStopped_Pos              1U                                         /*!< TPI FFSR: FtStopped Position */
+#define TPI_FFSR_FtStopped_Msk             (0x1UL << TPI_FFSR_FtStopped_Pos)           /*!< TPI FFSR: FtStopped Mask */
+
+#define TPI_FFSR_FlInProg_Pos               0U                                         /*!< TPI FFSR: FlInProg Position */
+#define TPI_FFSR_FlInProg_Msk              (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)        /*!< TPI FFSR: FlInProg Mask */
+
+/* TPI Formatter and Flush Control Register Definitions */
+#define TPI_FFCR_TrigIn_Pos                 8U                                         /*!< TPI FFCR: TrigIn Position */
+#define TPI_FFCR_TrigIn_Msk                (0x1UL << TPI_FFCR_TrigIn_Pos)              /*!< TPI FFCR: TrigIn Mask */
+
+#define TPI_FFCR_EnFCont_Pos                1U                                         /*!< TPI FFCR: EnFCont Position */
+#define TPI_FFCR_EnFCont_Msk               (0x1UL << TPI_FFCR_EnFCont_Pos)             /*!< TPI FFCR: EnFCont Mask */
+
+/* TPI TRIGGER Register Definitions */
+#define TPI_TRIGGER_TRIGGER_Pos             0U                                         /*!< TPI TRIGGER: TRIGGER Position */
+#define TPI_TRIGGER_TRIGGER_Msk            (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)      /*!< TPI TRIGGER: TRIGGER Mask */
+
+/* TPI Integration ETM Data Register Definitions (FIFO0) */
+#define TPI_FIFO0_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO0: ITM_ATVALID Position */
+#define TPI_FIFO0_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos)        /*!< TPI FIFO0: ITM_ATVALID Mask */
+
+#define TPI_FIFO0_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO0: ITM_bytecount Position */
+#define TPI_FIFO0_ITM_bytecount_Msk        (0x3UL << TPI_FIFO0_ITM_bytecount_Pos)      /*!< TPI FIFO0: ITM_bytecount Mask */
+
+#define TPI_FIFO0_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO0: ETM_ATVALID Position */
+#define TPI_FIFO0_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos)        /*!< TPI FIFO0: ETM_ATVALID Mask */
+
+#define TPI_FIFO0_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO0: ETM_bytecount Position */
+#define TPI_FIFO0_ETM_bytecount_Msk        (0x3UL << TPI_FIFO0_ETM_bytecount_Pos)      /*!< TPI FIFO0: ETM_bytecount Mask */
+
+#define TPI_FIFO0_ETM2_Pos                 16U                                         /*!< TPI FIFO0: ETM2 Position */
+#define TPI_FIFO0_ETM2_Msk                 (0xFFUL << TPI_FIFO0_ETM2_Pos)              /*!< TPI FIFO0: ETM2 Mask */
+
+#define TPI_FIFO0_ETM1_Pos                  8U                                         /*!< TPI FIFO0: ETM1 Position */
+#define TPI_FIFO0_ETM1_Msk                 (0xFFUL << TPI_FIFO0_ETM1_Pos)              /*!< TPI FIFO0: ETM1 Mask */
+
+#define TPI_FIFO0_ETM0_Pos                  0U                                         /*!< TPI FIFO0: ETM0 Position */
+#define TPI_FIFO0_ETM0_Msk                 (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/)          /*!< TPI FIFO0: ETM0 Mask */
+
+/* TPI ITATBCTR2 Register Definitions */
+#define TPI_ITATBCTR2_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR2: ATREADY Position */
+#define TPI_ITATBCTR2_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/)    /*!< TPI ITATBCTR2: ATREADY Mask */
+
+/* TPI Integration ITM Data Register Definitions (FIFO1) */
+#define TPI_FIFO1_ITM_ATVALID_Pos          29U                                         /*!< TPI FIFO1: ITM_ATVALID Position */
+#define TPI_FIFO1_ITM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos)        /*!< TPI FIFO1: ITM_ATVALID Mask */
+
+#define TPI_FIFO1_ITM_bytecount_Pos        27U                                         /*!< TPI FIFO1: ITM_bytecount Position */
+#define TPI_FIFO1_ITM_bytecount_Msk        (0x3UL << TPI_FIFO1_ITM_bytecount_Pos)      /*!< TPI FIFO1: ITM_bytecount Mask */
+
+#define TPI_FIFO1_ETM_ATVALID_Pos          26U                                         /*!< TPI FIFO1: ETM_ATVALID Position */
+#define TPI_FIFO1_ETM_ATVALID_Msk          (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos)        /*!< TPI FIFO1: ETM_ATVALID Mask */
+
+#define TPI_FIFO1_ETM_bytecount_Pos        24U                                         /*!< TPI FIFO1: ETM_bytecount Position */
+#define TPI_FIFO1_ETM_bytecount_Msk        (0x3UL << TPI_FIFO1_ETM_bytecount_Pos)      /*!< TPI FIFO1: ETM_bytecount Mask */
+
+#define TPI_FIFO1_ITM2_Pos                 16U                                         /*!< TPI FIFO1: ITM2 Position */
+#define TPI_FIFO1_ITM2_Msk                 (0xFFUL << TPI_FIFO1_ITM2_Pos)              /*!< TPI FIFO1: ITM2 Mask */
+
+#define TPI_FIFO1_ITM1_Pos                  8U                                         /*!< TPI FIFO1: ITM1 Position */
+#define TPI_FIFO1_ITM1_Msk                 (0xFFUL << TPI_FIFO1_ITM1_Pos)              /*!< TPI FIFO1: ITM1 Mask */
+
+#define TPI_FIFO1_ITM0_Pos                  0U                                         /*!< TPI FIFO1: ITM0 Position */
+#define TPI_FIFO1_ITM0_Msk                 (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/)          /*!< TPI FIFO1: ITM0 Mask */
+
+/* TPI ITATBCTR0 Register Definitions */
+#define TPI_ITATBCTR0_ATREADY_Pos           0U                                         /*!< TPI ITATBCTR0: ATREADY Position */
+#define TPI_ITATBCTR0_ATREADY_Msk          (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/)    /*!< TPI ITATBCTR0: ATREADY Mask */
+
+/* TPI Integration Mode Control Register Definitions */
+#define TPI_ITCTRL_Mode_Pos                 0U                                         /*!< TPI ITCTRL: Mode Position */
+#define TPI_ITCTRL_Mode_Msk                (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/)          /*!< TPI ITCTRL: Mode Mask */
+
+/* TPI DEVID Register Definitions */
+#define TPI_DEVID_NRZVALID_Pos             11U                                         /*!< TPI DEVID: NRZVALID Position */
+#define TPI_DEVID_NRZVALID_Msk             (0x1UL << TPI_DEVID_NRZVALID_Pos)           /*!< TPI DEVID: NRZVALID Mask */
+
+#define TPI_DEVID_MANCVALID_Pos            10U                                         /*!< TPI DEVID: MANCVALID Position */
+#define TPI_DEVID_MANCVALID_Msk            (0x1UL << TPI_DEVID_MANCVALID_Pos)          /*!< TPI DEVID: MANCVALID Mask */
+
+#define TPI_DEVID_PTINVALID_Pos             9U                                         /*!< TPI DEVID: PTINVALID Position */
+#define TPI_DEVID_PTINVALID_Msk            (0x1UL << TPI_DEVID_PTINVALID_Pos)          /*!< TPI DEVID: PTINVALID Mask */
+
+#define TPI_DEVID_MinBufSz_Pos              6U                                         /*!< TPI DEVID: MinBufSz Position */
+#define TPI_DEVID_MinBufSz_Msk             (0x7UL << TPI_DEVID_MinBufSz_Pos)           /*!< TPI DEVID: MinBufSz Mask */
+
+#define TPI_DEVID_AsynClkIn_Pos             5U                                         /*!< TPI DEVID: AsynClkIn Position */
+#define TPI_DEVID_AsynClkIn_Msk            (0x1UL << TPI_DEVID_AsynClkIn_Pos)          /*!< TPI DEVID: AsynClkIn Mask */
+
+#define TPI_DEVID_NrTraceInput_Pos          0U                                         /*!< TPI DEVID: NrTraceInput Position */
+#define TPI_DEVID_NrTraceInput_Msk         (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)  /*!< TPI DEVID: NrTraceInput Mask */
+
+/* TPI DEVTYPE Register Definitions */
+#define TPI_DEVTYPE_MajorType_Pos           4U                                         /*!< TPI DEVTYPE: MajorType Position */
+#define TPI_DEVTYPE_MajorType_Msk          (0xFUL << TPI_DEVTYPE_MajorType_Pos)        /*!< TPI DEVTYPE: MajorType Mask */
+
+#define TPI_DEVTYPE_SubType_Pos             0U                                         /*!< TPI DEVTYPE: SubType Position */
+#define TPI_DEVTYPE_SubType_Msk            (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)      /*!< TPI DEVTYPE: SubType Mask */
+
+/*@}*/ /* end of group CMSIS_TPI */
+
+
+#if (__MPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_MPU     Memory Protection Unit (MPU)
+  \brief    Type definitions for the Memory Protection Unit (MPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __IM  uint32_t TYPE;                   /*!< Offset: 0x000 (R/ )  MPU Type Register */
+  __IOM uint32_t CTRL;                   /*!< Offset: 0x004 (R/W)  MPU Control Register */
+  __IOM uint32_t RNR;                    /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register */
+  __IOM uint32_t RBAR;                   /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register */
+  __IOM uint32_t RASR;                   /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A1;                /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register */
+  __IOM uint32_t RASR_A1;                /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A2;                /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register */
+  __IOM uint32_t RASR_A2;                /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IOM uint32_t RBAR_A3;                /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register */
+  __IOM uint32_t RASR_A3;                /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register Definitions */
+#define MPU_TYPE_IREGION_Pos               16U                                            /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8U                                            /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0U                                            /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL /*<< MPU_TYPE_SEPARATE_Pos*/)             /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register Definitions */
+#define MPU_CTRL_PRIVDEFENA_Pos             2U                                            /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1U                                            /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0U                                            /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL /*<< MPU_CTRL_ENABLE_Pos*/)               /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register Definitions */
+#define MPU_RNR_REGION_Pos                  0U                                            /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL /*<< MPU_RNR_REGION_Pos*/)             /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register Definitions */
+#define MPU_RBAR_ADDR_Pos                   5U                                            /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4U                                            /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0U                                            /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL /*<< MPU_RBAR_REGION_Pos*/)             /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register Definitions */
+#define MPU_RASR_ATTRS_Pos                 16U                                            /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_XN_Pos                    28U                                            /*!< MPU RASR: ATTRS.XN Position */
+#define MPU_RASR_XN_Msk                    (1UL << MPU_RASR_XN_Pos)                       /*!< MPU RASR: ATTRS.XN Mask */
+
+#define MPU_RASR_AP_Pos                    24U                                            /*!< MPU RASR: ATTRS.AP Position */
+#define MPU_RASR_AP_Msk                    (0x7UL << MPU_RASR_AP_Pos)                     /*!< MPU RASR: ATTRS.AP Mask */
+
+#define MPU_RASR_TEX_Pos                   19U                                            /*!< MPU RASR: ATTRS.TEX Position */
+#define MPU_RASR_TEX_Msk                   (0x7UL << MPU_RASR_TEX_Pos)                    /*!< MPU RASR: ATTRS.TEX Mask */
+
+#define MPU_RASR_S_Pos                     18U                                            /*!< MPU RASR: ATTRS.S Position */
+#define MPU_RASR_S_Msk                     (1UL << MPU_RASR_S_Pos)                        /*!< MPU RASR: ATTRS.S Mask */
+
+#define MPU_RASR_C_Pos                     17U                                            /*!< MPU RASR: ATTRS.C Position */
+#define MPU_RASR_C_Msk                     (1UL << MPU_RASR_C_Pos)                        /*!< MPU RASR: ATTRS.C Mask */
+
+#define MPU_RASR_B_Pos                     16U                                            /*!< MPU RASR: ATTRS.B Position */
+#define MPU_RASR_B_Msk                     (1UL << MPU_RASR_B_Pos)                        /*!< MPU RASR: ATTRS.B Mask */
+
+#define MPU_RASR_SRD_Pos                    8U                                            /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1U                                            /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0U                                            /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL /*<< MPU_RASR_ENABLE_Pos*/)               /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1U)
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_FPU     Floating Point Unit (FPU)
+  \brief    Type definitions for the Floating Point Unit (FPU)
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+        uint32_t RESERVED0[1U];
+  __IOM uint32_t FPCCR;                  /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register */
+  __IOM uint32_t FPCAR;                  /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register */
+  __IOM uint32_t FPDSCR;                 /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register */
+  __IM  uint32_t MVFR0;                  /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0 */
+  __IM  uint32_t MVFR1;                  /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1 */
+} FPU_Type;
+
+/* Floating-Point Context Control Register Definitions */
+#define FPU_FPCCR_ASPEN_Pos                31U                                            /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30U                                            /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8U                                            /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6U                                            /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5U                                            /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4U                                            /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3U                                            /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1U                                            /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0U                                            /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL /*<< FPU_FPCCR_LSPACT_Pos*/)              /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register Definitions */
+#define FPU_FPCAR_ADDRESS_Pos               3U                                            /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register Definitions */
+#define FPU_FPDSCR_AHP_Pos                 26U                                            /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25U                                            /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24U                                            /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22U                                            /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 Definitions */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28U                                            /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24U                                            /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20U                                            /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16U                                            /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12U                                            /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8U                                            /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4U                                            /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0U                                            /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/)  /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 Definitions */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28U                                            /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24U                                            /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4U                                            /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0U                                            /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/)          /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/**
+  \ingroup  CMSIS_core_register
+  \defgroup CMSIS_CoreDebug       Core Debug Registers (CoreDebug)
+  \brief    Type definitions for the Core Debug Registers
+  @{
+ */
+
+/**
+  \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IOM uint32_t DHCSR;                  /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register */
+  __OM  uint32_t DCRSR;                  /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register */
+  __IOM uint32_t DCRDR;                  /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register */
+  __IOM uint32_t DEMCR;                  /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register Definitions */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16U                                            /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25U                                            /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24U                                            /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19U                                            /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18U                                            /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17U                                            /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16U                                            /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5U                                            /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3U                                            /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2U                                            /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1U                                            /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0U                                            /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/)     /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register Definitions */
+#define CoreDebug_DCRSR_REGWnR_Pos         16U                                            /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0U                                            /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/)     /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register Definitions */
+#define CoreDebug_DEMCR_TRCENA_Pos         24U                                            /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19U                                            /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18U                                            /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17U                                            /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16U                                            /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10U                                            /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9U                                            /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8U                                            /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7U                                            /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6U                                            /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5U                                            /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4U                                            /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0U                                            /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/)  /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_bitfield     Core register bit field macros
+  \brief      Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
+  @{
+ */
+
+/**
+  \brief   Mask and shift a bit field value for use in a register bit range.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of the bit field.
+  \return           Masked and shifted value.
+*/
+#define _VAL2FLD(field, value)    ((value << field ## _Pos) & field ## _Msk)
+
+/**
+  \brief     Mask and shift a register value to extract a bit filed value.
+  \param[in] field  Name of the register bit field.
+  \param[in] value  Value of register.
+  \return           Masked and shifted bit field value.
+*/
+#define _FLD2VAL(field, value)    ((value & field ## _Msk) >> field ## _Pos)
+
+/*@} end of group CMSIS_core_bitfield */
+
+
+/**
+  \ingroup    CMSIS_core_register
+  \defgroup   CMSIS_core_base     Core Definitions
+  \brief      Definitions for base addresses, unions, and structures.
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address */
+#define DWT_BASE            (0xE0001000UL)                            /*!< DWT Base Address */
+#define TPI_BASE            (0xE0040000UL)                            /*!< TPI Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct */
+#define DWT                 ((DWT_Type       *)     DWT_BASE      )   /*!< DWT configuration struct */
+#define TPI                 ((TPI_Type       *)     TPI_BASE      )   /*!< TPI configuration struct */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct */
+
+#if (__MPU_PRESENT == 1U)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit */
+#endif
+
+#if (__FPU_PRESENT == 1U)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+ ******************************************************************************/
+/**
+  \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_NVICFunctions NVIC Functions
+  \brief    Functions that manage interrupts and exceptions via the NVIC.
+  @{
+ */
+
+/**
+  \brief   Set Priority Grouping
+  \details Sets the priority grouping field using the required unlock sequence.
+           The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+           Only values from 0..7 are used.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]      PriorityGroup  Priority grouping field.
+ */
+__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);             /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change               */
+  reg_value  =  (reg_value                                   |
+                ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8U)                      );              /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/**
+  \brief   Get Priority Grouping
+  \details Reads the priority grouping field from the NVIC Interrupt Controller.
+  \return                Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
+}
+
+
+/**
+  \brief   Enable External Interrupt
+  \details Enables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Disable External Interrupt
+  \details Disables a device-specific interrupt in the NVIC interrupt controller.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Pending Interrupt
+  \details Reads the pending register in the NVIC and returns the pending bit for the specified interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not pending.
+  \return             1  Interrupt status is pending.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Pending Interrupt
+  \details Sets the pending bit of an external interrupt.
+  \param [in]      IRQn  Interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Clear Pending Interrupt
+  \details Clears the pending bit of an external interrupt.
+  \param [in]      IRQn  External interrupt number. Value cannot be negative.
+ */
+__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
+}
+
+
+/**
+  \brief   Get Active Interrupt
+  \details Reads the active register in NVIC and returns the active bit.
+  \param [in]      IRQn  Interrupt number.
+  \return             0  Interrupt status is not active.
+  \return             1  Interrupt status is active.
+ */
+__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
+}
+
+
+/**
+  \brief   Set Interrupt Priority
+  \details Sets the priority of an interrupt.
+  \note    The priority cannot be set for every core interrupt.
+  \param [in]      IRQn  Interrupt number.
+  \param [in]  priority  Priority to set.
+ */
+__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if ((int32_t)(IRQn) < 0)
+  {
+    SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+  else
+  {
+    NVIC->IP[((uint32_t)(int32_t)IRQn)]               = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
+  }
+}
+
+
+/**
+  \brief   Get Interrupt Priority
+  \details Reads the priority of an interrupt.
+           The interrupt number can be positive to specify an external (device specific) interrupt,
+           or negative to specify an internal (core) interrupt.
+  \param [in]   IRQn  Interrupt number.
+  \return             Interrupt Priority.
+                      Value is aligned automatically to the implemented priority bits of the microcontroller.
+ */
+__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if ((int32_t)(IRQn) < 0)
+  {
+    return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
+  }
+  else
+  {
+    return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)]               >> (8U - __NVIC_PRIO_BITS)));
+  }
+}
+
+
+/**
+  \brief   Encode Priority
+  \details Encodes the priority for an interrupt with the given priority group,
+           preemptive priority value, and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
+  \param [in]     PriorityGroup  Used priority group.
+  \param [in]   PreemptPriority  Preemptive priority value (starting from 0).
+  \param [in]       SubPriority  Subpriority value (starting from 0).
+  \return                        Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
+ */
+__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  return (
+           ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
+           ((SubPriority     & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL)))
+         );
+}
+
+
+/**
+  \brief   Decode Priority
+  \details Decodes an interrupt priority value with a given priority group to
+           preemptive priority value and subpriority value.
+           In case of a conflict between priority grouping and available
+           priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+  \param [in]         Priority   Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
+  \param [in]     PriorityGroup  Used priority group.
+  \param [out] pPreemptPriority  Preemptive priority value (starting from 0).
+  \param [out]     pSubPriority  Subpriority value (starting from 0).
+ */
+__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL);   /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
+  SubPriorityBits     = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
+  *pSubPriority     = (Priority                   ) & (uint32_t)((1UL << (SubPriorityBits    )) - 1UL);
+}
+
+
+/**
+  \brief   System Reset
+  \details Initiates a system reset request to reset the MCU.
+ */
+__STATIC_INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos)    |
+                           (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                            SCB_AIRCR_SYSRESETREQ_Msk    );         /* Keep priority group unchanged */
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+  }
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
+  \brief    Functions that configure the System.
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0U)
+
+/**
+  \brief   System Tick Configuration
+  \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
+           Counter is in free running mode to generate periodic interrupts.
+  \param [in]  ticks  Number of ticks between two interrupts.
+  \return          0  Function succeeded.
+  \return          1  Function failed.
+  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+  {
+    return (1UL);                                                   /* Reload value impossible */
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
+  return (0UL);                                                     /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/**
+  \ingroup  CMSIS_Core_FunctionInterface
+  \defgroup CMSIS_core_DebugFunctions ITM Functions
+  \brief    Functions that access the ITM debug interface.
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< External variable to receive characters. */
+#define                 ITM_RXBUFFER_EMPTY   0x5AA55AA5U /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
+
+
+/**
+  \brief   ITM Send Character
+  \details Transmits a character via the ITM channel 0, and
+           \li Just returns when no debugger is connected that has booked the output.
+           \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
+  \param [in]     ch  Character to transmit.
+  \returns            Character to transmit.
+ */
+__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) &&      /* ITM enabled */
+      ((ITM->TER & 1UL               ) != 0UL)   )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0U].u32 == 0UL)
+    {
+      __NOP();
+    }
+    ITM->PORT[0U].u8 = (uint8_t)ch;
+  }
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Receive Character
+  \details Inputs a character via the external variable \ref ITM_RxBuffer.
+  \return             Received character.
+  \return         -1  No character pending.
+ */
+__STATIC_INLINE int32_t ITM_ReceiveChar (void)
+{
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
+  {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/**
+  \brief   ITM Check Character
+  \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
+  \return          0  No character available.
+  \return          1  Character available.
+ */
+__STATIC_INLINE int32_t ITM_CheckChar (void)
+{
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
+  {
+    return (0);                              /* no character available */
+  }
+  else
+  {
+    return (1);                              /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
\ No newline at end of file

diff --git a/src/device/core_cmFunc.h b/src/device/core_cmFunc.h
new file mode 100644 (file)
index 0000000..ca319a5
--- /dev/null
+++ b/src/device/core_cmFunc.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**\r
+ * @file     core_cmFunc.h\r
+ * @brief    CMSIS Cortex-M Core Function Access Header File\r
+ * @version  V4.30\r
+ * @date     20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+   All rights reserved.\r
+   Redistribution and use in source and binary forms, with or without\r
+   modification, are permitted provided that the following conditions are met:\r
+   - Redistributions of source code must retain the above copyright\r
+     notice, this list of conditions and the following disclaimer.\r
+   - Redistributions in binary form must reproduce the above copyright\r
+     notice, this list of conditions and the following disclaimer in the\r
+     documentation and/or other materials provided with the distribution.\r
+   - Neither the name of ARM nor the names of its contributors may be used\r
+     to endorse or promote products derived from this software without\r
+     specific prior written permission.\r
+   *\r
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+   POSSIBILITY OF SUCH DAMAGE.\r
+   ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if   defined ( __ICCARM__ )\r
+ #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMFUNC_H\r
+#define __CORE_CMFUNC_H\r
+\r
+\r
+/* ###########################  Core Function Access  ########################### */\r
+/** \ingroup  CMSIS_Core_FunctionInterface\r
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions\r
+  @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if   defined ( __CC_ARM )\r
+  #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+  #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+  #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+  #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+  /*\r
+   * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+   * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+   * Including the CMSIS ones.\r
+   */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+  #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of CMSIS_Core_RegAccFunctions */\r
+\r
+#endif /* __CORE_CMFUNC_H */\r

diff --git a/src/device/core_cmInstr.h b/src/device/core_cmInstr.h
new file mode 100644 (file)
index 0000000..a0a5064
--- /dev/null
+++ b/src/device/core_cmInstr.h
@@ -0,0 +1,87 @@
+/**************************************************************************//**\r
+ * @file     core_cmInstr.h\r
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File\r
+ * @version  V4.30\r
+ * @date     20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+   All rights reserved.\r
+   Redistribution and use in source and binary forms, with or without\r
+   modification, are permitted provided that the following conditions are met:\r
+   - Redistributions of source code must retain the above copyright\r
+     notice, this list of conditions and the following disclaimer.\r
+   - Redistributions in binary form must reproduce the above copyright\r
+     notice, this list of conditions and the following disclaimer in the\r
+     documentation and/or other materials provided with the distribution.\r
+   - Neither the name of ARM nor the names of its contributors may be used\r
+     to endorse or promote products derived from this software without\r
+     specific prior written permission.\r
+   *\r
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+   POSSIBILITY OF SUCH DAMAGE.\r
+   ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if   defined ( __ICCARM__ )\r
+ #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMINSTR_H\r
+#define __CORE_CMINSTR_H\r
+\r
+\r
+/* ##########################  Core Instruction Access  ######################### */\r
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface\r
+  Access to dedicated instructions\r
+  @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if   defined ( __CC_ARM )\r
+  #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+  #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+  #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+  #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+  /*\r
+   * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+   * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+   * Including the CMSIS ones.\r
+   */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+  #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */\r
+\r
+#endif /* __CORE_CMINSTR_H */\r

diff --git a/src/device/core_cmSimd.h b/src/device/core_cmSimd.h
new file mode 100644 (file)
index 0000000..4d76bf9
--- /dev/null
+++ b/src/device/core_cmSimd.h
@@ -0,0 +1,96 @@
+/**************************************************************************//**\r
+ * @file     core_cmSimd.h\r
+ * @brief    CMSIS Cortex-M SIMD Header File\r
+ * @version  V4.30\r
+ * @date     20. October 2015\r
+ ******************************************************************************/\r
+/* Copyright (c) 2009 - 2015 ARM LIMITED\r
+\r
+   All rights reserved.\r
+   Redistribution and use in source and binary forms, with or without\r
+   modification, are permitted provided that the following conditions are met:\r
+   - Redistributions of source code must retain the above copyright\r
+     notice, this list of conditions and the following disclaimer.\r
+   - Redistributions in binary form must reproduce the above copyright\r
+     notice, this list of conditions and the following disclaimer in the\r
+     documentation and/or other materials provided with the distribution.\r
+   - Neither the name of ARM nor the names of its contributors may be used\r
+     to endorse or promote products derived from this software without\r
+     specific prior written permission.\r
+   *\r
+   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\r
+   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\r
+   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE\r
+   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE\r
+   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\r
+   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\r
+   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\r
+   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\r
+   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\r
+   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\r
+   POSSIBILITY OF SUCH DAMAGE.\r
+   ---------------------------------------------------------------------------*/\r
+\r
+\r
+#if   defined ( __ICCARM__ )\r
+ #pragma system_include         /* treat file as system include file for MISRA check */\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #pragma clang system_header   /* treat file as system include file */\r
+#endif\r
+\r
+#ifndef __CORE_CMSIMD_H\r
+#define __CORE_CMSIMD_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif\r
+\r
+\r
+/* ###################  Compiler specific Intrinsics  ########################### */\r
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics\r
+  Access to dedicated SIMD instructions\r
+  @{\r
+*/\r
+\r
+/*------------------ RealView Compiler -----------------*/\r
+#if   defined ( __CC_ARM )\r
+  #include "cmsis_armcc.h"\r
+\r
+/*------------------ ARM Compiler V6 -------------------*/\r
+#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)\r
+  #include "cmsis_armcc_V6.h"\r
+\r
+/*------------------ GNU Compiler ----------------------*/\r
+#elif defined ( __GNUC__ )\r
+  #include "cmsis_gcc.h"\r
+\r
+/*------------------ ICC Compiler ----------------------*/\r
+#elif defined ( __ICCARM__ )\r
+  #include <cmsis_iar.h>\r
+\r
+/*------------------ TI CCS Compiler -------------------*/\r
+#elif defined ( __TMS470__ )\r
+  #include <cmsis_ccs.h>\r
+\r
+/*------------------ TASKING Compiler ------------------*/\r
+#elif defined ( __TASKING__ )\r
+  /*\r
+   * The CMSIS functions have been implemented as intrinsics in the compiler.\r
+   * Please use "carm -?i" to get an up to date list of all intrinsics,\r
+   * Including the CMSIS ones.\r
+   */\r
+\r
+/*------------------ COSMIC Compiler -------------------*/\r
+#elif defined ( __CSMC__ )\r
+  #include <cmsis_csm.h>\r
+\r
+#endif\r
+\r
+/*@} end of group CMSIS_SIMD_intrinsics */\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+#endif /* __CORE_CMSIMD_H */\r

diff --git a/src/device/stm32f4xx.h b/src/device/stm32f4xx.h
new file mode 100644 (file)
index 0000000..58b2883
--- /dev/null
+++ b/src/device/stm32f4xx.h
@@ -0,0 +1,9979 @@
+/**\r
+  ******************************************************************************\r
+  * @file    stm32f4xx.h\r
+  * @author  MCD Application Team\r
+  * @version V1.2.0RC2 - edited by Keil\r
+  * @date    20-February-2013\r
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. \r
+  *          This file contains all the peripheral register's definitions, bits \r
+  *          definitions and memory mapping for STM32F4xx devices.            \r
+  *            \r
+  *          The file is the unique include file that the application programmer\r
+  *          is using in the C source code, usually in main.c. This file contains:\r
+  *           - Configuration section that allows to select:\r
+  *              - The device used in the target application\r
+  *              - To use or not the peripheral�s drivers in application code(i.e. \r
+  *                code will be based on direct access to peripheral�s registers \r
+  *                rather than drivers API), this option is controlled by \r
+  *                "#define USE_STDPERIPH_DRIVER"\r
+  *              - To change few application-specific parameters such as the HSE \r
+  *                crystal frequency\r
+  *           - Data structures and the address mapping for all peripherals\r
+  *           - Peripheral's registers declarations and bits definition\r
+  *           - Macros to access peripheral�s registers hardware\r
+  *  \r
+  ******************************************************************************\r
+  * @attention\r
+  *\r
+  * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>\r
+  *\r
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");\r
+  * You may not use this file except in compliance with the License.\r
+  * You may obtain a copy of the License at:\r
+  *\r
+  *        http://www.st.com/software_license_agreement_liberty_v2\r
+  *\r
+  * Unless required by applicable law or agreed to in writing, software \r
+  * distributed under the License is distributed on an "AS IS" BASIS, \r
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\r
+  * See the License for the specific language governing permissions and\r
+  * limitations under the License.\r
+  *\r
+  ******************************************************************************  \r
+  */ \r
+\r
+/** @addtogroup CMSIS\r
+  * @{\r
+  */\r
+\r
+/** @addtogroup stm32f4xx\r
+  * @{\r
+  */\r
+    \r
+#ifndef __STM32F4xx_H\r
+#define __STM32F4xx_H\r
+\r
+#ifdef __cplusplus\r
+ extern "C" {\r
+#endif /* __cplusplus */\r
+  \r
+/** @addtogroup Library_configuration_section\r
+  * @{\r
+  */\r
+  \r
+/* Uncomment the line below according to the target STM32 device used in your\r
+   application \r
+  */\r
+\r
+#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X) \r
+  #define STM32F40XX    /*!< STM32F40xx/41xx Devices */\r
+  /* #define STM32F427X */   /*!< STM32F427x/437x Devices */\r
+  /* #define STM32F429X */   /*!< STM32F429x/439x Devices */\r
+#endif\r
+\r
+\r
+/*  Tip: To avoid modifying this file each time you need to switch between these\r
+        devices, you can define the device in your toolchain compiler preprocessor.\r
+  */\r
+\r
+#if !defined (STM32F40XX) && !defined (STM32F427X) && !defined (STM32F429X)\r
+ #error "Please select first the target STM32F4xx device used in your application (in stm32f4xx.h file)"\r
+#endif\r
+\r
+#if !defined  (USE_STDPERIPH_DRIVER)\r
+/**\r
+ * @brief Comment the line below if you will not use the peripherals drivers.\r
+   In this case, these drivers will not be included and the application code will \r
+   be based on direct access to peripherals registers \r
+   */\r
+  /*#define USE_STDPERIPH_DRIVER */\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/**\r
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)\r
+   used in your application \r
+   \r
+   Tip: To avoid modifying this file each time you need to use different HSE, you\r
+        can define the HSE value in your toolchain compiler preprocessor.\r
+  */           \r
+\r
+#if !defined  (HSE_VALUE) \r
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */\r
+  \r
+#endif /* HSE_VALUE */\r
+\r
+/**\r
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup \r
+   Timeout value \r
+   */\r
+#if !defined  (HSE_STARTUP_TIMEOUT) \r
+  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0600)   /*!< Time out for HSE start up */\r
+#endif /* HSE_STARTUP_TIMEOUT */   \r
+\r
+#if !defined  (HSI_VALUE)   \r
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/\r
+#endif /* HSI_VALUE */   \r
+\r
+/**\r
+ * @brief STM32F4XX Standard Peripherals Library version number V1.2.0CR2\r
+   */\r
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  \r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */\r
+#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x02) /*!< [7:0]  release candidate */ \r
+#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\\r
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\\r
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\\r
+                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))\r
+                                             \r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Configuration_section_for_CMSIS\r
+  * @{\r
+  */\r
+\r
+/**\r
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals \r
+ */\r
+#define __CM4_REV                 0x0001  /*!< Core revision r0p1                            */\r
+#define __MPU_PRESENT             1       /*!< STM32F4XX provides an MPU                     */\r
+#define __NVIC_PRIO_BITS          4       /*!< STM32F4XX uses 4 Bits for the Priority Levels */\r
+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */\r
+#define __FPU_PRESENT             1       /*!< FPU present                                   */\r
+\r
+/**\r
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device \r
+ *        in @ref Library_configuration_section \r
+ */\r
+typedef enum IRQn\r
+{\r
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/\r
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */\r
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */\r
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */\r
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */\r
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */\r
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */\r
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */\r
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */\r
+/******  STM32 specific Interrupt Numbers **********************************************************************/\r
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */\r
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */\r
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */\r
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */\r
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */\r
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */\r
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */\r
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */\r
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */\r
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */\r
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */\r
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */\r
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */\r
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */\r
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */\r
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */\r
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */\r
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */\r
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */\r
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */\r
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */\r
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */\r
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */\r
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */\r
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */\r
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */\r
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */\r
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */\r
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */\r
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */\r
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */\r
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */\r
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */\r
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */\r
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  \r
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */\r
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */\r
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */\r
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */\r
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */\r
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */\r
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */\r
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    \r
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */\r
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */\r
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */\r
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */\r
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined(STM32F429X)\r
+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */\r
+#endif /* STM32F429X */ \r
+\r
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */\r
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */\r
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */\r
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */\r
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */\r
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */\r
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */\r
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */\r
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */\r
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */\r
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */\r
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */\r
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */\r
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */\r
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */\r
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */\r
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */\r
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */\r
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */\r
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */\r
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */\r
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */\r
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */\r
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */\r
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */\r
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */\r
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */\r
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */\r
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */\r
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */\r
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */\r
+  HASH_RNG_IRQn               = 80,     /*!< Hash and Rng global interrupt                                     */\r
+\r
+#if defined(STM32F40XX)\r
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */\r
+#endif /* STM32F40XX */\r
+\r
+#if defined (STM32F427X) \r
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r
+  SPI6_IRQn                   = 86      /*!< SPI6 global Interrupt                                             */\r
+#endif /* STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */\r
+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */\r
+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */\r
+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */\r
+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */\r
+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */\r
+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */\r
+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                              */\r
+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                        */\r
+  DMA2D_IRQn                  = 90      /*!< DMA2D global Interrupt                                            */\r
+#endif /* STM32F429X */  \r
+} IRQn_Type;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */\r
+#include "system_stm32f4xx.h"\r
+#include <stdint.h>\r
+\r
+/** @addtogroup Exported_types\r
+  * @{\r
+  */  \r
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */\r
+typedef int32_t  s32;\r
+typedef int16_t s16;\r
+typedef int8_t  s8;\r
+\r
+typedef const int32_t sc32;  /*!< Read Only */\r
+typedef const int16_t sc16;  /*!< Read Only */\r
+typedef const int8_t sc8;   /*!< Read Only */\r
+\r
+typedef __IO int32_t  vs32;\r
+typedef __IO int16_t  vs16;\r
+typedef __IO int8_t   vs8;\r
+\r
+typedef __I int32_t vsc32;  /*!< Read Only */\r
+typedef __I int16_t vsc16;  /*!< Read Only */\r
+typedef __I int8_t vsc8;   /*!< Read Only */\r
+\r
+typedef uint32_t  u32;\r
+typedef uint16_t u16;\r
+typedef uint8_t  u8;\r
+\r
+typedef const uint32_t uc32;  /*!< Read Only */\r
+typedef const uint16_t uc16;  /*!< Read Only */\r
+typedef const uint8_t uc8;   /*!< Read Only */\r
+\r
+typedef __IO uint32_t  vu32;\r
+typedef __IO uint16_t vu16;\r
+typedef __IO uint8_t  vu8;\r
+\r
+typedef __I uint32_t vuc32;  /*!< Read Only */\r
+typedef __I uint16_t vuc16;  /*!< Read Only */\r
+typedef __I uint8_t vuc8;   /*!< Read Only */\r
+\r
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;\r
+\r
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;\r
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))\r
+\r
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Peripheral_registers_structures\r
+  * @{\r
+  */   \r
+\r
+/** \r
+  * @brief Analog to Digital Converter  \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */\r
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      \r
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */\r
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */\r
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */\r
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */\r
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */\r
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */\r
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */\r
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */\r
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */\r
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */\r
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */\r
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */\r
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/\r
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */\r
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */\r
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */\r
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */\r
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */\r
+} ADC_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */\r
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */\r
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual\r
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */\r
+} ADC_Common_TypeDef;\r
+\r
+\r
+/** \r
+  * @brief Controller Area Network TxMailBox \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */\r
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */\r
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */\r
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */\r
+} CAN_TxMailBox_TypeDef;\r
+\r
+/** \r
+  * @brief Controller Area Network FIFOMailBox \r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */\r
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */\r
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */\r
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */\r
+} CAN_FIFOMailBox_TypeDef;\r
+\r
+/** \r
+  * @brief Controller Area Network FilterRegister \r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */\r
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */\r
+} CAN_FilterRegister_TypeDef;\r
+\r
+/** \r
+  * @brief Controller Area Network \r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */\r
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */\r
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */\r
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */\r
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */\r
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */\r
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */\r
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */\r
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */\r
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */\r
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */\r
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */\r
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */\r
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */\r
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */\r
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */\r
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */\r
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */\r
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */\r
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */\r
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ \r
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */\r
+} CAN_TypeDef;\r
+\r
+/** \r
+  * @brief CRC calculation unit \r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */\r
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */\r
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */\r
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */\r
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */\r
+} CRC_TypeDef;\r
+\r
+/** \r
+  * @brief Digital to Analog Converter\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */\r
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */\r
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */\r
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */\r
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */\r
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */\r
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */\r
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */\r
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */\r
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */\r
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */\r
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */\r
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */\r
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */\r
+} DAC_TypeDef;\r
+\r
+/** \r
+  * @brief Debug MCU\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */\r
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */\r
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */\r
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */\r
+}DBGMCU_TypeDef;\r
+\r
+/** \r
+  * @brief DCMI\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */\r
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */\r
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */\r
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */\r
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */\r
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */\r
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */\r
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */\r
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */\r
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */\r
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */\r
+} DCMI_TypeDef;\r
+\r
+/** \r
+  * @brief DMA Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */\r
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */\r
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */\r
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */\r
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */\r
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */\r
+} DMA_Stream_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */\r
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */\r
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */\r
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */\r
+} DMA_TypeDef;\r
+\r
+#if defined (STM32F429X) \r
+/** \r
+  * @brief DMA2D Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */\r
+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */\r
+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */\r
+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */\r
+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */\r
+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */\r
+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */\r
+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */\r
+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */\r
+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */\r
+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */\r
+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */\r
+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */\r
+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */\r
+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */\r
+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */\r
+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */\r
+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */\r
+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */\r
+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */\r
+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */\r
+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */\r
+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */\r
+} DMA2D_TypeDef;\r
+#endif /* STM32F429X  */\r
+\r
+/** \r
+  * @brief Ethernet MAC\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MACCR;\r
+  __IO uint32_t MACFFR;\r
+  __IO uint32_t MACHTHR;\r
+  __IO uint32_t MACHTLR;\r
+  __IO uint32_t MACMIIAR;\r
+  __IO uint32_t MACMIIDR;\r
+  __IO uint32_t MACFCR;\r
+  __IO uint32_t MACVLANTR;             /*    8 */\r
+  uint32_t      RESERVED0[2];\r
+  __IO uint32_t MACRWUFFR;             /*   11 */\r
+  __IO uint32_t MACPMTCSR;\r
+  uint32_t      RESERVED1[2];\r
+  __IO uint32_t MACSR;                 /*   15 */\r
+  __IO uint32_t MACIMR;\r
+  __IO uint32_t MACA0HR;\r
+  __IO uint32_t MACA0LR;\r
+  __IO uint32_t MACA1HR;\r
+  __IO uint32_t MACA1LR;\r
+  __IO uint32_t MACA2HR;\r
+  __IO uint32_t MACA2LR;\r
+  __IO uint32_t MACA3HR;\r
+  __IO uint32_t MACA3LR;               /*   24 */\r
+  uint32_t      RESERVED2[40];\r
+  __IO uint32_t MMCCR;                 /*   65 */\r
+  __IO uint32_t MMCRIR;\r
+  __IO uint32_t MMCTIR;\r
+  __IO uint32_t MMCRIMR;\r
+  __IO uint32_t MMCTIMR;               /*   69 */\r
+  uint32_t      RESERVED3[14];\r
+  __IO uint32_t MMCTGFSCCR;            /*   84 */\r
+  __IO uint32_t MMCTGFMSCCR;\r
+  uint32_t      RESERVED4[5];\r
+  __IO uint32_t MMCTGFCR;\r
+  uint32_t      RESERVED5[10];\r
+  __IO uint32_t MMCRFCECR;\r
+  __IO uint32_t MMCRFAECR;\r
+  uint32_t      RESERVED6[10];\r
+  __IO uint32_t MMCRGUFCR;\r
+  uint32_t      RESERVED7[334];\r
+  __IO uint32_t PTPTSCR;\r
+  __IO uint32_t PTPSSIR;\r
+  __IO uint32_t PTPTSHR;\r
+  __IO uint32_t PTPTSLR;\r
+  __IO uint32_t PTPTSHUR;\r
+  __IO uint32_t PTPTSLUR;\r
+  __IO uint32_t PTPTSAR;\r
+  __IO uint32_t PTPTTHR;\r
+  __IO uint32_t PTPTTLR;\r
+  __IO uint32_t RESERVED8;\r
+  __IO uint32_t PTPTSSR;\r
+  uint32_t      RESERVED9[565];\r
+  __IO uint32_t DMABMR;\r
+  __IO uint32_t DMATPDR;\r
+  __IO uint32_t DMARPDR;\r
+  __IO uint32_t DMARDLAR;\r
+  __IO uint32_t DMATDLAR;\r
+  __IO uint32_t DMASR;\r
+  __IO uint32_t DMAOMR;\r
+  __IO uint32_t DMAIER;\r
+  __IO uint32_t DMAMFBOCR;\r
+  __IO uint32_t DMARSWTR;\r
+  uint32_t      RESERVED10[8];\r
+  __IO uint32_t DMACHTDR;\r
+  __IO uint32_t DMACHRDR;\r
+  __IO uint32_t DMACHTBAR;\r
+  __IO uint32_t DMACHRBAR;\r
+} ETH_TypeDef;\r
+\r
+/** \r
+  * @brief External Interrupt/Event Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */\r
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */\r
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */\r
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */\r
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */\r
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */\r
+} EXTI_TypeDef;\r
+\r
+/** \r
+  * @brief FLASH Registers\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t ACR;      /*!< FLASH access control register,   Address offset: 0x00 */\r
+  __IO uint32_t KEYR;     /*!< FLASH key register,              Address offset: 0x04 */\r
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,       Address offset: 0x08 */\r
+  __IO uint32_t SR;       /*!< FLASH status register,           Address offset: 0x0C */\r
+  __IO uint32_t CR;       /*!< FLASH control register,          Address offset: 0x10 */\r
+  __IO uint32_t OPTCR;    /*!< FLASH option control register ,  Address offset: 0x14 */\r
+  __IO uint32_t OPTCR1;   /*!< FLASH option control register 1, Address offset: 0x18 */\r
+} FLASH_TypeDef;\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/** \r
+  * @brief Flexible Static Memory Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   \r
+} FSMC_Bank1_TypeDef; \r
+\r
+/** \r
+  * @brief Flexible Static Memory Controller Bank1E\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FSMC_Bank1E_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Static Memory Controller Bank2\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\r
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\r
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\r
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\r
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\r
+} FSMC_Bank2_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Static Memory Controller Bank3\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\r
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\r
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\r
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */\r
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\r
+} FSMC_Bank3_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Static Memory Controller Bank4\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\r
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\r
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\r
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\r
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\r
+} FSMC_Bank4_TypeDef; \r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+  * @brief Flexible Memory Controller\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   \r
+} FMC_Bank1_TypeDef; \r
+\r
+/** \r
+  * @brief Flexible Memory Controller Bank1E\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */\r
+} FMC_Bank1E_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Memory Controller Bank2\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */\r
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */\r
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */\r
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */\r
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */\r
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */\r
+} FMC_Bank2_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Memory Controller Bank3\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */\r
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */\r
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */\r
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */\r
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */\r
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */\r
+} FMC_Bank3_TypeDef;\r
+\r
+/** \r
+  * @brief Flexible Memory Controller Bank4\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */\r
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */\r
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */\r
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */\r
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */\r
+} FMC_Bank4_TypeDef; \r
+\r
+/** \r
+  * @brief Flexible Memory Controller Bank5_6\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */\r
+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */\r
+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */\r
+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */\r
+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */\r
+} FMC_Bank5_6_TypeDef; \r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief General Purpose I/O\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */\r
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */\r
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */\r
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */\r
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */\r
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */\r
+  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */\r
+  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */\r
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */\r
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */\r
+} GPIO_TypeDef;\r
+\r
+/** \r
+  * @brief System configuration controller\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */\r
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */\r
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */\r
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ \r
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */\r
+} SYSCFG_TypeDef;\r
+\r
+/** \r
+  * @brief Inter-integrated Circuit Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */\r
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */\r
+  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */\r
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */\r
+  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */\r
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */\r
+  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */\r
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */\r
+  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */\r
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */\r
+  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */\r
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */\r
+  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */\r
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */\r
+  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */\r
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */\r
+  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */\r
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */\r
+  __IO uint16_t FLTR;       /*!< I2C FLTR register,          Address offset: 0x24 */\r
+  uint16_t      RESERVED9;  /*!< Reserved, 0x26                                   */\r
+} I2C_TypeDef;\r
+\r
+/** \r
+  * @brief Independent WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */\r
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */\r
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */\r
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */\r
+} IWDG_TypeDef;\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+  * @brief LCD-TFT Display Controller\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04 */\r
+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */\r
+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */\r
+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */\r
+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */\r
+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */\r
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20 */\r
+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */\r
+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28 */\r
+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */\r
+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30 */\r
+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */\r
+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */\r
+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */\r
+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */\r
+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */\r
+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                       Address offset: 0x48 */\r
+} LTDC_TypeDef;  \r
+\r
+/** \r
+  * @brief LCD-TFT Display layer x Controller\r
+  */\r
+  \r
+typedef struct\r
+{  \r
+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */\r
+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */\r
+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */\r
+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */\r
+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */\r
+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */\r
+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */\r
+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */\r
+  uint32_t      RESERVED0[2];  /*!< Reserved */\r
+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */\r
+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */\r
+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */\r
+  uint32_t      RESERVED1[3];  /*!< Reserved */\r
+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */\r
+\r
+} LTDC_Layer_TypeDef;\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief Power Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */\r
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */\r
+} PWR_TypeDef;\r
+\r
+/** \r
+  * @brief Reset and Clock Control\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */\r
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */\r
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */\r
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */\r
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */\r
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */\r
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */\r
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */\r
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */\r
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */\r
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */\r
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */\r
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */\r
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */\r
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */\r
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */\r
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */\r
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */\r
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */\r
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */\r
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */\r
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */\r
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */\r
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */\r
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */\r
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */\r
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */\r
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */\r
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */\r
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */\r
+\r
+#if defined (STM32F427X)  \r
+  uint32_t      RESERVED7;     /*!< Reserved, 0x88                                                                    */\r
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\r
+#endif /* STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+  __IO uint32_t PLLSAICFGR;    /*!< RCC PLLSAI configuration register,                           Address offset: 0x88 */\r
+  __IO uint32_t DCKCFGR;       /*!< RCC Dedicated Clocks configuration register,                 Address offset: 0x8C */\r
+#endif /* STM32F429X */\r
+\r
+} RCC_TypeDef;\r
+\r
+/** \r
+  * @brief Real-Time Clock\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */\r
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */\r
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */\r
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */\r
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */\r
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */\r
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */\r
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */\r
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */\r
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */\r
+  __IO uint32_t SSR;     /*!< RTC sub second register,                                  Address offset: 0x28 */\r
+  __IO uint32_t SHIFTR;  /*!< RTC shift control register,                               Address offset: 0x2C */\r
+  __IO uint32_t TSTR;    /*!< RTC time stamp time register,                             Address offset: 0x30 */\r
+  __IO uint32_t TSDR;    /*!< RTC time stamp date register,                             Address offset: 0x34 */\r
+  __IO uint32_t TSSSR;   /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */\r
+  __IO uint32_t CALR;    /*!< RTC calibration register,                                 Address offset: 0x3C */\r
+  __IO uint32_t TAFCR;   /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */\r
+  __IO uint32_t ALRMASSR;/*!< RTC alarm A sub second register,                          Address offset: 0x44 */\r
+  __IO uint32_t ALRMBSSR;/*!< RTC alarm B sub second register,                          Address offset: 0x48 */\r
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */\r
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */\r
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */\r
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */\r
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */\r
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */\r
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */\r
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */\r
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */\r
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */\r
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */\r
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */\r
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */\r
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */\r
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */\r
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */\r
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */\r
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */\r
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */\r
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */\r
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */\r
+} RTC_TypeDef;\r
+\r
+#if defined (STM32F429X)\r
+/** \r
+  * @brief Serial Audio Interface\r
+  */\r
+  \r
+typedef struct\r
+{\r
+  __IO uint32_t GCR;      /*!< SAI global configuration register,        Address offset: 0x00 */\r
+} SAI_TypeDef;\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */\r
+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */\r
+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */\r
+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */\r
+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */\r
+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */\r
+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */\r
+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */\r
+} SAI_Block_TypeDef;\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief SD host Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */\r
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */\r
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */\r
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */\r
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */\r
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */\r
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */\r
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */\r
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */\r
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */\r
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */\r
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */\r
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */\r
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */\r
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */\r
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */\r
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */\r
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */\r
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */\r
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */\r
+} SDIO_TypeDef;\r
+\r
+/** \r
+  * @brief Serial Peripheral Interface\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */\r
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */\r
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */\r
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */\r
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */\r
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */\r
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */\r
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */\r
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */\r
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */\r
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */\r
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */\r
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */\r
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */\r
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */\r
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */\r
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */\r
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */\r
+} SPI_TypeDef;\r
+\r
+/** \r
+  * @brief TIM\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */\r
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */\r
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */\r
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */\r
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */\r
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */\r
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */\r
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */\r
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */\r
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */\r
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */\r
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */\r
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */\r
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */\r
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */\r
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */\r
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */\r
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */\r
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */\r
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */\r
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */\r
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */\r
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */\r
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */\r
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */\r
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */\r
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */\r
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */\r
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */\r
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */\r
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */\r
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */\r
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */\r
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */\r
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */\r
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */\r
+} TIM_TypeDef;\r
+\r
+/** \r
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter\r
+  */\r
+ \r
+typedef struct\r
+{\r
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */\r
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */\r
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */\r
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */\r
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */\r
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */\r
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */\r
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */\r
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */\r
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */\r
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */\r
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */\r
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */\r
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */\r
+} USART_TypeDef;\r
+\r
+/** \r
+  * @brief Window WATCHDOG\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */\r
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */\r
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */\r
+} WWDG_TypeDef;\r
+\r
+/** \r
+  * @brief Crypto Processor\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */\r
+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */\r
+  __IO uint32_t DR;         /*!< CRYP data input register,                                 Address offset: 0x08 */\r
+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */\r
+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */\r
+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */\r
+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */\r
+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */\r
+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */\r
+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */\r
+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */\r
+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */\r
+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */\r
+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */\r
+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */\r
+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */\r
+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */\r
+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */\r
+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */\r
+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */\r
+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */\r
+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */\r
+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */\r
+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */\r
+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */\r
+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */\r
+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */\r
+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */\r
+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */\r
+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */\r
+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */\r
+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */\r
+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */\r
+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */\r
+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */\r
+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */\r
+} CRYP_TypeDef;\r
+\r
+/** \r
+  * @brief HASH\r
+  */\r
+  \r
+typedef struct \r
+{\r
+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */\r
+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */\r
+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */\r
+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */\r
+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */\r
+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */\r
+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */\r
+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */\r
+} HASH_TypeDef;\r
+\r
+/** \r
+  * @brief HASH_DIGEST\r
+  */\r
+  \r
+typedef struct \r
+{\r
+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */ \r
+} HASH_DIGEST_TypeDef;\r
+\r
+/** \r
+  * @brief RNG\r
+  */\r
+  \r
+typedef struct \r
+{\r
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */\r
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */\r
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */\r
+} RNG_TypeDef;\r
+\r
+/** \r
+  * @brief USB OTG FS\r
+  */\r
+#pragma anon_unions\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t GOTGCTL;\r
+  __IO uint32_t GOTGINT;\r
+  __IO uint32_t GAHBCFG;\r
+  __IO uint32_t GUSBCFG;\r
+  __IO uint32_t GRSTCTL;\r
+  __IO uint32_t GINTSTS;\r
+  __IO uint32_t GINTMSK;\r
+  __IO uint32_t GRXSTSR;\r
+  __IO uint32_t GRXSTSP;\r
+  __IO uint32_t GRXFSIZ;\r
+  union {\r
+    __IO uint32_t HNPTXFSIZ;\r
+    __IO uint32_t DIEPTXF0;\r
+  };\r
+  __IO uint32_t HNPTXSTS;\r
+  __IO uint32_t GI2CCTL;\r
+       uint32_t RESERVED0;\r
+  __IO uint32_t GCCFG;\r
+  __IO uint32_t CID;\r
+       uint32_t RESERVED1[48];\r
+  __IO uint32_t HPTXFSIZ;\r
+  __IO uint32_t DIEPTXF1;\r
+  __IO uint32_t DIEPTXF2;\r
+  __IO uint32_t DIEPTXF3;\r
+  __IO uint32_t DIEPTXF4;\r
+  __IO uint32_t DIEPTXF5;\r
+  __IO uint32_t DIEPTXF6;\r
+  __IO uint32_t DIEPTXF7;\r
+  __IO uint32_t DIEPTXF8;\r
+  __IO uint32_t DIEPTXF9;\r
+  __IO uint32_t DIEPTXF10;\r
+  __IO uint32_t DIEPTXF11;\r
+  __IO uint32_t DIEPTXF12;\r
+  __IO uint32_t DIEPTXF13;\r
+  __IO uint32_t DIEPTXF14;\r
+  __IO uint32_t DIEPTXF15;\r
+       uint32_t RESERVED2[176];\r
+  __IO uint32_t HCFG;\r
+  __IO uint32_t HFIR;\r
+  __IO uint32_t HFNUM;\r
+       uint32_t RESERVED3;\r
+  __IO uint32_t HPTXSTS;\r
+  __IO uint32_t HAINT;\r
+  __IO uint32_t HAINTMSK;\r
+       uint32_t RESERVED4[9];\r
+  __IO uint32_t HPRT;\r
+       uint32_t RESERVED5[47];\r
+  __IO uint32_t HCCHAR0;\r
+       uint32_t RESERVED6;\r
+  __IO uint32_t HCINT0;\r
+  __IO uint32_t HCINTMSK0;\r
+  __IO uint32_t HCTSIZ0;\r
+       uint32_t RESERVED7[3];\r
+  __IO uint32_t HCCHAR1;\r
+       uint32_t RESERVED8;\r
+  __IO uint32_t HCINT1;\r
+  __IO uint32_t HCINTMSK1;\r
+  __IO uint32_t HCTSIZ1;\r
+       uint32_t RESERVED9[3];\r
+  __IO uint32_t HCCHAR2;\r
+       uint32_t RESERVED10;\r
+  __IO uint32_t HCINT2;\r
+  __IO uint32_t HCINTMSK2;\r
+  __IO uint32_t HCTSIZ2;\r
+       uint32_t RESERVED11[3];\r
+  __IO uint32_t HCCHR3;\r
+       uint32_t RESERVED12;\r
+  __IO uint32_t HCINT3;\r
+  __IO uint32_t HCINTMSK3;\r
+  __IO uint32_t HCTSIZ3;\r
+       uint32_t RESERVED13[3];\r
+  __IO uint32_t HCCHR4;\r
+       uint32_t RESERVED14;\r
+  __IO uint32_t HCINT4;\r
+  __IO uint32_t HCINTMSK4;\r
+  __IO uint32_t HCTSIZ4;\r
+       uint32_t RESERVED15[3];\r
+  __IO uint32_t HCCHR5;\r
+       uint32_t RESERVED16;\r
+  __IO uint32_t HCINT5;\r
+  __IO uint32_t HCINTMSK5;\r
+  __IO uint32_t HCTSIZ5;\r
+       uint32_t RESERVED17[3];\r
+  __IO uint32_t HCCHR6;\r
+       uint32_t RESERVED18;\r
+  __IO uint32_t HCINT6;\r
+  __IO uint32_t HCINTMSK6;\r
+  __IO uint32_t HCTSIZ6;\r
+       uint32_t RESERVED19[3];\r
+  __IO uint32_t HCCHR7;\r
+       uint32_t RESERVED20;\r
+  __IO uint32_t HCINT7;\r
+  __IO uint32_t HCINTMSK7;\r
+  __IO uint32_t HCTSIZ7;\r
+       uint32_t RESERVED21[3];\r
+  __IO uint32_t HCCHR8;\r
+       uint32_t RESERVED22;\r
+  __IO uint32_t HCINT8;\r
+  __IO uint32_t HCINTMSK8;\r
+  __IO uint32_t HCTSIZ8;\r
+       uint32_t RESERVED23[3];\r
+  __IO uint32_t HCCHR9;\r
+       uint32_t RESERVED24;\r
+  __IO uint32_t HCINT9;\r
+  __IO uint32_t HCINTMSK9;\r
+  __IO uint32_t HCTSIZ9;\r
+       uint32_t RESERVED25[3];\r
+  __IO uint32_t HCCHR10;\r
+       uint32_t RESERVED26;\r
+  __IO uint32_t HCINT10;\r
+  __IO uint32_t HCINTMSK10;\r
+  __IO uint32_t HCTSIZ10;\r
+       uint32_t RESERVED27[3];\r
+  __IO uint32_t HCCHR11;\r
+       uint32_t RESERVED28;\r
+  __IO uint32_t HCINT11;\r
+  __IO uint32_t HCINTMSK11;\r
+  __IO uint32_t HCTSIZ11;\r
+       uint32_t RESERVED29[3];\r
+  __IO uint32_t HCCHR12;\r
+       uint32_t RESERVED30;\r
+  __IO uint32_t HCINT12;\r
+  __IO uint32_t HCINTMSK12;\r
+  __IO uint32_t HCTSIZ12;\r
+       uint32_t RESERVED31[3];\r
+  __IO uint32_t HCCHR13;\r
+       uint32_t RESERVED32;\r
+  __IO uint32_t HCINT13;\r
+  __IO uint32_t HCINTMSK13;\r
+  __IO uint32_t HCTSIZ13;\r
+       uint32_t RESERVED33[3];\r
+  __IO uint32_t HCCHR14;\r
+       uint32_t RESERVED34;\r
+  __IO uint32_t HCINT14;\r
+  __IO uint32_t HCINTMSK14;\r
+  __IO uint32_t HCTSIZ14;\r
+       uint32_t RESERVED35[3];\r
+  __IO uint32_t HCCHR15;\r
+       uint32_t RESERVED36;\r
+  __IO uint32_t HCINT15;\r
+  __IO uint32_t HCINTMSK15;\r
+  __IO uint32_t HCTSIZ15;\r
+       uint32_t RESERVED37[3];\r
+       uint32_t RESERVED38[64];\r
+  __IO uint32_t DCFG;\r
+  __IO uint32_t DCTL;\r
+  __IO uint32_t DSTS;\r
+       uint32_t RESERVED39;\r
+  __IO uint32_t DIEPMSK;\r
+  __IO uint32_t DOEPMSK;\r
+  __IO uint32_t DAINT;\r
+  __IO uint32_t DAINTMSK;\r
+       uint32_t RESERVED40[2];\r
+  __IO uint32_t DVBUSDIS;\r
+  __IO uint32_t DVBUSPULSE;\r
+       uint32_t RESERVED41;\r
+  __IO uint32_t DIEPEMPMSK;\r
+       uint32_t RESERVED42[50];\r
+  __IO uint32_t DIEPCTL0;\r
+       uint32_t RESERVED43;\r
+  __IO uint32_t DIEPINT0;\r
+       uint32_t RESERVED44;\r
+  __IO uint32_t DIEPTSIZ0;\r
+       uint32_t RESERVED45;\r
+  __IO uint32_t DTXFSTS0;\r
+       uint32_t RESERVED46;\r
+  __IO uint32_t DIEPCTL1;\r
+       uint32_t RESERVED47;\r
+  __IO uint32_t DIEPINT1;\r
+       uint32_t RESERVED48;\r
+  __IO uint32_t DIEPTSIZ1;\r
+       uint32_t RESERVED49;\r
+  __IO uint32_t DTXFSTS1;\r
+       uint32_t RESERVED50;\r
+  __IO uint32_t DIEPCTL2;\r
+       uint32_t RESERVED51;\r
+  __IO uint32_t DIEPINT2;\r
+       uint32_t RESERVED52;\r
+  __IO uint32_t DIEPTSIZ2;\r
+       uint32_t RESERVED53;\r
+  __IO uint32_t DTXFSTS2;\r
+       uint32_t RESERVED54;\r
+  __IO uint32_t DIEPCTL3;\r
+       uint32_t RESERVED55;\r
+  __IO uint32_t DIEPINT3;\r
+       uint32_t RESERVED56;\r
+  __IO uint32_t DIEPTSIZ3;\r
+       uint32_t RESERVED57;\r
+  __IO uint32_t DTXFSTS3;\r
+       uint32_t RESERVED58;\r
+  __IO uint32_t DIEPCTL4;\r
+       uint32_t RESERVED59;\r
+  __IO uint32_t DIEPINT4;\r
+       uint32_t RESERVED60;\r
+  __IO uint32_t DIEPTSIZ4;\r
+       uint32_t RESERVED61;\r
+  __IO uint32_t DTXFSTS4;\r
+       uint32_t RESERVED62;\r
+  __IO uint32_t DIEPCTL5;\r
+       uint32_t RESERVED63;\r
+  __IO uint32_t DIEPINT5;\r
+       uint32_t RESERVED64;\r
+  __IO uint32_t DIEPTSIZ5;\r
+       uint32_t RESERVED65[3];\r
+  __IO uint32_t DIEPCTL6;\r
+       uint32_t RESERVED66;\r
+  __IO uint32_t DIEPINT6;\r
+       uint32_t RESERVED67;\r
+  __IO uint32_t DIEPTSIZ6;\r
+       uint32_t RESERVED68[3];\r
+  __IO uint32_t DIEPCTL7;\r
+       uint32_t RESERVED69;\r
+  __IO uint32_t DIEPINT7;\r
+       uint32_t RESERVED70;\r
+  __IO uint32_t DIEPTSIZ7;\r
+       uint32_t RESERVED71[3];\r
+  __IO uint32_t DIEPCTL8;\r
+       uint32_t RESERVED72;\r
+  __IO uint32_t DIEPINT8;\r
+       uint32_t RESERVED73;\r
+  __IO uint32_t DIEPTSIZ8;\r
+       uint32_t RESERVED74[3];\r
+  __IO uint32_t DIEPCTL9;\r
+       uint32_t RESERVED75;\r
+  __IO uint32_t DIEPINT9;\r
+       uint32_t RESERVED76;\r
+  __IO uint32_t DIEPTSIZ9;\r
+       uint32_t RESERVED77[3];\r
+  __IO uint32_t DIEPCTL10;\r
+       uint32_t RESERVED78;\r
+  __IO uint32_t DIEPINT10;\r
+       uint32_t RESERVED79;\r
+  __IO uint32_t DIEPTSIZ10;\r
+       uint32_t RESERVED80[3];\r
+  __IO uint32_t DIEPCTL11;\r
+       uint32_t RESERVED81;\r
+  __IO uint32_t DIEPINT11;\r
+       uint32_t RESERVED82;\r
+  __IO uint32_t DIEPTSIZ11;\r
+       uint32_t RESERVED83[3];\r
+  __IO uint32_t DIEPCTL12;\r
+       uint32_t RESERVED84;\r
+  __IO uint32_t DIEPINT12;\r
+       uint32_t RESERVED85;\r
+  __IO uint32_t DIEPTSIZ86;\r
+       uint32_t RESERVED86[3];\r
+  __IO uint32_t DIEPCTL13;\r
+       uint32_t RESERVED87;\r
+  __IO uint32_t DIEPINT13;\r
+       uint32_t RESERVED88;\r
+  __IO uint32_t DIEPTSIZ13;\r
+       uint32_t RESERVED89[3];\r
+  __IO uint32_t DIEPCTL14;\r
+       uint32_t RESERVED90;\r
+  __IO uint32_t DIEPINT14;\r
+       uint32_t RESERVED91;\r
+  __IO uint32_t DIEPTSIZ14;\r
+       uint32_t RESERVED92[3];\r
+  __IO uint32_t DIEPCTL15;\r
+       uint32_t RESERVED93;\r
+  __IO uint32_t DIEPINT15;\r
+       uint32_t RESERVED94;\r
+  __IO uint32_t DIEPTSIZ15;\r
+       uint32_t RESERVED95[3];\r
+  __IO uint32_t DOEPCTL0;\r
+       uint32_t RESERVED96;\r
+  __IO uint32_t DOEPINT0;\r
+       uint32_t RESERVED97;\r
+  __IO uint32_t DOEPTSIZ0;\r
+       uint32_t RESERVED98[3];\r
+  __IO uint32_t DOEPCTL1;\r
+       uint32_t RESERVED99;\r
+  __IO uint32_t DOEPINT1;\r
+       uint32_t RESERVED100;\r
+  __IO uint32_t DOEPTSIZ1;\r
+       uint32_t RESERVED101[3];\r
+  __IO uint32_t DOEPCTL2;\r
+       uint32_t RESERVED102;\r
+  __IO uint32_t DOEPINT2;\r
+       uint32_t RESERVED103;\r
+  __IO uint32_t DOEPTSIZ2;\r
+       uint32_t RESERVED104[3];\r
+  __IO uint32_t DOEPCTL3;\r
+       uint32_t RESERVED105;\r
+  __IO uint32_t DOEPINT3;\r
+       uint32_t RESERVED106;\r
+  __IO uint32_t DOEPTSIZ3;\r
+       uint32_t RESERVED107[3];\r
+  __IO uint32_t DOEPCTL4;\r
+       uint32_t RESERVED108;\r
+  __IO uint32_t DOEPINT4;\r
+       uint32_t RESERVED109;\r
+  __IO uint32_t DOEPTSIZ4;\r
+       uint32_t RESERVED110[3];\r
+  __IO uint32_t DOEPCTL5;\r
+       uint32_t RESERVED111;\r
+  __IO uint32_t DOEPINT5;\r
+       uint32_t RESERVED112;\r
+  __IO uint32_t DOEPTSIZ5;\r
+       uint32_t RESERVED113[3];\r
+  __IO uint32_t DOEPCTL6;\r
+       uint32_t RESERVED114;\r
+  __IO uint32_t DOEPINT6;\r
+       uint32_t RESERVED115;\r
+  __IO uint32_t DOEPTSIZ6;\r
+       uint32_t RESERVED116[3];\r
+  __IO uint32_t DOEPCTL7;\r
+       uint32_t RESERVED117;\r
+  __IO uint32_t DOEPINT7;\r
+       uint32_t RESERVED118;\r
+  __IO uint32_t DOEPTSIZ7;\r
+       uint32_t RESERVED119[3];\r
+  __IO uint32_t DOEPCTL8;\r
+       uint32_t RESERVED120;\r
+  __IO uint32_t DOEPINT8;\r
+       uint32_t RESERVED121;\r
+  __IO uint32_t DOEPTSIZ8;\r
+       uint32_t RESERVED122[3];\r
+  __IO uint32_t DOEPCTL9;\r
+       uint32_t RESERVED123;\r
+  __IO uint32_t DOEPINT9;\r
+       uint32_t RESERVED124;\r
+  __IO uint32_t DOEPTSIZ9;\r
+       uint32_t RESERVED125[3];\r
+  __IO uint32_t DOEPCTL10;\r
+       uint32_t RESERVED126;\r
+  __IO uint32_t DOEPINT10;\r
+       uint32_t RESERVED127;\r
+  __IO uint32_t DOEPTSIZ10;\r
+       uint32_t RESERVED128[3];\r
+  __IO uint32_t DOEPCTL11;\r
+       uint32_t RESERVED129;\r
+  __IO uint32_t DOEPINT11;\r
+       uint32_t RESERVED130;\r
+  __IO uint32_t DOEPTSIZ11;\r
+       uint32_t RESERVED131[3];\r
+  __IO uint32_t DOEPCTL12;\r
+       uint32_t RESERVED132;\r
+  __IO uint32_t DOEPINT12;\r
+       uint32_t RESERVED133;\r
+  __IO uint32_t DOEPTSIZ12;\r
+       uint32_t RESERVED134[3];\r
+  __IO uint32_t DOEPCTL13;\r
+       uint32_t RESERVED135;\r
+  __IO uint32_t DOEPINT13;\r
+       uint32_t RESERVED136;\r
+  __IO uint32_t DOEPTSIZ13;\r
+       uint32_t RESERVED137[3];\r
+  __IO uint32_t DOEPCTL14;\r
+       uint32_t RESERVED138;\r
+  __IO uint32_t DOEPINT14;\r
+       uint32_t RESERVED139;\r
+  __IO uint32_t DOEPTSIZ14;\r
+       uint32_t RESERVED140[3];\r
+  __IO uint32_t DOEPCTL15;\r
+       uint32_t RESERVED141;\r
+  __IO uint32_t DOEPINT15;\r
+       uint32_t RESERVED142;\r
+  __IO uint32_t DOEPTSIZ15;\r
+       uint32_t RESERVED143[3];\r
+       uint32_t RESERVED144[64];\r
+  __IO uint32_t PCGCCTL;\r
+} OTG_FS_TypeDef;\r
+\r
+/** \r
+  * @brief USB OTG HS\r
+  */\r
+\r
+typedef struct\r
+{\r
+  __IO uint32_t GOTGCTL;\r
+  __IO uint32_t GOTGINT;\r
+  __IO uint32_t GAHBCFG;\r
+  __IO uint32_t GUSBCFG;\r
+  __IO uint32_t GRSTCTL;\r
+  __IO uint32_t GINTSTS;\r
+  __IO uint32_t GINTMSK;\r
+  __IO uint32_t GRXSTSR;\r
+  __IO uint32_t GRXSTSP;\r
+  __IO uint32_t GRXFSIZ;\r
+  union {\r
+    __IO uint32_t GNPTXFSIZ;\r
+    __IO uint32_t TX0FSIZ;\r
+  };\r
+  __IO uint32_t GNPTXSTS;\r
+  __IO uint32_t GI2CCTL;\r
+       uint32_t RESERVED0;\r
+  __IO uint32_t GCCFG;\r
+  __IO uint32_t CID;\r
+       uint32_t RESERVED1[48];\r
+  __IO uint32_t HPTXFSIZ;\r
+  __IO uint32_t DIEPTXF1;\r
+  __IO uint32_t DIEPTXF2;\r
+  __IO uint32_t DIEPTXF3;\r
+  __IO uint32_t DIEPTXF4;\r
+  __IO uint32_t DIEPTXF5;\r
+  __IO uint32_t DIEPTXF6;\r
+  __IO uint32_t DIEPTXF7;\r
+  __IO uint32_t DIEPTXF8;\r
+  __IO uint32_t DIEPTXF9;\r
+  __IO uint32_t DIEPTXF10;\r
+  __IO uint32_t DIEPTXF11;\r
+  __IO uint32_t DIEPTXF12;\r
+  __IO uint32_t DIEPTXF13;\r
+  __IO uint32_t DIEPTXF14;\r
+  __IO uint32_t DIEPTXF15;\r
+       uint32_t RESERVED2[176];\r
+  __IO uint32_t HCFG;\r
+  __IO uint32_t HFIR;\r
+  __IO uint32_t HFNUM;\r
+       uint32_t RESERVED3;\r
+  __IO uint32_t HPTXSTS;\r
+  __IO uint32_t HAINT;\r
+  __IO uint32_t HAINTMSK;\r
+       uint32_t RESERVED4[9];\r
+  __IO uint32_t HPRT;\r
+       uint32_t RESERVED5[47];\r
+  __IO uint32_t HCCHAR0;\r
+  __IO uint32_t HCSPLT0;\r
+  __IO uint32_t HCINT0;\r
+  __IO uint32_t HCINTMSK0;\r
+  __IO uint32_t HCTSIZ0;\r
+  __IO uint32_t HCDMA0;\r
+       uint32_t RESERVED6[2];\r
+  __IO uint32_t HCCHAR1;\r
+  __IO uint32_t HCSPLT1;\r
+  __IO uint32_t HCINT1;\r
+  __IO uint32_t HCINTMSK1;\r
+  __IO uint32_t HCTSIZ1;\r
+  __IO uint32_t HCDMA1;\r
+       uint32_t RESERVED7[2];\r
+  __IO uint32_t HCCHAR2;\r
+  __IO uint32_t HCSPLT2;\r
+  __IO uint32_t HCINT2;\r
+  __IO uint32_t HCINTMSK2;\r
+  __IO uint32_t HCTSIZ2;\r
+  __IO uint32_t HCDMA2;\r
+       uint32_t RESERVED8[2];\r
+  __IO uint32_t HCCHAR3;\r
+  __IO uint32_t HCSPLT3;\r
+  __IO uint32_t HCINT3;\r
+  __IO uint32_t HCINTMSK3;\r
+  __IO uint32_t HCTSIZ3;\r
+  __IO uint32_t HCDMA3;\r
+       uint32_t RESERVED9[2];\r
+  __IO uint32_t HCCHAR4;\r
+  __IO uint32_t HCSPLT4;\r
+  __IO uint32_t HCINT4;\r
+  __IO uint32_t HCINTMSK4;\r
+  __IO uint32_t HCTSIZ4;\r
+  __IO uint32_t HCDMA4;\r
+       uint32_t RESERVED10[2];\r
+  __IO uint32_t HCCHAR5;\r
+  __IO uint32_t HCSPLT5;\r
+  __IO uint32_t HCINT5;\r
+  __IO uint32_t HCINTMSK5;\r
+  __IO uint32_t HCTSIZ5;\r
+  __IO uint32_t HCDMA5;\r
+       uint32_t RESERVED11[2];\r
+  __IO uint32_t HCCHAR6;\r
+  __IO uint32_t HCSPLT6;\r
+  __IO uint32_t HCINT6;\r
+  __IO uint32_t HCINTMSK6;\r
+  __IO uint32_t HCTSIZ6;\r
+  __IO uint32_t HCDMA6;\r
+       uint32_t RESERVED12[2];\r
+  __IO uint32_t HCCHAR7;\r
+  __IO uint32_t HCSPLT7;\r
+  __IO uint32_t HCINT7;\r
+  __IO uint32_t HCINTMSK7;\r
+  __IO uint32_t HCTSIZ7;\r
+  __IO uint32_t HCDMA7;\r
+       uint32_t RESERVED13[2];\r
+  __IO uint32_t HCCHAR8;\r
+  __IO uint32_t HCSPLT8;\r
+  __IO uint32_t HCINT8;\r
+  __IO uint32_t HCINTMSK8;\r
+  __IO uint32_t HCTSIZ8;\r
+  __IO uint32_t HCDMA8;\r
+       uint32_t RESERVED14[2];\r
+  __IO uint32_t HCCHAR9;\r
+  __IO uint32_t HCSPLT9;\r
+  __IO uint32_t HCINT9;\r
+  __IO uint32_t HCINTMSK9;\r
+  __IO uint32_t HCTSIZ9;\r
+  __IO uint32_t HCDMA9;\r
+       uint32_t RESERVED15[2];\r
+  __IO uint32_t HCCHAR10;\r
+  __IO uint32_t HCSPLT10;\r
+  __IO uint32_t HCINT10;\r
+  __IO uint32_t HCINTMSK10;\r
+  __IO uint32_t HCTSIZ10;\r
+  __IO uint32_t HCDMA10;\r
+       uint32_t RESERVED16[2];\r
+  __IO uint32_t HCCHAR11;\r
+  __IO uint32_t HCSPLT11;\r
+  __IO uint32_t HCINT11;\r
+  __IO uint32_t HCINTMSK11;\r
+  __IO uint32_t HCTSIZ11;\r
+  __IO uint32_t HCDMA11;\r
+       uint32_t RESERVED17[2];\r
+  __IO uint32_t HCCHAR12;\r
+  __IO uint32_t HCSPLT12;\r
+  __IO uint32_t HCINT12;\r
+  __IO uint32_t HCINTMSK12;\r
+  __IO uint32_t HCTSIZ12;\r
+  __IO uint32_t HCDMA12;\r
+       uint32_t RESERVED18[2];\r
+  __IO uint32_t HCCHAR13;\r
+  __IO uint32_t HCSPLT13;\r
+  __IO uint32_t HCINT13;\r
+  __IO uint32_t HCINTMSK13;\r
+  __IO uint32_t HCTSIZ13;\r
+  __IO uint32_t HCDMA13;\r
+       uint32_t RESERVED19[2];\r
+  __IO uint32_t HCCHAR14;\r
+  __IO uint32_t HCSPLT14;\r
+  __IO uint32_t HCINT14;\r
+  __IO uint32_t HCINTMSK14;\r
+  __IO uint32_t HCTSIZ14;\r
+  __IO uint32_t HCDMA14;\r
+       uint32_t RESERVED20[2];\r
+  __IO uint32_t HCCHAR15;\r
+  __IO uint32_t HCSPLT15;\r
+  __IO uint32_t HCINT15;\r
+  __IO uint32_t HCINTMSK15;\r
+  __IO uint32_t HCTSIZ15;\r
+  __IO uint32_t HCDMA15;\r
+       uint32_t RESERVED21[2];\r
+       uint32_t RESERVED22[64];\r
+  __IO uint32_t DCFG;\r
+  __IO uint32_t DCTL;\r
+  __IO uint32_t DSTS;\r
+       uint32_t RESERVED23;\r
+  __IO uint32_t DIEPMSK;\r
+  __IO uint32_t DOEPMSK;\r
+  __IO uint32_t DAINT;\r
+  __IO uint32_t DAINTMSK;\r
+       uint32_t RESERVED24[2];\r
+  __IO uint32_t DVBUSDIS;\r
+  __IO uint32_t DVBUSPULSE;\r
+       uint32_t RESERVED25;\r
+  __IO uint32_t DIEPEMPMSK;\r
+  __IO uint32_t EACHHINT;\r
+  __IO uint32_t EACHHINTMSK;\r
+  __IO uint32_t DIEPEACHMSK1;\r
+       uint32_t RESERVED26[15];\r
+  __IO uint32_t DOEPEACHMSK1;\r
+       uint32_t RESERVED27[31];\r
+  __IO uint32_t DIEPCTL0;\r
+       uint32_t RESERVED28;\r
+  __IO uint32_t DIEPINT0;\r
+       uint32_t RESERVED29;\r
+  __IO uint32_t DIEPTSIZ0;\r
+  __IO uint32_t DIEPDMA0;\r
+  __IO uint32_t DTXFSTS0;\r
+       uint32_t RESERVED30;\r
+  __IO uint32_t DIEPCTL1;\r
+       uint32_t RESERVED31;\r
+  __IO uint32_t DIEPINT1;\r
+       uint32_t RESERVED32;\r
+  __IO uint32_t DIEPTSIZ1;\r
+  __IO uint32_t DIEPDMA1;\r
+  __IO uint32_t DTXFSTS1;\r
+       uint32_t RESERVED33;\r
+  __IO uint32_t DIEPCTL2;\r
+       uint32_t RESERVED34;\r
+  __IO uint32_t DIEPINT2;\r
+       uint32_t RESERVED35;\r
+  __IO uint32_t DIEPTSIZ2;\r
+  __IO uint32_t DIEPDMA2;\r
+  __IO uint32_t DTXFSTS2;\r
+       uint32_t RESERVED36;\r
+  __IO uint32_t DIEPCTL3;\r
+       uint32_t RESERVED37;\r
+  __IO uint32_t DIEPINT3;\r
+       uint32_t RESERVED38;\r
+  __IO uint32_t DIEPTSIZ3;\r
+  __IO uint32_t DIEPDMA3;\r
+  __IO uint32_t DTXFSTS3;\r
+       uint32_t RESERVED39;\r
+  __IO uint32_t DIEPCTL4;\r
+       uint32_t RESERVED40;\r
+  __IO uint32_t DIEPINT4;\r
+       uint32_t RESERVED41;\r
+  __IO uint32_t DIEPTSIZ4;\r
+  __IO uint32_t DIEPDMA4;\r
+  __IO uint32_t DTXFSTS4;\r
+       uint32_t RESERVED42;\r
+  __IO uint32_t DIEPCTL5;\r
+       uint32_t RESERVED43;\r
+  __IO uint32_t DIEPINT5;\r
+       uint32_t RESERVED44;\r
+  __IO uint32_t DIEPTSIZ5;\r
+  __IO uint32_t DIEPDMA5;\r
+  __IO uint32_t DTXFSTS5;\r
+       uint32_t RESERVED45;\r
+  __IO uint32_t DIEPCTL6;\r
+       uint32_t RESERVED46;\r
+  __IO uint32_t DIEPINT6;\r
+       uint32_t RESERVED47;\r
+  __IO uint32_t DIEPTSIZ6;\r
+  __IO uint32_t DIEPDMA6;\r
+  __IO uint32_t DTXFSTS6;\r
+       uint32_t RESERVED48;\r
+  __IO uint32_t DIEPCTL7;\r
+       uint32_t RESERVED49;\r
+  __IO uint32_t DIEPINT7;\r
+       uint32_t RESERVED50;\r
+  __IO uint32_t DIEPTSIZ7;\r
+  __IO uint32_t DIEPDMA7;\r
+  __IO uint32_t DTXFSTS7;\r
+       uint32_t RESERVED51;\r
+  __IO uint32_t DIEPCTL8;\r
+       uint32_t RESERVED52;\r
+  __IO uint32_t DIEPINT8;\r
+       uint32_t RESERVED53;\r
+  __IO uint32_t DIEPTSIZ8;\r
+  __IO uint32_t DIEPDMA8;\r
+  __IO uint32_t DTXFSTS8;\r
+       uint32_t RESERVED54;\r
+  __IO uint32_t DIEPCTL9;\r
+       uint32_t RESERVED55;\r
+  __IO uint32_t DIEPINT9;\r
+       uint32_t RESERVED56;\r
+  __IO uint32_t DIEPTSIZ9;\r
+  __IO uint32_t DIEPDMA9;\r
+  __IO uint32_t DTXFSTS9;\r
+       uint32_t RESERVED57;\r
+  __IO uint32_t DIEPCTL10;\r
+       uint32_t RESERVED58;\r
+  __IO uint32_t DIEPINT10;\r
+       uint32_t RESERVED59;\r
+  __IO uint32_t DIEPTSIZ10;\r
+  __IO uint32_t DIEPDMA10;\r
+  __IO uint32_t DTXFSTS10;\r
+       uint32_t RESERVED60;\r
+  __IO uint32_t DIEPCTL11;\r
+       uint32_t RESERVED61;\r
+  __IO uint32_t DIEPINT11;\r
+       uint32_t RESERVED62;\r
+  __IO uint32_t DIEPTSIZ11;\r
+  __IO uint32_t DIEPDMA11;\r
+  __IO uint32_t DTXFSTS11;\r
+       uint32_t RESERVED63;\r
+  __IO uint32_t DIEPCTL12;\r
+       uint32_t RESERVED64;\r
+  __IO uint32_t DIEPINT12;\r
+       uint32_t RESERVED65;\r
+  __IO uint32_t DIEPTSIZ12;\r
+  __IO uint32_t DIEPDMA12;\r
+  __IO uint32_t DTXFSTS12;\r
+       uint32_t RESERVED66;\r
+  __IO uint32_t DIEPCTL13;\r
+       uint32_t RESERVED67;\r
+  __IO uint32_t DIEPINT13;\r
+       uint32_t RESERVED68;\r
+  __IO uint32_t DIEPTSIZ13;\r
+  __IO uint32_t DIEPDMA13;\r
+  __IO uint32_t DTXFSTS13;\r
+       uint32_t RESERVED69;\r
+  __IO uint32_t DIEPCTL14;\r
+       uint32_t RESERVED70;\r
+  __IO uint32_t DIEPINT14;\r
+       uint32_t RESERVED71;\r
+  __IO uint32_t DIEPTSIZ14;\r
+  __IO uint32_t DIEPDMA14;\r
+  __IO uint32_t DTXFSTS14;\r
+       uint32_t RESERVED72;\r
+  __IO uint32_t DIEPCTL15;\r
+       uint32_t RESERVED73;\r
+  __IO uint32_t DIEPINT15;\r
+       uint32_t RESERVED74;\r
+  __IO uint32_t DIEPTSIZ15;\r
+  __IO uint32_t DIEPDMA15;\r
+  __IO uint32_t DTXFSTS15;\r
+       uint32_t RESERVED75;\r
+  __IO uint32_t DOEPCTL0;\r
+       uint32_t RESERVED76;\r
+  __IO uint32_t DOEPINT0;\r
+       uint32_t RESERVED77;\r
+  __IO uint32_t DOEPTSIZ0;\r
+  __IO uint32_t DOEPDMAB0;\r
+       uint32_t RESERVED78[2];\r
+  __IO uint32_t DOEPCTL1;\r
+       uint32_t RESERVED79;\r
+  __IO uint32_t DOEPINT1;\r
+       uint32_t RESERVED80;\r
+  __IO uint32_t DOEPTSIZ1;\r
+  __IO uint32_t DOEPDMAB1;\r
+       uint32_t RESERVED81[2];\r
+  __IO uint32_t DOEPCTL2;\r
+       uint32_t RESERVED82;\r
+  __IO uint32_t DOEPINT2;\r
+       uint32_t RESERVED83;\r
+  __IO uint32_t DOEPTSIZ2;\r
+  __IO uint32_t DOEPDMAB2;\r
+       uint32_t RESERVED84[2];\r
+  __IO uint32_t DOEPCTL3;\r
+       uint32_t RESERVED85;\r
+  __IO uint32_t DOEPINT3;\r
+       uint32_t RESERVED86;\r
+  __IO uint32_t DOEPTSIZ3;\r
+  __IO uint32_t DOEPDMAB3;\r
+       uint32_t RESERVED87[2];\r
+  __IO uint32_t DOEPCTL4;\r
+       uint32_t RESERVED88;\r
+  __IO uint32_t DOEPINT4;\r
+       uint32_t RESERVED89;\r
+  __IO uint32_t DOEPTSIZ4;\r
+  __IO uint32_t DOEPDMAB4;\r
+       uint32_t RESERVED90[2];\r
+  __IO uint32_t DOEPCTL5;\r
+       uint32_t RESERVED91;\r
+  __IO uint32_t DOEPINT5;\r
+       uint32_t RESERVED92;\r
+  __IO uint32_t DOEPTSIZ5;\r
+  __IO uint32_t DOEPDMAB5;\r
+       uint32_t RESERVED93[2];\r
+  __IO uint32_t DOEPCTL6;\r
+       uint32_t RESERVED94;\r
+  __IO uint32_t DOEPINT6;\r
+       uint32_t RESERVED95;\r
+  __IO uint32_t DOEPTSIZ6;\r
+  __IO uint32_t DOEPDMAB6;\r
+       uint32_t RESERVED96[2];\r
+  __IO uint32_t DOEPCTL7;\r
+       uint32_t RESERVED97;\r
+  __IO uint32_t DOEPINT7;\r
+       uint32_t RESERVED98;\r
+  __IO uint32_t DOEPTSIZ7;\r
+  __IO uint32_t DOEPDMAB7;\r
+       uint32_t RESERVED99[2];\r
+  __IO uint32_t DOEPCTL8;\r
+       uint32_t RESERVED100;\r
+  __IO uint32_t DOEPINT8;\r
+       uint32_t RESERVED101;\r
+  __IO uint32_t DOEPTSIZ8;\r
+  __IO uint32_t DOEPDMAB8;\r
+       uint32_t RESERVED102[2];\r
+  __IO uint32_t DOEPCTL9;\r
+       uint32_t RESERVED103;\r
+  __IO uint32_t DOEPINT9;\r
+       uint32_t RESERVED104;\r
+  __IO uint32_t DOEPTSIZ9;\r
+  __IO uint32_t DOEPDMAB9;\r
+       uint32_t RESERVED105[2];\r
+  __IO uint32_t DOEPCTL10;\r
+       uint32_t RESERVED106;\r
+  __IO uint32_t DOEPINT10;\r
+       uint32_t RESERVED107;\r
+  __IO uint32_t DOEPTSIZ10;\r
+  __IO uint32_t DOEPDMAB10;\r
+       uint32_t RESERVED108[2];\r
+  __IO uint32_t DOEPCTL11;\r
+       uint32_t RESERVED109;\r
+  __IO uint32_t DOEPINT11;\r
+       uint32_t RESERVED110;\r
+  __IO uint32_t DOEPTSIZ11;\r
+  __IO uint32_t DOEPDMAB11;\r
+       uint32_t RESERVED111[2];\r
+  __IO uint32_t DOEPCTL12;\r
+       uint32_t RESERVED112;\r
+  __IO uint32_t DOEPINT12;\r
+       uint32_t RESERVED113;\r
+  __IO uint32_t DOEPTSIZ12;\r
+  __IO uint32_t DOEPDMAB12;\r
+       uint32_t RESERVED114[2];\r
+  __IO uint32_t DOEPCTL13;\r
+       uint32_t RESERVED115;\r
+  __IO uint32_t DOEPINT13;\r
+       uint32_t RESERVED116;\r
+  __IO uint32_t DOEPTSIZ13;\r
+  __IO uint32_t DOEPDMAB13;\r
+       uint32_t RESERVED117[2];\r
+  __IO uint32_t DOEPCTL14;\r
+       uint32_t RESERVED118;\r
+  __IO uint32_t DOEPINT14;\r
+       uint32_t RESERVED119;\r
+  __IO uint32_t DOEPTSIZ14;\r
+  __IO uint32_t DOEPDMAB14;\r
+       uint32_t RESERVED120[2];\r
+  __IO uint32_t DOEPCTL15;\r
+       uint32_t RESERVED121;\r
+  __IO uint32_t DOEPINT15;\r
+       uint32_t RESERVED122;\r
+  __IO uint32_t DOEPTSIZ15;\r
+  __IO uint32_t DOEPDMAB15;\r
+       uint32_t RESERVED123[2];\r
+       uint32_t RESERVED143[64];\r
+  __IO uint32_t PCGCCTL;\r
+} OTG_HS_TypeDef;\r
+#pragma no_anon_unions\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @addtogroup Peripheral_memory_map\r
+  * @{\r
+  */\r
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH(up to 1 MB) base address in the alias region                         */\r
+#define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */\r
+#define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */\r
+#define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */\r
+#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */\r
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */\r
+#define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address                                                */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define FMC_R_BASE            ((uint32_t)0xA0000000) /*!< FMC registers base address                                                 */\r
+#endif /* STM32F429X */\r
+\r
+#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */\r
+#define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */\r
+#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */\r
+#define SRAM3_BB_BASE         ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region                              */\r
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */\r
+#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */\r
+\r
+/* Legacy defines */\r
+#define SRAM_BASE             SRAM1_BASE\r
+#define SRAM_BB_BASE          SRAM1_BB_BASE\r
+\r
+\r
+/*!< Peripheral memory map */\r
+#define APB1PERIPH_BASE       PERIPH_BASE\r
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)\r
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)\r
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)\r
+\r
+/*!< APB1 peripherals */\r
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)\r
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)\r
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)\r
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)\r
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)\r
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)\r
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)\r
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)\r
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)\r
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)\r
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)\r
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)\r
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)\r
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)\r
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)\r
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)\r
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)\r
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)\r
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)\r
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)\r
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)\r
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)\r
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)\r
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)\r
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)\r
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)\r
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)\r
+#define UART7_BASE            (APB1PERIPH_BASE + 0x7800)\r
+#define UART8_BASE            (APB1PERIPH_BASE + 0x7C00)\r
+\r
+/*!< APB2 peripherals */\r
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)\r
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)\r
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)\r
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)\r
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)\r
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)\r
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)\r
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)\r
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)\r
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)\r
+#define SPI4_BASE             (APB2PERIPH_BASE + 0x3400)\r
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)\r
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)\r
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)\r
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)\r
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)\r
+#define SPI5_BASE             (APB2PERIPH_BASE + 0x5000)\r
+#define SPI6_BASE             (APB2PERIPH_BASE + 0x5400)\r
+\r
+#if defined (STM32F429X)\r
+#define SAI1_BASE             (APB2PERIPH_BASE + 0x5800)\r
+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004)\r
+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024)\r
+#define LTDC_BASE             (APB2PERIPH_BASE + 0x6800)\r
+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84)\r
+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104) \r
+#endif /* STM32F429X */\r
+\r
+/*!< AHB1 peripherals */\r
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)\r
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)\r
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)\r
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)\r
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)\r
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)\r
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)\r
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)\r
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)\r
+\r
+#if defined (STM32F429X)\r
+#define GPIOJ_BASE            (AHB1PERIPH_BASE + 0x2400)\r
+#define GPIOK_BASE            (AHB1PERIPH_BASE + 0x2800)\r
+#endif /* STM32F429X */\r
+\r
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)\r
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)\r
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00)\r
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)\r
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)\r
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)\r
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)\r
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)\r
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)\r
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)\r
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)\r
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)\r
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)\r
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)\r
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)\r
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)\r
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)\r
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)\r
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)\r
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)\r
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)\r
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)\r
+#define ETH_MAC_BASE          (ETH_BASE)\r
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)\r
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)\r
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)\r
+#define OTG_HS_BASE           (AHB1PERIPH_BASE + 0x20000)\r
+#define OTG_HS_DFIFO0_BASE    (OTG_HS_BASE + 0x01000)\r
+#define OTG_HS_DFIFO1_BASE    (OTG_HS_BASE + 0x02000)\r
+#define OTG_HS_DFIFO2_BASE    (OTG_HS_BASE + 0x03000)\r
+#define OTG_HS_DFIFO3_BASE    (OTG_HS_BASE + 0x04000)\r
+#define OTG_HS_DFIFO4_BASE    (OTG_HS_BASE + 0x05000)\r
+#define OTG_HS_DFIFO5_BASE    (OTG_HS_BASE + 0x06000)\r
+#define OTG_HS_DFIFO6_BASE    (OTG_HS_BASE + 0x07000)\r
+#define OTG_HS_DFIFO7_BASE    (OTG_HS_BASE + 0x08000)\r
+#define OTG_HS_DFIFO8_BASE    (OTG_HS_BASE + 0x09000)\r
+#define OTG_HS_DFIFO9_BASE    (OTG_HS_BASE + 0x0A000)\r
+#define OTG_HS_DFIFO10_BASE   (OTG_HS_BASE + 0x0B000)\r
+#define OTG_HS_DFIFO11_BASE   (OTG_HS_BASE + 0x0C000)\r
+#define OTG_HS_DFIFO12_BASE   (OTG_HS_BASE + 0x0D000)\r
+#define OTG_HS_DFIFO13_BASE   (OTG_HS_BASE + 0x0E000)\r
+#define OTG_HS_DFIFO14_BASE   (OTG_HS_BASE + 0x0F000)\r
+#define OTG_HS_DFIFO15_BASE   (OTG_HS_BASE + 0x10000)\r
+\r
+#if defined (STM32F429X)\r
+#define DMA2D_BASE            (AHB1PERIPH_BASE + 0xB000)\r
+#endif /* STM32F429X */\r
+\r
+/*!< AHB2 peripherals */\r
+#define OTG_FS_BASE           (AHB2PERIPH_BASE + 0x00000)\r
+#define OTG_FS_DFIFO0_BASE    (OTG_FS_BASE + 0x01000)\r
+#define OTG_FS_DFIFO1_BASE    (OTG_FS_BASE + 0x02000)\r
+#define OTG_FS_DFIFO2_BASE    (OTG_FS_BASE + 0x03000)\r
+#define OTG_FS_DFIFO3_BASE    (OTG_FS_BASE + 0x04000)\r
+#define OTG_FS_DFIFO4_BASE    (OTG_FS_BASE + 0x05000)\r
+#define OTG_FS_DFIFO5_BASE    (OTG_FS_BASE + 0x06000)\r
+#define OTG_FS_DFIFO6_BASE    (OTG_FS_BASE + 0x07000)\r
+#define OTG_FS_DFIFO7_BASE    (OTG_FS_BASE + 0x08000)\r
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)\r
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)\r
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)\r
+#define HASH_DIGEST_BASE      (AHB2PERIPH_BASE + 0x60710)\r
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/*!< FSMC Bankx registers base address */\r
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)\r
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)\r
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)\r
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)\r
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/*!< FMC Bankx registers base address */\r
+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000)\r
+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104)\r
+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060)\r
+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080)\r
+#define FMC_Bank4_R_BASE      (FMC_R_BASE + 0x00A0)\r
+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140)\r
+#endif /* STM32F429X */\r
+\r
+/* Debug MCU registers base address */\r
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)\r
+\r
+/**\r
+  * @}\r
+  */\r
+  \r
+/** @addtogroup Peripheral_declaration\r
+  * @{\r
+  */  \r
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)\r
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)\r
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)\r
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)\r
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)\r
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)\r
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)\r
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)\r
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)\r
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)\r
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)\r
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)\r
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)\r
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)\r
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)\r
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)\r
+#define USART2              ((USART_TypeDef *) USART2_BASE)\r
+#define USART3              ((USART_TypeDef *) USART3_BASE)\r
+#define UART4               ((USART_TypeDef *) UART4_BASE)\r
+#define UART5               ((USART_TypeDef *) UART5_BASE)\r
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)\r
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)\r
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)\r
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)\r
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)\r
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)\r
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)\r
+#define UART7               ((USART_TypeDef *) UART7_BASE)\r
+#define UART8               ((USART_TypeDef *) UART8_BASE)\r
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)\r
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)\r
+#define USART1              ((USART_TypeDef *) USART1_BASE)\r
+#define USART6              ((USART_TypeDef *) USART6_BASE)\r
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)\r
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)\r
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)\r
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)\r
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)\r
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE) \r
+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)\r
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)\r
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)\r
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)\r
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)\r
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)\r
+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)\r
+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)\r
+\r
+#if defined (STM32F429X)\r
+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)\r
+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)\r
+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)\r
+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)\r
+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)\r
+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)\r
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)\r
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)\r
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)\r
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)\r
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)\r
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)\r
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)\r
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)\r
+\r
+#if defined (STM32F429X)\r
+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)\r
+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)\r
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)\r
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)\r
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)\r
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)\r
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)\r
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)\r
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)\r
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)\r
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)\r
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)\r
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)\r
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)\r
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)\r
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)\r
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)\r
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)\r
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)\r
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)\r
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)\r
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)\r
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  \r
+#define OTG_HS              ((OTG_HS_TypeDef *) OTG_HS_BASE)  \r
+#define OTG_HS_DFIFO0       (((uint32_t *) OTG_HS_DFIFO0_BASE)  )\r
+#define OTG_HS_DFIFO1       (((uint32_t *) OTG_HS_DFIFO1_BASE)  )\r
+#define OTG_HS_DFIFO2       (((uint32_t *) OTG_HS_DFIFO2_BASE)  )\r
+#define OTG_HS_DFIFO3       (((uint32_t *) OTG_HS_DFIFO3_BASE)  )\r
+#define OTG_HS_DFIFO4       (((uint32_t *) OTG_HS_DFIFO4_BASE)  )\r
+#define OTG_HS_DFIFO5       (((uint32_t *) OTG_HS_DFIFO5_BASE)  )\r
+#define OTG_HS_DFIFO6       (((uint32_t *) OTG_HS_DFIFO6_BASE)  )\r
+#define OTG_HS_DFIFO7       (((uint32_t *) OTG_HS_DFIFO7_BASE)  )\r
+#define OTG_HS_DFIFO8       (((uint32_t *) OTG_HS_DFIFO8_BASE)  )\r
+#define OTG_HS_DFIFO9       (((uint32_t *) OTG_HS_DFIFO9_BASE)  )\r
+#define OTG_HS_DFIFO10      (((uint32_t *) OTG_HS_DFIFO10_BASE) )\r
+#define OTG_HS_DFIFO11      (((uint32_t *) OTG_HS_DFIFO11_BASE) )\r
+#define OTG_HS_DFIFO12      (((uint32_t *) OTG_HS_DFIFO12_BASE) )\r
+#define OTG_HS_DFIFO13      (((uint32_t *) OTG_HS_DFIFO13_BASE) )\r
+#define OTG_HS_DFIFO14      (((uint32_t *) OTG_HS_DFIFO14_BASE) )\r
+#define OTG_HS_DFIFO15      (((uint32_t *) OTG_HS_DFIFO15_BASE) )\r
+#define OTG_FS              ((OTG_FS_TypeDef *) OTG_FS_BASE)  \r
+#define OTG_FS_DFIFO0       (((uint32_t *) OTG_FS_DFIFO0_BASE)  )\r
+#define OTG_FS_DFIFO1       (((uint32_t *) OTG_FS_DFIFO1_BASE)  )\r
+#define OTG_FS_DFIFO2       (((uint32_t *) OTG_FS_DFIFO2_BASE)  )\r
+#define OTG_FS_DFIFO3       (((uint32_t *) OTG_FS_DFIFO3_BASE)  )\r
+#define OTG_FS_DFIFO4       (((uint32_t *) OTG_FS_DFIFO4_BASE)  )\r
+#define OTG_FS_DFIFO5       (((uint32_t *) OTG_FS_DFIFO5_BASE)  )\r
+#define OTG_FS_DFIFO6       (((uint32_t *) OTG_FS_DFIFO6_BASE)  )\r
+#define OTG_FS_DFIFO7       (((uint32_t *) OTG_FS_DFIFO7_BASE)  )\r
+\r
+#if defined (STM32F429X)\r
+#define DMA2D               ((DMA2D_TypeDef *)DMA2D_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)\r
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)\r
+#define HASH                ((HASH_TypeDef *) HASH_BASE)\r
+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)\r
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)\r
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)\r
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)\r
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)\r
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define FMC_Bank1           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)\r
+#define FMC_Bank1E          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)\r
+#define FMC_Bank2           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)\r
+#define FMC_Bank3           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)\r
+#define FMC_Bank4           ((FMC_Bank4_TypeDef *) FMC_Bank4_R_BASE)\r
+#define FMC_Bank5_6         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)\r
+#endif /* STM32F429X */\r
+\r
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+/** @addtogroup Exported_constants\r
+  * @{\r
+  */\r
+  \r
+  /** @addtogroup Peripheral_Registers_Bits_Definition\r
+  * @{\r
+  */\r
+    \r
+/******************************************************************************/\r
+/*                         Peripheral Registers_Bits_Definition               */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Analog to Digital Converter                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for ADC_SR register  ********************/\r
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!<Analog watchdog flag */\r
+#define  ADC_SR_EOC                          ((uint8_t)0x02)               /*!<End of conversion */\r
+#define  ADC_SR_JEOC                         ((uint8_t)0x04)               /*!<Injected channel end of conversion */\r
+#define  ADC_SR_JSTRT                        ((uint8_t)0x08)               /*!<Injected channel Start flag */\r
+#define  ADC_SR_STRT                         ((uint8_t)0x10)               /*!<Regular channel Start flag */\r
+#define  ADC_SR_OVR                          ((uint8_t)0x20)               /*!<Overrun flag */\r
+\r
+/*******************  Bit definition for ADC_CR1 register  ********************/\r
+#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */\r
+#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!<Interrupt enable for EOC */\r
+#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!<AAnalog Watchdog interrupt enable */\r
+#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!<Interrupt enable for injected channels */\r
+#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!<Scan mode */\r
+#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!<Enable the watchdog on a single channel in scan mode */\r
+#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!<Automatic injected group conversion */\r
+#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!<Discontinuous mode on regular channels */\r
+#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!<Discontinuous mode on injected channels */\r
+#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */\r
+#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!<Analog watchdog enable on injected channels */\r
+#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!<Analog watchdog enable on regular channels */\r
+#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!<RES[2:0] bits (Resolution) */\r
+#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)         /*!<overrun interrupt enable */\r
+  \r
+/*******************  Bit definition for ADC_CR2 register  ********************/\r
+#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!<A/D Converter ON / OFF */\r
+#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!<Continuous Conversion */\r
+#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!<Direct Memory access mode */\r
+#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!<DMA disable selection (Single ADC) */\r
+#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!<End of conversion selection */\r
+#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!<Data Alignment */\r
+#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!<JEXTSEL[3:0] bits (External event select for injected group) */\r
+#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */\r
+#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!<Start Conversion of injected channels */\r
+#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!<EXTSEL[3:0] bits (External Event Select for regular group) */\r
+#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */\r
+#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!<Start Conversion of regular channels */\r
+\r
+/******************  Bit definition for ADC_SMPR1 register  *******************/\r
+#define  ADC_SMPR1_SMP10                     ((uint32_t)0x00000007)        /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */\r
+#define  ADC_SMPR1_SMP10_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP10_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP10_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP11                     ((uint32_t)0x00000038)        /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */\r
+#define  ADC_SMPR1_SMP11_0                   ((uint32_t)0x00000008)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP11_1                   ((uint32_t)0x00000010)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP11_2                   ((uint32_t)0x00000020)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP12                     ((uint32_t)0x000001C0)        /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */\r
+#define  ADC_SMPR1_SMP12_0                   ((uint32_t)0x00000040)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP12_1                   ((uint32_t)0x00000080)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP12_2                   ((uint32_t)0x00000100)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP13                     ((uint32_t)0x00000E00)        /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */\r
+#define  ADC_SMPR1_SMP13_0                   ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP13_1                   ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP13_2                   ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP14                     ((uint32_t)0x00007000)        /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */\r
+#define  ADC_SMPR1_SMP14_0                   ((uint32_t)0x00001000)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP14_1                   ((uint32_t)0x00002000)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP14_2                   ((uint32_t)0x00004000)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP15                     ((uint32_t)0x00038000)        /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */\r
+#define  ADC_SMPR1_SMP15_0                   ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP15_1                   ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP15_2                   ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP16                     ((uint32_t)0x001C0000)        /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */\r
+#define  ADC_SMPR1_SMP16_0                   ((uint32_t)0x00040000)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP16_1                   ((uint32_t)0x00080000)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP16_2                   ((uint32_t)0x00100000)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP17                     ((uint32_t)0x00E00000)        /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */\r
+#define  ADC_SMPR1_SMP17_0                   ((uint32_t)0x00200000)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP17_1                   ((uint32_t)0x00400000)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP17_2                   ((uint32_t)0x00800000)        /*!<Bit 2 */\r
+#define  ADC_SMPR1_SMP18                     ((uint32_t)0x07000000)        /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */\r
+#define  ADC_SMPR1_SMP18_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  ADC_SMPR1_SMP18_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  ADC_SMPR1_SMP18_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for ADC_SMPR2 register  *******************/\r
+#define  ADC_SMPR2_SMP0                      ((uint32_t)0x00000007)        /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */\r
+#define  ADC_SMPR2_SMP0_0                    ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP0_1                    ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP0_2                    ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP1                      ((uint32_t)0x00000038)        /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */\r
+#define  ADC_SMPR2_SMP1_0                    ((uint32_t)0x00000008)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP1_1                    ((uint32_t)0x00000010)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP1_2                    ((uint32_t)0x00000020)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP2                      ((uint32_t)0x000001C0)        /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */\r
+#define  ADC_SMPR2_SMP2_0                    ((uint32_t)0x00000040)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP2_1                    ((uint32_t)0x00000080)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP2_2                    ((uint32_t)0x00000100)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP3                      ((uint32_t)0x00000E00)        /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */\r
+#define  ADC_SMPR2_SMP3_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP3_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP3_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP4                      ((uint32_t)0x00007000)        /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */\r
+#define  ADC_SMPR2_SMP4_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP4_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP4_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP5                      ((uint32_t)0x00038000)        /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */\r
+#define  ADC_SMPR2_SMP5_0                    ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP5_1                    ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP5_2                    ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP6                      ((uint32_t)0x001C0000)        /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */\r
+#define  ADC_SMPR2_SMP6_0                    ((uint32_t)0x00040000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP6_1                    ((uint32_t)0x00080000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP6_2                    ((uint32_t)0x00100000)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP7                      ((uint32_t)0x00E00000)        /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */\r
+#define  ADC_SMPR2_SMP7_0                    ((uint32_t)0x00200000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP7_1                    ((uint32_t)0x00400000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP7_2                    ((uint32_t)0x00800000)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP8                      ((uint32_t)0x07000000)        /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */\r
+#define  ADC_SMPR2_SMP8_0                    ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP8_1                    ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP8_2                    ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  ADC_SMPR2_SMP9                      ((uint32_t)0x38000000)        /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */\r
+#define  ADC_SMPR2_SMP9_0                    ((uint32_t)0x08000000)        /*!<Bit 0 */\r
+#define  ADC_SMPR2_SMP9_1                    ((uint32_t)0x10000000)        /*!<Bit 1 */\r
+#define  ADC_SMPR2_SMP9_2                    ((uint32_t)0x20000000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for ADC_JOFR1 register  *******************/\r
+#define  ADC_JOFR1_JOFFSET1                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 1 */\r
+\r
+/******************  Bit definition for ADC_JOFR2 register  *******************/\r
+#define  ADC_JOFR2_JOFFSET2                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 2 */\r
+\r
+/******************  Bit definition for ADC_JOFR3 register  *******************/\r
+#define  ADC_JOFR3_JOFFSET3                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 3 */\r
+\r
+/******************  Bit definition for ADC_JOFR4 register  *******************/\r
+#define  ADC_JOFR4_JOFFSET4                  ((uint16_t)0x0FFF)            /*!<Data offset for injected channel 4 */\r
+\r
+/*******************  Bit definition for ADC_HTR register  ********************/\r
+#define  ADC_HTR_HT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog high threshold */\r
+\r
+/*******************  Bit definition for ADC_LTR register  ********************/\r
+#define  ADC_LTR_LT                          ((uint16_t)0x0FFF)            /*!<Analog watchdog low threshold */\r
+\r
+/*******************  Bit definition for ADC_SQR1 register  *******************/\r
+#define  ADC_SQR1_SQ13                       ((uint32_t)0x0000001F)        /*!<SQ13[4:0] bits (13th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ13_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_SQR1_SQ13_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_SQR1_SQ13_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_SQR1_SQ13_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_SQR1_SQ13_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_SQR1_SQ14                       ((uint32_t)0x000003E0)        /*!<SQ14[4:0] bits (14th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ14_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  ADC_SQR1_SQ14_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  ADC_SQR1_SQ14_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+#define  ADC_SQR1_SQ14_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */\r
+#define  ADC_SQR1_SQ14_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */\r
+#define  ADC_SQR1_SQ15                       ((uint32_t)0x00007C00)        /*!<SQ15[4:0] bits (15th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ15_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  ADC_SQR1_SQ15_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+#define  ADC_SQR1_SQ15_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */\r
+#define  ADC_SQR1_SQ15_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */\r
+#define  ADC_SQR1_SQ15_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */\r
+#define  ADC_SQR1_SQ16                       ((uint32_t)0x000F8000)        /*!<SQ16[4:0] bits (16th conversion in regular sequence) */\r
+#define  ADC_SQR1_SQ16_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_SQR1_SQ16_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_SQR1_SQ16_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_SQR1_SQ16_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */\r
+#define  ADC_SQR1_SQ16_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */\r
+#define  ADC_SQR1_L                          ((uint32_t)0x00F00000)        /*!<L[3:0] bits (Regular channel sequence length) */\r
+#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+/*******************  Bit definition for ADC_SQR2 register  *******************/\r
+#define  ADC_SQR2_SQ7                        ((uint32_t)0x0000001F)        /*!<SQ7[4:0] bits (7th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ7_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ7_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ7_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ7_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ7_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_SQR2_SQ8                        ((uint32_t)0x000003E0)        /*!<SQ8[4:0] bits (8th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ8_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ8_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ8_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ8_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ8_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */\r
+#define  ADC_SQR2_SQ9                        ((uint32_t)0x00007C00)        /*!<SQ9[4:0] bits (9th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ9_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ9_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ9_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ9_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ9_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */\r
+#define  ADC_SQR2_SQ10                       ((uint32_t)0x000F8000)        /*!<SQ10[4:0] bits (10th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ10_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ10_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ10_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ10_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ10_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */\r
+#define  ADC_SQR2_SQ11                       ((uint32_t)0x01F00000)        /*!<SQ11[4:0] bits (11th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ11_0                     ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ11_1                     ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ11_2                     ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ11_3                     ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ11_4                     ((uint32_t)0x01000000)        /*!<Bit 4 */\r
+#define  ADC_SQR2_SQ12                       ((uint32_t)0x3E000000)        /*!<SQ12[4:0] bits (12th conversion in regular sequence) */\r
+#define  ADC_SQR2_SQ12_0                     ((uint32_t)0x02000000)        /*!<Bit 0 */\r
+#define  ADC_SQR2_SQ12_1                     ((uint32_t)0x04000000)        /*!<Bit 1 */\r
+#define  ADC_SQR2_SQ12_2                     ((uint32_t)0x08000000)        /*!<Bit 2 */\r
+#define  ADC_SQR2_SQ12_3                     ((uint32_t)0x10000000)        /*!<Bit 3 */\r
+#define  ADC_SQR2_SQ12_4                     ((uint32_t)0x20000000)        /*!<Bit 4 */\r
+\r
+/*******************  Bit definition for ADC_SQR3 register  *******************/\r
+#define  ADC_SQR3_SQ1                        ((uint32_t)0x0000001F)        /*!<SQ1[4:0] bits (1st conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ1_0                      ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ1_1                      ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ1_2                      ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ1_3                      ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ1_4                      ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_SQR3_SQ2                        ((uint32_t)0x000003E0)        /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ2_0                      ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ2_1                      ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ2_2                      ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ2_3                      ((uint32_t)0x00000100)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ2_4                      ((uint32_t)0x00000200)        /*!<Bit 4 */\r
+#define  ADC_SQR3_SQ3                        ((uint32_t)0x00007C00)        /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ3_0                      ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ3_1                      ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ3_2                      ((uint32_t)0x00001000)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ3_3                      ((uint32_t)0x00002000)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ3_4                      ((uint32_t)0x00004000)        /*!<Bit 4 */\r
+#define  ADC_SQR3_SQ4                        ((uint32_t)0x000F8000)        /*!<SQ4[4:0] bits (4th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ4_0                      ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ4_1                      ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ4_2                      ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ4_3                      ((uint32_t)0x00040000)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ4_4                      ((uint32_t)0x00080000)        /*!<Bit 4 */\r
+#define  ADC_SQR3_SQ5                        ((uint32_t)0x01F00000)        /*!<SQ5[4:0] bits (5th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ5_0                      ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ5_1                      ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ5_2                      ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ5_3                      ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ5_4                      ((uint32_t)0x01000000)        /*!<Bit 4 */\r
+#define  ADC_SQR3_SQ6                        ((uint32_t)0x3E000000)        /*!<SQ6[4:0] bits (6th conversion in regular sequence) */\r
+#define  ADC_SQR3_SQ6_0                      ((uint32_t)0x02000000)        /*!<Bit 0 */\r
+#define  ADC_SQR3_SQ6_1                      ((uint32_t)0x04000000)        /*!<Bit 1 */\r
+#define  ADC_SQR3_SQ6_2                      ((uint32_t)0x08000000)        /*!<Bit 2 */\r
+#define  ADC_SQR3_SQ6_3                      ((uint32_t)0x10000000)        /*!<Bit 3 */\r
+#define  ADC_SQR3_SQ6_4                      ((uint32_t)0x20000000)        /*!<Bit 4 */\r
+\r
+/*******************  Bit definition for ADC_JSQR register  *******************/\r
+#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */  \r
+#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!<Bit 3 */\r
+#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!<Bit 4 */\r
+#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!<Bit 2 */\r
+#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!<Bit 3 */\r
+#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!<Bit 4 */\r
+#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */\r
+#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!<Bit 0 */\r
+#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!<Bit 1 */\r
+#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!<Bit 2 */\r
+#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!<Bit 3 */\r
+#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!<Bit 4 */\r
+#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!<JL[1:0] bits (Injected Sequence length) */\r
+#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for ADC_JDR1 register  *******************/\r
+#define  ADC_JDR1_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR2 register  *******************/\r
+#define  ADC_JDR2_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR3 register  *******************/\r
+#define  ADC_JDR3_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/*******************  Bit definition for ADC_JDR4 register  *******************/\r
+#define  ADC_JDR4_JDATA                      ((uint16_t)0xFFFF)            /*!<Injected data */\r
+\r
+/********************  Bit definition for ADC_DR register  ********************/\r
+#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!<Regular data */\r
+#define  ADC_DR_ADC2DATA                     ((uint32_t)0xFFFF0000)        /*!<ADC2 data */\r
+\r
+/*******************  Bit definition for ADC_CSR register  ********************/\r
+#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!<ADC1 Analog watchdog flag */\r
+#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!<ADC1 End of conversion */\r
+#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!<ADC1 Injected channel end of conversion */\r
+#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!<ADC1 Injected channel Start flag */\r
+#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!<ADC1 Regular channel Start flag */\r
+#define  ADC_CSR_DOVR1                       ((uint32_t)0x00000020)        /*!<ADC1 DMA overrun  flag */\r
+#define  ADC_CSR_AWD2                        ((uint32_t)0x00000100)        /*!<ADC2 Analog watchdog flag */\r
+#define  ADC_CSR_EOC2                        ((uint32_t)0x00000200)        /*!<ADC2 End of conversion */\r
+#define  ADC_CSR_JEOC2                       ((uint32_t)0x00000400)        /*!<ADC2 Injected channel end of conversion */\r
+#define  ADC_CSR_JSTRT2                      ((uint32_t)0x00000800)        /*!<ADC2 Injected channel Start flag */\r
+#define  ADC_CSR_STRT2                       ((uint32_t)0x00001000)        /*!<ADC2 Regular channel Start flag */\r
+#define  ADC_CSR_DOVR2                       ((uint32_t)0x00002000)        /*!<ADC2 DMA overrun  flag */\r
+#define  ADC_CSR_AWD3                        ((uint32_t)0x00010000)        /*!<ADC3 Analog watchdog flag */\r
+#define  ADC_CSR_EOC3                        ((uint32_t)0x00020000)        /*!<ADC3 End of conversion */\r
+#define  ADC_CSR_JEOC3                       ((uint32_t)0x00040000)        /*!<ADC3 Injected channel end of conversion */\r
+#define  ADC_CSR_JSTRT3                      ((uint32_t)0x00080000)        /*!<ADC3 Injected channel Start flag */\r
+#define  ADC_CSR_STRT3                       ((uint32_t)0x00100000)        /*!<ADC3 Regular channel Start flag */\r
+#define  ADC_CSR_DOVR3                       ((uint32_t)0x00200000)        /*!<ADC3 DMA overrun  flag */\r
+\r
+/*******************  Bit definition for ADC_CCR register  ********************/\r
+#define  ADC_CCR_MULTI                       ((uint32_t)0x0000001F)        /*!<MULTI[4:0] bits (Multi-ADC mode selection) */  \r
+#define  ADC_CCR_MULTI_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  ADC_CCR_MULTI_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  ADC_CCR_MULTI_2                     ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  ADC_CCR_MULTI_3                     ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  ADC_CCR_MULTI_4                     ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  ADC_CCR_DELAY                       ((uint32_t)0x00000F00)        /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */  \r
+#define  ADC_CCR_DELAY_0                     ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  ADC_CCR_DELAY_1                     ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  ADC_CCR_DELAY_2                     ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  ADC_CCR_DELAY_3                     ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  ADC_CCR_DDS                         ((uint32_t)0x00002000)        /*!<DMA disable selection (Multi-ADC mode) */\r
+#define  ADC_CCR_DMA                         ((uint32_t)0x0000C000)        /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */  \r
+#define  ADC_CCR_DMA_0                       ((uint32_t)0x00004000)        /*!<Bit 0 */\r
+#define  ADC_CCR_DMA_1                       ((uint32_t)0x00008000)        /*!<Bit 1 */\r
+#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!<ADCPRE[1:0] bits (ADC prescaler) */  \r
+#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  ADC_CCR_VBATE                       ((uint32_t)0x00400000)        /*!<VBAT Enable */\r
+#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!<Temperature Sensor and VREFINT Enable */\r
+\r
+/*******************  Bit definition for ADC_CDR register  ********************/\r
+#define  ADC_CDR_DATA1                      ((uint32_t)0x0000FFFF)         /*!<1st data of a pair of regular conversions */\r
+#define  ADC_CDR_DATA2                      ((uint32_t)0xFFFF0000)         /*!<2nd data of a pair of regular conversions */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Controller Area Network                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*!<CAN control and status registers */\r
+/*******************  Bit definition for CAN_MCR register  ********************/\r
+#define  CAN_MCR_INRQ                        ((uint16_t)0x0001)            /*!<Initialization Request */\r
+#define  CAN_MCR_SLEEP                       ((uint16_t)0x0002)            /*!<Sleep Mode Request */\r
+#define  CAN_MCR_TXFP                        ((uint16_t)0x0004)            /*!<Transmit FIFO Priority */\r
+#define  CAN_MCR_RFLM                        ((uint16_t)0x0008)            /*!<Receive FIFO Locked Mode */\r
+#define  CAN_MCR_NART                        ((uint16_t)0x0010)            /*!<No Automatic Retransmission */\r
+#define  CAN_MCR_AWUM                        ((uint16_t)0x0020)            /*!<Automatic Wakeup Mode */\r
+#define  CAN_MCR_ABOM                        ((uint16_t)0x0040)            /*!<Automatic Bus-Off Management */\r
+#define  CAN_MCR_TTCM                        ((uint16_t)0x0080)            /*!<Time Triggered Communication Mode */\r
+#define  CAN_MCR_RESET                       ((uint16_t)0x8000)            /*!<bxCAN software master reset */\r
+\r
+/*******************  Bit definition for CAN_MSR register  ********************/\r
+#define  CAN_MSR_INAK                        ((uint16_t)0x0001)            /*!<Initialization Acknowledge */\r
+#define  CAN_MSR_SLAK                        ((uint16_t)0x0002)            /*!<Sleep Acknowledge */\r
+#define  CAN_MSR_ERRI                        ((uint16_t)0x0004)            /*!<Error Interrupt */\r
+#define  CAN_MSR_WKUI                        ((uint16_t)0x0008)            /*!<Wakeup Interrupt */\r
+#define  CAN_MSR_SLAKI                       ((uint16_t)0x0010)            /*!<Sleep Acknowledge Interrupt */\r
+#define  CAN_MSR_TXM                         ((uint16_t)0x0100)            /*!<Transmit Mode */\r
+#define  CAN_MSR_RXM                         ((uint16_t)0x0200)            /*!<Receive Mode */\r
+#define  CAN_MSR_SAMP                        ((uint16_t)0x0400)            /*!<Last Sample Point */\r
+#define  CAN_MSR_RX                          ((uint16_t)0x0800)            /*!<CAN Rx Signal */\r
+\r
+/*******************  Bit definition for CAN_TSR register  ********************/\r
+#define  CAN_TSR_RQCP0                       ((uint32_t)0x00000001)        /*!<Request Completed Mailbox0 */\r
+#define  CAN_TSR_TXOK0                       ((uint32_t)0x00000002)        /*!<Transmission OK of Mailbox0 */\r
+#define  CAN_TSR_ALST0                       ((uint32_t)0x00000004)        /*!<Arbitration Lost for Mailbox0 */\r
+#define  CAN_TSR_TERR0                       ((uint32_t)0x00000008)        /*!<Transmission Error of Mailbox0 */\r
+#define  CAN_TSR_ABRQ0                       ((uint32_t)0x00000080)        /*!<Abort Request for Mailbox0 */\r
+#define  CAN_TSR_RQCP1                       ((uint32_t)0x00000100)        /*!<Request Completed Mailbox1 */\r
+#define  CAN_TSR_TXOK1                       ((uint32_t)0x00000200)        /*!<Transmission OK of Mailbox1 */\r
+#define  CAN_TSR_ALST1                       ((uint32_t)0x00000400)        /*!<Arbitration Lost for Mailbox1 */\r
+#define  CAN_TSR_TERR1                       ((uint32_t)0x00000800)        /*!<Transmission Error of Mailbox1 */\r
+#define  CAN_TSR_ABRQ1                       ((uint32_t)0x00008000)        /*!<Abort Request for Mailbox 1 */\r
+#define  CAN_TSR_RQCP2                       ((uint32_t)0x00010000)        /*!<Request Completed Mailbox2 */\r
+#define  CAN_TSR_TXOK2                       ((uint32_t)0x00020000)        /*!<Transmission OK of Mailbox 2 */\r
+#define  CAN_TSR_ALST2                       ((uint32_t)0x00040000)        /*!<Arbitration Lost for mailbox 2 */\r
+#define  CAN_TSR_TERR2                       ((uint32_t)0x00080000)        /*!<Transmission Error of Mailbox 2 */\r
+#define  CAN_TSR_ABRQ2                       ((uint32_t)0x00800000)        /*!<Abort Request for Mailbox 2 */\r
+#define  CAN_TSR_CODE                        ((uint32_t)0x03000000)        /*!<Mailbox Code */\r
+\r
+#define  CAN_TSR_TME                         ((uint32_t)0x1C000000)        /*!<TME[2:0] bits */\r
+#define  CAN_TSR_TME0                        ((uint32_t)0x04000000)        /*!<Transmit Mailbox 0 Empty */\r
+#define  CAN_TSR_TME1                        ((uint32_t)0x08000000)        /*!<Transmit Mailbox 1 Empty */\r
+#define  CAN_TSR_TME2                        ((uint32_t)0x10000000)        /*!<Transmit Mailbox 2 Empty */\r
+\r
+#define  CAN_TSR_LOW                         ((uint32_t)0xE0000000)        /*!<LOW[2:0] bits */\r
+#define  CAN_TSR_LOW0                        ((uint32_t)0x20000000)        /*!<Lowest Priority Flag for Mailbox 0 */\r
+#define  CAN_TSR_LOW1                        ((uint32_t)0x40000000)        /*!<Lowest Priority Flag for Mailbox 1 */\r
+#define  CAN_TSR_LOW2                        ((uint32_t)0x80000000)        /*!<Lowest Priority Flag for Mailbox 2 */\r
+\r
+/*******************  Bit definition for CAN_RF0R register  *******************/\r
+#define  CAN_RF0R_FMP0                       ((uint8_t)0x03)               /*!<FIFO 0 Message Pending */\r
+#define  CAN_RF0R_FULL0                      ((uint8_t)0x08)               /*!<FIFO 0 Full */\r
+#define  CAN_RF0R_FOVR0                      ((uint8_t)0x10)               /*!<FIFO 0 Overrun */\r
+#define  CAN_RF0R_RFOM0                      ((uint8_t)0x20)               /*!<Release FIFO 0 Output Mailbox */\r
+\r
+/*******************  Bit definition for CAN_RF1R register  *******************/\r
+#define  CAN_RF1R_FMP1                       ((uint8_t)0x03)               /*!<FIFO 1 Message Pending */\r
+#define  CAN_RF1R_FULL1                      ((uint8_t)0x08)               /*!<FIFO 1 Full */\r
+#define  CAN_RF1R_FOVR1                      ((uint8_t)0x10)               /*!<FIFO 1 Overrun */\r
+#define  CAN_RF1R_RFOM1                      ((uint8_t)0x20)               /*!<Release FIFO 1 Output Mailbox */\r
+\r
+/********************  Bit definition for CAN_IER register  *******************/\r
+#define  CAN_IER_TMEIE                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Empty Interrupt Enable */\r
+#define  CAN_IER_FMPIE0                      ((uint32_t)0x00000002)        /*!<FIFO Message Pending Interrupt Enable */\r
+#define  CAN_IER_FFIE0                       ((uint32_t)0x00000004)        /*!<FIFO Full Interrupt Enable */\r
+#define  CAN_IER_FOVIE0                      ((uint32_t)0x00000008)        /*!<FIFO Overrun Interrupt Enable */\r
+#define  CAN_IER_FMPIE1                      ((uint32_t)0x00000010)        /*!<FIFO Message Pending Interrupt Enable */\r
+#define  CAN_IER_FFIE1                       ((uint32_t)0x00000020)        /*!<FIFO Full Interrupt Enable */\r
+#define  CAN_IER_FOVIE1                      ((uint32_t)0x00000040)        /*!<FIFO Overrun Interrupt Enable */\r
+#define  CAN_IER_EWGIE                       ((uint32_t)0x00000100)        /*!<Error Warning Interrupt Enable */\r
+#define  CAN_IER_EPVIE                       ((uint32_t)0x00000200)        /*!<Error Passive Interrupt Enable */\r
+#define  CAN_IER_BOFIE                       ((uint32_t)0x00000400)        /*!<Bus-Off Interrupt Enable */\r
+#define  CAN_IER_LECIE                       ((uint32_t)0x00000800)        /*!<Last Error Code Interrupt Enable */\r
+#define  CAN_IER_ERRIE                       ((uint32_t)0x00008000)        /*!<Error Interrupt Enable */\r
+#define  CAN_IER_WKUIE                       ((uint32_t)0x00010000)        /*!<Wakeup Interrupt Enable */\r
+#define  CAN_IER_SLKIE                       ((uint32_t)0x00020000)        /*!<Sleep Interrupt Enable */\r
+\r
+/********************  Bit definition for CAN_ESR register  *******************/\r
+#define  CAN_ESR_EWGF                        ((uint32_t)0x00000001)        /*!<Error Warning Flag */\r
+#define  CAN_ESR_EPVF                        ((uint32_t)0x00000002)        /*!<Error Passive Flag */\r
+#define  CAN_ESR_BOFF                        ((uint32_t)0x00000004)        /*!<Bus-Off Flag */\r
+\r
+#define  CAN_ESR_LEC                         ((uint32_t)0x00000070)        /*!<LEC[2:0] bits (Last Error Code) */\r
+#define  CAN_ESR_LEC_0                       ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  CAN_ESR_LEC_1                       ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  CAN_ESR_LEC_2                       ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+\r
+#define  CAN_ESR_TEC                         ((uint32_t)0x00FF0000)        /*!<Least significant byte of the 9-bit Transmit Error Counter */\r
+#define  CAN_ESR_REC                         ((uint32_t)0xFF000000)        /*!<Receive Error Counter */\r
+\r
+/*******************  Bit definition for CAN_BTR register  ********************/\r
+#define  CAN_BTR_BRP                         ((uint32_t)0x000003FF)        /*!<Baud Rate Prescaler */\r
+#define  CAN_BTR_TS1                         ((uint32_t)0x000F0000)        /*!<Time Segment 1 */\r
+#define  CAN_BTR_TS2                         ((uint32_t)0x00700000)        /*!<Time Segment 2 */\r
+#define  CAN_BTR_SJW                         ((uint32_t)0x03000000)        /*!<Resynchronization Jump Width */\r
+#define  CAN_BTR_LBKM                        ((uint32_t)0x40000000)        /*!<Loop Back Mode (Debug) */\r
+#define  CAN_BTR_SILM                        ((uint32_t)0x80000000)        /*!<Silent Mode */\r
+\r
+/*!<Mailbox registers */\r
+/******************  Bit definition for CAN_TI0R register  ********************/\r
+#define  CAN_TI0R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */\r
+#define  CAN_TI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */\r
+#define  CAN_TI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */\r
+#define  CAN_TI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */\r
+#define  CAN_TI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */\r
+\r
+/******************  Bit definition for CAN_TDT0R register  *******************/\r
+#define  CAN_TDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */\r
+#define  CAN_TDT0R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */\r
+#define  CAN_TDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */\r
+\r
+/******************  Bit definition for CAN_TDL0R register  *******************/\r
+#define  CAN_TDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */\r
+#define  CAN_TDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */\r
+#define  CAN_TDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */\r
+#define  CAN_TDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */\r
+\r
+/******************  Bit definition for CAN_TDH0R register  *******************/\r
+#define  CAN_TDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */\r
+#define  CAN_TDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */\r
+#define  CAN_TDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */\r
+#define  CAN_TDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_TI1R register  *******************/\r
+#define  CAN_TI1R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */\r
+#define  CAN_TI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */\r
+#define  CAN_TI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */\r
+#define  CAN_TI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */\r
+#define  CAN_TI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_TDT1R register  ******************/\r
+#define  CAN_TDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */\r
+#define  CAN_TDT1R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */\r
+#define  CAN_TDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_TDL1R register  ******************/\r
+#define  CAN_TDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */\r
+#define  CAN_TDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */\r
+#define  CAN_TDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */\r
+#define  CAN_TDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_TDH1R register  ******************/\r
+#define  CAN_TDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */\r
+#define  CAN_TDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */\r
+#define  CAN_TDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */\r
+#define  CAN_TDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_TI2R register  *******************/\r
+#define  CAN_TI2R_TXRQ                       ((uint32_t)0x00000001)        /*!<Transmit Mailbox Request */\r
+#define  CAN_TI2R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */\r
+#define  CAN_TI2R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */\r
+#define  CAN_TI2R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */\r
+#define  CAN_TI2R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_TDT2R register  ******************/  \r
+#define  CAN_TDT2R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */\r
+#define  CAN_TDT2R_TGT                       ((uint32_t)0x00000100)        /*!<Transmit Global Time */\r
+#define  CAN_TDT2R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_TDL2R register  ******************/\r
+#define  CAN_TDL2R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */\r
+#define  CAN_TDL2R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */\r
+#define  CAN_TDL2R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */\r
+#define  CAN_TDL2R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_TDH2R register  ******************/\r
+#define  CAN_TDH2R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */\r
+#define  CAN_TDH2R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */\r
+#define  CAN_TDH2R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */\r
+#define  CAN_TDH2R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_RI0R register  *******************/\r
+#define  CAN_RI0R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */\r
+#define  CAN_RI0R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */\r
+#define  CAN_RI0R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended Identifier */\r
+#define  CAN_RI0R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_RDT0R register  ******************/\r
+#define  CAN_RDT0R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */\r
+#define  CAN_RDT0R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */\r
+#define  CAN_RDT0R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_RDL0R register  ******************/\r
+#define  CAN_RDL0R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */\r
+#define  CAN_RDL0R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */\r
+#define  CAN_RDL0R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */\r
+#define  CAN_RDL0R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_RDH0R register  ******************/\r
+#define  CAN_RDH0R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */\r
+#define  CAN_RDH0R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */\r
+#define  CAN_RDH0R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */\r
+#define  CAN_RDH0R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */\r
+\r
+/*******************  Bit definition for CAN_RI1R register  *******************/\r
+#define  CAN_RI1R_RTR                        ((uint32_t)0x00000002)        /*!<Remote Transmission Request */\r
+#define  CAN_RI1R_IDE                        ((uint32_t)0x00000004)        /*!<Identifier Extension */\r
+#define  CAN_RI1R_EXID                       ((uint32_t)0x001FFFF8)        /*!<Extended identifier */\r
+#define  CAN_RI1R_STID                       ((uint32_t)0xFFE00000)        /*!<Standard Identifier or Extended Identifier */\r
+\r
+/*******************  Bit definition for CAN_RDT1R register  ******************/\r
+#define  CAN_RDT1R_DLC                       ((uint32_t)0x0000000F)        /*!<Data Length Code */\r
+#define  CAN_RDT1R_FMI                       ((uint32_t)0x0000FF00)        /*!<Filter Match Index */\r
+#define  CAN_RDT1R_TIME                      ((uint32_t)0xFFFF0000)        /*!<Message Time Stamp */\r
+\r
+/*******************  Bit definition for CAN_RDL1R register  ******************/\r
+#define  CAN_RDL1R_DATA0                     ((uint32_t)0x000000FF)        /*!<Data byte 0 */\r
+#define  CAN_RDL1R_DATA1                     ((uint32_t)0x0000FF00)        /*!<Data byte 1 */\r
+#define  CAN_RDL1R_DATA2                     ((uint32_t)0x00FF0000)        /*!<Data byte 2 */\r
+#define  CAN_RDL1R_DATA3                     ((uint32_t)0xFF000000)        /*!<Data byte 3 */\r
+\r
+/*******************  Bit definition for CAN_RDH1R register  ******************/\r
+#define  CAN_RDH1R_DATA4                     ((uint32_t)0x000000FF)        /*!<Data byte 4 */\r
+#define  CAN_RDH1R_DATA5                     ((uint32_t)0x0000FF00)        /*!<Data byte 5 */\r
+#define  CAN_RDH1R_DATA6                     ((uint32_t)0x00FF0000)        /*!<Data byte 6 */\r
+#define  CAN_RDH1R_DATA7                     ((uint32_t)0xFF000000)        /*!<Data byte 7 */\r
+\r
+/*!<CAN filter registers */\r
+/*******************  Bit definition for CAN_FMR register  ********************/\r
+#define  CAN_FMR_FINIT                       ((uint8_t)0x01)               /*!<Filter Init Mode */\r
+\r
+/*******************  Bit definition for CAN_FM1R register  *******************/\r
+#define  CAN_FM1R_FBM                        ((uint16_t)0x3FFF)            /*!<Filter Mode */\r
+#define  CAN_FM1R_FBM0                       ((uint16_t)0x0001)            /*!<Filter Init Mode bit 0 */\r
+#define  CAN_FM1R_FBM1                       ((uint16_t)0x0002)            /*!<Filter Init Mode bit 1 */\r
+#define  CAN_FM1R_FBM2                       ((uint16_t)0x0004)            /*!<Filter Init Mode bit 2 */\r
+#define  CAN_FM1R_FBM3                       ((uint16_t)0x0008)            /*!<Filter Init Mode bit 3 */\r
+#define  CAN_FM1R_FBM4                       ((uint16_t)0x0010)            /*!<Filter Init Mode bit 4 */\r
+#define  CAN_FM1R_FBM5                       ((uint16_t)0x0020)            /*!<Filter Init Mode bit 5 */\r
+#define  CAN_FM1R_FBM6                       ((uint16_t)0x0040)            /*!<Filter Init Mode bit 6 */\r
+#define  CAN_FM1R_FBM7                       ((uint16_t)0x0080)            /*!<Filter Init Mode bit 7 */\r
+#define  CAN_FM1R_FBM8                       ((uint16_t)0x0100)            /*!<Filter Init Mode bit 8 */\r
+#define  CAN_FM1R_FBM9                       ((uint16_t)0x0200)            /*!<Filter Init Mode bit 9 */\r
+#define  CAN_FM1R_FBM10                      ((uint16_t)0x0400)            /*!<Filter Init Mode bit 10 */\r
+#define  CAN_FM1R_FBM11                      ((uint16_t)0x0800)            /*!<Filter Init Mode bit 11 */\r
+#define  CAN_FM1R_FBM12                      ((uint16_t)0x1000)            /*!<Filter Init Mode bit 12 */\r
+#define  CAN_FM1R_FBM13                      ((uint16_t)0x2000)            /*!<Filter Init Mode bit 13 */\r
+\r
+/*******************  Bit definition for CAN_FS1R register  *******************/\r
+#define  CAN_FS1R_FSC                        ((uint16_t)0x3FFF)            /*!<Filter Scale Configuration */\r
+#define  CAN_FS1R_FSC0                       ((uint16_t)0x0001)            /*!<Filter Scale Configuration bit 0 */\r
+#define  CAN_FS1R_FSC1                       ((uint16_t)0x0002)            /*!<Filter Scale Configuration bit 1 */\r
+#define  CAN_FS1R_FSC2                       ((uint16_t)0x0004)            /*!<Filter Scale Configuration bit 2 */\r
+#define  CAN_FS1R_FSC3                       ((uint16_t)0x0008)            /*!<Filter Scale Configuration bit 3 */\r
+#define  CAN_FS1R_FSC4                       ((uint16_t)0x0010)            /*!<Filter Scale Configuration bit 4 */\r
+#define  CAN_FS1R_FSC5                       ((uint16_t)0x0020)            /*!<Filter Scale Configuration bit 5 */\r
+#define  CAN_FS1R_FSC6                       ((uint16_t)0x0040)            /*!<Filter Scale Configuration bit 6 */\r
+#define  CAN_FS1R_FSC7                       ((uint16_t)0x0080)            /*!<Filter Scale Configuration bit 7 */\r
+#define  CAN_FS1R_FSC8                       ((uint16_t)0x0100)            /*!<Filter Scale Configuration bit 8 */\r
+#define  CAN_FS1R_FSC9                       ((uint16_t)0x0200)            /*!<Filter Scale Configuration bit 9 */\r
+#define  CAN_FS1R_FSC10                      ((uint16_t)0x0400)            /*!<Filter Scale Configuration bit 10 */\r
+#define  CAN_FS1R_FSC11                      ((uint16_t)0x0800)            /*!<Filter Scale Configuration bit 11 */\r
+#define  CAN_FS1R_FSC12                      ((uint16_t)0x1000)            /*!<Filter Scale Configuration bit 12 */\r
+#define  CAN_FS1R_FSC13                      ((uint16_t)0x2000)            /*!<Filter Scale Configuration bit 13 */\r
+\r
+/******************  Bit definition for CAN_FFA1R register  *******************/\r
+#define  CAN_FFA1R_FFA                       ((uint16_t)0x3FFF)            /*!<Filter FIFO Assignment */\r
+#define  CAN_FFA1R_FFA0                      ((uint16_t)0x0001)            /*!<Filter FIFO Assignment for Filter 0 */\r
+#define  CAN_FFA1R_FFA1                      ((uint16_t)0x0002)            /*!<Filter FIFO Assignment for Filter 1 */\r
+#define  CAN_FFA1R_FFA2                      ((uint16_t)0x0004)            /*!<Filter FIFO Assignment for Filter 2 */\r
+#define  CAN_FFA1R_FFA3                      ((uint16_t)0x0008)            /*!<Filter FIFO Assignment for Filter 3 */\r
+#define  CAN_FFA1R_FFA4                      ((uint16_t)0x0010)            /*!<Filter FIFO Assignment for Filter 4 */\r
+#define  CAN_FFA1R_FFA5                      ((uint16_t)0x0020)            /*!<Filter FIFO Assignment for Filter 5 */\r
+#define  CAN_FFA1R_FFA6                      ((uint16_t)0x0040)            /*!<Filter FIFO Assignment for Filter 6 */\r
+#define  CAN_FFA1R_FFA7                      ((uint16_t)0x0080)            /*!<Filter FIFO Assignment for Filter 7 */\r
+#define  CAN_FFA1R_FFA8                      ((uint16_t)0x0100)            /*!<Filter FIFO Assignment for Filter 8 */\r
+#define  CAN_FFA1R_FFA9                      ((uint16_t)0x0200)            /*!<Filter FIFO Assignment for Filter 9 */\r
+#define  CAN_FFA1R_FFA10                     ((uint16_t)0x0400)            /*!<Filter FIFO Assignment for Filter 10 */\r
+#define  CAN_FFA1R_FFA11                     ((uint16_t)0x0800)            /*!<Filter FIFO Assignment for Filter 11 */\r
+#define  CAN_FFA1R_FFA12                     ((uint16_t)0x1000)            /*!<Filter FIFO Assignment for Filter 12 */\r
+#define  CAN_FFA1R_FFA13                     ((uint16_t)0x2000)            /*!<Filter FIFO Assignment for Filter 13 */\r
+\r
+/*******************  Bit definition for CAN_FA1R register  *******************/\r
+#define  CAN_FA1R_FACT                       ((uint16_t)0x3FFF)            /*!<Filter Active */\r
+#define  CAN_FA1R_FACT0                      ((uint16_t)0x0001)            /*!<Filter 0 Active */\r
+#define  CAN_FA1R_FACT1                      ((uint16_t)0x0002)            /*!<Filter 1 Active */\r
+#define  CAN_FA1R_FACT2                      ((uint16_t)0x0004)            /*!<Filter 2 Active */\r
+#define  CAN_FA1R_FACT3                      ((uint16_t)0x0008)            /*!<Filter 3 Active */\r
+#define  CAN_FA1R_FACT4                      ((uint16_t)0x0010)            /*!<Filter 4 Active */\r
+#define  CAN_FA1R_FACT5                      ((uint16_t)0x0020)            /*!<Filter 5 Active */\r
+#define  CAN_FA1R_FACT6                      ((uint16_t)0x0040)            /*!<Filter 6 Active */\r
+#define  CAN_FA1R_FACT7                      ((uint16_t)0x0080)            /*!<Filter 7 Active */\r
+#define  CAN_FA1R_FACT8                      ((uint16_t)0x0100)            /*!<Filter 8 Active */\r
+#define  CAN_FA1R_FACT9                      ((uint16_t)0x0200)            /*!<Filter 9 Active */\r
+#define  CAN_FA1R_FACT10                     ((uint16_t)0x0400)            /*!<Filter 10 Active */\r
+#define  CAN_FA1R_FACT11                     ((uint16_t)0x0800)            /*!<Filter 11 Active */\r
+#define  CAN_FA1R_FACT12                     ((uint16_t)0x1000)            /*!<Filter 12 Active */\r
+#define  CAN_FA1R_FACT13                     ((uint16_t)0x2000)            /*!<Filter 13 Active */\r
+\r
+/*******************  Bit definition for CAN_F0R1 register  *******************/\r
+#define  CAN_F0R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F0R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F0R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F0R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F0R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F0R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F0R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F0R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F0R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F0R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F0R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F0R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F0R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F0R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F0R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F0R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F0R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F0R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F0R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F0R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F0R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F0R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F0R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F0R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F0R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F0R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F0R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F0R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F0R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F0R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F0R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F0R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F1R1 register  *******************/\r
+#define  CAN_F1R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F1R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F1R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F1R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F1R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F1R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F1R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F1R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F1R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F1R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F1R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F1R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F1R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F1R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F1R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F1R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F1R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F1R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F1R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F1R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F1R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F1R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F1R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F1R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F1R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F1R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F1R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F1R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F1R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F1R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F1R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F1R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F2R1 register  *******************/\r
+#define  CAN_F2R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F2R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F2R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F2R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F2R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F2R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F2R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F2R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F2R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F2R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F2R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F2R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F2R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F2R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F2R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F2R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F2R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F2R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F2R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F2R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F2R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F2R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F2R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F2R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F2R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F2R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F2R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F2R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F2R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F2R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F2R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F2R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F3R1 register  *******************/\r
+#define  CAN_F3R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F3R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F3R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F3R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F3R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F3R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F3R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F3R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F3R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F3R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F3R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F3R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F3R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F3R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F3R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F3R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F3R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F3R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F3R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F3R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F3R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F3R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F3R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F3R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F3R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F3R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F3R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F3R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F3R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F3R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F3R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F3R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F4R1 register  *******************/\r
+#define  CAN_F4R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F4R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F4R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F4R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F4R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F4R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F4R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F4R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F4R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F4R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F4R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F4R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F4R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F4R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F4R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F4R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F4R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F4R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F4R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F4R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F4R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F4R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F4R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F4R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F4R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F4R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F4R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F4R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F4R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F4R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F4R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F4R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F5R1 register  *******************/\r
+#define  CAN_F5R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F5R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F5R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F5R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F5R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F5R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F5R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F5R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F5R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F5R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F5R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F5R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F5R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F5R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F5R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F5R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F5R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F5R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F5R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F5R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F5R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F5R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F5R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F5R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F5R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F5R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F5R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F5R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F5R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F5R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F5R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F5R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F6R1 register  *******************/\r
+#define  CAN_F6R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F6R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F6R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F6R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F6R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F6R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F6R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F6R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F6R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F6R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F6R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F6R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F6R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F6R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F6R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F6R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F6R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F6R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F6R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F6R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F6R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F6R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F6R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F6R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F6R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F6R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F6R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F6R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F6R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F6R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F6R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F6R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F7R1 register  *******************/\r
+#define  CAN_F7R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F7R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F7R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F7R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F7R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F7R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F7R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F7R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F7R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F7R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F7R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F7R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F7R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F7R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F7R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F7R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F7R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F7R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F7R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F7R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F7R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F7R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F7R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F7R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F7R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F7R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F7R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F7R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F7R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F7R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F7R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F7R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F8R1 register  *******************/\r
+#define  CAN_F8R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F8R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F8R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F8R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F8R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F8R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F8R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F8R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F8R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F8R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F8R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F8R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F8R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F8R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F8R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F8R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F8R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F8R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F8R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F8R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F8R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F8R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F8R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F8R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F8R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F8R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F8R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F8R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F8R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F8R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F8R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F8R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F9R1 register  *******************/\r
+#define  CAN_F9R1_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F9R1_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F9R1_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F9R1_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F9R1_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F9R1_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F9R1_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F9R1_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F9R1_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F9R1_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F9R1_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F9R1_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F9R1_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F9R1_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F9R1_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F9R1_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F9R1_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F9R1_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F9R1_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F9R1_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F9R1_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F9R1_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F9R1_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F9R1_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F9R1_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F9R1_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F9R1_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F9R1_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F9R1_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F9R1_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F9R1_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F9R1_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F10R1 register  ******************/\r
+#define  CAN_F10R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F10R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F10R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F10R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F10R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F10R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F10R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F10R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F10R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F10R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F10R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F10R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F10R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F10R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F10R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F10R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F10R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F10R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F10R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F10R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F10R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F10R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F10R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F10R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F10R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F10R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F10R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F10R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F10R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F10R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F10R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F10R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F11R1 register  ******************/\r
+#define  CAN_F11R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F11R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F11R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F11R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F11R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F11R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F11R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F11R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F11R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F11R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F11R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F11R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F11R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F11R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F11R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F11R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F11R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F11R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F11R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F11R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F11R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F11R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F11R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F11R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F11R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F11R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F11R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F11R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F11R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F11R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F11R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F11R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F12R1 register  ******************/\r
+#define  CAN_F12R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F12R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F12R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F12R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F12R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F12R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F12R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F12R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F12R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F12R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F12R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F12R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F12R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F12R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F12R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F12R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F12R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F12R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F12R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F12R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F12R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F12R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F12R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F12R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F12R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F12R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F12R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F12R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F12R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F12R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F12R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F12R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F13R1 register  ******************/\r
+#define  CAN_F13R1_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F13R1_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F13R1_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F13R1_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F13R1_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F13R1_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F13R1_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F13R1_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F13R1_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F13R1_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F13R1_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F13R1_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F13R1_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F13R1_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F13R1_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F13R1_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F13R1_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F13R1_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F13R1_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F13R1_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F13R1_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F13R1_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F13R1_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F13R1_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F13R1_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F13R1_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F13R1_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F13R1_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F13R1_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F13R1_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F13R1_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F13R1_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F0R2 register  *******************/\r
+#define  CAN_F0R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F0R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F0R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F0R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F0R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F0R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F0R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F0R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F0R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F0R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F0R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F0R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F0R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F0R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F0R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F0R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F0R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F0R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F0R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F0R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F0R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F0R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F0R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F0R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F0R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F0R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F0R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F0R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F0R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F0R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F0R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F0R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F1R2 register  *******************/\r
+#define  CAN_F1R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F1R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F1R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F1R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F1R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F1R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F1R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F1R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F1R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F1R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F1R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F1R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F1R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F1R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F1R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F1R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F1R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F1R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F1R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F1R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F1R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F1R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F1R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F1R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F1R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F1R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F1R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F1R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F1R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F1R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F1R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F1R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F2R2 register  *******************/\r
+#define  CAN_F2R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F2R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F2R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F2R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F2R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F2R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F2R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F2R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F2R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F2R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F2R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F2R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F2R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F2R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F2R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F2R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F2R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F2R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F2R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F2R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F2R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F2R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F2R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F2R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F2R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F2R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F2R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F2R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F2R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F2R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F2R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F2R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F3R2 register  *******************/\r
+#define  CAN_F3R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F3R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F3R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F3R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F3R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F3R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F3R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F3R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F3R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F3R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F3R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F3R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F3R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F3R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F3R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F3R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F3R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F3R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F3R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F3R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F3R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F3R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F3R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F3R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F3R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F3R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F3R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F3R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F3R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F3R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F3R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F3R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F4R2 register  *******************/\r
+#define  CAN_F4R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F4R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F4R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F4R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F4R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F4R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F4R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F4R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F4R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F4R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F4R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F4R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F4R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F4R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F4R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F4R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F4R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F4R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F4R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F4R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F4R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F4R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F4R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F4R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F4R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F4R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F4R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F4R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F4R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F4R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F4R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F4R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F5R2 register  *******************/\r
+#define  CAN_F5R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F5R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F5R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F5R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F5R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F5R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F5R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F5R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F5R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F5R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F5R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F5R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F5R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F5R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F5R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F5R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F5R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F5R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F5R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F5R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F5R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F5R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F5R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F5R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F5R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F5R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F5R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F5R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F5R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F5R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F5R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F5R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F6R2 register  *******************/\r
+#define  CAN_F6R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F6R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F6R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F6R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F6R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F6R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F6R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F6R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F6R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F6R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F6R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F6R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F6R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F6R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F6R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F6R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F6R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F6R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F6R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F6R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F6R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F6R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F6R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F6R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F6R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F6R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F6R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F6R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F6R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F6R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F6R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F6R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F7R2 register  *******************/\r
+#define  CAN_F7R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F7R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F7R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F7R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F7R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F7R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F7R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F7R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F7R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F7R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F7R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F7R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F7R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F7R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F7R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F7R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F7R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F7R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F7R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F7R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F7R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F7R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F7R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F7R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F7R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F7R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F7R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F7R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F7R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F7R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F7R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F7R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F8R2 register  *******************/\r
+#define  CAN_F8R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F8R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F8R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F8R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F8R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F8R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F8R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F8R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F8R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F8R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F8R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F8R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F8R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F8R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F8R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F8R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F8R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F8R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F8R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F8R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F8R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F8R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F8R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F8R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F8R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F8R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F8R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F8R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F8R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F8R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F8R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F8R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F9R2 register  *******************/\r
+#define  CAN_F9R2_FB0                        ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F9R2_FB1                        ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F9R2_FB2                        ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F9R2_FB3                        ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F9R2_FB4                        ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F9R2_FB5                        ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F9R2_FB6                        ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F9R2_FB7                        ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F9R2_FB8                        ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F9R2_FB9                        ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F9R2_FB10                       ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F9R2_FB11                       ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F9R2_FB12                       ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F9R2_FB13                       ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F9R2_FB14                       ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F9R2_FB15                       ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F9R2_FB16                       ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F9R2_FB17                       ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F9R2_FB18                       ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F9R2_FB19                       ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F9R2_FB20                       ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F9R2_FB21                       ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F9R2_FB22                       ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F9R2_FB23                       ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F9R2_FB24                       ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F9R2_FB25                       ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F9R2_FB26                       ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F9R2_FB27                       ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F9R2_FB28                       ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F9R2_FB29                       ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F9R2_FB30                       ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F9R2_FB31                       ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F10R2 register  ******************/\r
+#define  CAN_F10R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F10R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F10R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F10R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F10R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F10R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F10R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F10R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F10R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F10R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F10R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F10R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F10R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F10R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F10R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F10R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F10R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F10R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F10R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F10R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F10R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F10R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F10R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F10R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F10R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F10R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F10R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F10R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F10R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F10R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F10R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F10R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F11R2 register  ******************/\r
+#define  CAN_F11R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F11R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F11R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F11R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F11R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F11R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F11R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F11R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F11R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F11R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F11R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F11R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F11R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F11R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F11R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F11R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F11R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F11R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F11R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F11R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F11R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F11R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F11R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F11R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F11R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F11R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F11R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F11R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F11R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F11R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F11R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F11R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F12R2 register  ******************/\r
+#define  CAN_F12R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F12R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F12R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F12R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F12R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F12R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F12R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F12R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F12R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F12R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F12R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F12R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F12R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F12R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F12R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F12R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F12R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F12R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F12R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F12R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F12R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F12R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F12R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F12R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F12R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F12R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F12R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F12R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F12R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F12R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F12R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F12R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/*******************  Bit definition for CAN_F13R2 register  ******************/\r
+#define  CAN_F13R2_FB0                       ((uint32_t)0x00000001)        /*!<Filter bit 0 */\r
+#define  CAN_F13R2_FB1                       ((uint32_t)0x00000002)        /*!<Filter bit 1 */\r
+#define  CAN_F13R2_FB2                       ((uint32_t)0x00000004)        /*!<Filter bit 2 */\r
+#define  CAN_F13R2_FB3                       ((uint32_t)0x00000008)        /*!<Filter bit 3 */\r
+#define  CAN_F13R2_FB4                       ((uint32_t)0x00000010)        /*!<Filter bit 4 */\r
+#define  CAN_F13R2_FB5                       ((uint32_t)0x00000020)        /*!<Filter bit 5 */\r
+#define  CAN_F13R2_FB6                       ((uint32_t)0x00000040)        /*!<Filter bit 6 */\r
+#define  CAN_F13R2_FB7                       ((uint32_t)0x00000080)        /*!<Filter bit 7 */\r
+#define  CAN_F13R2_FB8                       ((uint32_t)0x00000100)        /*!<Filter bit 8 */\r
+#define  CAN_F13R2_FB9                       ((uint32_t)0x00000200)        /*!<Filter bit 9 */\r
+#define  CAN_F13R2_FB10                      ((uint32_t)0x00000400)        /*!<Filter bit 10 */\r
+#define  CAN_F13R2_FB11                      ((uint32_t)0x00000800)        /*!<Filter bit 11 */\r
+#define  CAN_F13R2_FB12                      ((uint32_t)0x00001000)        /*!<Filter bit 12 */\r
+#define  CAN_F13R2_FB13                      ((uint32_t)0x00002000)        /*!<Filter bit 13 */\r
+#define  CAN_F13R2_FB14                      ((uint32_t)0x00004000)        /*!<Filter bit 14 */\r
+#define  CAN_F13R2_FB15                      ((uint32_t)0x00008000)        /*!<Filter bit 15 */\r
+#define  CAN_F13R2_FB16                      ((uint32_t)0x00010000)        /*!<Filter bit 16 */\r
+#define  CAN_F13R2_FB17                      ((uint32_t)0x00020000)        /*!<Filter bit 17 */\r
+#define  CAN_F13R2_FB18                      ((uint32_t)0x00040000)        /*!<Filter bit 18 */\r
+#define  CAN_F13R2_FB19                      ((uint32_t)0x00080000)        /*!<Filter bit 19 */\r
+#define  CAN_F13R2_FB20                      ((uint32_t)0x00100000)        /*!<Filter bit 20 */\r
+#define  CAN_F13R2_FB21                      ((uint32_t)0x00200000)        /*!<Filter bit 21 */\r
+#define  CAN_F13R2_FB22                      ((uint32_t)0x00400000)        /*!<Filter bit 22 */\r
+#define  CAN_F13R2_FB23                      ((uint32_t)0x00800000)        /*!<Filter bit 23 */\r
+#define  CAN_F13R2_FB24                      ((uint32_t)0x01000000)        /*!<Filter bit 24 */\r
+#define  CAN_F13R2_FB25                      ((uint32_t)0x02000000)        /*!<Filter bit 25 */\r
+#define  CAN_F13R2_FB26                      ((uint32_t)0x04000000)        /*!<Filter bit 26 */\r
+#define  CAN_F13R2_FB27                      ((uint32_t)0x08000000)        /*!<Filter bit 27 */\r
+#define  CAN_F13R2_FB28                      ((uint32_t)0x10000000)        /*!<Filter bit 28 */\r
+#define  CAN_F13R2_FB29                      ((uint32_t)0x20000000)        /*!<Filter bit 29 */\r
+#define  CAN_F13R2_FB30                      ((uint32_t)0x40000000)        /*!<Filter bit 30 */\r
+#define  CAN_F13R2_FB31                      ((uint32_t)0x80000000)        /*!<Filter bit 31 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          CRC calculation unit                              */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for CRC_DR register  *********************/\r
+#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */\r
+\r
+\r
+/*******************  Bit definition for CRC_IDR register  ********************/\r
+#define  CRC_IDR_IDR                         ((uint8_t)0xFF)        /*!< General-purpose 8-bit data register bits */\r
+\r
+\r
+/********************  Bit definition for CRC_CR register  ********************/\r
+#define  CRC_CR_RESET                        ((uint8_t)0x01)        /*!< RESET bit */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                            Crypto Processor                                */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************* Bits definition for CRYP_CR register  ********************/\r
+#define CRYP_CR_ALGODIR                      ((uint32_t)0x00000004)\r
+\r
+#define CRYP_CR_ALGOMODE                     ((uint32_t)0x00080038)\r
+#define CRYP_CR_ALGOMODE_0                   ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_1                   ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_2                   ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_TDES_ECB            ((uint32_t)0x00000000)\r
+#define CRYP_CR_ALGOMODE_TDES_CBC            ((uint32_t)0x00000008)\r
+#define CRYP_CR_ALGOMODE_DES_ECB             ((uint32_t)0x00000010)\r
+#define CRYP_CR_ALGOMODE_DES_CBC             ((uint32_t)0x00000018)\r
+#define CRYP_CR_ALGOMODE_AES_ECB             ((uint32_t)0x00000020)\r
+#define CRYP_CR_ALGOMODE_AES_CBC             ((uint32_t)0x00000028)\r
+#define CRYP_CR_ALGOMODE_AES_CTR             ((uint32_t)0x00000030)\r
+#define CRYP_CR_ALGOMODE_AES_KEY             ((uint32_t)0x00000038)\r
+\r
+#define CRYP_CR_DATATYPE                     ((uint32_t)0x000000C0)\r
+#define CRYP_CR_DATATYPE_0                   ((uint32_t)0x00000040)\r
+#define CRYP_CR_DATATYPE_1                   ((uint32_t)0x00000080)\r
+#define CRYP_CR_KEYSIZE                      ((uint32_t)0x00000300)\r
+#define CRYP_CR_KEYSIZE_0                    ((uint32_t)0x00000100)\r
+#define CRYP_CR_KEYSIZE_1                    ((uint32_t)0x00000200)\r
+#define CRYP_CR_FFLUSH                       ((uint32_t)0x00004000)\r
+#define CRYP_CR_CRYPEN                       ((uint32_t)0x00008000)\r
+\r
+#define CRYP_CR_GCM_CCMPH                    ((uint32_t)0x00030000)\r
+#define CRYP_CR_GCM_CCMPH_0                  ((uint32_t)0x00010000)\r
+#define CRYP_CR_GCM_CCMPH_1                  ((uint32_t)0x00020000)\r
+#define CRYP_CR_ALGOMODE_3                   ((uint32_t)0x00080000) \r
+\r
+/****************** Bits definition for CRYP_SR register  *********************/\r
+#define CRYP_SR_IFEM                         ((uint32_t)0x00000001)\r
+#define CRYP_SR_IFNF                         ((uint32_t)0x00000002)\r
+#define CRYP_SR_OFNE                         ((uint32_t)0x00000004)\r
+#define CRYP_SR_OFFU                         ((uint32_t)0x00000008)\r
+#define CRYP_SR_BUSY                         ((uint32_t)0x00000010)\r
+/****************** Bits definition for CRYP_DMACR register  ******************/\r
+#define CRYP_DMACR_DIEN                      ((uint32_t)0x00000001)\r
+#define CRYP_DMACR_DOEN                      ((uint32_t)0x00000002)\r
+/*****************  Bits definition for CRYP_IMSCR register  ******************/\r
+#define CRYP_IMSCR_INIM                      ((uint32_t)0x00000001)\r
+#define CRYP_IMSCR_OUTIM                     ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_RISR register  *******************/\r
+#define CRYP_RISR_OUTRIS                     ((uint32_t)0x00000001)\r
+#define CRYP_RISR_INRIS                      ((uint32_t)0x00000002)\r
+/****************** Bits definition for CRYP_MISR register  *******************/\r
+#define CRYP_MISR_INMIS                      ((uint32_t)0x00000001)\r
+#define CRYP_MISR_OUTMIS                     ((uint32_t)0x00000002)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Digital to Analog Converter                           */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for DAC_CR register  ********************/\r
+#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */\r
+#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */\r
+#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */\r
+\r
+#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */\r
+#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */\r
+#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */\r
+#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */\r
+\r
+#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */\r
+#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */\r
+#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */\r
+\r
+#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */\r
+#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */\r
+#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */\r
+#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */\r
+#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */\r
+\r
+#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */\r
+#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */\r
+#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */\r
+#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */\r
+\r
+#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */\r
+#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */\r
+#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */\r
+\r
+#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */\r
+#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */\r
+\r
+/*****************  Bit definition for DAC_SWTRIGR register  ******************/\r
+#define  DAC_SWTRIGR_SWTRIG1                 ((uint8_t)0x01)               /*!<DAC channel1 software trigger */\r
+#define  DAC_SWTRIGR_SWTRIG2                 ((uint8_t)0x02)               /*!<DAC channel2 software trigger */\r
+\r
+/*****************  Bit definition for DAC_DHR12R1 register  ******************/\r
+#define  DAC_DHR12R1_DACC1DHR                ((uint16_t)0x0FFF)            /*!<DAC channel1 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L1 register  ******************/\r
+#define  DAC_DHR12L1_DACC1DHR                ((uint16_t)0xFFF0)            /*!<DAC channel1 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R1 register  ******************/\r
+#define  DAC_DHR8R1_DACC1DHR                 ((uint8_t)0xFF)               /*!<DAC channel1 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12R2 register  ******************/\r
+#define  DAC_DHR12R2_DACC2DHR                ((uint16_t)0x0FFF)            /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12L2 register  ******************/\r
+#define  DAC_DHR12L2_DACC2DHR                ((uint16_t)0xFFF0)            /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8R2 register  ******************/\r
+#define  DAC_DHR8R2_DACC2DHR                 ((uint8_t)0xFF)               /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12RD register  ******************/\r
+#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */\r
+#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */\r
+\r
+/*****************  Bit definition for DAC_DHR12LD register  ******************/\r
+#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */\r
+#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */\r
+\r
+/******************  Bit definition for DAC_DHR8RD register  ******************/\r
+#define  DAC_DHR8RD_DACC1DHR                 ((uint16_t)0x00FF)            /*!<DAC channel1 8-bit Right aligned data */\r
+#define  DAC_DHR8RD_DACC2DHR                 ((uint16_t)0xFF00)            /*!<DAC channel2 8-bit Right aligned data */\r
+\r
+/*******************  Bit definition for DAC_DOR1 register  *******************/\r
+#define  DAC_DOR1_DACC1DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel1 data output */\r
+\r
+/*******************  Bit definition for DAC_DOR2 register  *******************/\r
+#define  DAC_DOR2_DACC2DOR                   ((uint16_t)0x0FFF)            /*!<DAC channel2 data output */\r
+\r
+/********************  Bit definition for DAC_SR register  ********************/\r
+#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */\r
+#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 Debug MCU                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    DCMI                                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for DCMI_CR register  ******************/\r
+#define DCMI_CR_CAPTURE                      ((uint32_t)0x00000001)\r
+#define DCMI_CR_CM                           ((uint32_t)0x00000002)\r
+#define DCMI_CR_CROP                         ((uint32_t)0x00000004)\r
+#define DCMI_CR_JPEG                         ((uint32_t)0x00000008)\r
+#define DCMI_CR_ESS                          ((uint32_t)0x00000010)\r
+#define DCMI_CR_PCKPOL                       ((uint32_t)0x00000020)\r
+#define DCMI_CR_HSPOL                        ((uint32_t)0x00000040)\r
+#define DCMI_CR_VSPOL                        ((uint32_t)0x00000080)\r
+#define DCMI_CR_FCRC_0                       ((uint32_t)0x00000100)\r
+#define DCMI_CR_FCRC_1                       ((uint32_t)0x00000200)\r
+#define DCMI_CR_EDM_0                        ((uint32_t)0x00000400)\r
+#define DCMI_CR_EDM_1                        ((uint32_t)0x00000800)\r
+#define DCMI_CR_CRE                          ((uint32_t)0x00001000)\r
+#define DCMI_CR_ENABLE                       ((uint32_t)0x00004000)\r
+\r
+/********************  Bits definition for DCMI_SR register  ******************/\r
+#define DCMI_SR_HSYNC                        ((uint32_t)0x00000001)\r
+#define DCMI_SR_VSYNC                        ((uint32_t)0x00000002)\r
+#define DCMI_SR_FNE                          ((uint32_t)0x00000004)\r
+\r
+/********************  Bits definition for DCMI_RISR register  ****************/\r
+#define DCMI_RISR_FRAME_RIS                  ((uint32_t)0x00000001)\r
+#define DCMI_RISR_OVF_RIS                    ((uint32_t)0x00000002)\r
+#define DCMI_RISR_ERR_RIS                    ((uint32_t)0x00000004)\r
+#define DCMI_RISR_VSYNC_RIS                  ((uint32_t)0x00000008)\r
+#define DCMI_RISR_LINE_RIS                   ((uint32_t)0x00000010)\r
+\r
+/********************  Bits definition for DCMI_IER register  *****************/\r
+#define DCMI_IER_FRAME_IE                    ((uint32_t)0x00000001)\r
+#define DCMI_IER_OVF_IE                      ((uint32_t)0x00000002)\r
+#define DCMI_IER_ERR_IE                      ((uint32_t)0x00000004)\r
+#define DCMI_IER_VSYNC_IE                    ((uint32_t)0x00000008)\r
+#define DCMI_IER_LINE_IE                     ((uint32_t)0x00000010)\r
+\r
+/********************  Bits definition for DCMI_MISR register  ****************/\r
+#define DCMI_MISR_FRAME_MIS                  ((uint32_t)0x00000001)\r
+#define DCMI_MISR_OVF_MIS                    ((uint32_t)0x00000002)\r
+#define DCMI_MISR_ERR_MIS                    ((uint32_t)0x00000004)\r
+#define DCMI_MISR_VSYNC_MIS                  ((uint32_t)0x00000008)\r
+#define DCMI_MISR_LINE_MIS                   ((uint32_t)0x00000010)\r
+\r
+/********************  Bits definition for DCMI_ICR register  *****************/\r
+#define DCMI_ICR_FRAME_ISC                   ((uint32_t)0x00000001)\r
+#define DCMI_ICR_OVF_ISC                     ((uint32_t)0x00000002)\r
+#define DCMI_ICR_ERR_ISC                     ((uint32_t)0x00000004)\r
+#define DCMI_ICR_VSYNC_ISC                   ((uint32_t)0x00000008)\r
+#define DCMI_ICR_LINE_ISC                    ((uint32_t)0x00000010)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             DMA Controller                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for DMA_SxCR register  *****************/ \r
+#define DMA_SxCR_CHSEL                       ((uint32_t)0x0E000000)\r
+#define DMA_SxCR_CHSEL_0                     ((uint32_t)0x02000000)\r
+#define DMA_SxCR_CHSEL_1                     ((uint32_t)0x04000000)\r
+#define DMA_SxCR_CHSEL_2                     ((uint32_t)0x08000000) \r
+#define DMA_SxCR_MBURST                      ((uint32_t)0x01800000)\r
+#define DMA_SxCR_MBURST_0                    ((uint32_t)0x00800000)\r
+#define DMA_SxCR_MBURST_1                    ((uint32_t)0x01000000)\r
+#define DMA_SxCR_PBURST                      ((uint32_t)0x00600000)\r
+#define DMA_SxCR_PBURST_0                    ((uint32_t)0x00200000)\r
+#define DMA_SxCR_PBURST_1                    ((uint32_t)0x00400000)\r
+#define DMA_SxCR_ACK                         ((uint32_t)0x00100000)\r
+#define DMA_SxCR_CT                          ((uint32_t)0x00080000)  \r
+#define DMA_SxCR_DBM                         ((uint32_t)0x00040000)\r
+#define DMA_SxCR_PL                          ((uint32_t)0x00030000)\r
+#define DMA_SxCR_PL_0                        ((uint32_t)0x00010000)\r
+#define DMA_SxCR_PL_1                        ((uint32_t)0x00020000)\r
+#define DMA_SxCR_PINCOS                      ((uint32_t)0x00008000)\r
+#define DMA_SxCR_MSIZE                       ((uint32_t)0x00006000)\r
+#define DMA_SxCR_MSIZE_0                     ((uint32_t)0x00002000)\r
+#define DMA_SxCR_MSIZE_1                     ((uint32_t)0x00004000)\r
+#define DMA_SxCR_PSIZE                       ((uint32_t)0x00001800)\r
+#define DMA_SxCR_PSIZE_0                     ((uint32_t)0x00000800)\r
+#define DMA_SxCR_PSIZE_1                     ((uint32_t)0x00001000)\r
+#define DMA_SxCR_MINC                        ((uint32_t)0x00000400)\r
+#define DMA_SxCR_PINC                        ((uint32_t)0x00000200)\r
+#define DMA_SxCR_CIRC                        ((uint32_t)0x00000100)\r
+#define DMA_SxCR_DIR                         ((uint32_t)0x000000C0)\r
+#define DMA_SxCR_DIR_0                       ((uint32_t)0x00000040)\r
+#define DMA_SxCR_DIR_1                       ((uint32_t)0x00000080)\r
+#define DMA_SxCR_PFCTRL                      ((uint32_t)0x00000020)\r
+#define DMA_SxCR_TCIE                        ((uint32_t)0x00000010)\r
+#define DMA_SxCR_HTIE                        ((uint32_t)0x00000008)\r
+#define DMA_SxCR_TEIE                        ((uint32_t)0x00000004)\r
+#define DMA_SxCR_DMEIE                       ((uint32_t)0x00000002)\r
+#define DMA_SxCR_EN                          ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for DMA_SxCNDTR register  **************/\r
+#define DMA_SxNDT                            ((uint32_t)0x0000FFFF)\r
+#define DMA_SxNDT_0                          ((uint32_t)0x00000001)\r
+#define DMA_SxNDT_1                          ((uint32_t)0x00000002)\r
+#define DMA_SxNDT_2                          ((uint32_t)0x00000004)\r
+#define DMA_SxNDT_3                          ((uint32_t)0x00000008)\r
+#define DMA_SxNDT_4                          ((uint32_t)0x00000010)\r
+#define DMA_SxNDT_5                          ((uint32_t)0x00000020)\r
+#define DMA_SxNDT_6                          ((uint32_t)0x00000040)\r
+#define DMA_SxNDT_7                          ((uint32_t)0x00000080)\r
+#define DMA_SxNDT_8                          ((uint32_t)0x00000100)\r
+#define DMA_SxNDT_9                          ((uint32_t)0x00000200)\r
+#define DMA_SxNDT_10                         ((uint32_t)0x00000400)\r
+#define DMA_SxNDT_11                         ((uint32_t)0x00000800)\r
+#define DMA_SxNDT_12                         ((uint32_t)0x00001000)\r
+#define DMA_SxNDT_13                         ((uint32_t)0x00002000)\r
+#define DMA_SxNDT_14                         ((uint32_t)0x00004000)\r
+#define DMA_SxNDT_15                         ((uint32_t)0x00008000)\r
+\r
+/********************  Bits definition for DMA_SxFCR register  ****************/ \r
+#define DMA_SxFCR_FEIE                       ((uint32_t)0x00000080)\r
+#define DMA_SxFCR_FS                         ((uint32_t)0x00000038)\r
+#define DMA_SxFCR_FS_0                       ((uint32_t)0x00000008)\r
+#define DMA_SxFCR_FS_1                       ((uint32_t)0x00000010)\r
+#define DMA_SxFCR_FS_2                       ((uint32_t)0x00000020)\r
+#define DMA_SxFCR_DMDIS                      ((uint32_t)0x00000004)\r
+#define DMA_SxFCR_FTH                        ((uint32_t)0x00000003)\r
+#define DMA_SxFCR_FTH_0                      ((uint32_t)0x00000001)\r
+#define DMA_SxFCR_FTH_1                      ((uint32_t)0x00000002)\r
+\r
+/********************  Bits definition for DMA_LISR register  *****************/ \r
+#define DMA_LISR_TCIF3                       ((uint32_t)0x08000000)\r
+#define DMA_LISR_HTIF3                       ((uint32_t)0x04000000)\r
+#define DMA_LISR_TEIF3                       ((uint32_t)0x02000000)\r
+#define DMA_LISR_DMEIF3                      ((uint32_t)0x01000000)\r
+#define DMA_LISR_FEIF3                       ((uint32_t)0x00400000)\r
+#define DMA_LISR_TCIF2                       ((uint32_t)0x00200000)\r
+#define DMA_LISR_HTIF2                       ((uint32_t)0x00100000)\r
+#define DMA_LISR_TEIF2                       ((uint32_t)0x00080000)\r
+#define DMA_LISR_DMEIF2                      ((uint32_t)0x00040000)\r
+#define DMA_LISR_FEIF2                       ((uint32_t)0x00010000)\r
+#define DMA_LISR_TCIF1                       ((uint32_t)0x00000800)\r
+#define DMA_LISR_HTIF1                       ((uint32_t)0x00000400)\r
+#define DMA_LISR_TEIF1                       ((uint32_t)0x00000200)\r
+#define DMA_LISR_DMEIF1                      ((uint32_t)0x00000100)\r
+#define DMA_LISR_FEIF1                       ((uint32_t)0x00000040)\r
+#define DMA_LISR_TCIF0                       ((uint32_t)0x00000020)\r
+#define DMA_LISR_HTIF0                       ((uint32_t)0x00000010)\r
+#define DMA_LISR_TEIF0                       ((uint32_t)0x00000008)\r
+#define DMA_LISR_DMEIF0                      ((uint32_t)0x00000004)\r
+#define DMA_LISR_FEIF0                       ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for DMA_HISR register  *****************/ \r
+#define DMA_HISR_TCIF7                       ((uint32_t)0x08000000)\r
+#define DMA_HISR_HTIF7                       ((uint32_t)0x04000000)\r
+#define DMA_HISR_TEIF7                       ((uint32_t)0x02000000)\r
+#define DMA_HISR_DMEIF7                      ((uint32_t)0x01000000)\r
+#define DMA_HISR_FEIF7                       ((uint32_t)0x00400000)\r
+#define DMA_HISR_TCIF6                       ((uint32_t)0x00200000)\r
+#define DMA_HISR_HTIF6                       ((uint32_t)0x00100000)\r
+#define DMA_HISR_TEIF6                       ((uint32_t)0x00080000)\r
+#define DMA_HISR_DMEIF6                      ((uint32_t)0x00040000)\r
+#define DMA_HISR_FEIF6                       ((uint32_t)0x00010000)\r
+#define DMA_HISR_TCIF5                       ((uint32_t)0x00000800)\r
+#define DMA_HISR_HTIF5                       ((uint32_t)0x00000400)\r
+#define DMA_HISR_TEIF5                       ((uint32_t)0x00000200)\r
+#define DMA_HISR_DMEIF5                      ((uint32_t)0x00000100)\r
+#define DMA_HISR_FEIF5                       ((uint32_t)0x00000040)\r
+#define DMA_HISR_TCIF4                       ((uint32_t)0x00000020)\r
+#define DMA_HISR_HTIF4                       ((uint32_t)0x00000010)\r
+#define DMA_HISR_TEIF4                       ((uint32_t)0x00000008)\r
+#define DMA_HISR_DMEIF4                      ((uint32_t)0x00000004)\r
+#define DMA_HISR_FEIF4                       ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for DMA_LIFCR register  ****************/ \r
+#define DMA_LIFCR_CTCIF3                     ((uint32_t)0x08000000)\r
+#define DMA_LIFCR_CHTIF3                     ((uint32_t)0x04000000)\r
+#define DMA_LIFCR_CTEIF3                     ((uint32_t)0x02000000)\r
+#define DMA_LIFCR_CDMEIF3                    ((uint32_t)0x01000000)\r
+#define DMA_LIFCR_CFEIF3                     ((uint32_t)0x00400000)\r
+#define DMA_LIFCR_CTCIF2                     ((uint32_t)0x00200000)\r
+#define DMA_LIFCR_CHTIF2                     ((uint32_t)0x00100000)\r
+#define DMA_LIFCR_CTEIF2                     ((uint32_t)0x00080000)\r
+#define DMA_LIFCR_CDMEIF2                    ((uint32_t)0x00040000)\r
+#define DMA_LIFCR_CFEIF2                     ((uint32_t)0x00010000)\r
+#define DMA_LIFCR_CTCIF1                     ((uint32_t)0x00000800)\r
+#define DMA_LIFCR_CHTIF1                     ((uint32_t)0x00000400)\r
+#define DMA_LIFCR_CTEIF1                     ((uint32_t)0x00000200)\r
+#define DMA_LIFCR_CDMEIF1                    ((uint32_t)0x00000100)\r
+#define DMA_LIFCR_CFEIF1                     ((uint32_t)0x00000040)\r
+#define DMA_LIFCR_CTCIF0                     ((uint32_t)0x00000020)\r
+#define DMA_LIFCR_CHTIF0                     ((uint32_t)0x00000010)\r
+#define DMA_LIFCR_CTEIF0                     ((uint32_t)0x00000008)\r
+#define DMA_LIFCR_CDMEIF0                    ((uint32_t)0x00000004)\r
+#define DMA_LIFCR_CFEIF0                     ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for DMA_HIFCR  register  ****************/ \r
+#define DMA_HIFCR_CTCIF7                     ((uint32_t)0x08000000)\r
+#define DMA_HIFCR_CHTIF7                     ((uint32_t)0x04000000)\r
+#define DMA_HIFCR_CTEIF7                     ((uint32_t)0x02000000)\r
+#define DMA_HIFCR_CDMEIF7                    ((uint32_t)0x01000000)\r
+#define DMA_HIFCR_CFEIF7                     ((uint32_t)0x00400000)\r
+#define DMA_HIFCR_CTCIF6                     ((uint32_t)0x00200000)\r
+#define DMA_HIFCR_CHTIF6                     ((uint32_t)0x00100000)\r
+#define DMA_HIFCR_CTEIF6                     ((uint32_t)0x00080000)\r
+#define DMA_HIFCR_CDMEIF6                    ((uint32_t)0x00040000)\r
+#define DMA_HIFCR_CFEIF6                     ((uint32_t)0x00010000)\r
+#define DMA_HIFCR_CTCIF5                     ((uint32_t)0x00000800)\r
+#define DMA_HIFCR_CHTIF5                     ((uint32_t)0x00000400)\r
+#define DMA_HIFCR_CTEIF5                     ((uint32_t)0x00000200)\r
+#define DMA_HIFCR_CDMEIF5                    ((uint32_t)0x00000100)\r
+#define DMA_HIFCR_CFEIF5                     ((uint32_t)0x00000040)\r
+#define DMA_HIFCR_CTCIF4                     ((uint32_t)0x00000020)\r
+#define DMA_HIFCR_CHTIF4                     ((uint32_t)0x00000010)\r
+#define DMA_HIFCR_CTEIF4                     ((uint32_t)0x00000008)\r
+#define DMA_HIFCR_CDMEIF4                    ((uint32_t)0x00000004)\r
+#define DMA_HIFCR_CFEIF4                     ((uint32_t)0x00000001)\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         AHB Master DMA2D Controller (DMA2D)                */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for DMA2D_CR register  ******************/\r
+\r
+#define DMA2D_CR_START                     ((uint32_t)0x00000001)               /*!< Start transfer */\r
+#define DMA2D_CR_SUSP                      ((uint32_t)0x00000002)               /*!< Suspend transfer */\r
+#define DMA2D_CR_ABORT                     ((uint32_t)0x00000004)               /*!< Abort transfer */\r
+#define DMA2D_CR_TEIE                      ((uint32_t)0x00000100)               /*!< Transfer Error Interrupt Enable */\r
+#define DMA2D_CR_TCIE                      ((uint32_t)0x00000200)               /*!< Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_TWIE                      ((uint32_t)0x00000400)               /*!< Transfer Watermark Interrupt Enable */\r
+#define DMA2D_CR_CAEIE                     ((uint32_t)0x00000800)               /*!< CLUT Access Error Interrupt Enable */\r
+#define DMA2D_CR_CTCIE                     ((uint32_t)0x00001000)               /*!< CLUT Transfer Complete Interrupt Enable */\r
+#define DMA2D_CR_CEIE                      ((uint32_t)0x00002000)               /*!< Configuration Error Interrupt Enable */\r
+#define DMA2D_CR_MODE                      ((uint32_t)0x00030000)               /*!< DMA2D Mode */\r
+\r
+/********************  Bit definition for DMA2D_ISR register  *****************/\r
+\r
+#define DMA2D_ISR_TEIF                     ((uint32_t)0x00000001)               /*!< Transfer Error Interrupt Flag */\r
+#define DMA2D_ISR_TCIF                     ((uint32_t)0x00000002)               /*!< Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_TWIF                     ((uint32_t)0x00000004)               /*!< Transfer Watermark Interrupt Flag */\r
+#define DMA2D_ISR_CAEIF                    ((uint32_t)0x00000008)               /*!< CLUT Access Error Interrupt Flag */\r
+#define DMA2D_ISR_CTCIF                    ((uint32_t)0x00000010)               /*!< CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_ISR_CEIF                     ((uint32_t)0x00000020)               /*!< Configuration Error Interrupt Flag */\r
+\r
+/********************  Bit definition for DMA2D_IFSR register  ****************/\r
+\r
+#define DMA2D_IFSR_CTEIF                   ((uint32_t)0x00000001)               /*!< Clears Transfer Error Interrupt Flag */\r
+#define DMA2D_IFSR_CTCIF                   ((uint32_t)0x00000002)               /*!< Clears Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CTWIF                   ((uint32_t)0x00000004)               /*!< Clears Transfer Watermark Interrupt Flag */\r
+#define DMA2D_IFSR_CCAEIF                  ((uint32_t)0x00000008)               /*!< Clears CLUT Access Error Interrupt Flag */\r
+#define DMA2D_IFSR_CCTCIF                  ((uint32_t)0x00000010)               /*!< Clears CLUT Transfer Complete Interrupt Flag */\r
+#define DMA2D_IFSR_CCEIF                   ((uint32_t)0x00000020)               /*!< Clears Configuration Error Interrupt Flag */\r
+\r
+/********************  Bit definition for DMA2D_FGMAR register  ***************/\r
+\r
+#define DMA2D_FGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */\r
+\r
+/********************  Bit definition for DMA2D_FGOR register  ****************/\r
+\r
+#define DMA2D_FGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */\r
+\r
+/********************  Bit definition for DMA2D_BGMAR register  ***************/\r
+\r
+#define DMA2D_BGMAR_MA                     ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */\r
+\r
+/********************  Bit definition for DMA2D_BGOR register  ****************/\r
+\r
+#define DMA2D_BGOR_LO                      ((uint32_t)0x00003FFF)               /*!< Line Offset */\r
+\r
+/********************  Bit definition for DMA2D_FGPFCCR register  *************/\r
+\r
+#define DMA2D_FGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */\r
+#define DMA2D_FGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */\r
+#define DMA2D_FGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */\r
+#define DMA2D_FGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */\r
+#define DMA2D_FGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha mode */\r
+#define DMA2D_FGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */\r
+\r
+/********************  Bit definition for DMA2D_FGCOLR register  **************/\r
+\r
+#define DMA2D_FGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */\r
+#define DMA2D_FGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */\r
+#define DMA2D_FGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */   \r
+\r
+/********************  Bit definition for DMA2D_BGPFCCR register  *************/\r
+\r
+#define DMA2D_BGPFCCR_CM                   ((uint32_t)0x0000000F)               /*!< Color mode */\r
+#define DMA2D_BGPFCCR_CCM                  ((uint32_t)0x00000010)               /*!< CLUT Color mode */\r
+#define DMA2D_BGPFCCR_START                ((uint32_t)0x00000020)               /*!< Start */\r
+#define DMA2D_BGPFCCR_CS                   ((uint32_t)0x0000FF00)               /*!< CLUT size */\r
+#define DMA2D_BGPFCCR_AM                   ((uint32_t)0x00030000)               /*!< Alpha Mode */\r
+#define DMA2D_BGPFCCR_ALPHA                ((uint32_t)0xFF000000)               /*!< Alpha value */\r
+\r
+/********************  Bit definition for DMA2D_BGCOLR register  **************/\r
+\r
+#define DMA2D_BGCOLR_BLUE                  ((uint32_t)0x000000FF)               /*!< Blue Value */\r
+#define DMA2D_BGCOLR_GREEN                 ((uint32_t)0x0000FF00)               /*!< Green Value */\r
+#define DMA2D_BGCOLR_RED                   ((uint32_t)0x00FF0000)               /*!< Red Value */\r
+\r
+/********************  Bit definition for DMA2D_FGCMAR register  **************/\r
+\r
+#define DMA2D_FGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */\r
+\r
+/********************  Bit definition for DMA2D_BGCMAR register  **************/\r
+\r
+#define DMA2D_BGCMAR_MA                    ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */\r
+\r
+/********************  Bit definition for DMA2D_OPFCCR register  **************/\r
+\r
+#define DMA2D_OPFCCR_CM                    ((uint32_t)0x00000007)               /*!< Color mode */\r
+\r
+/********************  Bit definition for DMA2D_OCOLR register  ***************/\r
+\r
+/*!<Mode_ARGB8888/RGB888 */\r
+\r
+#define DMA2D_OCOLR_BLUE_1                 ((uint32_t)0x000000FF)               /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_1                ((uint32_t)0x0000FF00)               /*!< GREEN Value  */\r
+#define DMA2D_OCOLR_RED_1                  ((uint32_t)0x00FF0000)               /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_1                ((uint32_t)0xFF000000)               /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_RGB565 */\r
+#define DMA2D_OCOLR_BLUE_2                 ((uint32_t)0x0000001F)               /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_2                ((uint32_t)0x000007E0)               /*!< GREEN Value  */\r
+#define DMA2D_OCOLR_RED_2                  ((uint32_t)0x0000F800)               /*!< Red Value */\r
+\r
+/*!<Mode_ARGB1555 */\r
+#define DMA2D_OCOLR_BLUE_3                 ((uint32_t)0x0000001F)               /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_3                ((uint32_t)0x000003E0)               /*!< GREEN Value  */\r
+#define DMA2D_OCOLR_RED_3                  ((uint32_t)0x00007C00)               /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_3                ((uint32_t)0x00008000)               /*!< Alpha Channel Value */\r
+\r
+/*!<Mode_ARGB4444 */\r
+#define DMA2D_OCOLR_BLUE_4                 ((uint32_t)0x0000000F)               /*!< BLUE Value */\r
+#define DMA2D_OCOLR_GREEN_4                ((uint32_t)0x000000F0)               /*!< GREEN Value  */\r
+#define DMA2D_OCOLR_RED_4                  ((uint32_t)0x00000F00)               /*!< Red Value */\r
+#define DMA2D_OCOLR_ALPHA_4                ((uint32_t)0x0000F000)               /*!< Alpha Channel Value */\r
+\r
+/********************  Bit definition for DMA2D_OMAR register  ****************/\r
+\r
+#define DMA2D_OMAR_MA                      ((uint32_t)0xFFFFFFFF)               /*!< Memory Address */\r
+\r
+/********************  Bit definition for DMA2D_OOR register  *****************/\r
+\r
+#define DMA2D_OOR_LO                       ((uint32_t)0x00003FFF)               /*!< Line Offset */\r
+\r
+/********************  Bit definition for DMA2D_NLR register  *****************/\r
+\r
+#define DMA2D_NLR_NL                       ((uint32_t)0x0000FFFF)               /*!< Number of Lines */\r
+#define DMA2D_NLR_PL                       ((uint32_t)0x3FFF0000)               /*!< Pixel per Lines */\r
+\r
+/********************  Bit definition for DMA2D_LWR register  *****************/\r
+\r
+#define DMA2D_LWR_LW                       ((uint32_t)0x0000FFFF)               /*!< Line Watermark */\r
+\r
+/********************  Bit definition for DMA2D_AMTCR register  ***************/\r
+\r
+#define DMA2D_AMTCR_EN                     ((uint32_t)0x00000001)               /*!< Enable */\r
+#define DMA2D_AMTCR_DT                     ((uint32_t)0x0000FF00)               /*!< Dead Time */\r
+\r
+\r
+\r
+/********************  Bit definition for DMA2D_FGCLUT register  **************/\r
+                                                                     \r
+/********************  Bit definition for DMA2D_BGCLUT register  **************/\r
+#endif /* STM32F429X */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                    External Interrupt/Event Controller                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for EXTI_IMR register  *******************/\r
+#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */\r
+#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */\r
+#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */\r
+#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */\r
+#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */\r
+#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */\r
+#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */\r
+#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */\r
+#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */\r
+#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */\r
+#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */\r
+#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */\r
+#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */\r
+#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */\r
+#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */\r
+#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */\r
+#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */\r
+#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */\r
+#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */\r
+#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */\r
+\r
+/*******************  Bit definition for EXTI_EMR register  *******************/\r
+#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */\r
+#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */\r
+#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */\r
+#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */\r
+#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */\r
+#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */\r
+#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */\r
+#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */\r
+#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */\r
+#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */\r
+#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */\r
+#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */\r
+#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */\r
+#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */\r
+#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */\r
+#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */\r
+#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */\r
+#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */\r
+#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */\r
+#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */\r
+\r
+/******************  Bit definition for EXTI_RTSR register  *******************/\r
+#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */\r
+#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */\r
+#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */\r
+#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */\r
+#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */\r
+#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */\r
+#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */\r
+#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */\r
+#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */\r
+#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */\r
+#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */\r
+#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */\r
+#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */\r
+#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */\r
+#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */\r
+#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */\r
+#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */\r
+#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */\r
+#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */\r
+#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */\r
+\r
+/******************  Bit definition for EXTI_FTSR register  *******************/\r
+#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */\r
+#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */\r
+#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */\r
+#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */\r
+#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */\r
+#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */\r
+#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */\r
+#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */\r
+#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */\r
+#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */\r
+#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */\r
+#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */\r
+#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */\r
+#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */\r
+#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */\r
+#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */\r
+#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */\r
+#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */\r
+#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */\r
+#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */\r
+\r
+/******************  Bit definition for EXTI_SWIER register  ******************/\r
+#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */\r
+#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */\r
+#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */\r
+#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */\r
+#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */\r
+#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */\r
+#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */\r
+#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */\r
+#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */\r
+#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */\r
+#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */\r
+#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */\r
+#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */\r
+#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */\r
+#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */\r
+#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */\r
+#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */\r
+#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */\r
+#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */\r
+#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */\r
+\r
+/*******************  Bit definition for EXTI_PR register  ********************/\r
+#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */\r
+#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit for line 1 */\r
+#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit for line 2 */\r
+#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit for line 3 */\r
+#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit for line 4 */\r
+#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit for line 5 */\r
+#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit for line 6 */\r
+#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit for line 7 */\r
+#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit for line 8 */\r
+#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit for line 9 */\r
+#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit for line 10 */\r
+#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit for line 11 */\r
+#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit for line 12 */\r
+#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit for line 13 */\r
+#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit for line 14 */\r
+#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit for line 15 */\r
+#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit for line 16 */\r
+#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */\r
+#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */\r
+#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    FLASH                                   */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bits definition for FLASH_ACR register  *****************/\r
+#define FLASH_ACR_LATENCY                    ((uint32_t)0x0000000F)\r
+#define FLASH_ACR_LATENCY_0WS                ((uint32_t)0x00000000)\r
+#define FLASH_ACR_LATENCY_1WS                ((uint32_t)0x00000001)\r
+#define FLASH_ACR_LATENCY_2WS                ((uint32_t)0x00000002)\r
+#define FLASH_ACR_LATENCY_3WS                ((uint32_t)0x00000003)\r
+#define FLASH_ACR_LATENCY_4WS                ((uint32_t)0x00000004)\r
+#define FLASH_ACR_LATENCY_5WS                ((uint32_t)0x00000005)\r
+#define FLASH_ACR_LATENCY_6WS                ((uint32_t)0x00000006)\r
+#define FLASH_ACR_LATENCY_7WS                ((uint32_t)0x00000007)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_ACR_LATENCY_8WS                ((uint32_t)0x00000008)\r
+#define FLASH_ACR_LATENCY_9WS                ((uint32_t)0x00000009)\r
+#define FLASH_ACR_LATENCY_10WS               ((uint32_t)0x0000000A)\r
+#define FLASH_ACR_LATENCY_11WS               ((uint32_t)0x0000000B)\r
+#define FLASH_ACR_LATENCY_12WS               ((uint32_t)0x0000000C)\r
+#define FLASH_ACR_LATENCY_13WS               ((uint32_t)0x0000000D)\r
+#define FLASH_ACR_LATENCY_14WS               ((uint32_t)0x0000000E)\r
+#define FLASH_ACR_LATENCY_15WS               ((uint32_t)0x0000000F)\r
+#endif /* STM32F429X */\r
+\r
+#define FLASH_ACR_PRFTEN                     ((uint32_t)0x00000100)\r
+#define FLASH_ACR_ICEN                       ((uint32_t)0x00000200)\r
+#define FLASH_ACR_DCEN                       ((uint32_t)0x00000400)\r
+#define FLASH_ACR_ICRST                      ((uint32_t)0x00000800)\r
+#define FLASH_ACR_DCRST                      ((uint32_t)0x00001000)\r
+#define FLASH_ACR_BYTE0_ADDRESS              ((uint32_t)0x40023C00)\r
+#define FLASH_ACR_BYTE2_ADDRESS              ((uint32_t)0x40023C03)\r
+\r
+/*******************  Bits definition for FLASH_SR register  ******************/\r
+#define FLASH_SR_EOP                         ((uint32_t)0x00000001)\r
+#define FLASH_SR_SOP                         ((uint32_t)0x00000002)\r
+#define FLASH_SR_WRPERR                      ((uint32_t)0x00000010)\r
+#define FLASH_SR_PGAERR                      ((uint32_t)0x00000020)\r
+#define FLASH_SR_PGPERR                      ((uint32_t)0x00000040)\r
+#define FLASH_SR_PGSERR                      ((uint32_t)0x00000080)\r
+#define FLASH_SR_BSY                         ((uint32_t)0x00010000)\r
+\r
+/*******************  Bits definition for FLASH_CR register  ******************/\r
+#define FLASH_CR_PG                          ((uint32_t)0x00000001)\r
+#define FLASH_CR_SER                         ((uint32_t)0x00000002)\r
+#define FLASH_CR_MER                         ((uint32_t)0x00000004)\r
+#define FLASH_CR_MER1                        FLASH_CR_MER\r
+#define FLASH_CR_SNB                         ((uint32_t)0x000000F8)\r
+#define FLASH_CR_SNB_0                       ((uint32_t)0x00000008)\r
+#define FLASH_CR_SNB_1                       ((uint32_t)0x00000010)\r
+#define FLASH_CR_SNB_2                       ((uint32_t)0x00000020)\r
+#define FLASH_CR_SNB_3                       ((uint32_t)0x00000040)\r
+#define FLASH_CR_SNB_4                       ((uint32_t)0x00000040)\r
+#define FLASH_CR_PSIZE                       ((uint32_t)0x00000300)\r
+#define FLASH_CR_PSIZE_0                     ((uint32_t)0x00000100)\r
+#define FLASH_CR_PSIZE_1                     ((uint32_t)0x00000200)\r
+#define FLASH_CR_MER2                        ((uint32_t)0x00008000)\r
+#define FLASH_CR_STRT                        ((uint32_t)0x00010000)\r
+#define FLASH_CR_EOPIE                       ((uint32_t)0x01000000)\r
+#define FLASH_CR_LOCK                        ((uint32_t)0x80000000)\r
+\r
+/*******************  Bits definition for FLASH_OPTCR register  ***************/\r
+#define FLASH_OPTCR_OPTLOCK                 ((uint32_t)0x00000001)\r
+#define FLASH_OPTCR_OPTSTRT                 ((uint32_t)0x00000002)\r
+#define FLASH_OPTCR_BOR_LEV_0               ((uint32_t)0x00000004)\r
+#define FLASH_OPTCR_BOR_LEV_1               ((uint32_t)0x00000008)\r
+#define FLASH_OPTCR_BOR_LEV                 ((uint32_t)0x0000000C)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_OPTCR_BFB2                    ((uint32_t)0x00000010)\r
+#endif /* STM32F429X */\r
+\r
+#define FLASH_OPTCR_WDG_SW                  ((uint32_t)0x00000020)\r
+#define FLASH_OPTCR_nRST_STOP               ((uint32_t)0x00000040)\r
+#define FLASH_OPTCR_nRST_STDBY              ((uint32_t)0x00000080)\r
+#define FLASH_OPTCR_RDP                     ((uint32_t)0x0000FF00)\r
+#define FLASH_OPTCR_RDP_0                   ((uint32_t)0x00000100)\r
+#define FLASH_OPTCR_RDP_1                   ((uint32_t)0x00000200)\r
+#define FLASH_OPTCR_RDP_2                   ((uint32_t)0x00000400)\r
+#define FLASH_OPTCR_RDP_3                   ((uint32_t)0x00000800)\r
+#define FLASH_OPTCR_RDP_4                   ((uint32_t)0x00001000)\r
+#define FLASH_OPTCR_RDP_5                   ((uint32_t)0x00002000)\r
+#define FLASH_OPTCR_RDP_6                   ((uint32_t)0x00004000)\r
+#define FLASH_OPTCR_RDP_7                   ((uint32_t)0x00008000)\r
+#define FLASH_OPTCR_nWRP                    ((uint32_t)0x0FFF0000)\r
+#define FLASH_OPTCR_nWRP_0                  ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR_nWRP_1                  ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR_nWRP_2                  ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR_nWRP_3                  ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR_nWRP_4                  ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR_nWRP_5                  ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR_nWRP_6                  ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR_nWRP_7                  ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR_nWRP_8                  ((uint32_t)0x01000000)\r
+#define FLASH_OPTCR_nWRP_9                  ((uint32_t)0x02000000)\r
+#define FLASH_OPTCR_nWRP_10                 ((uint32_t)0x04000000)\r
+#define FLASH_OPTCR_nWRP_11                 ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F429X)\r
+#define FLASH_OPTCR_DB1M                    ((uint32_t)0x40000000) \r
+#define FLASH_OPTCR_SPRMOD                  ((uint32_t)0x80000000) \r
+#endif /* STM32F429X */\r
+                                             \r
+/******************  Bits definition for FLASH_OPTCR1 register  ***************/\r
+#define FLASH_OPTCR1_nWRP                    ((uint32_t)0x0FFF0000)\r
+#define FLASH_OPTCR1_nWRP_0                  ((uint32_t)0x00010000)\r
+#define FLASH_OPTCR1_nWRP_1                  ((uint32_t)0x00020000)\r
+#define FLASH_OPTCR1_nWRP_2                  ((uint32_t)0x00040000)\r
+#define FLASH_OPTCR1_nWRP_3                  ((uint32_t)0x00080000)\r
+#define FLASH_OPTCR1_nWRP_4                  ((uint32_t)0x00100000)\r
+#define FLASH_OPTCR1_nWRP_5                  ((uint32_t)0x00200000)\r
+#define FLASH_OPTCR1_nWRP_6                  ((uint32_t)0x00400000)\r
+#define FLASH_OPTCR1_nWRP_7                  ((uint32_t)0x00800000)\r
+#define FLASH_OPTCR1_nWRP_8                  ((uint32_t)0x01000000)\r
+#define FLASH_OPTCR1_nWRP_9                  ((uint32_t)0x02000000)\r
+#define FLASH_OPTCR1_nWRP_10                 ((uint32_t)0x04000000)\r
+#define FLASH_OPTCR1_nWRP_11                 ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F40XX) || defined (STM32F427X)\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                       Flexible Static Memory Controller                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for FSMC_BCR1 register  *******************/\r
+#define  FSMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FSMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FSMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FSMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FSMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FSMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */\r
+#define  FSMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */\r
+#define  FSMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */\r
+#define  FSMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */\r
+#define  FSMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */\r
+#define  FSMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */\r
+#define  FSMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */\r
+#define  FSMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */\r
+#define  FSMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */\r
+#define  FSMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */\r
+\r
+/******************  Bit definition for FSMC_BCR2 register  *******************/\r
+#define  FSMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                */\r
+#define  FSMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FSMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FSMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FSMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FSMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */\r
+#define  FSMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */\r
+#define  FSMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */\r
+#define  FSMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */\r
+#define  FSMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */\r
+#define  FSMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */\r
+#define  FSMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */\r
+#define  FSMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */\r
+#define  FSMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */\r
+#define  FSMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */\r
+\r
+/******************  Bit definition for FSMC_BCR3 register  *******************/\r
+#define  FSMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FSMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FSMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FSMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FSMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FSMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */\r
+#define  FSMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */\r
+#define  FSMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */\r
+#define  FSMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */\r
+#define  FSMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */\r
+#define  FSMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */\r
+#define  FSMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */\r
+#define  FSMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */\r
+#define  FSMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */\r
+#define  FSMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */\r
+\r
+/******************  Bit definition for FSMC_BCR4 register  *******************/\r
+#define  FSMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit */\r
+#define  FSMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FSMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FSMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FSMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FSMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable                    */\r
+#define  FSMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit                       */\r
+#define  FSMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit               */\r
+#define  FSMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support             */\r
+#define  FSMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration              */\r
+#define  FSMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit                       */\r
+#define  FSMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit                        */\r
+#define  FSMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable                   */\r
+#define  FSMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait                      */\r
+#define  FSMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable                     */\r
+\r
+/******************  Bit definition for FSMC_BTR1 register  ******************/\r
+#define  FSMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FSMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BTR2 register  *******************/\r
+#define  FSMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FSMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for FSMC_BTR3 register  *******************/\r
+#define  FSMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FSMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BTR4 register  *******************/\r
+#define  FSMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FSMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BWTR1 register  ******************/\r
+#define  FSMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BWTR2 register  ******************/\r
+#define  FSMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/\r
+#define  FSMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BWTR3 register  ******************/\r
+#define  FSMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_BWTR4 register  ******************/\r
+#define  FSMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FSMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FSMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FSMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FSMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FSMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FSMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FSMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FSMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FSMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FSMC_PCR2 register  *******************/\r
+#define  FSMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */\r
+#define  FSMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FSMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */\r
+\r
+#define  FSMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FSMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */\r
+\r
+#define  FSMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define  FSMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FSMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FSMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FSMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define  FSMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FSMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FSMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FSMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size) */\r
+#define  FSMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FSMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FSMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FSMC_PCR3 register  *******************/\r
+#define  FSMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */\r
+#define  FSMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FSMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */\r
+\r
+#define  FSMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FSMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */\r
+\r
+#define  FSMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define  FSMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FSMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FSMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FSMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define  FSMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FSMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FSMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FSMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define  FSMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FSMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FSMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FSMC_PCR4 register  *******************/\r
+#define  FSMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit */\r
+#define  FSMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FSMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type */\r
+\r
+#define  FSMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FSMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FSMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FSMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit */\r
+\r
+#define  FSMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay) */\r
+#define  FSMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FSMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FSMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FSMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay) */\r
+#define  FSMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FSMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FSMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FSMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FSMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size) */\r
+#define  FSMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FSMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FSMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/*******************  Bit definition for FSMC_SR2 register  *******************/\r
+#define  FSMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */\r
+#define  FSMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */\r
+#define  FSMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */\r
+#define  FSMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define  FSMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */\r
+#define  FSMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */\r
+#define  FSMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */\r
+\r
+/*******************  Bit definition for FSMC_SR3 register  *******************/\r
+#define  FSMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */\r
+#define  FSMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */\r
+#define  FSMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */\r
+#define  FSMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define  FSMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */\r
+#define  FSMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */\r
+#define  FSMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */\r
+\r
+/*******************  Bit definition for FSMC_SR4 register  *******************/\r
+#define  FSMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                 */\r
+#define  FSMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                       */\r
+#define  FSMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status                */\r
+#define  FSMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit   */\r
+#define  FSMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit         */\r
+#define  FSMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit  */\r
+#define  FSMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty */\r
+\r
+/******************  Bit definition for FSMC_PMEM2 register  ******************/\r
+#define  FSMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define  FSMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define  FSMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define  FSMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define  FSMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PMEM3 register  ******************/\r
+#define  FSMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define  FSMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define  FSMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define  FSMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define  FSMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PMEM4 register  ******************/\r
+#define  FSMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define  FSMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define  FSMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define  FSMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define  FSMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PATT2 register  ******************/\r
+#define  FSMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define  FSMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define  FSMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define  FSMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define  FSMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PATT3 register  ******************/\r
+#define  FSMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define  FSMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define  FSMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define  FSMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define  FSMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PATT4 register  ******************/\r
+#define  FSMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define  FSMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define  FSMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define  FSMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define  FSMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_PIO4 register  *******************/\r
+#define  FSMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define  FSMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FSMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FSMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FSMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FSMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FSMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FSMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FSMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define  FSMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FSMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FSMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FSMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FSMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FSMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FSMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FSMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define  FSMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FSMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FSMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FSMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FSMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FSMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FSMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FSMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FSMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define  FSMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FSMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FSMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FSMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FSMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FSMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FSMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FSMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FSMC_ECCR2 register  ******************/\r
+#define  FSMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */\r
+\r
+/******************  Bit definition for FSMC_ECCR3 register  ******************/\r
+#define  FSMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          Flexible Memory Controller                        */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for FMC_BCR1 register  *******************/\r
+#define  FMC_BCR1_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FMC_BCR1_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FMC_BCR1_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FMC_BCR1_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_BCR1_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR1_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FMC_BCR1_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BCR1_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR1_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */\r
+#define  FMC_BCR1_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */\r
+#define  FMC_BCR1_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */\r
+#define  FMC_BCR1_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */\r
+#define  FMC_BCR1_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */\r
+#define  FMC_BCR1_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */\r
+#define  FMC_BCR1_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */\r
+#define  FMC_BCR1_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */\r
+#define  FMC_BCR1_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */\r
+#define  FMC_BCR1_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */\r
+#define  FMC_BCR1_CCLKEN                    ((uint32_t)0x00100000)        /*!<Continous clock enable     */\r
+\r
+/******************  Bit definition for FMC_BCR2 register  *******************/\r
+#define  FMC_BCR2_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FMC_BCR2_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FMC_BCR2_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FMC_BCR2_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_BCR2_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR2_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FMC_BCR2_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BCR2_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR2_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */\r
+#define  FMC_BCR2_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */\r
+#define  FMC_BCR2_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */\r
+#define  FMC_BCR2_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */\r
+#define  FMC_BCR2_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */\r
+#define  FMC_BCR2_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */\r
+#define  FMC_BCR2_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */\r
+#define  FMC_BCR2_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */\r
+#define  FMC_BCR2_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */\r
+#define  FMC_BCR2_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */\r
+\r
+/******************  Bit definition for FMC_BCR3 register  *******************/\r
+#define  FMC_BCR3_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FMC_BCR3_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FMC_BCR3_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FMC_BCR3_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_BCR3_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR3_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FMC_BCR3_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BCR3_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR3_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */\r
+#define  FMC_BCR3_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */\r
+#define  FMC_BCR3_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */\r
+#define  FMC_BCR3_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */\r
+#define  FMC_BCR3_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */\r
+#define  FMC_BCR3_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */\r
+#define  FMC_BCR3_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */\r
+#define  FMC_BCR3_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */\r
+#define  FMC_BCR3_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */\r
+#define  FMC_BCR3_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */\r
+\r
+/******************  Bit definition for FMC_BCR4 register  *******************/\r
+#define  FMC_BCR4_MBKEN                     ((uint32_t)0x00000001)        /*!<Memory bank enable bit                 */\r
+#define  FMC_BCR4_MUXEN                     ((uint32_t)0x00000002)        /*!<Address/data multiplexing enable bit   */\r
+\r
+#define  FMC_BCR4_MTYP                      ((uint32_t)0x0000000C)        /*!<MTYP[1:0] bits (Memory type)           */\r
+#define  FMC_BCR4_MTYP_0                    ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_BCR4_MTYP_1                    ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR4_MWID                      ((uint32_t)0x00000030)        /*!<MWID[1:0] bits (Memory data bus width) */\r
+#define  FMC_BCR4_MWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BCR4_MWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_BCR4_FACCEN                    ((uint32_t)0x00000040)        /*!<Flash access enable        */\r
+#define  FMC_BCR4_BURSTEN                   ((uint32_t)0x00000100)        /*!<Burst enable bit           */\r
+#define  FMC_BCR4_WAITPOL                   ((uint32_t)0x00000200)        /*!<Wait signal polarity bit   */\r
+#define  FMC_BCR4_WRAPMOD                   ((uint32_t)0x00000400)        /*!<Wrapped burst mode support */\r
+#define  FMC_BCR4_WAITCFG                   ((uint32_t)0x00000800)        /*!<Wait timing configuration  */\r
+#define  FMC_BCR4_WREN                      ((uint32_t)0x00001000)        /*!<Write enable bit           */\r
+#define  FMC_BCR4_WAITEN                    ((uint32_t)0x00002000)        /*!<Wait enable bit            */\r
+#define  FMC_BCR4_EXTMOD                    ((uint32_t)0x00004000)        /*!<Extended mode enable       */\r
+#define  FMC_BCR4_ASYNCWAIT                 ((uint32_t)0x00008000)        /*!<Asynchronous wait          */\r
+#define  FMC_BCR4_CBURSTRW                  ((uint32_t)0x00080000)        /*!<Write burst enable         */\r
+\r
+/******************  Bit definition for FMC_BTR1 register  ******************/\r
+#define  FMC_BTR1_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BTR1_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BTR1_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BTR1_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BTR1_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR1_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */\r
+#define  FMC_BTR1_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BTR1_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BTR1_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BTR1_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR1_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BTR1_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BTR1_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BTR1_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BTR1_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BTR1_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BTR1_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BTR1_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BTR1_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BTR1_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FMC_BTR1_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_BTR1_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_BTR1_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_BTR1_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR1_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BTR1_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BTR1_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BTR1_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BTR1_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR1_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BTR1_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BTR1_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BTR1_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BTR1_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR1_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BTR1_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BTR1_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BTR2 register  *******************/\r
+#define  FMC_BTR2_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BTR2_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BTR2_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BTR2_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BTR2_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR2_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BTR2_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BTR2_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BTR2_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BTR2_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR2_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BTR2_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BTR2_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BTR2_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BTR2_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BTR2_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BTR2_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BTR2_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BTR2_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BTR2_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FMC_BTR2_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_BTR2_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_BTR2_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_BTR2_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR2_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BTR2_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BTR2_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BTR2_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BTR2_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR2_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BTR2_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BTR2_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BTR2_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BTR2_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR2_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BTR2_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BTR2_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for FMC_BTR3 register  *******************/\r
+#define  FMC_BTR3_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BTR3_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BTR3_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BTR3_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BTR3_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR3_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BTR3_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BTR3_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BTR3_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BTR3_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR3_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BTR3_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BTR3_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BTR3_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BTR3_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BTR3_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BTR3_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BTR3_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BTR3_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BTR3_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FMC_BTR3_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_BTR3_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_BTR3_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_BTR3_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR3_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BTR3_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BTR3_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BTR3_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BTR3_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR3_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BTR3_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BTR3_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BTR3_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BTR3_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR3_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BTR3_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BTR3_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BTR4 register  *******************/\r
+#define  FMC_BTR4_ADDSET                    ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BTR4_ADDSET_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BTR4_ADDSET_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BTR4_ADDSET_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BTR4_ADDSET_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR4_ADDHLD                    ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BTR4_ADDHLD_0                  ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BTR4_ADDHLD_1                  ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BTR4_ADDHLD_2                  ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BTR4_ADDHLD_3                  ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR4_DATAST                    ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BTR4_DATAST_0                  ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BTR4_DATAST_1                  ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BTR4_DATAST_2                  ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BTR4_DATAST_3                  ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BTR4_DATAST_4                  ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BTR4_DATAST_5                  ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BTR4_DATAST_6                  ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BTR4_DATAST_7                  ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BTR4_BUSTURN                   ((uint32_t)0x000F0000)        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */\r
+#define  FMC_BTR4_BUSTURN_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_BTR4_BUSTURN_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_BTR4_BUSTURN_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_BTR4_BUSTURN_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR4_CLKDIV                    ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BTR4_CLKDIV_0                  ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BTR4_CLKDIV_1                  ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BTR4_CLKDIV_2                  ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BTR4_CLKDIV_3                  ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR4_DATLAT                    ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BTR4_DATLAT_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BTR4_DATLAT_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BTR4_DATLAT_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BTR4_DATLAT_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BTR4_ACCMOD                    ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BTR4_ACCMOD_0                  ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BTR4_ACCMOD_1                  ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BWTR1 register  ******************/\r
+#define  FMC_BWTR1_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BWTR1_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BWTR1_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BWTR1_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR1_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BWTR1_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BWTR1_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BWTR1_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR1_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BWTR1_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BWTR1_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BWTR1_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BWTR1_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BWTR1_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BWTR1_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BWTR1_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BWTR1_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BWTR1_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BWTR1_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BWTR1_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR1_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BWTR1_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BWTR1_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BWTR1_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR1_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BWTR1_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR1_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BWTR2 register  ******************/\r
+#define  FMC_BWTR2_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BWTR2_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BWTR2_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BWTR2_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR2_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BWTR2_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BWTR2_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BWTR2_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR2_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BWTR2_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BWTR2_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BWTR2_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BWTR2_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BWTR2_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BWTR2_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BWTR2_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BWTR2_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BWTR2_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1*/\r
+#define  FMC_BWTR2_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BWTR2_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR2_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BWTR2_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BWTR2_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BWTR2_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR2_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BWTR2_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR2_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BWTR3 register  ******************/\r
+#define  FMC_BWTR3_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BWTR3_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BWTR3_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BWTR3_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR3_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BWTR3_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BWTR3_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BWTR3_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR3_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BWTR3_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BWTR3_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BWTR3_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BWTR3_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BWTR3_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BWTR3_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BWTR3_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BWTR3_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BWTR3_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BWTR3_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BWTR3_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR3_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BWTR3_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BWTR3_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BWTR3_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR3_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BWTR3_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR3_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_BWTR4 register  ******************/\r
+#define  FMC_BWTR4_ADDSET                   ((uint32_t)0x0000000F)        /*!<ADDSET[3:0] bits (Address setup phase duration) */\r
+#define  FMC_BWTR4_ADDSET_0                 ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_ADDSET_1                 ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_BWTR4_ADDSET_2                 ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_BWTR4_ADDSET_3                 ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR4_ADDHLD                   ((uint32_t)0x000000F0)        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */\r
+#define  FMC_BWTR4_ADDHLD_0                 ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_ADDHLD_1                 ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_BWTR4_ADDHLD_2                 ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_BWTR4_ADDHLD_3                 ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR4_DATAST                   ((uint32_t)0x0000FF00)        /*!<DATAST [3:0] bits (Data-phase duration) */\r
+#define  FMC_BWTR4_DATAST_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_DATAST_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_BWTR4_DATAST_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_BWTR4_DATAST_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_BWTR4_DATAST_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_BWTR4_DATAST_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_BWTR4_DATAST_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_BWTR4_DATAST_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_BWTR4_CLKDIV                   ((uint32_t)0x00F00000)        /*!<CLKDIV[3:0] bits (Clock divide ratio) */\r
+#define  FMC_BWTR4_CLKDIV_0                 ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_CLKDIV_1                 ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_BWTR4_CLKDIV_2                 ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+#define  FMC_BWTR4_CLKDIV_3                 ((uint32_t)0x00800000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR4_DATLAT                   ((uint32_t)0x0F000000)        /*!<DATLA[3:0] bits (Data latency) */\r
+#define  FMC_BWTR4_DATLAT_0                 ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_DATLAT_1                 ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_BWTR4_DATLAT_2                 ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_BWTR4_DATLAT_3                 ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+\r
+#define  FMC_BWTR4_ACCMOD                   ((uint32_t)0x30000000)        /*!<ACCMOD[1:0] bits (Access mode) */\r
+#define  FMC_BWTR4_ACCMOD_0                 ((uint32_t)0x10000000)        /*!<Bit 0 */\r
+#define  FMC_BWTR4_ACCMOD_1                 ((uint32_t)0x20000000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_PCR2 register  *******************/\r
+#define  FMC_PCR2_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */\r
+#define  FMC_PCR2_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FMC_PCR2_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */\r
+\r
+#define  FMC_PCR2_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FMC_PCR2_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_PCR2_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_PCR2_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */\r
+\r
+#define  FMC_PCR2_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */\r
+#define  FMC_PCR2_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FMC_PCR2_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FMC_PCR2_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FMC_PCR2_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR2_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */\r
+#define  FMC_PCR2_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FMC_PCR2_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FMC_PCR2_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FMC_PCR2_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR2_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[1:0] bits (ECC page size)           */\r
+#define  FMC_PCR2_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FMC_PCR2_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FMC_PCR2_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FMC_PCR3 register  *******************/\r
+#define  FMC_PCR3_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */\r
+#define  FMC_PCR3_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FMC_PCR3_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */\r
+\r
+#define  FMC_PCR3_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FMC_PCR3_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_PCR3_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_PCR3_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */\r
+\r
+#define  FMC_PCR3_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */\r
+#define  FMC_PCR3_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FMC_PCR3_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FMC_PCR3_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FMC_PCR3_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR3_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */\r
+#define  FMC_PCR3_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FMC_PCR3_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FMC_PCR3_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FMC_PCR3_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR3_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */\r
+#define  FMC_PCR3_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FMC_PCR3_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FMC_PCR3_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FMC_PCR4 register  *******************/\r
+#define  FMC_PCR4_PWAITEN                   ((uint32_t)0x00000002)        /*!<Wait feature enable bit                   */\r
+#define  FMC_PCR4_PBKEN                     ((uint32_t)0x00000004)        /*!<PC Card/NAND Flash memory bank enable bit */\r
+#define  FMC_PCR4_PTYP                      ((uint32_t)0x00000008)        /*!<Memory type                               */\r
+\r
+#define  FMC_PCR4_PWID                      ((uint32_t)0x00000030)        /*!<PWID[1:0] bits (NAND Flash databus width) */\r
+#define  FMC_PCR4_PWID_0                    ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_PCR4_PWID_1                    ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_PCR4_ECCEN                     ((uint32_t)0x00000040)        /*!<ECC computation logic enable bit          */\r
+\r
+#define  FMC_PCR4_TCLR                      ((uint32_t)0x00001E00)        /*!<TCLR[3:0] bits (CLE to RE delay)          */\r
+#define  FMC_PCR4_TCLR_0                    ((uint32_t)0x00000200)        /*!<Bit 0 */\r
+#define  FMC_PCR4_TCLR_1                    ((uint32_t)0x00000400)        /*!<Bit 1 */\r
+#define  FMC_PCR4_TCLR_2                    ((uint32_t)0x00000800)        /*!<Bit 2 */\r
+#define  FMC_PCR4_TCLR_3                    ((uint32_t)0x00001000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR4_TAR                       ((uint32_t)0x0001E000)        /*!<TAR[3:0] bits (ALE to RE delay)           */\r
+#define  FMC_PCR4_TAR_0                     ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FMC_PCR4_TAR_1                     ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+#define  FMC_PCR4_TAR_2                     ((uint32_t)0x00008000)        /*!<Bit 2 */\r
+#define  FMC_PCR4_TAR_3                     ((uint32_t)0x00010000)        /*!<Bit 3 */\r
+\r
+#define  FMC_PCR4_ECCPS                     ((uint32_t)0x000E0000)        /*!<ECCPS[2:0] bits (ECC page size)           */\r
+#define  FMC_PCR4_ECCPS_0                   ((uint32_t)0x00020000)        /*!<Bit 0 */\r
+#define  FMC_PCR4_ECCPS_1                   ((uint32_t)0x00040000)        /*!<Bit 1 */\r
+#define  FMC_PCR4_ECCPS_2                   ((uint32_t)0x00080000)        /*!<Bit 2 */\r
+\r
+/*******************  Bit definition for FMC_SR2 register  *******************/\r
+#define  FMC_SR2_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */\r
+#define  FMC_SR2_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */\r
+#define  FMC_SR2_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */\r
+#define  FMC_SR2_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define  FMC_SR2_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */\r
+#define  FMC_SR2_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */\r
+#define  FMC_SR2_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */\r
+\r
+/*******************  Bit definition for FMC_SR3 register  *******************/\r
+#define  FMC_SR3_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */\r
+#define  FMC_SR3_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */\r
+#define  FMC_SR3_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */\r
+#define  FMC_SR3_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define  FMC_SR3_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */\r
+#define  FMC_SR3_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */\r
+#define  FMC_SR3_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */\r
+\r
+/*******************  Bit definition for FMC_SR4 register  *******************/\r
+#define  FMC_SR4_IRS                        ((uint8_t)0x01)               /*!<Interrupt Rising Edge status                */\r
+#define  FMC_SR4_ILS                        ((uint8_t)0x02)               /*!<Interrupt Level status                      */\r
+#define  FMC_SR4_IFS                        ((uint8_t)0x04)               /*!<Interrupt Falling Edge status               */\r
+#define  FMC_SR4_IREN                       ((uint8_t)0x08)               /*!<Interrupt Rising Edge detection Enable bit  */\r
+#define  FMC_SR4_ILEN                       ((uint8_t)0x10)               /*!<Interrupt Level detection Enable bit        */\r
+#define  FMC_SR4_IFEN                       ((uint8_t)0x20)               /*!<Interrupt Falling Edge detection Enable bit */\r
+#define  FMC_SR4_FEMPT                      ((uint8_t)0x40)               /*!<FIFO empty                                  */\r
+\r
+/******************  Bit definition for FMC_PMEM2 register  ******************/\r
+#define  FMC_PMEM2_MEMSET2                  ((uint32_t)0x000000FF)        /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */\r
+#define  FMC_PMEM2_MEMSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PMEM2_MEMSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PMEM2_MEMSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PMEM2_MEMSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PMEM2_MEMSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PMEM2_MEMSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PMEM2_MEMSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PMEM2_MEMSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM2_MEMWAIT2                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */\r
+#define  FMC_PMEM2_MEMWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PMEM2_MEMWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PMEM2_MEMWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PMEM2_MEMWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PMEM2_MEMWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PMEM2_MEMWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PMEM2_MEMWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PMEM2_MEMWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM2_MEMHOLD2                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */\r
+#define  FMC_PMEM2_MEMHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PMEM2_MEMHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PMEM2_MEMHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PMEM2_MEMHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PMEM2_MEMHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PMEM2_MEMHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PMEM2_MEMHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PMEM2_MEMHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM2_MEMHIZ2                  ((uint32_t)0xFF000000)        /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */\r
+#define  FMC_PMEM2_MEMHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PMEM2_MEMHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PMEM2_MEMHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PMEM2_MEMHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PMEM2_MEMHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PMEM2_MEMHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PMEM2_MEMHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PMEM2_MEMHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PMEM3 register  ******************/\r
+#define  FMC_PMEM3_MEMSET3                  ((uint32_t)0x000000FF)        /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */\r
+#define  FMC_PMEM3_MEMSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PMEM3_MEMSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PMEM3_MEMSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PMEM3_MEMSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PMEM3_MEMSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PMEM3_MEMSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PMEM3_MEMSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PMEM3_MEMSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM3_MEMWAIT3                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */\r
+#define  FMC_PMEM3_MEMWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PMEM3_MEMWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PMEM3_MEMWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PMEM3_MEMWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PMEM3_MEMWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PMEM3_MEMWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PMEM3_MEMWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PMEM3_MEMWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM3_MEMHOLD3                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */\r
+#define  FMC_PMEM3_MEMHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PMEM3_MEMHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PMEM3_MEMHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PMEM3_MEMHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PMEM3_MEMHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PMEM3_MEMHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PMEM3_MEMHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PMEM3_MEMHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM3_MEMHIZ3                  ((uint32_t)0xFF000000)        /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */\r
+#define  FMC_PMEM3_MEMHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PMEM3_MEMHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PMEM3_MEMHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PMEM3_MEMHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PMEM3_MEMHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PMEM3_MEMHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PMEM3_MEMHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PMEM3_MEMHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PMEM4 register  ******************/\r
+#define  FMC_PMEM4_MEMSET4                  ((uint32_t)0x000000FF)        /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */\r
+#define  FMC_PMEM4_MEMSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PMEM4_MEMSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PMEM4_MEMSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PMEM4_MEMSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PMEM4_MEMSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PMEM4_MEMSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PMEM4_MEMSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PMEM4_MEMSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM4_MEMWAIT4                 ((uint32_t)0x0000FF00)        /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */\r
+#define  FMC_PMEM4_MEMWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PMEM4_MEMWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PMEM4_MEMWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PMEM4_MEMWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PMEM4_MEMWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PMEM4_MEMWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PMEM4_MEMWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PMEM4_MEMWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM4_MEMHOLD4                 ((uint32_t)0x00FF0000)        /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */\r
+#define  FMC_PMEM4_MEMHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PMEM4_MEMHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PMEM4_MEMHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PMEM4_MEMHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PMEM4_MEMHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PMEM4_MEMHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PMEM4_MEMHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PMEM4_MEMHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PMEM4_MEMHIZ4                  ((uint32_t)0xFF000000)        /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */\r
+#define  FMC_PMEM4_MEMHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PMEM4_MEMHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PMEM4_MEMHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PMEM4_MEMHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PMEM4_MEMHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PMEM4_MEMHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PMEM4_MEMHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PMEM4_MEMHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PATT2 register  ******************/\r
+#define  FMC_PATT2_ATTSET2                  ((uint32_t)0x000000FF)        /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */\r
+#define  FMC_PATT2_ATTSET2_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PATT2_ATTSET2_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PATT2_ATTSET2_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PATT2_ATTSET2_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PATT2_ATTSET2_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PATT2_ATTSET2_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PATT2_ATTSET2_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PATT2_ATTSET2_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT2_ATTWAIT2                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */\r
+#define  FMC_PATT2_ATTWAIT2_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PATT2_ATTWAIT2_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PATT2_ATTWAIT2_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PATT2_ATTWAIT2_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PATT2_ATTWAIT2_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PATT2_ATTWAIT2_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PATT2_ATTWAIT2_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PATT2_ATTWAIT2_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT2_ATTHOLD2                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */\r
+#define  FMC_PATT2_ATTHOLD2_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PATT2_ATTHOLD2_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PATT2_ATTHOLD2_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PATT2_ATTHOLD2_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PATT2_ATTHOLD2_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PATT2_ATTHOLD2_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PATT2_ATTHOLD2_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PATT2_ATTHOLD2_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT2_ATTHIZ2                  ((uint32_t)0xFF000000)        /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */\r
+#define  FMC_PATT2_ATTHIZ2_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PATT2_ATTHIZ2_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PATT2_ATTHIZ2_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PATT2_ATTHIZ2_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PATT2_ATTHIZ2_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PATT2_ATTHIZ2_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PATT2_ATTHIZ2_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PATT2_ATTHIZ2_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PATT3 register  ******************/\r
+#define  FMC_PATT3_ATTSET3                  ((uint32_t)0x000000FF)        /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */\r
+#define  FMC_PATT3_ATTSET3_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PATT3_ATTSET3_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PATT3_ATTSET3_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PATT3_ATTSET3_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PATT3_ATTSET3_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PATT3_ATTSET3_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PATT3_ATTSET3_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PATT3_ATTSET3_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT3_ATTWAIT3                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */\r
+#define  FMC_PATT3_ATTWAIT3_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PATT3_ATTWAIT3_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PATT3_ATTWAIT3_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PATT3_ATTWAIT3_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PATT3_ATTWAIT3_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PATT3_ATTWAIT3_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PATT3_ATTWAIT3_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PATT3_ATTWAIT3_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT3_ATTHOLD3                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */\r
+#define  FMC_PATT3_ATTHOLD3_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PATT3_ATTHOLD3_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PATT3_ATTHOLD3_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PATT3_ATTHOLD3_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PATT3_ATTHOLD3_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PATT3_ATTHOLD3_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PATT3_ATTHOLD3_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PATT3_ATTHOLD3_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT3_ATTHIZ3                  ((uint32_t)0xFF000000)        /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */\r
+#define  FMC_PATT3_ATTHIZ3_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PATT3_ATTHIZ3_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PATT3_ATTHIZ3_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PATT3_ATTHIZ3_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PATT3_ATTHIZ3_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PATT3_ATTHIZ3_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PATT3_ATTHIZ3_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PATT3_ATTHIZ3_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PATT4 register  ******************/\r
+#define  FMC_PATT4_ATTSET4                  ((uint32_t)0x000000FF)        /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */\r
+#define  FMC_PATT4_ATTSET4_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PATT4_ATTSET4_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PATT4_ATTSET4_2                ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PATT4_ATTSET4_3                ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PATT4_ATTSET4_4                ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PATT4_ATTSET4_5                ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PATT4_ATTSET4_6                ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PATT4_ATTSET4_7                ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT4_ATTWAIT4                 ((uint32_t)0x0000FF00)        /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */\r
+#define  FMC_PATT4_ATTWAIT4_0               ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PATT4_ATTWAIT4_1               ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PATT4_ATTWAIT4_2               ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PATT4_ATTWAIT4_3               ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PATT4_ATTWAIT4_4               ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PATT4_ATTWAIT4_5               ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PATT4_ATTWAIT4_6               ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PATT4_ATTWAIT4_7               ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT4_ATTHOLD4                 ((uint32_t)0x00FF0000)        /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */\r
+#define  FMC_PATT4_ATTHOLD4_0               ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PATT4_ATTHOLD4_1               ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PATT4_ATTHOLD4_2               ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PATT4_ATTHOLD4_3               ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PATT4_ATTHOLD4_4               ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PATT4_ATTHOLD4_5               ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PATT4_ATTHOLD4_6               ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PATT4_ATTHOLD4_7               ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PATT4_ATTHIZ4                  ((uint32_t)0xFF000000)        /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */\r
+#define  FMC_PATT4_ATTHIZ4_0                ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PATT4_ATTHIZ4_1                ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PATT4_ATTHIZ4_2                ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PATT4_ATTHIZ4_3                ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PATT4_ATTHIZ4_4                ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PATT4_ATTHIZ4_5                ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PATT4_ATTHIZ4_6                ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PATT4_ATTHIZ4_7                ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_PIO4 register  *******************/\r
+#define  FMC_PIO4_IOSET4                    ((uint32_t)0x000000FF)        /*!<IOSET4[7:0] bits (I/O 4 setup time) */\r
+#define  FMC_PIO4_IOSET4_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_PIO4_IOSET4_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_PIO4_IOSET4_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_PIO4_IOSET4_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  FMC_PIO4_IOSET4_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  FMC_PIO4_IOSET4_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  FMC_PIO4_IOSET4_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  FMC_PIO4_IOSET4_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  FMC_PIO4_IOWAIT4                   ((uint32_t)0x0000FF00)        /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */\r
+#define  FMC_PIO4_IOWAIT4_0                 ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_PIO4_IOWAIT4_1                 ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_PIO4_IOWAIT4_2                 ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_PIO4_IOWAIT4_3                 ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  FMC_PIO4_IOWAIT4_4                 ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  FMC_PIO4_IOWAIT4_5                 ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  FMC_PIO4_IOWAIT4_6                 ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+#define  FMC_PIO4_IOWAIT4_7                 ((uint32_t)0x00008000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PIO4_IOHOLD4                   ((uint32_t)0x00FF0000)        /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */\r
+#define  FMC_PIO4_IOHOLD4_0                 ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_PIO4_IOHOLD4_1                 ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_PIO4_IOHOLD4_2                 ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+#define  FMC_PIO4_IOHOLD4_3                 ((uint32_t)0x00080000)        /*!<Bit 3 */\r
+#define  FMC_PIO4_IOHOLD4_4                 ((uint32_t)0x00100000)        /*!<Bit 4 */\r
+#define  FMC_PIO4_IOHOLD4_5                 ((uint32_t)0x00200000)        /*!<Bit 5 */\r
+#define  FMC_PIO4_IOHOLD4_6                 ((uint32_t)0x00400000)        /*!<Bit 6 */\r
+#define  FMC_PIO4_IOHOLD4_7                 ((uint32_t)0x00800000)        /*!<Bit 7 */\r
+\r
+#define  FMC_PIO4_IOHIZ4                    ((uint32_t)0xFF000000)        /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */\r
+#define  FMC_PIO4_IOHIZ4_0                  ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_PIO4_IOHIZ4_1                  ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_PIO4_IOHIZ4_2                  ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+#define  FMC_PIO4_IOHIZ4_3                  ((uint32_t)0x08000000)        /*!<Bit 3 */\r
+#define  FMC_PIO4_IOHIZ4_4                  ((uint32_t)0x10000000)        /*!<Bit 4 */\r
+#define  FMC_PIO4_IOHIZ4_5                  ((uint32_t)0x20000000)        /*!<Bit 5 */\r
+#define  FMC_PIO4_IOHIZ4_6                  ((uint32_t)0x40000000)        /*!<Bit 6 */\r
+#define  FMC_PIO4_IOHIZ4_7                  ((uint32_t)0x80000000)        /*!<Bit 7 */\r
+\r
+/******************  Bit definition for FMC_ECCR2 register  ******************/\r
+#define  FMC_ECCR2_ECC2                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */\r
+\r
+/******************  Bit definition for FMC_ECCR3 register  ******************/\r
+#define  FMC_ECCR3_ECC3                     ((uint32_t)0xFFFFFFFF)        /*!<ECC result */\r
+\r
+/******************  Bit definition for FMC_SDCR1 register  ******************/\r
+#define  FMC_SDCR1_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */\r
+#define  FMC_SDCR1_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR1_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */\r
+#define  FMC_SDCR1_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR1_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */\r
+#define  FMC_SDCR1_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR1_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */\r
+\r
+#define  FMC_SDCR1_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */\r
+#define  FMC_SDCR1_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR1_WP                       ((uint32_t)0x00000200)        /*!<Write protection */\r
+\r
+#define  FMC_SDCR1_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDRAM clock configuration */\r
+#define  FMC_SDCR1_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR1_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */\r
+\r
+#define  FMC_SDCR1_RPIPE                    ((uint32_t)0x00006000)        /*!<Write protection */\r
+#define  FMC_SDCR1_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FMC_SDCR1_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_SDCR2 register  ******************/\r
+#define  FMC_SDCR2_NC                       ((uint32_t)0x00000003)        /*!<NC[1:0] bits (Number of column bits) */\r
+#define  FMC_SDCR2_NC_0                     ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_NC_1                     ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR2_NR                       ((uint32_t)0x0000000C)        /*!<NR[1:0] bits (Number of row bits) */\r
+#define  FMC_SDCR2_NR_0                     ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_NR_1                     ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR2_MWID                     ((uint32_t)0x00000030)        /*!<NR[1:0] bits (Number of row bits) */\r
+#define  FMC_SDCR2_MWID_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_MWID_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR2_NB                       ((uint32_t)0x00000040)        /*!<Number of internal bank */\r
+\r
+#define  FMC_SDCR2_CAS                      ((uint32_t)0x00000180)        /*!<CAS[1:0] bits (CAS latency) */\r
+#define  FMC_SDCR2_CAS_0                    ((uint32_t)0x00000080)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_CAS_1                    ((uint32_t)0x00000100)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR2_WP                       ((uint32_t)0x00000200)        /*!<Write protection */\r
+\r
+#define  FMC_SDCR2_SDCLK                    ((uint32_t)0x00000C00)        /*!<SDCLK[1:0] (SDRAM clock configuration) */\r
+#define  FMC_SDCR2_SDCLK_0                  ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_SDCLK_1                  ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDCR2_RBURST                   ((uint32_t)0x00001000)        /*!<Read burst */\r
+\r
+#define  FMC_SDCR2_RPIPE                    ((uint32_t)0x00006000)        /*!<RPIPE[1:0](Read pipe) */\r
+#define  FMC_SDCR2_RPIPE_0                  ((uint32_t)0x00002000)        /*!<Bit 0 */\r
+#define  FMC_SDCR2_RPIPE_1                  ((uint32_t)0x00004000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for FMC_SDTR1 register  ******************/\r
+#define  FMC_SDTR1_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define  FMC_SDTR1_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_SDTR1_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+                                            \r
+#define  FMC_SDTR1_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define  FMC_SDTR1_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_SDTR1_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_SDTR1_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define  FMC_SDTR1_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_SDTR1_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FMC_SDTR1_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define  FMC_SDTR1_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR1_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define  FMC_SDTR1_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR1_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define  FMC_SDTR1_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR1_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */\r
+#define  FMC_SDTR1_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_SDTR1_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_SDTR1_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FMC_SDTR2 register  ******************/\r
+#define  FMC_SDTR2_TMRD                     ((uint32_t)0x0000000F)        /*!<TMRD[3:0] bits (Load mode register to active) */\r
+#define  FMC_SDTR2_TMRD_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TMRD_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TMRD_2                   ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  FMC_SDTR2_TMRD_3                   ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+                                            \r
+#define  FMC_SDTR2_TXSR                     ((uint32_t)0x000000F0)        /*!<TXSR[3:0] bits (Exit self refresh) */\r
+#define  FMC_SDTR2_TXSR_0                   ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TXSR_1                   ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TXSR_2                   ((uint32_t)0x00000040)        /*!<Bit 2 */\r
+#define  FMC_SDTR2_TXSR_3                   ((uint32_t)0x00000080)        /*!<Bit 3 */\r
+\r
+#define  FMC_SDTR2_TRAS                     ((uint32_t)0x00000F00)        /*!<TRAS[3:0] bits (Self refresh time) */\r
+#define  FMC_SDTR2_TRAS_0                   ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TRAS_1                   ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TRAS_2                   ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  FMC_SDTR2_TRAS_3                   ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  FMC_SDTR2_TRC                      ((uint32_t)0x0000F000)        /*!<TRC[2:0] bits (Row cycle delay) */\r
+#define  FMC_SDTR2_TRC_0                    ((uint32_t)0x00001000)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TRC_1                    ((uint32_t)0x00002000)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TRC_2                    ((uint32_t)0x00004000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR2_TWR                      ((uint32_t)0x000F0000)        /*!<TRC[2:0] bits (Write recovery delay) */\r
+#define  FMC_SDTR2_TWR_0                    ((uint32_t)0x00010000)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TWR_1                    ((uint32_t)0x00020000)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TWR_2                    ((uint32_t)0x00040000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR2_TRP                      ((uint32_t)0x00F00000)        /*!<TRP[2:0] bits (Row precharge delay) */\r
+#define  FMC_SDTR2_TRP_0                    ((uint32_t)0x00100000)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TRP_1                    ((uint32_t)0x00200000)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TRP_2                    ((uint32_t)0x00400000)        /*!<Bit 2 */\r
+\r
+#define  FMC_SDTR2_TRCD                     ((uint32_t)0x0F000000)        /*!<TRP[2:0] bits (Row to column delay) */\r
+#define  FMC_SDTR2_TRCD_0                   ((uint32_t)0x01000000)        /*!<Bit 0 */\r
+#define  FMC_SDTR2_TRCD_1                   ((uint32_t)0x02000000)        /*!<Bit 1 */\r
+#define  FMC_SDTR2_TRCD_2                   ((uint32_t)0x04000000)        /*!<Bit 2 */\r
+\r
+/******************  Bit definition for FMC_SDCMR register  ******************/\r
+#define  FMC_SDCMR_MODE                     ((uint32_t)0x00000007)        /*!<MODE[2:0] bits (Command mode) */\r
+#define  FMC_SDCMR_MODE_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  FMC_SDCMR_MODE_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  FMC_SDCMR_MODE_2                   ((uint32_t)0x00000003)        /*!<Bit 2 */\r
+                                            \r
+#define  FMC_SDCMR_CTB2                     ((uint32_t)0x00000008)        /*!<Command target 2 */\r
+\r
+#define  FMC_SDCMR_CTB1                     ((uint32_t)0x00000010)        /*!<Command target 1 */\r
+\r
+#define  FMC_SDCMR_NRFS                     ((uint32_t)0x000001E0)        /*!<NRFS[3:0] bits (Number of auto-refresh) */\r
+#define  FMC_SDCMR_NRFS_0                   ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  FMC_SDCMR_NRFS_1                   ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  FMC_SDCMR_NRFS_2                   ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+#define  FMC_SDCMR_NRFS_3                   ((uint32_t)0x00000100)        /*!<Bit 3 */\r
+\r
+#define  FMC_SDCMR_MRD                      ((uint32_t)0x003FFE00)        /*!<MRD[12:0] bits (Mode register definition) */\r
+\r
+/******************  Bit definition for FMC_SDRTR register  ******************/\r
+#define  FMC_SDRTR_CRE                      ((uint32_t)0x00000001)        /*!<Clear refresh error flag */\r
+\r
+#define  FMC_SDRTR_COUNT                    ((uint32_t)0x00003FFE)        /*!<COUNT[12:0] bits (Refresh timer count) */\r
+\r
+#define  FMC_SDRTR_REIE                     ((uint32_t)0x00004000)        /*!<RES interupt enable */\r
+\r
+/******************  Bit definition for FMC_SDSR register  ******************/\r
+#define  FMC_SDSR_RE                        ((uint32_t)0x00000001)        /*!<Refresh error flag */\r
+\r
+#define  FMC_SDSR_MODES1                    ((uint32_t)0x00000006)        /*!<MODES1[1:0]bits (Status mode for bank 1) */\r
+#define  FMC_SDSR_MODES1_0                  ((uint32_t)0x00000002)        /*!<Bit 0 */\r
+#define  FMC_SDSR_MODES1_1                  ((uint32_t)0x00000004)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDSR_MODES2                    ((uint32_t)0x00000018)        /*!<MODES2[1:0]bits (Status mode for bank 2) */\r
+#define  FMC_SDSR_MODES2_0                  ((uint32_t)0x00000008)        /*!<Bit 0 */\r
+#define  FMC_SDSR_MODES2_1                  ((uint32_t)0x00000010)        /*!<Bit 1 */\r
+\r
+#define  FMC_SDSR_BUSY                      ((uint32_t)0x00000020)        /*!<Busy status */\r
+\r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                            General Purpose I/O                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bits definition for GPIO_MODER register  *****************/\r
+#define GPIO_MODER_MODER0                    ((uint32_t)0x00000003)\r
+#define GPIO_MODER_MODER0_0                  ((uint32_t)0x00000001)\r
+#define GPIO_MODER_MODER0_1                  ((uint32_t)0x00000002)\r
+\r
+#define GPIO_MODER_MODER1                    ((uint32_t)0x0000000C)\r
+#define GPIO_MODER_MODER1_0                  ((uint32_t)0x00000004)\r
+#define GPIO_MODER_MODER1_1                  ((uint32_t)0x00000008)\r
+\r
+#define GPIO_MODER_MODER2                    ((uint32_t)0x00000030)\r
+#define GPIO_MODER_MODER2_0                  ((uint32_t)0x00000010)\r
+#define GPIO_MODER_MODER2_1                  ((uint32_t)0x00000020)\r
+\r
+#define GPIO_MODER_MODER3                    ((uint32_t)0x000000C0)\r
+#define GPIO_MODER_MODER3_0                  ((uint32_t)0x00000040)\r
+#define GPIO_MODER_MODER3_1                  ((uint32_t)0x00000080)\r
+\r
+#define GPIO_MODER_MODER4                    ((uint32_t)0x00000300)\r
+#define GPIO_MODER_MODER4_0                  ((uint32_t)0x00000100)\r
+#define GPIO_MODER_MODER4_1                  ((uint32_t)0x00000200)\r
+\r
+#define GPIO_MODER_MODER5                    ((uint32_t)0x00000C00)\r
+#define GPIO_MODER_MODER5_0                  ((uint32_t)0x00000400)\r
+#define GPIO_MODER_MODER5_1                  ((uint32_t)0x00000800)\r
+\r
+#define GPIO_MODER_MODER6                    ((uint32_t)0x00003000)\r
+#define GPIO_MODER_MODER6_0                  ((uint32_t)0x00001000)\r
+#define GPIO_MODER_MODER6_1                  ((uint32_t)0x00002000)\r
+\r
+#define GPIO_MODER_MODER7                    ((uint32_t)0x0000C000)\r
+#define GPIO_MODER_MODER7_0                  ((uint32_t)0x00004000)\r
+#define GPIO_MODER_MODER7_1                  ((uint32_t)0x00008000)\r
+\r
+#define GPIO_MODER_MODER8                    ((uint32_t)0x00030000)\r
+#define GPIO_MODER_MODER8_0                  ((uint32_t)0x00010000)\r
+#define GPIO_MODER_MODER8_1                  ((uint32_t)0x00020000)\r
+\r
+#define GPIO_MODER_MODER9                    ((uint32_t)0x000C0000)\r
+#define GPIO_MODER_MODER9_0                  ((uint32_t)0x00040000)\r
+#define GPIO_MODER_MODER9_1                  ((uint32_t)0x00080000)\r
+\r
+#define GPIO_MODER_MODER10                   ((uint32_t)0x00300000)\r
+#define GPIO_MODER_MODER10_0                 ((uint32_t)0x00100000)\r
+#define GPIO_MODER_MODER10_1                 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_MODER_MODER11                   ((uint32_t)0x00C00000)\r
+#define GPIO_MODER_MODER11_0                 ((uint32_t)0x00400000)\r
+#define GPIO_MODER_MODER11_1                 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_MODER_MODER12                   ((uint32_t)0x03000000)\r
+#define GPIO_MODER_MODER12_0                 ((uint32_t)0x01000000)\r
+#define GPIO_MODER_MODER12_1                 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_MODER_MODER13                   ((uint32_t)0x0C000000)\r
+#define GPIO_MODER_MODER13_0                 ((uint32_t)0x04000000)\r
+#define GPIO_MODER_MODER13_1                 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_MODER_MODER14                   ((uint32_t)0x30000000)\r
+#define GPIO_MODER_MODER14_0                 ((uint32_t)0x10000000)\r
+#define GPIO_MODER_MODER14_1                 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_MODER_MODER15                   ((uint32_t)0xC0000000)\r
+#define GPIO_MODER_MODER15_0                 ((uint32_t)0x40000000)\r
+#define GPIO_MODER_MODER15_1                 ((uint32_t)0x80000000)\r
+\r
+/******************  Bits definition for GPIO_OTYPER register  ****************/\r
+#define GPIO_OTYPER_OT_0                     ((uint32_t)0x00000001)\r
+#define GPIO_OTYPER_OT_1                     ((uint32_t)0x00000002)\r
+#define GPIO_OTYPER_OT_2                     ((uint32_t)0x00000004)\r
+#define GPIO_OTYPER_OT_3                     ((uint32_t)0x00000008)\r
+#define GPIO_OTYPER_OT_4                     ((uint32_t)0x00000010)\r
+#define GPIO_OTYPER_OT_5                     ((uint32_t)0x00000020)\r
+#define GPIO_OTYPER_OT_6                     ((uint32_t)0x00000040)\r
+#define GPIO_OTYPER_OT_7                     ((uint32_t)0x00000080)\r
+#define GPIO_OTYPER_OT_8                     ((uint32_t)0x00000100)\r
+#define GPIO_OTYPER_OT_9                     ((uint32_t)0x00000200)\r
+#define GPIO_OTYPER_OT_10                    ((uint32_t)0x00000400)\r
+#define GPIO_OTYPER_OT_11                    ((uint32_t)0x00000800)\r
+#define GPIO_OTYPER_OT_12                    ((uint32_t)0x00001000)\r
+#define GPIO_OTYPER_OT_13                    ((uint32_t)0x00002000)\r
+#define GPIO_OTYPER_OT_14                    ((uint32_t)0x00004000)\r
+#define GPIO_OTYPER_OT_15                    ((uint32_t)0x00008000)\r
+\r
+/******************  Bits definition for GPIO_OSPEEDR register  ***************/\r
+#define GPIO_OSPEEDER_OSPEEDR0               ((uint32_t)0x00000003)\r
+#define GPIO_OSPEEDER_OSPEEDR0_0             ((uint32_t)0x00000001)\r
+#define GPIO_OSPEEDER_OSPEEDR0_1             ((uint32_t)0x00000002)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR1               ((uint32_t)0x0000000C)\r
+#define GPIO_OSPEEDER_OSPEEDR1_0             ((uint32_t)0x00000004)\r
+#define GPIO_OSPEEDER_OSPEEDR1_1             ((uint32_t)0x00000008)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR2               ((uint32_t)0x00000030)\r
+#define GPIO_OSPEEDER_OSPEEDR2_0             ((uint32_t)0x00000010)\r
+#define GPIO_OSPEEDER_OSPEEDR2_1             ((uint32_t)0x00000020)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR3               ((uint32_t)0x000000C0)\r
+#define GPIO_OSPEEDER_OSPEEDR3_0             ((uint32_t)0x00000040)\r
+#define GPIO_OSPEEDER_OSPEEDR3_1             ((uint32_t)0x00000080)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR4               ((uint32_t)0x00000300)\r
+#define GPIO_OSPEEDER_OSPEEDR4_0             ((uint32_t)0x00000100)\r
+#define GPIO_OSPEEDER_OSPEEDR4_1             ((uint32_t)0x00000200)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR5               ((uint32_t)0x00000C00)\r
+#define GPIO_OSPEEDER_OSPEEDR5_0             ((uint32_t)0x00000400)\r
+#define GPIO_OSPEEDER_OSPEEDR5_1             ((uint32_t)0x00000800)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR6               ((uint32_t)0x00003000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_0             ((uint32_t)0x00001000)\r
+#define GPIO_OSPEEDER_OSPEEDR6_1             ((uint32_t)0x00002000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR7               ((uint32_t)0x0000C000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_0             ((uint32_t)0x00004000)\r
+#define GPIO_OSPEEDER_OSPEEDR7_1             ((uint32_t)0x00008000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR8               ((uint32_t)0x00030000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_0             ((uint32_t)0x00010000)\r
+#define GPIO_OSPEEDER_OSPEEDR8_1             ((uint32_t)0x00020000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR9               ((uint32_t)0x000C0000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_0             ((uint32_t)0x00040000)\r
+#define GPIO_OSPEEDER_OSPEEDR9_1             ((uint32_t)0x00080000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR10              ((uint32_t)0x00300000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_0            ((uint32_t)0x00100000)\r
+#define GPIO_OSPEEDER_OSPEEDR10_1            ((uint32_t)0x00200000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR11              ((uint32_t)0x00C00000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_0            ((uint32_t)0x00400000)\r
+#define GPIO_OSPEEDER_OSPEEDR11_1            ((uint32_t)0x00800000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR12              ((uint32_t)0x03000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_0            ((uint32_t)0x01000000)\r
+#define GPIO_OSPEEDER_OSPEEDR12_1            ((uint32_t)0x02000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR13              ((uint32_t)0x0C000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_0            ((uint32_t)0x04000000)\r
+#define GPIO_OSPEEDER_OSPEEDR13_1            ((uint32_t)0x08000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR14              ((uint32_t)0x30000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_0            ((uint32_t)0x10000000)\r
+#define GPIO_OSPEEDER_OSPEEDR14_1            ((uint32_t)0x20000000)\r
+\r
+#define GPIO_OSPEEDER_OSPEEDR15              ((uint32_t)0xC0000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_0            ((uint32_t)0x40000000)\r
+#define GPIO_OSPEEDER_OSPEEDR15_1            ((uint32_t)0x80000000)\r
+\r
+/******************  Bits definition for GPIO_PUPDR register  *****************/\r
+#define GPIO_PUPDR_PUPDR0                    ((uint32_t)0x00000003)\r
+#define GPIO_PUPDR_PUPDR0_0                  ((uint32_t)0x00000001)\r
+#define GPIO_PUPDR_PUPDR0_1                  ((uint32_t)0x00000002)\r
+\r
+#define GPIO_PUPDR_PUPDR1                    ((uint32_t)0x0000000C)\r
+#define GPIO_PUPDR_PUPDR1_0                  ((uint32_t)0x00000004)\r
+#define GPIO_PUPDR_PUPDR1_1                  ((uint32_t)0x00000008)\r
+\r
+#define GPIO_PUPDR_PUPDR2                    ((uint32_t)0x00000030)\r
+#define GPIO_PUPDR_PUPDR2_0                  ((uint32_t)0x00000010)\r
+#define GPIO_PUPDR_PUPDR2_1                  ((uint32_t)0x00000020)\r
+\r
+#define GPIO_PUPDR_PUPDR3                    ((uint32_t)0x000000C0)\r
+#define GPIO_PUPDR_PUPDR3_0                  ((uint32_t)0x00000040)\r
+#define GPIO_PUPDR_PUPDR3_1                  ((uint32_t)0x00000080)\r
+\r
+#define GPIO_PUPDR_PUPDR4                    ((uint32_t)0x00000300)\r
+#define GPIO_PUPDR_PUPDR4_0                  ((uint32_t)0x00000100)\r
+#define GPIO_PUPDR_PUPDR4_1                  ((uint32_t)0x00000200)\r
+\r
+#define GPIO_PUPDR_PUPDR5                    ((uint32_t)0x00000C00)\r
+#define GPIO_PUPDR_PUPDR5_0                  ((uint32_t)0x00000400)\r
+#define GPIO_PUPDR_PUPDR5_1                  ((uint32_t)0x00000800)\r
+\r
+#define GPIO_PUPDR_PUPDR6                    ((uint32_t)0x00003000)\r
+#define GPIO_PUPDR_PUPDR6_0                  ((uint32_t)0x00001000)\r
+#define GPIO_PUPDR_PUPDR6_1                  ((uint32_t)0x00002000)\r
+\r
+#define GPIO_PUPDR_PUPDR7                    ((uint32_t)0x0000C000)\r
+#define GPIO_PUPDR_PUPDR7_0                  ((uint32_t)0x00004000)\r
+#define GPIO_PUPDR_PUPDR7_1                  ((uint32_t)0x00008000)\r
+\r
+#define GPIO_PUPDR_PUPDR8                    ((uint32_t)0x00030000)\r
+#define GPIO_PUPDR_PUPDR8_0                  ((uint32_t)0x00010000)\r
+#define GPIO_PUPDR_PUPDR8_1                  ((uint32_t)0x00020000)\r
+\r
+#define GPIO_PUPDR_PUPDR9                    ((uint32_t)0x000C0000)\r
+#define GPIO_PUPDR_PUPDR9_0                  ((uint32_t)0x00040000)\r
+#define GPIO_PUPDR_PUPDR9_1                  ((uint32_t)0x00080000)\r
+\r
+#define GPIO_PUPDR_PUPDR10                   ((uint32_t)0x00300000)\r
+#define GPIO_PUPDR_PUPDR10_0                 ((uint32_t)0x00100000)\r
+#define GPIO_PUPDR_PUPDR10_1                 ((uint32_t)0x00200000)\r
+\r
+#define GPIO_PUPDR_PUPDR11                   ((uint32_t)0x00C00000)\r
+#define GPIO_PUPDR_PUPDR11_0                 ((uint32_t)0x00400000)\r
+#define GPIO_PUPDR_PUPDR11_1                 ((uint32_t)0x00800000)\r
+\r
+#define GPIO_PUPDR_PUPDR12                   ((uint32_t)0x03000000)\r
+#define GPIO_PUPDR_PUPDR12_0                 ((uint32_t)0x01000000)\r
+#define GPIO_PUPDR_PUPDR12_1                 ((uint32_t)0x02000000)\r
+\r
+#define GPIO_PUPDR_PUPDR13                   ((uint32_t)0x0C000000)\r
+#define GPIO_PUPDR_PUPDR13_0                 ((uint32_t)0x04000000)\r
+#define GPIO_PUPDR_PUPDR13_1                 ((uint32_t)0x08000000)\r
+\r
+#define GPIO_PUPDR_PUPDR14                   ((uint32_t)0x30000000)\r
+#define GPIO_PUPDR_PUPDR14_0                 ((uint32_t)0x10000000)\r
+#define GPIO_PUPDR_PUPDR14_1                 ((uint32_t)0x20000000)\r
+\r
+#define GPIO_PUPDR_PUPDR15                   ((uint32_t)0xC0000000)\r
+#define GPIO_PUPDR_PUPDR15_0                 ((uint32_t)0x40000000)\r
+#define GPIO_PUPDR_PUPDR15_1                 ((uint32_t)0x80000000)\r
+\r
+/******************  Bits definition for GPIO_IDR register  *******************/\r
+#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)\r
+#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)\r
+#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)\r
+#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)\r
+#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)\r
+#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)\r
+#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)\r
+#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)\r
+#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)\r
+#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)\r
+#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)\r
+#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)\r
+#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)\r
+#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)\r
+#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)\r
+#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)\r
+/* Old GPIO_IDR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_IDR_0                    GPIO_IDR_IDR_0\r
+#define GPIO_OTYPER_IDR_1                    GPIO_IDR_IDR_1\r
+#define GPIO_OTYPER_IDR_2                    GPIO_IDR_IDR_2\r
+#define GPIO_OTYPER_IDR_3                    GPIO_IDR_IDR_3\r
+#define GPIO_OTYPER_IDR_4                    GPIO_IDR_IDR_4\r
+#define GPIO_OTYPER_IDR_5                    GPIO_IDR_IDR_5\r
+#define GPIO_OTYPER_IDR_6                    GPIO_IDR_IDR_6\r
+#define GPIO_OTYPER_IDR_7                    GPIO_IDR_IDR_7\r
+#define GPIO_OTYPER_IDR_8                    GPIO_IDR_IDR_8\r
+#define GPIO_OTYPER_IDR_9                    GPIO_IDR_IDR_9\r
+#define GPIO_OTYPER_IDR_10                   GPIO_IDR_IDR_10\r
+#define GPIO_OTYPER_IDR_11                   GPIO_IDR_IDR_11\r
+#define GPIO_OTYPER_IDR_12                   GPIO_IDR_IDR_12\r
+#define GPIO_OTYPER_IDR_13                   GPIO_IDR_IDR_13\r
+#define GPIO_OTYPER_IDR_14                   GPIO_IDR_IDR_14\r
+#define GPIO_OTYPER_IDR_15                   GPIO_IDR_IDR_15\r
+\r
+/******************  Bits definition for GPIO_ODR register  *******************/\r
+#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)\r
+#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)\r
+#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)\r
+#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)\r
+#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)\r
+#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)\r
+#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)\r
+#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)\r
+#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)\r
+#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)\r
+#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)\r
+#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)\r
+#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)\r
+#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)\r
+#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)\r
+#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)\r
+/* Old GPIO_ODR register bits definition, maintained for legacy purpose */\r
+#define GPIO_OTYPER_ODR_0                    GPIO_ODR_ODR_0\r
+#define GPIO_OTYPER_ODR_1                    GPIO_ODR_ODR_1\r
+#define GPIO_OTYPER_ODR_2                    GPIO_ODR_ODR_2\r
+#define GPIO_OTYPER_ODR_3                    GPIO_ODR_ODR_3\r
+#define GPIO_OTYPER_ODR_4                    GPIO_ODR_ODR_4\r
+#define GPIO_OTYPER_ODR_5                    GPIO_ODR_ODR_5\r
+#define GPIO_OTYPER_ODR_6                    GPIO_ODR_ODR_6\r
+#define GPIO_OTYPER_ODR_7                    GPIO_ODR_ODR_7\r
+#define GPIO_OTYPER_ODR_8                    GPIO_ODR_ODR_8\r
+#define GPIO_OTYPER_ODR_9                    GPIO_ODR_ODR_9\r
+#define GPIO_OTYPER_ODR_10                   GPIO_ODR_ODR_10\r
+#define GPIO_OTYPER_ODR_11                   GPIO_ODR_ODR_11\r
+#define GPIO_OTYPER_ODR_12                   GPIO_ODR_ODR_12\r
+#define GPIO_OTYPER_ODR_13                   GPIO_ODR_ODR_13\r
+#define GPIO_OTYPER_ODR_14                   GPIO_ODR_ODR_14\r
+#define GPIO_OTYPER_ODR_15                   GPIO_ODR_ODR_15\r
+\r
+/******************  Bits definition for GPIO_BSRR register  ******************/\r
+#define GPIO_BSRR_BS_0                       ((uint32_t)0x00000001)\r
+#define GPIO_BSRR_BS_1                       ((uint32_t)0x00000002)\r
+#define GPIO_BSRR_BS_2                       ((uint32_t)0x00000004)\r
+#define GPIO_BSRR_BS_3                       ((uint32_t)0x00000008)\r
+#define GPIO_BSRR_BS_4                       ((uint32_t)0x00000010)\r
+#define GPIO_BSRR_BS_5                       ((uint32_t)0x00000020)\r
+#define GPIO_BSRR_BS_6                       ((uint32_t)0x00000040)\r
+#define GPIO_BSRR_BS_7                       ((uint32_t)0x00000080)\r
+#define GPIO_BSRR_BS_8                       ((uint32_t)0x00000100)\r
+#define GPIO_BSRR_BS_9                       ((uint32_t)0x00000200)\r
+#define GPIO_BSRR_BS_10                      ((uint32_t)0x00000400)\r
+#define GPIO_BSRR_BS_11                      ((uint32_t)0x00000800)\r
+#define GPIO_BSRR_BS_12                      ((uint32_t)0x00001000)\r
+#define GPIO_BSRR_BS_13                      ((uint32_t)0x00002000)\r
+#define GPIO_BSRR_BS_14                      ((uint32_t)0x00004000)\r
+#define GPIO_BSRR_BS_15                      ((uint32_t)0x00008000)\r
+#define GPIO_BSRR_BR_0                       ((uint32_t)0x00010000)\r
+#define GPIO_BSRR_BR_1                       ((uint32_t)0x00020000)\r
+#define GPIO_BSRR_BR_2                       ((uint32_t)0x00040000)\r
+#define GPIO_BSRR_BR_3                       ((uint32_t)0x00080000)\r
+#define GPIO_BSRR_BR_4                       ((uint32_t)0x00100000)\r
+#define GPIO_BSRR_BR_5                       ((uint32_t)0x00200000)\r
+#define GPIO_BSRR_BR_6                       ((uint32_t)0x00400000)\r
+#define GPIO_BSRR_BR_7                       ((uint32_t)0x00800000)\r
+#define GPIO_BSRR_BR_8                       ((uint32_t)0x01000000)\r
+#define GPIO_BSRR_BR_9                       ((uint32_t)0x02000000)\r
+#define GPIO_BSRR_BR_10                      ((uint32_t)0x04000000)\r
+#define GPIO_BSRR_BR_11                      ((uint32_t)0x08000000)\r
+#define GPIO_BSRR_BR_12                      ((uint32_t)0x10000000)\r
+#define GPIO_BSRR_BR_13                      ((uint32_t)0x20000000)\r
+#define GPIO_BSRR_BR_14                      ((uint32_t)0x40000000)\r
+#define GPIO_BSRR_BR_15                      ((uint32_t)0x80000000)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    HASH                                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bits definition for HASH_CR register  ********************/\r
+#define HASH_CR_INIT                         ((uint32_t)0x00000004)\r
+#define HASH_CR_DMAE                         ((uint32_t)0x00000008)\r
+#define HASH_CR_DATATYPE                     ((uint32_t)0x00000030)\r
+#define HASH_CR_DATATYPE_0                   ((uint32_t)0x00000010)\r
+#define HASH_CR_DATATYPE_1                   ((uint32_t)0x00000020)\r
+#define HASH_CR_MODE                         ((uint32_t)0x00000040)\r
+#define HASH_CR_ALGO                         ((uint32_t)0x00040080)\r
+#define HASH_CR_ALGO_0                       ((uint32_t)0x00000080)\r
+#define HASH_CR_ALGO_1                       ((uint32_t)0x00040000)\r
+#define HASH_CR_NBW                          ((uint32_t)0x00000F00)\r
+#define HASH_CR_NBW_0                        ((uint32_t)0x00000100)\r
+#define HASH_CR_NBW_1                        ((uint32_t)0x00000200)\r
+#define HASH_CR_NBW_2                        ((uint32_t)0x00000400)\r
+#define HASH_CR_NBW_3                        ((uint32_t)0x00000800)\r
+#define HASH_CR_DINNE                        ((uint32_t)0x00001000)\r
+#define HASH_CR_MDMAT                        ((uint32_t)0x00002000)\r
+#define HASH_CR_LKEY                         ((uint32_t)0x00010000)\r
+\r
+/******************  Bits definition for HASH_STR register  *******************/\r
+#define HASH_STR_NBW                         ((uint32_t)0x0000001F)\r
+#define HASH_STR_NBW_0                       ((uint32_t)0x00000001)\r
+#define HASH_STR_NBW_1                       ((uint32_t)0x00000002)\r
+#define HASH_STR_NBW_2                       ((uint32_t)0x00000004)\r
+#define HASH_STR_NBW_3                       ((uint32_t)0x00000008)\r
+#define HASH_STR_NBW_4                       ((uint32_t)0x00000010)\r
+#define HASH_STR_DCAL                        ((uint32_t)0x00000100)\r
+\r
+/******************  Bits definition for HASH_IMR register  *******************/\r
+#define HASH_IMR_DINIM                       ((uint32_t)0x00000001)\r
+#define HASH_IMR_DCIM                        ((uint32_t)0x00000002)\r
+\r
+/******************  Bits definition for HASH_SR register  ********************/\r
+#define HASH_SR_DINIS                        ((uint32_t)0x00000001)\r
+#define HASH_SR_DCIS                         ((uint32_t)0x00000002)\r
+#define HASH_SR_DMAS                         ((uint32_t)0x00000004)\r
+#define HASH_SR_BUSY                         ((uint32_t)0x00000008)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      Inter-integrated Circuit Interface                    */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for I2C_CR1 register  ********************/\r
+#define  I2C_CR1_PE                          ((uint16_t)0x0001)            /*!<Peripheral Enable                             */\r
+#define  I2C_CR1_SMBUS                       ((uint16_t)0x0002)            /*!<SMBus Mode                                    */\r
+#define  I2C_CR1_SMBTYPE                     ((uint16_t)0x0008)            /*!<SMBus Type                                    */\r
+#define  I2C_CR1_ENARP                       ((uint16_t)0x0010)            /*!<ARP Enable                                    */\r
+#define  I2C_CR1_ENPEC                       ((uint16_t)0x0020)            /*!<PEC Enable                                    */\r
+#define  I2C_CR1_ENGC                        ((uint16_t)0x0040)            /*!<General Call Enable                           */\r
+#define  I2C_CR1_NOSTRETCH                   ((uint16_t)0x0080)            /*!<Clock Stretching Disable (Slave mode)         */\r
+#define  I2C_CR1_START                       ((uint16_t)0x0100)            /*!<Start Generation                              */\r
+#define  I2C_CR1_STOP                        ((uint16_t)0x0200)            /*!<Stop Generation                               */\r
+#define  I2C_CR1_ACK                         ((uint16_t)0x0400)            /*!<Acknowledge Enable                            */\r
+#define  I2C_CR1_POS                         ((uint16_t)0x0800)            /*!<Acknowledge/PEC Position (for data reception) */\r
+#define  I2C_CR1_PEC                         ((uint16_t)0x1000)            /*!<Packet Error Checking                         */\r
+#define  I2C_CR1_ALERT                       ((uint16_t)0x2000)            /*!<SMBus Alert                                   */\r
+#define  I2C_CR1_SWRST                       ((uint16_t)0x8000)            /*!<Software Reset                                */\r
+\r
+/*******************  Bit definition for I2C_CR2 register  ********************/\r
+#define  I2C_CR2_FREQ                        ((uint16_t)0x003F)            /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */\r
+#define  I2C_CR2_FREQ_0                      ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  I2C_CR2_FREQ_1                      ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  I2C_CR2_FREQ_2                      ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  I2C_CR2_FREQ_3                      ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  I2C_CR2_FREQ_4                      ((uint16_t)0x0010)            /*!<Bit 4 */\r
+#define  I2C_CR2_FREQ_5                      ((uint16_t)0x0020)            /*!<Bit 5 */\r
+\r
+#define  I2C_CR2_ITERREN                     ((uint16_t)0x0100)            /*!<Error Interrupt Enable  */\r
+#define  I2C_CR2_ITEVTEN                     ((uint16_t)0x0200)            /*!<Event Interrupt Enable  */\r
+#define  I2C_CR2_ITBUFEN                     ((uint16_t)0x0400)            /*!<Buffer Interrupt Enable */\r
+#define  I2C_CR2_DMAEN                       ((uint16_t)0x0800)            /*!<DMA Requests Enable     */\r
+#define  I2C_CR2_LAST                        ((uint16_t)0x1000)            /*!<DMA Last Transfer       */\r
+\r
+/*******************  Bit definition for I2C_OAR1 register  *******************/\r
+#define  I2C_OAR1_ADD1_7                     ((uint16_t)0x00FE)            /*!<Interface Address */\r
+#define  I2C_OAR1_ADD8_9                     ((uint16_t)0x0300)            /*!<Interface Address */\r
+\r
+#define  I2C_OAR1_ADD0                       ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  I2C_OAR1_ADD1                       ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  I2C_OAR1_ADD2                       ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  I2C_OAR1_ADD3                       ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  I2C_OAR1_ADD4                       ((uint16_t)0x0010)            /*!<Bit 4 */\r
+#define  I2C_OAR1_ADD5                       ((uint16_t)0x0020)            /*!<Bit 5 */\r
+#define  I2C_OAR1_ADD6                       ((uint16_t)0x0040)            /*!<Bit 6 */\r
+#define  I2C_OAR1_ADD7                       ((uint16_t)0x0080)            /*!<Bit 7 */\r
+#define  I2C_OAR1_ADD8                       ((uint16_t)0x0100)            /*!<Bit 8 */\r
+#define  I2C_OAR1_ADD9                       ((uint16_t)0x0200)            /*!<Bit 9 */\r
+\r
+#define  I2C_OAR1_ADDMODE                    ((uint16_t)0x8000)            /*!<Addressing Mode (Slave mode) */\r
+\r
+/*******************  Bit definition for I2C_OAR2 register  *******************/\r
+#define  I2C_OAR2_ENDUAL                     ((uint8_t)0x01)               /*!<Dual addressing mode enable */\r
+#define  I2C_OAR2_ADD2                       ((uint8_t)0xFE)               /*!<Interface address           */\r
+\r
+/********************  Bit definition for I2C_DR register  ********************/\r
+#define  I2C_DR_DR                           ((uint8_t)0xFF)               /*!<8-bit Data Register         */\r
+\r
+/*******************  Bit definition for I2C_SR1 register  ********************/\r
+#define  I2C_SR1_SB                          ((uint16_t)0x0001)            /*!<Start Bit (Master mode)                         */\r
+#define  I2C_SR1_ADDR                        ((uint16_t)0x0002)            /*!<Address sent (master mode)/matched (slave mode) */\r
+#define  I2C_SR1_BTF                         ((uint16_t)0x0004)            /*!<Byte Transfer Finished                          */\r
+#define  I2C_SR1_ADD10                       ((uint16_t)0x0008)            /*!<10-bit header sent (Master mode)                */\r
+#define  I2C_SR1_STOPF                       ((uint16_t)0x0010)            /*!<Stop detection (Slave mode)                     */\r
+#define  I2C_SR1_RXNE                        ((uint16_t)0x0040)            /*!<Data Register not Empty (receivers)             */\r
+#define  I2C_SR1_TXE                         ((uint16_t)0x0080)            /*!<Data Register Empty (transmitters)              */\r
+#define  I2C_SR1_BERR                        ((uint16_t)0x0100)            /*!<Bus Error                                       */\r
+#define  I2C_SR1_ARLO                        ((uint16_t)0x0200)            /*!<Arbitration Lost (master mode)                  */\r
+#define  I2C_SR1_AF                          ((uint16_t)0x0400)            /*!<Acknowledge Failure                             */\r
+#define  I2C_SR1_OVR                         ((uint16_t)0x0800)            /*!<Overrun/Underrun                                */\r
+#define  I2C_SR1_PECERR                      ((uint16_t)0x1000)            /*!<PEC Error in reception                          */\r
+#define  I2C_SR1_TIMEOUT                     ((uint16_t)0x4000)            /*!<Timeout or Tlow Error                           */\r
+#define  I2C_SR1_SMBALERT                    ((uint16_t)0x8000)            /*!<SMBus Alert                                     */\r
+\r
+/*******************  Bit definition for I2C_SR2 register  ********************/\r
+#define  I2C_SR2_MSL                         ((uint16_t)0x0001)            /*!<Master/Slave                              */\r
+#define  I2C_SR2_BUSY                        ((uint16_t)0x0002)            /*!<Bus Busy                                  */\r
+#define  I2C_SR2_TRA                         ((uint16_t)0x0004)            /*!<Transmitter/Receiver                      */\r
+#define  I2C_SR2_GENCALL                     ((uint16_t)0x0010)            /*!<General Call Address (Slave mode)         */\r
+#define  I2C_SR2_SMBDEFAULT                  ((uint16_t)0x0020)            /*!<SMBus Device Default Address (Slave mode) */\r
+#define  I2C_SR2_SMBHOST                     ((uint16_t)0x0040)            /*!<SMBus Host Header (Slave mode)            */\r
+#define  I2C_SR2_DUALF                       ((uint16_t)0x0080)            /*!<Dual Flag (Slave mode)                    */\r
+#define  I2C_SR2_PEC                         ((uint16_t)0xFF00)            /*!<Packet Error Checking Register            */\r
+\r
+/*******************  Bit definition for I2C_CCR register  ********************/\r
+#define  I2C_CCR_CCR                         ((uint16_t)0x0FFF)            /*!<Clock Control Register in Fast/Standard mode (Master mode) */\r
+#define  I2C_CCR_DUTY                        ((uint16_t)0x4000)            /*!<Fast Mode Duty Cycle                                       */\r
+#define  I2C_CCR_FS                          ((uint16_t)0x8000)            /*!<I2C Master Mode Selection                                  */\r
+\r
+/******************  Bit definition for I2C_TRISE register  *******************/\r
+#define  I2C_TRISE_TRISE                     ((uint8_t)0x3F)               /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */\r
+\r
+/******************  Bit definition for I2C_FLTR register  *******************/\r
+#define  I2C_FLTR_DNF                     ((uint8_t)0x0F)                  /*!<Digital Noise Filter */\r
+#define  I2C_FLTR_ANOFF                   ((uint8_t)0x10)                  /*!<Analog Noise Filter OFF */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           Independent WATCHDOG                             */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for IWDG_KR register  ********************/\r
+#define  IWDG_KR_KEY                         ((uint16_t)0xFFFF)            /*!<Key value (write only, read 0000h)  */\r
+\r
+/*******************  Bit definition for IWDG_PR register  ********************/\r
+#define  IWDG_PR_PR                          ((uint8_t)0x07)               /*!<PR[2:0] (Prescaler divider)         */\r
+#define  IWDG_PR_PR_0                        ((uint8_t)0x01)               /*!<Bit 0 */\r
+#define  IWDG_PR_PR_1                        ((uint8_t)0x02)               /*!<Bit 1 */\r
+#define  IWDG_PR_PR_2                        ((uint8_t)0x04)               /*!<Bit 2 */\r
+\r
+/*******************  Bit definition for IWDG_RLR register  *******************/\r
+#define  IWDG_RLR_RL                         ((uint16_t)0x0FFF)            /*!<Watchdog counter reload value        */\r
+\r
+/*******************  Bit definition for IWDG_SR register  ********************/\r
+#define  IWDG_SR_PVU                         ((uint8_t)0x01)               /*!<Watchdog prescaler value update      */\r
+#define  IWDG_SR_RVU                         ((uint8_t)0x02)               /*!<Watchdog counter reload value update */\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                      LCD-TFT Display Controller (LTDC)                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+\r
+/********************  Bit definition for LTDC_SSCR register  *****************/\r
+\r
+#define LTDC_SSCR_VSH                       ((uint32_t)0x000007FF)              /*!< Vertical Synchronization Height */\r
+#define LTDC_SSCR_HSW                       ((uint32_t)0x0FFF0000)              /*!< Horizontal Synchronization Width */\r
+\r
+/********************  Bit definition for LTDC_BPCR register  *****************/\r
+\r
+#define LTDC_BPCR_AVBP                      ((uint32_t)0x000007FF)              /*!< Accumulated Vertical Back Porch */\r
+#define LTDC_BPCR_AHBP                      ((uint32_t)0x0FFF0000)              /*!< Accumulated Horizontal Back Porch */\r
+\r
+/********************  Bit definition for LTDC_AWCR register  *****************/\r
+\r
+#define LTDC_AWCR_AAH                       ((uint32_t)0x000007FF)              /*!< Accumulated Active heigh */\r
+#define LTDC_AWCR_AAW                       ((uint32_t)0x0FFF0000)              /*!< Accumulated Active Width */\r
+\r
+/********************  Bit definition for LTDC_TWCR register  *****************/\r
+\r
+#define LTDC_TWCR_TOTALH                    ((uint32_t)0x000007FF)              /*!< Total Heigh */\r
+#define LTDC_TWCR_TOTALW                    ((uint32_t)0x0FFF0000)              /*!< Total Width */\r
+\r
+/********************  Bit definition for LTDC_GCR register  ******************/\r
+\r
+#define LTDC_GCR_LTDCEN                     ((uint32_t)0x00000001)              /*!< LCD-TFT controller enable bit */\r
+#define LTDC_GCR_DBW                        ((uint32_t)0x00000070)              /*!< Dither Blue Width */\r
+#define LTDC_GCR_DGW                        ((uint32_t)0x00000700)              /*!< Dither Green Width */\r
+#define LTDC_GCR_DRW                        ((uint32_t)0x00007000)              /*!< Dither Red Width */\r
+#define LTDC_GCR_DTEN                       ((uint32_t)0x00010000)              /*!< Dither Enable */\r
+#define LTDC_GCR_PCPOL                      ((uint32_t)0x10000000)              /*!< Pixel Clock Polarity */\r
+#define LTDC_GCR_DEPOL                      ((uint32_t)0x20000000)              /*!< Data Enable Polarity */\r
+#define LTDC_GCR_VSPOL                      ((uint32_t)0x40000000)              /*!< Vertical Synchronization Polarity */\r
+#define LTDC_GCR_HSPOL                      ((uint32_t)0x80000000)              /*!< Horizontal Synchronization Polarity */\r
+\r
+/********************  Bit definition for LTDC_SRCR register  *****************/\r
+\r
+#define LTDC_SRCR_IMR                      ((uint32_t)0x00000001)               /*!< Immediate Reload */\r
+#define LTDC_SRCR_VBR                      ((uint32_t)0x00000002)               /*!< Vertical Blanking Reload */\r
+\r
+/********************  Bit definition for LTDC_BCCR register  *****************/\r
+\r
+#define LTDC_BCCR_BCBLUE                    ((uint32_t)0x000000FF)              /*!< Background Blue value */\r
+#define LTDC_BCCR_BCGREEN                   ((uint32_t)0x0000FF00)              /*!< Background Green value */\r
+#define LTDC_BCCR_BCRED                     ((uint32_t)0x00FF0000)              /*!< Background Red value */\r
+\r
+/********************  Bit definition for LTDC_IER register  ******************/\r
+\r
+#define LTDC_IER_LIE                        ((uint32_t)0x00000001)              /*!< Line Interrupt Enable */\r
+#define LTDC_IER_FUIE                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Enable */\r
+#define LTDC_IER_TERRIE                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Enable */\r
+#define LTDC_IER_RRIE                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt enable */\r
+\r
+/********************  Bit definition for LTDC_ISR register  ******************/\r
+\r
+#define LTDC_ISR_LIF                        ((uint32_t)0x00000001)              /*!< Line Interrupt Flag */\r
+#define LTDC_ISR_FUIF                       ((uint32_t)0x00000002)              /*!< FIFO Underrun Interrupt Flag */\r
+#define LTDC_ISR_TERRIF                     ((uint32_t)0x00000004)              /*!< Transfer Error Interrupt Flag */\r
+#define LTDC_ISR_RRIF                       ((uint32_t)0x00000008)              /*!< Register Reload interrupt Flag */\r
+\r
+/********************  Bit definition for LTDC_ICR register  ******************/\r
+\r
+#define LTDC_ICR_CLIF                       ((uint32_t)0x00000001)              /*!< Clears the Line Interrupt Flag */\r
+#define LTDC_ICR_CFUIF                      ((uint32_t)0x00000002)              /*!< Clears the FIFO Underrun Interrupt Flag */\r
+#define LTDC_ICR_CTERRIF                    ((uint32_t)0x00000004)              /*!< Clears the Transfer Error Interrupt Flag */\r
+#define LTDC_ICR_CRRIF                      ((uint32_t)0x00000008)              /*!< Clears Register Reload interrupt Flag */\r
+\r
+/********************  Bit definition for LTDC_LIPCR register  ****************/\r
+\r
+#define LTDC_LIPCR_LIPOS                    ((uint32_t)0x000007FF)              /*!< Line Interrupt Position */\r
+\r
+/********************  Bit definition for LTDC_CPSR register  *****************/\r
+\r
+#define LTDC_CPSR_CYPOS                     ((uint32_t)0x0000FFFF)              /*!< Current Y Position */\r
+#define LTDC_CPSR_CXPOS                     ((uint32_t)0xFFFF0000)              /*!< Current X Position */\r
+\r
+/********************  Bit definition for LTDC_CDSR register  *****************/\r
+\r
+#define LTDC_CDSR_VDES                      ((uint32_t)0x00000001)              /*!< Vertical Data Enable Status */\r
+#define LTDC_CDSR_HDES                      ((uint32_t)0x00000002)              /*!< Horizontal Data Enable Status */\r
+#define LTDC_CDSR_VSYNCS                    ((uint32_t)0x00000004)              /*!< Vertical Synchronization Status */\r
+#define LTDC_CDSR_HSYNCS                    ((uint32_t)0x00000008)              /*!< Horizontal Synchronization Status */\r
+\r
+/********************  Bit definition for LTDC_LxCR register  *****************/\r
+\r
+#define LTDC_LxCR_LEN                       ((uint32_t)0x00000001)              /*!< Layer Enable */\r
+#define LTDC_LxCR_COLKEN                    ((uint32_t)0x00000002)              /*!< Color Keying Enable */\r
+#define LTDC_LxCR_CLUTEN                    ((uint32_t)0x00000010)              /*!< Color Lockup Table Enable */\r
+\r
+/********************  Bit definition for LTDC_LxWHPCR register  **************/\r
+\r
+#define LTDC_LxWHPCR_WHSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Horizontal Start Position */\r
+#define LTDC_LxWHPCR_WHSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Horizontal Stop Position */\r
+\r
+/********************  Bit definition for LTDC_LxWVPCR register  **************/\r
+\r
+#define LTDC_LxWVPCR_WVSTPOS                ((uint32_t)0x00000FFF)              /*!< Window Vertical Start Position */\r
+#define LTDC_LxWVPCR_WVSPPOS                ((uint32_t)0xFFFF0000)              /*!< Window Vertical Stop Position */\r
+\r
+/********************  Bit definition for LTDC_LxCKCR register  ***************/\r
+\r
+#define LTDC_LxCKCR_CKBLUE                  ((uint32_t)0x000000FF)              /*!< Color Key Blue value */\r
+#define LTDC_LxCKCR_CKGREEN                 ((uint32_t)0x0000FF00)              /*!< Color Key Green value */\r
+#define LTDC_LxCKCR_CKRED                   ((uint32_t)0x00FF0000)              /*!< Color Key Red value */\r
+\r
+/********************  Bit definition for LTDC_LxPFCR register  ***************/\r
+\r
+#define LTDC_LxPFCR_PF                      ((uint32_t)0x00000007)              /*!< Pixel Format */\r
+\r
+/********************  Bit definition for LTDC_LxCACR register  ***************/\r
+\r
+#define LTDC_LxCACR_CONSTA                  ((uint32_t)0x000000FF)              /*!< Constant Alpha */\r
+\r
+/********************  Bit definition for LTDC_LxDCCR register  ***************/\r
+\r
+#define LTDC_LxDCCR_DCBLUE                  ((uint32_t)0x000000FF)              /*!< Default Color Blue */\r
+#define LTDC_LxDCCR_DCGREEN                 ((uint32_t)0x0000FF00)              /*!< Default Color Green */\r
+#define LTDC_LxDCCR_DCRED                   ((uint32_t)0x00FF0000)              /*!< Default Color Red */\r
+#define LTDC_LxDCCR_DCALPHA                 ((uint32_t)0xFF000000)              /*!< Default Color Alpha */\r
+                                \r
+/********************  Bit definition for LTDC_LxBFCR register  ***************/\r
+\r
+#define LTDC_LxBFCR_BF2                     ((uint32_t)0x00000007)              /*!< Blending Factor 2 */\r
+#define LTDC_LxBFCR_BF1                     ((uint32_t)0x00000700)              /*!< Blending Factor 1 */\r
+\r
+/********************  Bit definition for LTDC_LxCFBAR register  **************/\r
+\r
+#define LTDC_LxCFBAR_CFBADD                 ((uint32_t)0xFFFFFFFF)              /*!< Color Frame Buffer Start Address */\r
+\r
+/********************  Bit definition for LTDC_LxCFBLR register  **************/\r
+\r
+#define LTDC_LxCFBLR_CFBLL                  ((uint32_t)0x00001FFF)              /*!< Color Frame Buffer Line Length */\r
+#define LTDC_LxCFBLR_CFBP                   ((uint32_t)0x1FFF0000)              /*!< Color Frame Buffer Pitch in bytes */\r
+\r
+/********************  Bit definition for LTDC_LxCFBLNR register  *************/\r
+\r
+#define LTDC_LxCFBLNR_CFBLNBR               ((uint32_t)0x000007FF)              /*!< Frame Buffer Line Number */\r
+\r
+/********************  Bit definition for LTDC_LxCLUTWR register  *************/\r
+\r
+#define LTDC_LxCLUTWR_BLUE                  ((uint32_t)0x000000FF)              /*!< Blue value */\r
+#define LTDC_LxCLUTWR_GREEN                 ((uint32_t)0x0000FF00)              /*!< Green value */\r
+#define LTDC_LxCLUTWR_RED                   ((uint32_t)0x00FF0000)              /*!< Red value */\r
+#define LTDC_LxCLUTWR_CLUTADD               ((uint32_t)0xFF000000)              /*!< CLUT address */\r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                             Power Control                                  */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for PWR_CR register  ********************/\r
+#define  PWR_CR_LPDS                         ((uint32_t)0x00000001)     /*!< Low-Power Deepsleep                 */\r
+#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep                */\r
+#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag                   */\r
+#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag                  */\r
+#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable       */\r
+\r
+#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */\r
+#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */\r
+#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */\r
+#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */\r
+\r
+/*!< PVD level configuration */\r
+#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */\r
+#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */\r
+#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */\r
+#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */\r
+#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */\r
+#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */\r
+#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */\r
+#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */\r
+\r
+#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection                     */\r
+#define  PWR_CR_FPDS                         ((uint32_t)0x00000200)     /*!< Flash power down in Stop mode                              */\r
+\r
+#if defined (STM32F429X)\r
+#define  PWR_CR_LPLVDS                       ((uint32_t)0x00000400)     /*!< Low-Power Regulator Low Voltage Scaling in Stop mode       */\r
+#define  PWR_CR_MRLVDS                       ((uint32_t)0x00000800)     /*!< Main regulator Low Voltage Scaling in Stop mode            */\r
+#endif /* STM32F429X */\r
+\r
+#define  PWR_CR_ADCDC1                       ((uint32_t)0x00002000)     /*!< Refer to AN4073 on how to use this bit */ \r
+\r
+#define  PWR_CR_VOS                          ((uint32_t)0x0000C000)     /*!< VOS[1:0] bits (Regulator voltage scaling output selection) */\r
+#define  PWR_CR_VOS_0                        ((uint32_t)0x00004000)     /*!< Bit 0 */\r
+#define  PWR_CR_VOS_1                        ((uint32_t)0x00008000)     /*!< Bit 1 */\r
+\r
+#if defined (STM32F429X)\r
+#define  PWR_CR_ODEN                         ((uint32_t)0x00010000)     /*!< Over Drive enable                   */\r
+#define  PWR_CR_ODSWEN                       ((uint32_t)0x00020000)     /*!< Over Drive switch enabled           */\r
+#define  PWR_CR_UDEN                         ((uint32_t)0x000C0000)     /*!< Under Drive enable in stop mode     */\r
+#define  PWR_CR_UDEN_0                       ((uint32_t)0x00040000)     /*!< Bit 0                               */\r
+#define  PWR_CR_UDEN_1                       ((uint32_t)0x00080000)     /*!< Bit 1                               */\r
+#endif /* STM32F429X */\r
+\r
+/* Legacy define */\r
+#define  PWR_CR_PMODE                        PWR_CR_VOS\r
+\r
+/*******************  Bit definition for PWR_CSR register  ********************/\r
+#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag                                      */\r
+#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag                                     */\r
+#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output                                       */\r
+#define  PWR_CSR_BRR                         ((uint32_t)0x00000008)     /*!< Backup regulator ready                           */\r
+#define  PWR_CSR_EWUP                        ((uint32_t)0x00000100)     /*!< Enable WKUP pin                                  */\r
+#define  PWR_CSR_BRE                         ((uint32_t)0x00000200)     /*!< Backup regulator enable                          */\r
+#define  PWR_CSR_VOSRDY                      ((uint32_t)0x00004000)     /*!< Regulator voltage scaling output selection ready */\r
+\r
+#if defined (STM32F429X)\r
+#define  PWR_CSR_ODRDY                       ((uint32_t)0x00010000)     /*!< Over Drive generator ready                       */\r
+#define  PWR_CSR_ODSWRDY                     ((uint32_t)0x00020000)     /*!< Over Drive Switch ready                          */\r
+#define  PWR_CSR_UDSWRDY                     ((uint32_t)0x000C0000)     /*!< Under Drive ready                                */\r
+#endif /* STM32F429X */\r
+/* Legacy define */\r
+#define  PWR_CSR_REGRDY                      PWR_CSR_VOSRDY\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                         Reset and Clock Control                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for RCC_CR register  ********************/\r
+#define  RCC_CR_HSION                        ((uint32_t)0x00000001)\r
+#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)\r
+\r
+#define  RCC_CR_HSITRIM                      ((uint32_t)0x000000F8)\r
+#define  RCC_CR_HSITRIM_0                    ((uint32_t)0x00000008)/*!<Bit 0 */\r
+#define  RCC_CR_HSITRIM_1                    ((uint32_t)0x00000010)/*!<Bit 1 */\r
+#define  RCC_CR_HSITRIM_2                    ((uint32_t)0x00000020)/*!<Bit 2 */\r
+#define  RCC_CR_HSITRIM_3                    ((uint32_t)0x00000040)/*!<Bit 3 */\r
+#define  RCC_CR_HSITRIM_4                    ((uint32_t)0x00000080)/*!<Bit 4 */\r
+\r
+#define  RCC_CR_HSICAL                       ((uint32_t)0x0000FF00)\r
+#define  RCC_CR_HSICAL_0                     ((uint32_t)0x00000100)/*!<Bit 0 */\r
+#define  RCC_CR_HSICAL_1                     ((uint32_t)0x00000200)/*!<Bit 1 */\r
+#define  RCC_CR_HSICAL_2                     ((uint32_t)0x00000400)/*!<Bit 2 */\r
+#define  RCC_CR_HSICAL_3                     ((uint32_t)0x00000800)/*!<Bit 3 */\r
+#define  RCC_CR_HSICAL_4                     ((uint32_t)0x00001000)/*!<Bit 4 */\r
+#define  RCC_CR_HSICAL_5                     ((uint32_t)0x00002000)/*!<Bit 5 */\r
+#define  RCC_CR_HSICAL_6                     ((uint32_t)0x00004000)/*!<Bit 6 */\r
+#define  RCC_CR_HSICAL_7                     ((uint32_t)0x00008000)/*!<Bit 7 */\r
+\r
+#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)\r
+#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)\r
+#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)\r
+#define  RCC_CR_CSSON                        ((uint32_t)0x00080000)\r
+#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)\r
+#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)\r
+#define  RCC_CR_PLLI2SON                     ((uint32_t)0x04000000)\r
+#define  RCC_CR_PLLI2SRDY                    ((uint32_t)0x08000000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_CR_PLLSAION                     ((uint32_t)0x10000000)\r
+#define  RCC_CR_PLLSAIRDY                    ((uint32_t)0x20000000)\r
+#endif /* STM32F429X */\r
+\r
+/********************  Bit definition for RCC_PLLCFGR register  ***************/\r
+#define  RCC_PLLCFGR_PLLM                    ((uint32_t)0x0000003F)\r
+#define  RCC_PLLCFGR_PLLM_0                  ((uint32_t)0x00000001)\r
+#define  RCC_PLLCFGR_PLLM_1                  ((uint32_t)0x00000002)\r
+#define  RCC_PLLCFGR_PLLM_2                  ((uint32_t)0x00000004)\r
+#define  RCC_PLLCFGR_PLLM_3                  ((uint32_t)0x00000008)\r
+#define  RCC_PLLCFGR_PLLM_4                  ((uint32_t)0x00000010)\r
+#define  RCC_PLLCFGR_PLLM_5                  ((uint32_t)0x00000020)\r
+\r
+#define  RCC_PLLCFGR_PLLN                     ((uint32_t)0x00007FC0)\r
+#define  RCC_PLLCFGR_PLLN_0                   ((uint32_t)0x00000040)\r
+#define  RCC_PLLCFGR_PLLN_1                   ((uint32_t)0x00000080)\r
+#define  RCC_PLLCFGR_PLLN_2                   ((uint32_t)0x00000100)\r
+#define  RCC_PLLCFGR_PLLN_3                   ((uint32_t)0x00000200)\r
+#define  RCC_PLLCFGR_PLLN_4                   ((uint32_t)0x00000400)\r
+#define  RCC_PLLCFGR_PLLN_5                   ((uint32_t)0x00000800)\r
+#define  RCC_PLLCFGR_PLLN_6                   ((uint32_t)0x00001000)\r
+#define  RCC_PLLCFGR_PLLN_7                   ((uint32_t)0x00002000)\r
+#define  RCC_PLLCFGR_PLLN_8                   ((uint32_t)0x00004000)\r
+\r
+#define  RCC_PLLCFGR_PLLP                    ((uint32_t)0x00030000)\r
+#define  RCC_PLLCFGR_PLLP_0                  ((uint32_t)0x00010000)\r
+#define  RCC_PLLCFGR_PLLP_1                  ((uint32_t)0x00020000)\r
+\r
+#define  RCC_PLLCFGR_PLLSRC                  ((uint32_t)0x00400000)\r
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32_t)0x00400000)\r
+#define  RCC_PLLCFGR_PLLSRC_HSI              ((uint32_t)0x00000000)\r
+\r
+#define  RCC_PLLCFGR_PLLQ                    ((uint32_t)0x0F000000)\r
+#define  RCC_PLLCFGR_PLLQ_0                  ((uint32_t)0x01000000)\r
+#define  RCC_PLLCFGR_PLLQ_1                  ((uint32_t)0x02000000)\r
+#define  RCC_PLLCFGR_PLLQ_2                  ((uint32_t)0x04000000)\r
+#define  RCC_PLLCFGR_PLLQ_3                  ((uint32_t)0x08000000)\r
+\r
+/********************  Bit definition for RCC_CFGR register  ******************/\r
+/*!< SW configuration */\r
+#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */\r
+#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */\r
+#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */\r
+\r
+#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000000)        /*!< HSI selected as system clock */\r
+#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000001)        /*!< HSE selected as system clock */\r
+#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000002)        /*!< PLL selected as system clock */\r
+\r
+/*!< SWS configuration */\r
+#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */\r
+#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */\r
+#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */\r
+\r
+#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000000)        /*!< HSI oscillator used as system clock */\r
+#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000004)        /*!< HSE oscillator used as system clock */\r
+#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x00000008)        /*!< PLL used as system clock */\r
+\r
+/*!< HPRE configuration */\r
+#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */\r
+#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */\r
+#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */\r
+#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */\r
+#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */\r
+\r
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */\r
+#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */\r
+#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */\r
+#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */\r
+#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */\r
+#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */\r
+#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */\r
+#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */\r
+#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */\r
+\r
+/*!< PPRE1 configuration */\r
+#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00001C00)        /*!< PRE1[2:0] bits (APB1 prescaler) */\r
+#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000400)        /*!< Bit 0 */\r
+#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000800)        /*!< Bit 1 */\r
+#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00001000)        /*!< Bit 2 */\r
+\r
+#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\r
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00001000)        /*!< HCLK divided by 2 */\r
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00001400)        /*!< HCLK divided by 4 */\r
+#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00001800)        /*!< HCLK divided by 8 */\r
+#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00001C00)        /*!< HCLK divided by 16 */\r
+\r
+/*!< PPRE2 configuration */\r
+#define  RCC_CFGR_PPRE2                      ((uint32_t)0x0000E000)        /*!< PRE2[2:0] bits (APB2 prescaler) */\r
+#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00002000)        /*!< Bit 0 */\r
+#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00004000)        /*!< Bit 1 */\r
+#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00008000)        /*!< Bit 2 */\r
+\r
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */\r
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00008000)        /*!< HCLK divided by 2 */\r
+#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x0000A000)        /*!< HCLK divided by 4 */\r
+#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x0000C000)        /*!< HCLK divided by 8 */\r
+#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x0000E000)        /*!< HCLK divided by 16 */\r
+\r
+/*!< RTCPRE configuration */\r
+#define  RCC_CFGR_RTCPRE                     ((uint32_t)0x001F0000)\r
+#define  RCC_CFGR_RTCPRE_0                   ((uint32_t)0x00010000)\r
+#define  RCC_CFGR_RTCPRE_1                   ((uint32_t)0x00020000)\r
+#define  RCC_CFGR_RTCPRE_2                   ((uint32_t)0x00040000)\r
+#define  RCC_CFGR_RTCPRE_3                   ((uint32_t)0x00080000)\r
+#define  RCC_CFGR_RTCPRE_4                   ((uint32_t)0x00100000)\r
+\r
+/*!< MCO1 configuration */\r
+#define  RCC_CFGR_MCO1                       ((uint32_t)0x00600000)\r
+#define  RCC_CFGR_MCO1_0                     ((uint32_t)0x00200000)\r
+#define  RCC_CFGR_MCO1_1                     ((uint32_t)0x00400000)\r
+\r
+#define  RCC_CFGR_I2SSRC                     ((uint32_t)0x00800000)\r
+\r
+#define  RCC_CFGR_MCO1PRE                    ((uint32_t)0x07000000)\r
+#define  RCC_CFGR_MCO1PRE_0                  ((uint32_t)0x01000000)\r
+#define  RCC_CFGR_MCO1PRE_1                  ((uint32_t)0x02000000)\r
+#define  RCC_CFGR_MCO1PRE_2                  ((uint32_t)0x04000000)\r
+\r
+#define  RCC_CFGR_MCO2PRE                    ((uint32_t)0x38000000)\r
+#define  RCC_CFGR_MCO2PRE_0                  ((uint32_t)0x08000000)\r
+#define  RCC_CFGR_MCO2PRE_1                  ((uint32_t)0x10000000)\r
+#define  RCC_CFGR_MCO2PRE_2                  ((uint32_t)0x20000000)\r
+\r
+#define  RCC_CFGR_MCO2                       ((uint32_t)0xC0000000)\r
+#define  RCC_CFGR_MCO2_0                     ((uint32_t)0x40000000)\r
+#define  RCC_CFGR_MCO2_1                     ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_CIR register  *******************/\r
+#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)\r
+#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)\r
+#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)\r
+#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)\r
+#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)\r
+#define  RCC_CIR_PLLI2SRDYF                  ((uint32_t)0x00000020)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_CIR_PLLSAIRDYF                  ((uint32_t)0x00000040)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)\r
+#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)\r
+#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)\r
+#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)\r
+#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)\r
+#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)\r
+#define  RCC_CIR_PLLI2SRDYIE                 ((uint32_t)0x00002000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_CIR_PLLSAIRDYIE                 ((uint32_t)0x00004000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)\r
+#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)\r
+#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)\r
+#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)\r
+#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)\r
+#define  RCC_CIR_PLLI2SRDYC                  ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_CIR_PLLSAIRDYC                  ((uint32_t)0x00400000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)\r
+\r
+/********************  Bit definition for RCC_AHB1RSTR register  **************/\r
+#define  RCC_AHB1RSTR_GPIOARST               ((uint32_t)0x00000001)\r
+#define  RCC_AHB1RSTR_GPIOBRST               ((uint32_t)0x00000002)\r
+#define  RCC_AHB1RSTR_GPIOCRST               ((uint32_t)0x00000004)\r
+#define  RCC_AHB1RSTR_GPIODRST               ((uint32_t)0x00000008)\r
+#define  RCC_AHB1RSTR_GPIOERST               ((uint32_t)0x00000010)\r
+#define  RCC_AHB1RSTR_GPIOFRST               ((uint32_t)0x00000020)\r
+#define  RCC_AHB1RSTR_GPIOGRST               ((uint32_t)0x00000040)\r
+#define  RCC_AHB1RSTR_GPIOHRST               ((uint32_t)0x00000080)\r
+#define  RCC_AHB1RSTR_GPIOIRST               ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1RSTR_GPIOJRST               ((uint32_t)0x00000200)\r
+#define  RCC_AHB1RSTR_GPIOKRST               ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1RSTR_CRCRST                 ((uint32_t)0x00001000)\r
+#define  RCC_AHB1RSTR_DMA1RST                ((uint32_t)0x00200000)\r
+#define  RCC_AHB1RSTR_DMA2RST                ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1RSTR_DMA2DRST               ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1RSTR_ETHMACRST              ((uint32_t)0x02000000)\r
+#define  RCC_AHB1RSTR_OTGHRST                ((uint32_t)0x10000000)\r
+\r
+/********************  Bit definition for RCC_AHB2RSTR register  **************/\r
+#define  RCC_AHB2RSTR_DCMIRST                ((uint32_t)0x00000001)\r
+#define  RCC_AHB2RSTR_CRYPRST                ((uint32_t)0x00000010)\r
+#define  RCC_AHB2RSTR_HASHRST                ((uint32_t)0x00000020)\r
+ /* maintained for legacy purpose */\r
+ #define  RCC_AHB2RSTR_HSAHRST                RCC_AHB2RSTR_HASHRST\r
+#define  RCC_AHB2RSTR_RNGRST                 ((uint32_t)0x00000040)\r
+#define  RCC_AHB2RSTR_OTGFSRST               ((uint32_t)0x00000080)\r
+\r
+/********************  Bit definition for RCC_AHB3RSTR register  **************/\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define  RCC_AHB3RSTR_FSMCRST                ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB3RSTR_FMCRST                ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+/********************  Bit definition for RCC_APB1RSTR register  **************/\r
+#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)\r
+#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)\r
+#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)\r
+#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)\r
+#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)\r
+#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)\r
+#define  RCC_APB1RSTR_TIM12RST               ((uint32_t)0x00000040)\r
+#define  RCC_APB1RSTR_TIM13RST               ((uint32_t)0x00000080)\r
+#define  RCC_APB1RSTR_TIM14RST               ((uint32_t)0x00000100)\r
+#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)\r
+#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)\r
+#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)\r
+#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)\r
+#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)\r
+#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)\r
+#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)\r
+#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)\r
+#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)\r
+#define  RCC_APB1RSTR_I2C3RST                ((uint32_t)0x00800000)\r
+#define  RCC_APB1RSTR_CAN1RST                ((uint32_t)0x02000000)\r
+#define  RCC_APB1RSTR_CAN2RST                ((uint32_t)0x04000000)\r
+#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)\r
+#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)\r
+#define  RCC_APB1RSTR_UART7RST               ((uint32_t)0x40000000)\r
+#define  RCC_APB1RSTR_UART8RST               ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_APB2RSTR register  **************/\r
+#define  RCC_APB2RSTR_TIM1RST                ((uint32_t)0x00000001)\r
+#define  RCC_APB2RSTR_TIM8RST                ((uint32_t)0x00000002)\r
+#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00000010)\r
+#define  RCC_APB2RSTR_USART6RST              ((uint32_t)0x00000020)\r
+#define  RCC_APB2RSTR_ADCRST                 ((uint32_t)0x00000100)\r
+#define  RCC_APB2RSTR_SDIORST                ((uint32_t)0x00000800)\r
+#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)\r
+#define  RCC_APB2RSTR_SPI4RST                ((uint32_t)0x00002000)\r
+#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00004000)\r
+#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00010000)\r
+#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00020000)\r
+#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00040000)\r
+#define  RCC_APB2RSTR_SPI5RST                ((uint32_t)0x00100000)\r
+#define  RCC_APB2RSTR_SPI6RST                ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_APB2RSTR_SAI1RST                ((uint32_t)0x00400000)\r
+#define  RCC_APB2RSTR_LTDCRST                ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/* Old SPI1RST bit definition, maintained for legacy purpose */\r
+#define  RCC_APB2RSTR_SPI1                   RCC_APB2RSTR_SPI1RST\r
+\r
+/********************  Bit definition for RCC_AHB1ENR register  ***************/\r
+#define  RCC_AHB1ENR_GPIOAEN                 ((uint32_t)0x00000001)\r
+#define  RCC_AHB1ENR_GPIOBEN                 ((uint32_t)0x00000002)\r
+#define  RCC_AHB1ENR_GPIOCEN                 ((uint32_t)0x00000004)\r
+#define  RCC_AHB1ENR_GPIODEN                 ((uint32_t)0x00000008)\r
+#define  RCC_AHB1ENR_GPIOEEN                 ((uint32_t)0x00000010)\r
+#define  RCC_AHB1ENR_GPIOFEN                 ((uint32_t)0x00000020)\r
+#define  RCC_AHB1ENR_GPIOGEN                 ((uint32_t)0x00000040)\r
+#define  RCC_AHB1ENR_GPIOHEN                 ((uint32_t)0x00000080)\r
+#define  RCC_AHB1ENR_GPIOIEN                 ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1ENR_GPIOJEN                 ((uint32_t)0x00000200)\r
+#define  RCC_AHB1ENR_GPIOKEN                 ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1ENR_CRCEN                   ((uint32_t)0x00001000)\r
+#define  RCC_AHB1ENR_BKPSRAMEN               ((uint32_t)0x00040000)\r
+#define  RCC_AHB1ENR_CCMDATARAMEN            ((uint32_t)0x00100000)\r
+#define  RCC_AHB1ENR_DMA1EN                  ((uint32_t)0x00200000)\r
+#define  RCC_AHB1ENR_DMA2EN                  ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1ENR_DMA2DEN                 ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1ENR_ETHMACEN                ((uint32_t)0x02000000)\r
+#define  RCC_AHB1ENR_ETHMACTXEN              ((uint32_t)0x04000000)\r
+#define  RCC_AHB1ENR_ETHMACRXEN              ((uint32_t)0x08000000)\r
+#define  RCC_AHB1ENR_ETHMACPTPEN             ((uint32_t)0x10000000)\r
+#define  RCC_AHB1ENR_OTGHSEN                 ((uint32_t)0x20000000)\r
+#define  RCC_AHB1ENR_OTGHSULPIEN             ((uint32_t)0x40000000)\r
+\r
+/********************  Bit definition for RCC_AHB2ENR register  ***************/\r
+#define  RCC_AHB2ENR_DCMIEN                  ((uint32_t)0x00000001)\r
+#define  RCC_AHB2ENR_CRYPEN                  ((uint32_t)0x00000010)\r
+#define  RCC_AHB2ENR_HASHEN                  ((uint32_t)0x00000020)\r
+#define  RCC_AHB2ENR_RNGEN                   ((uint32_t)0x00000040)\r
+#define  RCC_AHB2ENR_OTGFSEN                 ((uint32_t)0x00000080)\r
+\r
+/********************  Bit definition for RCC_AHB3ENR register  ***************/\r
+\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define  RCC_AHB3ENR_FSMCEN                  ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB3ENR_FMCEN                  ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+\r
+/********************  Bit definition for RCC_APB1ENR register  ***************/\r
+#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)\r
+#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)\r
+#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)\r
+#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)\r
+#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)\r
+#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)\r
+#define  RCC_APB1ENR_TIM12EN                 ((uint32_t)0x00000040)\r
+#define  RCC_APB1ENR_TIM13EN                 ((uint32_t)0x00000080)\r
+#define  RCC_APB1ENR_TIM14EN                 ((uint32_t)0x00000100)\r
+#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)\r
+#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)\r
+#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)\r
+#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)\r
+#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)\r
+#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)\r
+#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)\r
+#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)\r
+#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)\r
+#define  RCC_APB1ENR_I2C3EN                  ((uint32_t)0x00800000)\r
+#define  RCC_APB1ENR_CAN1EN                  ((uint32_t)0x02000000)\r
+#define  RCC_APB1ENR_CAN2EN                  ((uint32_t)0x04000000)\r
+#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)\r
+#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)\r
+#define  RCC_APB1ENR_UART7EN                 ((uint32_t)0x40000000)\r
+#define  RCC_APB1ENR_UART8EN                 ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_APB2ENR register  ***************/\r
+#define  RCC_APB2ENR_TIM1EN                  ((uint32_t)0x00000001)\r
+#define  RCC_APB2ENR_TIM8EN                  ((uint32_t)0x00000002)\r
+#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00000010)\r
+#define  RCC_APB2ENR_USART6EN                ((uint32_t)0x00000020)\r
+#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000100)\r
+#define  RCC_APB2ENR_ADC2EN                  ((uint32_t)0x00000200)\r
+#define  RCC_APB2ENR_ADC3EN                  ((uint32_t)0x00000400)\r
+#define  RCC_APB2ENR_SDIOEN                  ((uint32_t)0x00000800)\r
+#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)\r
+#define  RCC_APB2ENR_SPI4EN                  ((uint32_t)0x00002000)\r
+#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00004000)\r
+#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00010000)\r
+#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00020000)\r
+#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00040000)\r
+#define  RCC_APB2ENR_SPI5EN                  ((uint32_t)0x00100000)\r
+#define  RCC_APB2ENR_SPI6EN                  ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_APB2ENR_SAI1EN                  ((uint32_t)0x00400000)\r
+#define  RCC_APB2ENR_LTDCEN                  ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/********************  Bit definition for RCC_AHB1LPENR register  *************/\r
+#define  RCC_AHB1LPENR_GPIOALPEN             ((uint32_t)0x00000001)\r
+#define  RCC_AHB1LPENR_GPIOBLPEN             ((uint32_t)0x00000002)\r
+#define  RCC_AHB1LPENR_GPIOCLPEN             ((uint32_t)0x00000004)\r
+#define  RCC_AHB1LPENR_GPIODLPEN             ((uint32_t)0x00000008)\r
+#define  RCC_AHB1LPENR_GPIOELPEN             ((uint32_t)0x00000010)\r
+#define  RCC_AHB1LPENR_GPIOFLPEN             ((uint32_t)0x00000020)\r
+#define  RCC_AHB1LPENR_GPIOGLPEN             ((uint32_t)0x00000040)\r
+#define  RCC_AHB1LPENR_GPIOHLPEN             ((uint32_t)0x00000080)\r
+#define  RCC_AHB1LPENR_GPIOILPEN             ((uint32_t)0x00000100)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1LPENR_GPIOJLPEN             ((uint32_t)0x00000200)\r
+#define  RCC_AHB1LPENR_GPIOKLPEN             ((uint32_t)0x00000400)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1LPENR_CRCLPEN               ((uint32_t)0x00001000)\r
+#define  RCC_AHB1LPENR_FLITFLPEN             ((uint32_t)0x00008000)\r
+#define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)\r
+#define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)\r
+#define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)\r
+#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)\r
+#define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)\r
+#define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB1LPENR_DMA2DLPEN             ((uint32_t)0x00800000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_AHB1LPENR_ETHMACLPEN            ((uint32_t)0x02000000)\r
+#define  RCC_AHB1LPENR_ETHMACTXLPEN          ((uint32_t)0x04000000)\r
+#define  RCC_AHB1LPENR_ETHMACRXLPEN          ((uint32_t)0x08000000)\r
+#define  RCC_AHB1LPENR_ETHMACPTPLPEN         ((uint32_t)0x10000000)\r
+#define  RCC_AHB1LPENR_OTGHSLPEN             ((uint32_t)0x20000000)\r
+#define  RCC_AHB1LPENR_OTGHSULPILPEN         ((uint32_t)0x40000000)\r
+\r
+/********************  Bit definition for RCC_AHB2LPENR register  *************/\r
+#define  RCC_AHB2LPENR_DCMILPEN              ((uint32_t)0x00000001)\r
+#define  RCC_AHB2LPENR_CRYPLPEN              ((uint32_t)0x00000010)\r
+#define  RCC_AHB2LPENR_HASHLPEN              ((uint32_t)0x00000020)\r
+#define  RCC_AHB2LPENR_RNGLPEN               ((uint32_t)0x00000040)\r
+#define  RCC_AHB2LPENR_OTGFSLPEN             ((uint32_t)0x00000080)\r
+\r
+/********************  Bit definition for RCC_AHB3LPENR register  *************/\r
+#if defined(STM32F40XX) || defined(STM32F427X)\r
+#define  RCC_AHB3LPENR_FSMCLPEN              ((uint32_t)0x00000001)\r
+#endif /* STM32F40XX || STM32F427X */\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_AHB3LPENR_FMCLPEN              ((uint32_t)0x00000001)\r
+#endif /* STM32F429X */\r
+\r
+/********************  Bit definition for RCC_APB1LPENR register  *************/\r
+#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)\r
+#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)\r
+#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)\r
+#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)\r
+#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)\r
+#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)\r
+#define  RCC_APB1LPENR_TIM12LPEN             ((uint32_t)0x00000040)\r
+#define  RCC_APB1LPENR_TIM13LPEN             ((uint32_t)0x00000080)\r
+#define  RCC_APB1LPENR_TIM14LPEN             ((uint32_t)0x00000100)\r
+#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)\r
+#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)\r
+#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)\r
+#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)\r
+#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)\r
+#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)\r
+#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)\r
+#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)\r
+#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)\r
+#define  RCC_APB1LPENR_I2C3LPEN              ((uint32_t)0x00800000)\r
+#define  RCC_APB1LPENR_CAN1LPEN              ((uint32_t)0x02000000)\r
+#define  RCC_APB1LPENR_CAN2LPEN              ((uint32_t)0x04000000)\r
+#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)\r
+#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)\r
+#define  RCC_APB1LPENR_UART7LPEN             ((uint32_t)0x40000000)\r
+#define  RCC_APB1LPENR_UART8LPEN             ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_APB2LPENR register  *************/\r
+#define  RCC_APB2LPENR_TIM1LPEN              ((uint32_t)0x00000001)\r
+#define  RCC_APB2LPENR_TIM8LPEN              ((uint32_t)0x00000002)\r
+#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00000010)\r
+#define  RCC_APB2LPENR_USART6LPEN            ((uint32_t)0x00000020)\r
+#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000100)\r
+#define  RCC_APB2LPENR_ADC2PEN               ((uint32_t)0x00000200)\r
+#define  RCC_APB2LPENR_ADC3LPEN              ((uint32_t)0x00000400)\r
+#define  RCC_APB2LPENR_SDIOLPEN              ((uint32_t)0x00000800)\r
+#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)\r
+#define  RCC_APB2LPENR_SPI4LPEN              ((uint32_t)0x00002000)\r
+#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00004000)\r
+#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00010000)\r
+#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00020000)\r
+#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00040000)\r
+#define  RCC_APB2LPENR_SPI5LPEN              ((uint32_t)0x00100000)\r
+#define  RCC_APB2LPENR_SPI6LPEN              ((uint32_t)0x00200000)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_APB2LPENR_SAI1LPEN              ((uint32_t)0x00400000)\r
+#define  RCC_APB2LPENR_LTDCLPEN              ((uint32_t)0x04000000)\r
+#endif /* STM32F429X */\r
+\r
+/********************  Bit definition for RCC_BDCR register  ******************/\r
+#define  RCC_BDCR_LSEON                      ((uint32_t)0x00000001)\r
+#define  RCC_BDCR_LSERDY                     ((uint32_t)0x00000002)\r
+#define  RCC_BDCR_LSEBYP                     ((uint32_t)0x00000004)\r
+\r
+#define  RCC_BDCR_RTCSEL                    ((uint32_t)0x00000300)\r
+#define  RCC_BDCR_RTCSEL_0                  ((uint32_t)0x00000100)\r
+#define  RCC_BDCR_RTCSEL_1                  ((uint32_t)0x00000200)\r
+\r
+#define  RCC_BDCR_RTCEN                      ((uint32_t)0x00008000)\r
+#define  RCC_BDCR_BDRST                      ((uint32_t)0x00010000)\r
+\r
+/********************  Bit definition for RCC_CSR register  *******************/\r
+#define  RCC_CSR_LSION                       ((uint32_t)0x00000001)\r
+#define  RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)\r
+#define  RCC_CSR_RMVF                        ((uint32_t)0x01000000)\r
+#define  RCC_CSR_BORRSTF                     ((uint32_t)0x02000000)\r
+#define  RCC_CSR_PADRSTF                     ((uint32_t)0x04000000)\r
+#define  RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)\r
+#define  RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)\r
+#define  RCC_CSR_WDGRSTF                     ((uint32_t)0x20000000)\r
+#define  RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)\r
+#define  RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_SSCGR register  *****************/\r
+#define  RCC_SSCGR_MODPER                    ((uint32_t)0x00001FFF)\r
+#define  RCC_SSCGR_INCSTEP                   ((uint32_t)0x0FFFE000)\r
+#define  RCC_SSCGR_SPREADSEL                 ((uint32_t)0x40000000)\r
+#define  RCC_SSCGR_SSCGEN                    ((uint32_t)0x80000000)\r
+\r
+/********************  Bit definition for RCC_PLLI2SCFGR register  ************/\r
+#define  RCC_PLLI2SCFGR_PLLI2SN              ((uint32_t)0x00007FC0)\r
+\r
+#if defined (STM32F429X)\r
+#define  RCC_PLLI2SCFGR_PLLI2SQ              ((uint32_t)0x0F000000)\r
+#endif /* STM32F429X */\r
+\r
+#define  RCC_PLLI2SCFGR_PLLI2SR              ((uint32_t)0x70000000)\r
+\r
+#if defined (STM32F429X)\r
+/********************  Bit definition for RCC_PLLSAICFGR register  ************/\r
+#define  RCC_PLLSAICFGR_PLLI2SN              ((uint32_t)0x00007FC0)\r
+#define  RCC_PLLSAICFGR_PLLI2SQ              ((uint32_t)0x0F000000)\r
+#define  RCC_PLLSAICFGR_PLLI2SR              ((uint32_t)0x70000000)\r
+\r
+/********************  Bit definition for RCC_DCKCFGR register  ***************/\r
+#define  RCC_DCKCFGR_PLLI2SDIVQ              ((uint32_t)0x0000001F)\r
+#define  RCC_DCKCFGR_PLLSAIDIVQ              ((uint32_t)0x00001F00)\r
+#define  RCC_DCKCFGR_PLLSAIDIVR              ((uint32_t)0x00030000)\r
+#define  RCC_DCKCFGR_SAI1ASRC                ((uint32_t)0x00300000)\r
+#define  RCC_DCKCFGR_SAI1BSRC                ((uint32_t)0x00C00000)\r
+#endif /* STM32F429X */\r
+#define  RCC_DCKCFGR_TIMPRE                  ((uint32_t)0x01000000)\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    RNG                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for RNG_CR register  *******************/\r
+#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)\r
+#define RNG_CR_IE                            ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RNG_SR register  *******************/\r
+#define RNG_SR_DRDY                          ((uint32_t)0x00000001)\r
+#define RNG_SR_CECS                          ((uint32_t)0x00000002)\r
+#define RNG_SR_SECS                          ((uint32_t)0x00000004)\r
+#define RNG_SR_CEIS                          ((uint32_t)0x00000020)\r
+#define RNG_SR_SEIS                          ((uint32_t)0x00000040)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                           Real-Time Clock (RTC)                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bits definition for RTC_TR register  *******************/\r
+#define RTC_TR_PM                            ((uint32_t)0x00400000)\r
+#define RTC_TR_HT                            ((uint32_t)0x00300000)\r
+#define RTC_TR_HT_0                          ((uint32_t)0x00100000)\r
+#define RTC_TR_HT_1                          ((uint32_t)0x00200000)\r
+#define RTC_TR_HU                            ((uint32_t)0x000F0000)\r
+#define RTC_TR_HU_0                          ((uint32_t)0x00010000)\r
+#define RTC_TR_HU_1                          ((uint32_t)0x00020000)\r
+#define RTC_TR_HU_2                          ((uint32_t)0x00040000)\r
+#define RTC_TR_HU_3                          ((uint32_t)0x00080000)\r
+#define RTC_TR_MNT                           ((uint32_t)0x00007000)\r
+#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)\r
+#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)\r
+#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)\r
+#define RTC_TR_MNU                           ((uint32_t)0x00000F00)\r
+#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)\r
+#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)\r
+#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)\r
+#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)\r
+#define RTC_TR_ST                            ((uint32_t)0x00000070)\r
+#define RTC_TR_ST_0                          ((uint32_t)0x00000010)\r
+#define RTC_TR_ST_1                          ((uint32_t)0x00000020)\r
+#define RTC_TR_ST_2                          ((uint32_t)0x00000040)\r
+#define RTC_TR_SU                            ((uint32_t)0x0000000F)\r
+#define RTC_TR_SU_0                          ((uint32_t)0x00000001)\r
+#define RTC_TR_SU_1                          ((uint32_t)0x00000002)\r
+#define RTC_TR_SU_2                          ((uint32_t)0x00000004)\r
+#define RTC_TR_SU_3                          ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_DR register  *******************/\r
+#define RTC_DR_YT                            ((uint32_t)0x00F00000)\r
+#define RTC_DR_YT_0                          ((uint32_t)0x00100000)\r
+#define RTC_DR_YT_1                          ((uint32_t)0x00200000)\r
+#define RTC_DR_YT_2                          ((uint32_t)0x00400000)\r
+#define RTC_DR_YT_3                          ((uint32_t)0x00800000)\r
+#define RTC_DR_YU                            ((uint32_t)0x000F0000)\r
+#define RTC_DR_YU_0                          ((uint32_t)0x00010000)\r
+#define RTC_DR_YU_1                          ((uint32_t)0x00020000)\r
+#define RTC_DR_YU_2                          ((uint32_t)0x00040000)\r
+#define RTC_DR_YU_3                          ((uint32_t)0x00080000)\r
+#define RTC_DR_WDU                           ((uint32_t)0x0000E000)\r
+#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)\r
+#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)\r
+#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)\r
+#define RTC_DR_MT                            ((uint32_t)0x00001000)\r
+#define RTC_DR_MU                            ((uint32_t)0x00000F00)\r
+#define RTC_DR_MU_0                          ((uint32_t)0x00000100)\r
+#define RTC_DR_MU_1                          ((uint32_t)0x00000200)\r
+#define RTC_DR_MU_2                          ((uint32_t)0x00000400)\r
+#define RTC_DR_MU_3                          ((uint32_t)0x00000800)\r
+#define RTC_DR_DT                            ((uint32_t)0x00000030)\r
+#define RTC_DR_DT_0                          ((uint32_t)0x00000010)\r
+#define RTC_DR_DT_1                          ((uint32_t)0x00000020)\r
+#define RTC_DR_DU                            ((uint32_t)0x0000000F)\r
+#define RTC_DR_DU_0                          ((uint32_t)0x00000001)\r
+#define RTC_DR_DU_1                          ((uint32_t)0x00000002)\r
+#define RTC_DR_DU_2                          ((uint32_t)0x00000004)\r
+#define RTC_DR_DU_3                          ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_CR register  *******************/\r
+#define RTC_CR_COE                           ((uint32_t)0x00800000)\r
+#define RTC_CR_OSEL                          ((uint32_t)0x00600000)\r
+#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)\r
+#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)\r
+#define RTC_CR_POL                           ((uint32_t)0x00100000)\r
+#define RTC_CR_COSEL                         ((uint32_t)0x00080000)\r
+#define RTC_CR_BCK                           ((uint32_t)0x00040000)\r
+#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)\r
+#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)\r
+#define RTC_CR_TSIE                          ((uint32_t)0x00008000)\r
+#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)\r
+#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)\r
+#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)\r
+#define RTC_CR_TSE                           ((uint32_t)0x00000800)\r
+#define RTC_CR_WUTE                          ((uint32_t)0x00000400)\r
+#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)\r
+#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)\r
+#define RTC_CR_DCE                           ((uint32_t)0x00000080)\r
+#define RTC_CR_FMT                           ((uint32_t)0x00000040)\r
+#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)\r
+#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)\r
+#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)\r
+#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)\r
+#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)\r
+#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)\r
+#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)\r
+\r
+/********************  Bits definition for RTC_ISR register  ******************/\r
+#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)\r
+#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)\r
+#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)\r
+#define RTC_ISR_TSF                          ((uint32_t)0x00000800)\r
+#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)\r
+#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)\r
+#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)\r
+#define RTC_ISR_INIT                         ((uint32_t)0x00000080)\r
+#define RTC_ISR_INITF                        ((uint32_t)0x00000040)\r
+#define RTC_ISR_RSF                          ((uint32_t)0x00000020)\r
+#define RTC_ISR_INITS                        ((uint32_t)0x00000010)\r
+#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)\r
+#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)\r
+#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)\r
+#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for RTC_PRER register  *****************/\r
+#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)\r
+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)\r
+\r
+/********************  Bits definition for RTC_WUTR register  *****************/\r
+#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)\r
+\r
+/********************  Bits definition for RTC_CALIBR register  ***************/\r
+#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)\r
+#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)\r
+\r
+/********************  Bits definition for RTC_ALRMAR register  ***************/\r
+#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)\r
+#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)\r
+#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)\r
+#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)\r
+#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)\r
+#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)\r
+#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)\r
+#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)\r
+#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)\r
+#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)\r
+#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)\r
+#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)\r
+#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)\r
+#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)\r
+#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)\r
+#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)\r
+#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)\r
+#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)\r
+#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)\r
+#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)\r
+#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)\r
+#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)\r
+#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)\r
+#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)\r
+#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)\r
+#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)\r
+#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)\r
+#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)\r
+#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)\r
+#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)\r
+#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)\r
+#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)\r
+#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)\r
+#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)\r
+#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)\r
+#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)\r
+#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)\r
+#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)\r
+#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)\r
+#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_ALRMBR register  ***************/\r
+#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)\r
+#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)\r
+#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)\r
+#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)\r
+#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)\r
+#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)\r
+#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)\r
+#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)\r
+#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)\r
+#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)\r
+#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)\r
+#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)\r
+#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)\r
+#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)\r
+#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)\r
+#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)\r
+#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)\r
+#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)\r
+#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)\r
+#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)\r
+#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)\r
+#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)\r
+#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)\r
+#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)\r
+#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)\r
+#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)\r
+#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)\r
+#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)\r
+#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)\r
+#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)\r
+#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)\r
+#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)\r
+#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)\r
+#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)\r
+#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)\r
+#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)\r
+#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)\r
+#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)\r
+#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_WPR register  ******************/\r
+#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)\r
+\r
+/********************  Bits definition for RTC_SSR register  ******************/\r
+#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)\r
+\r
+/********************  Bits definition for RTC_SHIFTR register  ***************/\r
+#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)\r
+#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)\r
+\r
+/********************  Bits definition for RTC_TSTR register  *****************/\r
+#define RTC_TSTR_PM                          ((uint32_t)0x00400000)\r
+#define RTC_TSTR_HT                          ((uint32_t)0x00300000)\r
+#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)\r
+#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)\r
+#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)\r
+#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)\r
+#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)\r
+#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)\r
+#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)\r
+#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)\r
+#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)\r
+#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)\r
+#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)\r
+#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)\r
+#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)\r
+#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)\r
+#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)\r
+#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)\r
+#define RTC_TSTR_ST                          ((uint32_t)0x00000070)\r
+#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)\r
+#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)\r
+#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)\r
+#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)\r
+#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)\r
+#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)\r
+#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)\r
+#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_TSDR register  *****************/\r
+#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)\r
+#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)\r
+#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)\r
+#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)\r
+#define RTC_TSDR_MT                          ((uint32_t)0x00001000)\r
+#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)\r
+#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)\r
+#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)\r
+#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)\r
+#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)\r
+#define RTC_TSDR_DT                          ((uint32_t)0x00000030)\r
+#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)\r
+#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)\r
+#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)\r
+#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)\r
+#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)\r
+#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)\r
+#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)\r
+\r
+/********************  Bits definition for RTC_TSSSR register  ****************/\r
+#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)\r
+\r
+/********************  Bits definition for RTC_CAL register  *****************/\r
+#define RTC_CALR_CALP                        ((uint32_t)0x00008000)\r
+#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)\r
+#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)\r
+#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)\r
+#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)\r
+#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)\r
+#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)\r
+#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)\r
+#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)\r
+#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)\r
+#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)\r
+#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)\r
+#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)\r
+\r
+/********************  Bits definition for RTC_TAFCR register  ****************/\r
+#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)\r
+#define RTC_TAFCR_TSINSEL                    ((uint32_t)0x00020000)\r
+#define RTC_TAFCR_TAMPINSEL                  ((uint32_t)0x00010000)\r
+#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)\r
+#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)\r
+#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)\r
+#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)\r
+#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)\r
+#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)\r
+#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)\r
+#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)\r
+#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)\r
+#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)\r
+#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)\r
+#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)\r
+#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)\r
+#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)\r
+#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)\r
+\r
+/********************  Bits definition for RTC_ALRMASSR register  *************/\r
+#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)\r
+#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)\r
+#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)\r
+#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)\r
+#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)\r
+#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)\r
+\r
+/********************  Bits definition for RTC_ALRMBSSR register  *************/\r
+#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)\r
+#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)\r
+#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)\r
+#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)\r
+#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)\r
+#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)\r
+\r
+/********************  Bits definition for RTC_BKP0R register  ****************/\r
+#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP1R register  ****************/\r
+#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP2R register  ****************/\r
+#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP3R register  ****************/\r
+#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP4R register  ****************/\r
+#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP5R register  ****************/\r
+#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP6R register  ****************/\r
+#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP7R register  ****************/\r
+#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP8R register  ****************/\r
+#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP9R register  ****************/\r
+#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP10R register  ***************/\r
+#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP11R register  ***************/\r
+#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP12R register  ***************/\r
+#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP13R register  ***************/\r
+#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP14R register  ***************/\r
+#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP15R register  ***************/\r
+#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP16R register  ***************/\r
+#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP17R register  ***************/\r
+#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP18R register  ***************/\r
+#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+/********************  Bits definition for RTC_BKP19R register  ***************/\r
+#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)\r
+\r
+#if defined (STM32F429X)\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          Serial Audio Interface                            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for SAI_GCR register  *******************/\r
+#define  SAI_GCR_SYNCIN                  ((uint32_t)0x00000003)        /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */\r
+#define  SAI_GCR_SYNCIN_0                ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  SAI_GCR_SYNCIN_1                ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+\r
+#define  SAI_GCR_SYNCOUT                 ((uint32_t)0x00000030)        /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */\r
+#define  SAI_GCR_SYNCOUT_0               ((uint32_t)0x00000010)        /*!<Bit 0 */\r
+#define  SAI_GCR_SYNCOUT_1               ((uint32_t)0x00000020)        /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for SAI_xCR1 register  *******************/\r
+#define  SAI_xCR1_MODE                    ((uint32_t)0x00000003)        /*!<MODE[1:0] bits (Audio Block Mode)           */\r
+#define  SAI_xCR1_MODE_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  SAI_xCR1_MODE_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+\r
+#define  SAI_xCR1_PRTCFG                  ((uint32_t)0x0000000C)        /*!<PRTCFG[1:0] bits (Protocol Configuration)   */\r
+#define  SAI_xCR1_PRTCFG_0                ((uint32_t)0x00000004)        /*!<Bit 0 */\r
+#define  SAI_xCR1_PRTCFG_1                ((uint32_t)0x00000008)        /*!<Bit 1 */\r
+\r
+#define  SAI_xCR1_DS                      ((uint32_t)0x000000E0)        /*!<DS[1:0] bits (Data Size) */\r
+#define  SAI_xCR1_DS_0                    ((uint32_t)0x00000020)        /*!<Bit 0 */\r
+#define  SAI_xCR1_DS_1                    ((uint32_t)0x00000040)        /*!<Bit 1 */\r
+#define  SAI_xCR1_DS_2                    ((uint32_t)0x00000080)        /*!<Bit 2 */\r
+\r
+#define  SAI_xCR1_LSBFIRST                ((uint32_t)0x00000100)        /*!<LSB First Configuration  */\r
+#define  SAI_xCR1_CKSTR                   ((uint32_t)0x00000200)        /*!<ClocK STRobing edge      */\r
+\r
+#define  SAI_xCR1_SYNCEN                  ((uint32_t)0x00000C00)        /*!<SYNCEN[1:0](SYNChronization ENable) */\r
+#define  SAI_xCR1_SYNCEN_0                ((uint32_t)0x00000400)        /*!<Bit 0 */\r
+#define  SAI_xCR1_SYNCEN_1                ((uint32_t)0x00000800)        /*!<Bit 1 */\r
+\r
+#define  SAI_xCR1_MONO                    ((uint32_t)0x00001000)        /*!<Mono mode                  */\r
+#define  SAI_xCR1_OUTDRIV                 ((uint32_t)0x00002000)        /*!<Output Drive               */\r
+#define  SAI_xCR1_SAIEN                   ((uint32_t)0x00010000)        /*!<Audio Block enable         */\r
+#define  SAI_xCR1_DMAEN                   ((uint32_t)0x00020000)        /*!<DMA enable                 */\r
+#define  SAI_xCR1_NODIV                   ((uint32_t)0x00080000)        /*!<No Divider Configuration   */\r
+\r
+#define  SAI_xCR1_MCKDIV                  ((uint32_t)0x00780000)        /*!<MCKDIV[3:0] (Master ClocK Divider)  */\r
+#define  SAI_xCR1_MCKDIV_0                ((uint32_t)0x00080000)        /*!<Bit 0  */\r
+#define  SAI_xCR1_MCKDIV_1                ((uint32_t)0x00100000)        /*!<Bit 1  */\r
+#define  SAI_xCR1_MCKDIV_2                ((uint32_t)0x00200000)        /*!<Bit 2  */\r
+#define  SAI_xCR1_MCKDIV_3                ((uint32_t)0x00400000)        /*!<Bit 3  */\r
+\r
+/*******************  Bit definition for SAI_xCR2 register  *******************/\r
+#define  SAI_xCR2_FTH                     ((uint32_t)0x00000003)        /*!<FTH[1:0](Fifo THreshold)  */\r
+#define  SAI_xCR2_FTH_0                   ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  SAI_xCR2_FTH_1                   ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+\r
+#define  SAI_xCR2_FFLUSH                  ((uint32_t)0x00000008)        /*!<Fifo FLUSH                       */\r
+#define  SAI_xCR2_TRIS                    ((uint32_t)0x00000010)        /*!<TRIState Management on data line */\r
+#define  SAI_xCR2_MUTE                    ((uint32_t)0x00000020)        /*!<Mute mode                        */\r
+#define  SAI_xCR2_MUTEVAL                 ((uint32_t)0x00000040)        /*!<Muate value                      */\r
+\r
+#define  SAI_xCR2_MUTECNT                  ((uint32_t)0x00001F80)       /*!<MUTECNT[5:0] (MUTE counter) */\r
+#define  SAI_xCR2_MUTECNT_0               ((uint32_t)0x00000080)        /*!<Bit 0 */\r
+#define  SAI_xCR2_MUTECNT_1               ((uint32_t)0x00000100)        /*!<Bit 1 */\r
+#define  SAI_xCR2_MUTECNT_2               ((uint32_t)0x00000200)        /*!<Bit 2 */\r
+#define  SAI_xCR2_MUTECNT_3               ((uint32_t)0x00000400)        /*!<Bit 3 */\r
+#define  SAI_xCR2_MUTECNT_4               ((uint32_t)0x00000800)        /*!<Bit 4 */\r
+#define  SAI_xCR2_MUTECNT_5               ((uint32_t)0x00001000)        /*!<Bit 5 */\r
+\r
+#define  SAI_xCR2_CPL                     ((uint32_t)0x00080000)        /*!< Complement Bit             */\r
+\r
+#define  SAI_xCR2_COMP                    ((uint32_t)0x0000C000)        /*!<COMP[1:0] (Companding mode) */\r
+#define  SAI_xCR2_COMP_0                  ((uint32_t)0x00004000)        /*!<Bit 0 */\r
+#define  SAI_xCR2_COMP_1                  ((uint32_t)0x00008000)        /*!<Bit 1 */\r
+\r
+/******************  Bit definition for SAI_xFRCR register  *******************/\r
+#define  SAI_xFRCR_FRL                    ((uint32_t)0x000000FF)        /*!<FRL[1:0](Frame length)  */\r
+#define  SAI_xFRCR_FRL_0                  ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  SAI_xFRCR_FRL_1                  ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  SAI_xFRCR_FRL_2                  ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  SAI_xFRCR_FRL_3                  ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  SAI_xFRCR_FRL_4                  ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+#define  SAI_xFRCR_FRL_5                  ((uint32_t)0x00000020)        /*!<Bit 5 */\r
+#define  SAI_xFRCR_FRL_6                  ((uint32_t)0x00000040)        /*!<Bit 6 */\r
+#define  SAI_xFRCR_FRL_7                  ((uint32_t)0x00000080)        /*!<Bit 7 */\r
+\r
+#define  SAI_xFRCR_FSALL                  ((uint32_t)0x00007F00)        /*!<FRL[1:0] (Frame synchronization active level length)  */\r
+#define  SAI_xFRCR_FSALL_0                ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  SAI_xFRCR_FSALL_1                ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  SAI_xFRCR_FSALL_2                ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  SAI_xFRCR_FSALL_3                ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+#define  SAI_xFRCR_FSALL_4                ((uint32_t)0x00001000)        /*!<Bit 4 */\r
+#define  SAI_xFRCR_FSALL_5                ((uint32_t)0x00002000)        /*!<Bit 5 */\r
+#define  SAI_xFRCR_FSALL_6                ((uint32_t)0x00004000)        /*!<Bit 6 */\r
+\r
+#define  SAI_xFRCR_FSDEF                  ((uint32_t)0x00010000)        /*!< Frame Synchronization Definition */\r
+#define  SAI_xFRCR_FSPO                   ((uint32_t)0x00020000)        /*!<Frame Synchronization POLarity    */\r
+#define  SAI_xFRCR_FSOFF                  ((uint32_t)0x00040000)        /*!<Frame Synchronization OFFset      */\r
+\r
+/******************  Bit definition for SAI_xSLOTR register  *******************/\r
+#define  SAI_xSLOTR_FBOFF                 ((uint32_t)0x0000001F)        /*!<FRL[4:0](First Bit Offset)  */\r
+#define  SAI_xSLOTR_FBOFF_0               ((uint32_t)0x00000001)        /*!<Bit 0 */\r
+#define  SAI_xSLOTR_FBOFF_1               ((uint32_t)0x00000002)        /*!<Bit 1 */\r
+#define  SAI_xSLOTR_FBOFF_2               ((uint32_t)0x00000004)        /*!<Bit 2 */\r
+#define  SAI_xSLOTR_FBOFF_3               ((uint32_t)0x00000008)        /*!<Bit 3 */\r
+#define  SAI_xSLOTR_FBOFF_4               ((uint32_t)0x00000010)        /*!<Bit 4 */\r
+                                     \r
+#define  SAI_xSLOTR_SLOTSZ                ((uint32_t)0x000000C0)        /*!<SLOTSZ[1:0] (Slot size)  */\r
+#define  SAI_xSLOTR_SLOTSZ_0              ((uint32_t)0x00000040)        /*!<Bit 0 */\r
+#define  SAI_xSLOTR_SLOTSZ_1              ((uint32_t)0x00000080)        /*!<Bit 1 */\r
+\r
+#define  SAI_xSLOTR_NBSLOT                ((uint32_t)0x00000F00)        /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */\r
+#define  SAI_xSLOTR_NBSLOT_0              ((uint32_t)0x00000100)        /*!<Bit 0 */\r
+#define  SAI_xSLOTR_NBSLOT_1              ((uint32_t)0x00000200)        /*!<Bit 1 */\r
+#define  SAI_xSLOTR_NBSLOT_2              ((uint32_t)0x00000400)        /*!<Bit 2 */\r
+#define  SAI_xSLOTR_NBSLOT_3              ((uint32_t)0x00000800)        /*!<Bit 3 */\r
+\r
+#define  SAI_xSLOTR_SLOTEN                ((uint32_t)0xFFFF0000)        /*!<SLOTEN[15:0] (Slot Enable)  */\r
+\r
+/*******************  Bit definition for SAI_xIMR register  *******************/\r
+#define  SAI_xIMR_OVRUDRIE                ((uint32_t)0x00000001)        /*!<Overrun underrun interrupt enable                              */\r
+#define  SAI_xIMR_MUTEDETIE               ((uint32_t)0x00000002)        /*!<Mute detection interrupt enable                                */\r
+#define  SAI_xIMR_WCKCFGIE                ((uint32_t)0x00000004)        /*!<Wrong Clock Configuration interrupt enable                     */\r
+#define  SAI_xIMR_FREQIE                  ((uint32_t)0x00000008)        /*!<FIFO request interrupt enable                                  */\r
+#define  SAI_xIMR_CNRDYIE                 ((uint32_t)0x00000010)        /*!<Codec not ready interrupt enable                               */\r
+#define  SAI_xIMR_AFSDETIE                ((uint32_t)0x00000020)        /*!<Anticipated frame synchronization detection interrupt enable   */\r
+#define  SAI_xIMR_LFSDETIE                ((uint32_t)0x00000040)        /*!<Late frame synchronization detection interrupt enable          */\r
+\r
+/********************  Bit definition for SAI_xSR register  *******************/\r
+#define  SAI_xSR_OVRUDR                   ((uint32_t)0x00000001)         /*!<Overrun underrun                               */\r
+#define  SAI_xSR_MUTEDET                  ((uint32_t)0x00000002)         /*!<Mute detection                                 */\r
+#define  SAI_xSR_WCKCFG                   ((uint32_t)0x00000004)         /*!<Wrong Clock Configuration                      */\r
+#define  SAI_xSR_FREQ                     ((uint32_t)0x00000008)         /*!<FIFO request                                   */\r
+#define  SAI_xSR_CNRDY                    ((uint32_t)0x00000010)         /*!<Codec not ready                                */\r
+#define  SAI_xSR_AFSDET                   ((uint32_t)0x00000020)         /*!<Anticipated frame synchronization detection    */\r
+#define  SAI_xSR_LFSDET                   ((uint32_t)0x00000040)         /*!<Late frame synchronization detection           */\r
+\r
+#define  SAI_xSR_FLVL                     ((uint32_t)0x00070000)         /*!<FLVL[2:0] (FIFO Level Threshold)               */\r
+#define  SAI_xSR_FLVL_0                   ((uint32_t)0x00010000)         /*!<Bit 0 */\r
+#define  SAI_xSR_FLVL_1                   ((uint32_t)0x00020000)         /*!<Bit 1 */\r
+#define  SAI_xSR_FLVL_2                   ((uint32_t)0x00030000)         /*!<Bit 2 */\r
+\r
+/******************  Bit definition for SAI_xCLRFR register  ******************/\r
+#define  SAI_xCLRFR_COVRUDR               ((uint32_t)0x00000001)        /*!<Clear Overrun underrun                               */\r
+#define  SAI_xCLRFR_CMUTEDET              ((uint32_t)0x00000002)        /*!<Clear Mute detection                                 */\r
+#define  SAI_xCLRFR_CWCKCFG               ((uint32_t)0x00000004)        /*!<Clear Wrong Clock Configuration                      */\r
+#define  SAI_xCLRFR_CFREQ                 ((uint32_t)0x00000008)        /*!<Clear FIFO request                                   */\r
+#define  SAI_xCLRFR_CCNRDY                ((uint32_t)0x00000010)        /*!<Clear Codec not ready                                */\r
+#define  SAI_xCLRFR_CAFSDET               ((uint32_t)0x00000020)        /*!<Clear Anticipated frame synchronization detection    */\r
+#define  SAI_xCLRFR_CLFSDET               ((uint32_t)0x00000040)        /*!<Clear Late frame synchronization detection           */\r
+\r
+/******************  Bit definition for SAI_xDR register  ******************/\r
+#define  SAI_xDR_DATA                     ((uint32_t)0xFFFFFFFF)        \r
+#endif /* STM32F429X */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                          SD host Interface                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for SDIO_POWER register  ******************/\r
+#define  SDIO_POWER_PWRCTRL                  ((uint8_t)0x03)               /*!<PWRCTRL[1:0] bits (Power supply control bits) */\r
+#define  SDIO_POWER_PWRCTRL_0                ((uint8_t)0x01)               /*!<Bit 0 */\r
+#define  SDIO_POWER_PWRCTRL_1                ((uint8_t)0x02)               /*!<Bit 1 */\r
+\r
+/******************  Bit definition for SDIO_CLKCR register  ******************/\r
+#define  SDIO_CLKCR_CLKDIV                   ((uint16_t)0x00FF)            /*!<Clock divide factor             */\r
+#define  SDIO_CLKCR_CLKEN                    ((uint16_t)0x0100)            /*!<Clock enable bit                */\r
+#define  SDIO_CLKCR_PWRSAV                   ((uint16_t)0x0200)            /*!<Power saving configuration bit  */\r
+#define  SDIO_CLKCR_BYPASS                   ((uint16_t)0x0400)            /*!<Clock divider bypass enable bit */\r
+\r
+#define  SDIO_CLKCR_WIDBUS                   ((uint16_t)0x1800)            /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */\r
+#define  SDIO_CLKCR_WIDBUS_0                 ((uint16_t)0x0800)            /*!<Bit 0 */\r
+#define  SDIO_CLKCR_WIDBUS_1                 ((uint16_t)0x1000)            /*!<Bit 1 */\r
+\r
+#define  SDIO_CLKCR_NEGEDGE                  ((uint16_t)0x2000)            /*!<SDIO_CK dephasing selection bit */\r
+#define  SDIO_CLKCR_HWFC_EN                  ((uint16_t)0x4000)            /*!<HW Flow Control enable          */\r
+\r
+/*******************  Bit definition for SDIO_ARG register  *******************/\r
+#define  SDIO_ARG_CMDARG                     ((uint32_t)0xFFFFFFFF)            /*!<Command argument */\r
+\r
+/*******************  Bit definition for SDIO_CMD register  *******************/\r
+#define  SDIO_CMD_CMDINDEX                   ((uint16_t)0x003F)            /*!<Command Index                               */\r
+\r
+#define  SDIO_CMD_WAITRESP                   ((uint16_t)0x00C0)            /*!<WAITRESP[1:0] bits (Wait for response bits) */\r
+#define  SDIO_CMD_WAITRESP_0                 ((uint16_t)0x0040)            /*!< Bit 0 */\r
+#define  SDIO_CMD_WAITRESP_1                 ((uint16_t)0x0080)            /*!< Bit 1 */\r
+\r
+#define  SDIO_CMD_WAITINT                    ((uint16_t)0x0100)            /*!<CPSM Waits for Interrupt Request                               */\r
+#define  SDIO_CMD_WAITPEND                   ((uint16_t)0x0200)            /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */\r
+#define  SDIO_CMD_CPSMEN                     ((uint16_t)0x0400)            /*!<Command path state machine (CPSM) Enable bit                   */\r
+#define  SDIO_CMD_SDIOSUSPEND                ((uint16_t)0x0800)            /*!<SD I/O suspend command                                         */\r
+#define  SDIO_CMD_ENCMDCOMPL                 ((uint16_t)0x1000)            /*!<Enable CMD completion                                          */\r
+#define  SDIO_CMD_NIEN                       ((uint16_t)0x2000)            /*!<Not Interrupt Enable */\r
+#define  SDIO_CMD_CEATACMD                   ((uint16_t)0x4000)            /*!<CE-ATA command       */\r
+\r
+/*****************  Bit definition for SDIO_RESPCMD register  *****************/\r
+#define  SDIO_RESPCMD_RESPCMD                ((uint8_t)0x3F)               /*!<Response command index */\r
+\r
+/******************  Bit definition for SDIO_RESP0 register  ******************/\r
+#define  SDIO_RESP0_CARDSTATUS0              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */\r
+\r
+/******************  Bit definition for SDIO_RESP1 register  ******************/\r
+#define  SDIO_RESP1_CARDSTATUS1              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */\r
+\r
+/******************  Bit definition for SDIO_RESP2 register  ******************/\r
+#define  SDIO_RESP2_CARDSTATUS2              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */\r
+\r
+/******************  Bit definition for SDIO_RESP3 register  ******************/\r
+#define  SDIO_RESP3_CARDSTATUS3              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */\r
+\r
+/******************  Bit definition for SDIO_RESP4 register  ******************/\r
+#define  SDIO_RESP4_CARDSTATUS4              ((uint32_t)0xFFFFFFFF)        /*!<Card Status */\r
+\r
+/******************  Bit definition for SDIO_DTIMER register  *****************/\r
+#define  SDIO_DTIMER_DATATIME                ((uint32_t)0xFFFFFFFF)        /*!<Data timeout period. */\r
+\r
+/******************  Bit definition for SDIO_DLEN register  *******************/\r
+#define  SDIO_DLEN_DATALENGTH                ((uint32_t)0x01FFFFFF)        /*!<Data length value    */\r
+\r
+/******************  Bit definition for SDIO_DCTRL register  ******************/\r
+#define  SDIO_DCTRL_DTEN                     ((uint16_t)0x0001)            /*!<Data transfer enabled bit         */\r
+#define  SDIO_DCTRL_DTDIR                    ((uint16_t)0x0002)            /*!<Data transfer direction selection */\r
+#define  SDIO_DCTRL_DTMODE                   ((uint16_t)0x0004)            /*!<Data transfer mode selection      */\r
+#define  SDIO_DCTRL_DMAEN                    ((uint16_t)0x0008)            /*!<DMA enabled bit                   */\r
+\r
+#define  SDIO_DCTRL_DBLOCKSIZE               ((uint16_t)0x00F0)            /*!<DBLOCKSIZE[3:0] bits (Data block size) */\r
+#define  SDIO_DCTRL_DBLOCKSIZE_0             ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  SDIO_DCTRL_DBLOCKSIZE_1             ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  SDIO_DCTRL_DBLOCKSIZE_2             ((uint16_t)0x0040)            /*!<Bit 2 */\r
+#define  SDIO_DCTRL_DBLOCKSIZE_3             ((uint16_t)0x0080)            /*!<Bit 3 */\r
+\r
+#define  SDIO_DCTRL_RWSTART                  ((uint16_t)0x0100)            /*!<Read wait start         */\r
+#define  SDIO_DCTRL_RWSTOP                   ((uint16_t)0x0200)            /*!<Read wait stop          */\r
+#define  SDIO_DCTRL_RWMOD                    ((uint16_t)0x0400)            /*!<Read wait mode          */\r
+#define  SDIO_DCTRL_SDIOEN                   ((uint16_t)0x0800)            /*!<SD I/O enable functions */\r
+\r
+/******************  Bit definition for SDIO_DCOUNT register  *****************/\r
+#define  SDIO_DCOUNT_DATACOUNT               ((uint32_t)0x01FFFFFF)        /*!<Data count value */\r
+\r
+/******************  Bit definition for SDIO_STA register  ********************/\r
+#define  SDIO_STA_CCRCFAIL                   ((uint32_t)0x00000001)        /*!<Command response received (CRC check failed)  */\r
+#define  SDIO_STA_DCRCFAIL                   ((uint32_t)0x00000002)        /*!<Data block sent/received (CRC check failed)   */\r
+#define  SDIO_STA_CTIMEOUT                   ((uint32_t)0x00000004)        /*!<Command response timeout                      */\r
+#define  SDIO_STA_DTIMEOUT                   ((uint32_t)0x00000008)        /*!<Data timeout                                  */\r
+#define  SDIO_STA_TXUNDERR                   ((uint32_t)0x00000010)        /*!<Transmit FIFO underrun error                  */\r
+#define  SDIO_STA_RXOVERR                    ((uint32_t)0x00000020)        /*!<Received FIFO overrun error                   */\r
+#define  SDIO_STA_CMDREND                    ((uint32_t)0x00000040)        /*!<Command response received (CRC check passed)  */\r
+#define  SDIO_STA_CMDSENT                    ((uint32_t)0x00000080)        /*!<Command sent (no response required)           */\r
+#define  SDIO_STA_DATAEND                    ((uint32_t)0x00000100)        /*!<Data end (data counter, SDIDCOUNT, is zero)   */\r
+#define  SDIO_STA_STBITERR                   ((uint32_t)0x00000200)        /*!<Start bit not detected on all data signals in wide bus mode */\r
+#define  SDIO_STA_DBCKEND                    ((uint32_t)0x00000400)        /*!<Data block sent/received (CRC check passed)   */\r
+#define  SDIO_STA_CMDACT                     ((uint32_t)0x00000800)        /*!<Command transfer in progress                  */\r
+#define  SDIO_STA_TXACT                      ((uint32_t)0x00001000)        /*!<Data transmit in progress                     */\r
+#define  SDIO_STA_RXACT                      ((uint32_t)0x00002000)        /*!<Data receive in progress                      */\r
+#define  SDIO_STA_TXFIFOHE                   ((uint32_t)0x00004000)        /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */\r
+#define  SDIO_STA_RXFIFOHF                   ((uint32_t)0x00008000)        /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */\r
+#define  SDIO_STA_TXFIFOF                    ((uint32_t)0x00010000)        /*!<Transmit FIFO full                            */\r
+#define  SDIO_STA_RXFIFOF                    ((uint32_t)0x00020000)        /*!<Receive FIFO full                             */\r
+#define  SDIO_STA_TXFIFOE                    ((uint32_t)0x00040000)        /*!<Transmit FIFO empty                           */\r
+#define  SDIO_STA_RXFIFOE                    ((uint32_t)0x00080000)        /*!<Receive FIFO empty                            */\r
+#define  SDIO_STA_TXDAVL                     ((uint32_t)0x00100000)        /*!<Data available in transmit FIFO               */\r
+#define  SDIO_STA_RXDAVL                     ((uint32_t)0x00200000)        /*!<Data available in receive FIFO                */\r
+#define  SDIO_STA_SDIOIT                     ((uint32_t)0x00400000)        /*!<SDIO interrupt received                       */\r
+#define  SDIO_STA_CEATAEND                   ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received for CMD61 */\r
+\r
+/*******************  Bit definition for SDIO_ICR register  *******************/\r
+#define  SDIO_ICR_CCRCFAILC                  ((uint32_t)0x00000001)        /*!<CCRCFAIL flag clear bit */\r
+#define  SDIO_ICR_DCRCFAILC                  ((uint32_t)0x00000002)        /*!<DCRCFAIL flag clear bit */\r
+#define  SDIO_ICR_CTIMEOUTC                  ((uint32_t)0x00000004)        /*!<CTIMEOUT flag clear bit */\r
+#define  SDIO_ICR_DTIMEOUTC                  ((uint32_t)0x00000008)        /*!<DTIMEOUT flag clear bit */\r
+#define  SDIO_ICR_TXUNDERRC                  ((uint32_t)0x00000010)        /*!<TXUNDERR flag clear bit */\r
+#define  SDIO_ICR_RXOVERRC                   ((uint32_t)0x00000020)        /*!<RXOVERR flag clear bit  */\r
+#define  SDIO_ICR_CMDRENDC                   ((uint32_t)0x00000040)        /*!<CMDREND flag clear bit  */\r
+#define  SDIO_ICR_CMDSENTC                   ((uint32_t)0x00000080)        /*!<CMDSENT flag clear bit  */\r
+#define  SDIO_ICR_DATAENDC                   ((uint32_t)0x00000100)        /*!<DATAEND flag clear bit  */\r
+#define  SDIO_ICR_STBITERRC                  ((uint32_t)0x00000200)        /*!<STBITERR flag clear bit */\r
+#define  SDIO_ICR_DBCKENDC                   ((uint32_t)0x00000400)        /*!<DBCKEND flag clear bit  */\r
+#define  SDIO_ICR_SDIOITC                    ((uint32_t)0x00400000)        /*!<SDIOIT flag clear bit   */\r
+#define  SDIO_ICR_CEATAENDC                  ((uint32_t)0x00800000)        /*!<CEATAEND flag clear bit */\r
+\r
+/******************  Bit definition for SDIO_MASK register  *******************/\r
+#define  SDIO_MASK_CCRCFAILIE                ((uint32_t)0x00000001)        /*!<Command CRC Fail Interrupt Enable          */\r
+#define  SDIO_MASK_DCRCFAILIE                ((uint32_t)0x00000002)        /*!<Data CRC Fail Interrupt Enable             */\r
+#define  SDIO_MASK_CTIMEOUTIE                ((uint32_t)0x00000004)        /*!<Command TimeOut Interrupt Enable           */\r
+#define  SDIO_MASK_DTIMEOUTIE                ((uint32_t)0x00000008)        /*!<Data TimeOut Interrupt Enable              */\r
+#define  SDIO_MASK_TXUNDERRIE                ((uint32_t)0x00000010)        /*!<Tx FIFO UnderRun Error Interrupt Enable    */\r
+#define  SDIO_MASK_RXOVERRIE                 ((uint32_t)0x00000020)        /*!<Rx FIFO OverRun Error Interrupt Enable     */\r
+#define  SDIO_MASK_CMDRENDIE                 ((uint32_t)0x00000040)        /*!<Command Response Received Interrupt Enable */\r
+#define  SDIO_MASK_CMDSENTIE                 ((uint32_t)0x00000080)        /*!<Command Sent Interrupt Enable              */\r
+#define  SDIO_MASK_DATAENDIE                 ((uint32_t)0x00000100)        /*!<Data End Interrupt Enable                  */\r
+#define  SDIO_MASK_STBITERRIE                ((uint32_t)0x00000200)        /*!<Start Bit Error Interrupt Enable           */\r
+#define  SDIO_MASK_DBCKENDIE                 ((uint32_t)0x00000400)        /*!<Data Block End Interrupt Enable            */\r
+#define  SDIO_MASK_CMDACTIE                  ((uint32_t)0x00000800)        /*!<CCommand Acting Interrupt Enable           */\r
+#define  SDIO_MASK_TXACTIE                   ((uint32_t)0x00001000)        /*!<Data Transmit Acting Interrupt Enable      */\r
+#define  SDIO_MASK_RXACTIE                   ((uint32_t)0x00002000)        /*!<Data receive acting interrupt enabled      */\r
+#define  SDIO_MASK_TXFIFOHEIE                ((uint32_t)0x00004000)        /*!<Tx FIFO Half Empty interrupt Enable        */\r
+#define  SDIO_MASK_RXFIFOHFIE                ((uint32_t)0x00008000)        /*!<Rx FIFO Half Full interrupt Enable         */\r
+#define  SDIO_MASK_TXFIFOFIE                 ((uint32_t)0x00010000)        /*!<Tx FIFO Full interrupt Enable              */\r
+#define  SDIO_MASK_RXFIFOFIE                 ((uint32_t)0x00020000)        /*!<Rx FIFO Full interrupt Enable              */\r
+#define  SDIO_MASK_TXFIFOEIE                 ((uint32_t)0x00040000)        /*!<Tx FIFO Empty interrupt Enable             */\r
+#define  SDIO_MASK_RXFIFOEIE                 ((uint32_t)0x00080000)        /*!<Rx FIFO Empty interrupt Enable             */\r
+#define  SDIO_MASK_TXDAVLIE                  ((uint32_t)0x00100000)        /*!<Data available in Tx FIFO interrupt Enable */\r
+#define  SDIO_MASK_RXDAVLIE                  ((uint32_t)0x00200000)        /*!<Data available in Rx FIFO interrupt Enable */\r
+#define  SDIO_MASK_SDIOITIE                  ((uint32_t)0x00400000)        /*!<SDIO Mode Interrupt Received interrupt Enable */\r
+#define  SDIO_MASK_CEATAENDIE                ((uint32_t)0x00800000)        /*!<CE-ATA command completion signal received Interrupt Enable */\r
+\r
+/*****************  Bit definition for SDIO_FIFOCNT register  *****************/\r
+#define  SDIO_FIFOCNT_FIFOCOUNT              ((uint32_t)0x00FFFFFF)        /*!<Remaining number of words to be written to or read from the FIFO */\r
+\r
+/******************  Bit definition for SDIO_FIFO register  *******************/\r
+#define  SDIO_FIFO_FIFODATA                  ((uint32_t)0xFFFFFFFF)        /*!<Receive and transmit FIFO data */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                        Serial Peripheral Interface                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for SPI_CR1 register  ********************/\r
+#define  SPI_CR1_CPHA                        ((uint16_t)0x0001)            /*!<Clock Phase      */\r
+#define  SPI_CR1_CPOL                        ((uint16_t)0x0002)            /*!<Clock Polarity   */\r
+#define  SPI_CR1_MSTR                        ((uint16_t)0x0004)            /*!<Master Selection */\r
+\r
+#define  SPI_CR1_BR                          ((uint16_t)0x0038)            /*!<BR[2:0] bits (Baud Rate Control) */\r
+#define  SPI_CR1_BR_0                        ((uint16_t)0x0008)            /*!<Bit 0 */\r
+#define  SPI_CR1_BR_1                        ((uint16_t)0x0010)            /*!<Bit 1 */\r
+#define  SPI_CR1_BR_2                        ((uint16_t)0x0020)            /*!<Bit 2 */\r
+\r
+#define  SPI_CR1_SPE                         ((uint16_t)0x0040)            /*!<SPI Enable                          */\r
+#define  SPI_CR1_LSBFIRST                    ((uint16_t)0x0080)            /*!<Frame Format                        */\r
+#define  SPI_CR1_SSI                         ((uint16_t)0x0100)            /*!<Internal slave select               */\r
+#define  SPI_CR1_SSM                         ((uint16_t)0x0200)            /*!<Software slave management           */\r
+#define  SPI_CR1_RXONLY                      ((uint16_t)0x0400)            /*!<Receive only                        */\r
+#define  SPI_CR1_DFF                         ((uint16_t)0x0800)            /*!<Data Frame Format                   */\r
+#define  SPI_CR1_CRCNEXT                     ((uint16_t)0x1000)            /*!<Transmit CRC next                   */\r
+#define  SPI_CR1_CRCEN                       ((uint16_t)0x2000)            /*!<Hardware CRC calculation enable     */\r
+#define  SPI_CR1_BIDIOE                      ((uint16_t)0x4000)            /*!<Output enable in bidirectional mode */\r
+#define  SPI_CR1_BIDIMODE                    ((uint16_t)0x8000)            /*!<Bidirectional data mode enable      */\r
+\r
+/*******************  Bit definition for SPI_CR2 register  ********************/\r
+#define  SPI_CR2_RXDMAEN                     ((uint8_t)0x01)               /*!<Rx Buffer DMA Enable                 */\r
+#define  SPI_CR2_TXDMAEN                     ((uint8_t)0x02)               /*!<Tx Buffer DMA Enable                 */\r
+#define  SPI_CR2_SSOE                        ((uint8_t)0x04)               /*!<SS Output Enable                     */\r
+#define  SPI_CR2_ERRIE                       ((uint8_t)0x20)               /*!<Error Interrupt Enable               */\r
+#define  SPI_CR2_RXNEIE                      ((uint8_t)0x40)               /*!<RX buffer Not Empty Interrupt Enable */\r
+#define  SPI_CR2_TXEIE                       ((uint8_t)0x80)               /*!<Tx buffer Empty Interrupt Enable     */\r
+\r
+/********************  Bit definition for SPI_SR register  ********************/\r
+#define  SPI_SR_RXNE                         ((uint8_t)0x01)               /*!<Receive buffer Not Empty */\r
+#define  SPI_SR_TXE                          ((uint8_t)0x02)               /*!<Transmit buffer Empty    */\r
+#define  SPI_SR_CHSIDE                       ((uint8_t)0x04)               /*!<Channel side             */\r
+#define  SPI_SR_UDR                          ((uint8_t)0x08)               /*!<Underrun flag            */\r
+#define  SPI_SR_CRCERR                       ((uint8_t)0x10)               /*!<CRC Error flag           */\r
+#define  SPI_SR_MODF                         ((uint8_t)0x20)               /*!<Mode fault               */\r
+#define  SPI_SR_OVR                          ((uint8_t)0x40)               /*!<Overrun flag             */\r
+#define  SPI_SR_BSY                          ((uint8_t)0x80)               /*!<Busy flag                */\r
+\r
+/********************  Bit definition for SPI_DR register  ********************/\r
+#define  SPI_DR_DR                           ((uint16_t)0xFFFF)            /*!<Data Register           */\r
+\r
+/*******************  Bit definition for SPI_CRCPR register  ******************/\r
+#define  SPI_CRCPR_CRCPOLY                   ((uint16_t)0xFFFF)            /*!<CRC polynomial register */\r
+\r
+/******************  Bit definition for SPI_RXCRCR register  ******************/\r
+#define  SPI_RXCRCR_RXCRC                    ((uint16_t)0xFFFF)            /*!<Rx CRC Register         */\r
+\r
+/******************  Bit definition for SPI_TXCRCR register  ******************/\r
+#define  SPI_TXCRCR_TXCRC                    ((uint16_t)0xFFFF)            /*!<Tx CRC Register         */\r
+\r
+/******************  Bit definition for SPI_I2SCFGR register  *****************/\r
+#define  SPI_I2SCFGR_CHLEN                   ((uint16_t)0x0001)            /*!<Channel length (number of bits per audio channel) */\r
+\r
+#define  SPI_I2SCFGR_DATLEN                  ((uint16_t)0x0006)            /*!<DATLEN[1:0] bits (Data length to be transferred)  */\r
+#define  SPI_I2SCFGR_DATLEN_0                ((uint16_t)0x0002)            /*!<Bit 0 */\r
+#define  SPI_I2SCFGR_DATLEN_1                ((uint16_t)0x0004)            /*!<Bit 1 */\r
+\r
+#define  SPI_I2SCFGR_CKPOL                   ((uint16_t)0x0008)            /*!<steady state clock polarity               */\r
+\r
+#define  SPI_I2SCFGR_I2SSTD                  ((uint16_t)0x0030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */\r
+#define  SPI_I2SCFGR_I2SSTD_0                ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  SPI_I2SCFGR_I2SSTD_1                ((uint16_t)0x0020)            /*!<Bit 1 */\r
+\r
+#define  SPI_I2SCFGR_PCMSYNC                 ((uint16_t)0x0080)            /*!<PCM frame synchronization                 */\r
+\r
+#define  SPI_I2SCFGR_I2SCFG                  ((uint16_t)0x0300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */\r
+#define  SPI_I2SCFGR_I2SCFG_0                ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  SPI_I2SCFGR_I2SCFG_1                ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  SPI_I2SCFGR_I2SE                    ((uint16_t)0x0400)            /*!<I2S Enable         */\r
+#define  SPI_I2SCFGR_I2SMOD                  ((uint16_t)0x0800)            /*!<I2S mode selection */\r
+\r
+/******************  Bit definition for SPI_I2SPR register  *******************/\r
+#define  SPI_I2SPR_I2SDIV                    ((uint16_t)0x00FF)            /*!<I2S Linear prescaler         */\r
+#define  SPI_I2SPR_ODD                       ((uint16_t)0x0100)            /*!<Odd factor for the prescaler */\r
+#define  SPI_I2SPR_MCKOE                     ((uint16_t)0x0200)            /*!<Master Clock Output Enable   */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                 SYSCFG                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/******************  Bit definition for SYSCFG_MEMRMP register  ***************/  \r
+#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000007) /*!< SYSCFG_Memory Remap Config */\r
+#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001)\r
+#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002)\r
+#define SYSCFG_MEMRMP_MEM_MODE_2        ((uint32_t)0x00000004)\r
+\r
+#define SYSCFG_MEMRMP_UFB_MODE          ((uint32_t)0x00000100) /*!< User Flash Bank mode */\r
+\r
+/******************  Bit definition for SYSCFG_PMC register  ******************/\r
+#define SYSCFG_PMC_ADCxDC2              ((uint32_t)0x00070000) /*!< Refer to AN4073 on how to use this bit  */\r
+#define SYSCFG_PMC_ADC1DC2              ((uint32_t)0x00010000) /*!< Refer to AN4073 on how to use this bit  */\r
+#define SYSCFG_PMC_ADC2DC2              ((uint32_t)0x00020000) /*!< Refer to AN4073 on how to use this bit  */\r
+#define SYSCFG_PMC_ADC3DC2              ((uint32_t)0x00040000) /*!< Refer to AN4073 on how to use this bit  */\r
+\r
+#define SYSCFG_PMC_MII_RMII_SEL         ((uint32_t)0x00800000) /*!<Ethernet PHY interface selection */\r
+/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */\r
+#define SYSCFG_PMC_MII_RMII             SYSCFG_PMC_MII_RMII_SEL\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/\r
+#define SYSCFG_EXTICR1_EXTI0            ((uint16_t)0x000F) /*!<EXTI 0 configuration */\r
+#define SYSCFG_EXTICR1_EXTI1            ((uint16_t)0x00F0) /*!<EXTI 1 configuration */\r
+#define SYSCFG_EXTICR1_EXTI2            ((uint16_t)0x0F00) /*!<EXTI 2 configuration */\r
+#define SYSCFG_EXTICR1_EXTI3            ((uint16_t)0xF000) /*!<EXTI 3 configuration */\r
+/** \r
+  * @brief   EXTI0 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint16_t)0x0000) /*!<PA[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint16_t)0x0001) /*!<PB[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint16_t)0x0002) /*!<PC[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint16_t)0x0003) /*!<PD[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint16_t)0x0004) /*!<PE[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint16_t)0x0005) /*!<PF[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint16_t)0x0006) /*!<PG[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint16_t)0x0007) /*!<PH[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint16_t)0x0008) /*!<PI[0] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint16_t)0x0009) /*!<PJ[0] pin */\r
+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint16_t)0x000A) /*!<PK[0] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI1 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint16_t)0x0000) /*!<PA[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint16_t)0x0010) /*!<PB[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint16_t)0x0020) /*!<PC[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint16_t)0x0030) /*!<PD[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint16_t)0x0040) /*!<PE[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint16_t)0x0050) /*!<PF[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint16_t)0x0060) /*!<PG[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint16_t)0x0070) /*!<PH[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint16_t)0x0080) /*!<PI[1] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint16_t)0x0090) /*!<PJ[1] pin */\r
+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint16_t)0x00A0) /*!<PK[1] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI2 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint16_t)0x0000) /*!<PA[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint16_t)0x0100) /*!<PB[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint16_t)0x0200) /*!<PC[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint16_t)0x0300) /*!<PD[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint16_t)0x0400) /*!<PE[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint16_t)0x0500) /*!<PF[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint16_t)0x0600) /*!<PG[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint16_t)0x0700) /*!<PH[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint16_t)0x0800) /*!<PI[2] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint16_t)0x0900) /*!<PJ[2] pin */\r
+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint16_t)0x0A00) /*!<PK[2] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI3 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint16_t)0x0000) /*!<PA[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint16_t)0x1000) /*!<PB[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint16_t)0x2000) /*!<PC[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint16_t)0x3000) /*!<PD[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint16_t)0x4000) /*!<PE[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint16_t)0x5000) /*!<PF[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint16_t)0x6000) /*!<PG[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint16_t)0x7000) /*!<PH[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint16_t)0x8000) /*!<PI[3] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint16_t)0x9000) /*!<PJ[3] pin */\r
+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint16_t)0xA000) /*!<PK[3] pin */\r
+#endif /* STM32F429X */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/\r
+#define SYSCFG_EXTICR2_EXTI4            ((uint16_t)0x000F) /*!<EXTI 4 configuration */\r
+#define SYSCFG_EXTICR2_EXTI5            ((uint16_t)0x00F0) /*!<EXTI 5 configuration */\r
+#define SYSCFG_EXTICR2_EXTI6            ((uint16_t)0x0F00) /*!<EXTI 6 configuration */\r
+#define SYSCFG_EXTICR2_EXTI7            ((uint16_t)0xF000) /*!<EXTI 7 configuration */\r
+/** \r
+  * @brief   EXTI4 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint16_t)0x0000) /*!<PA[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint16_t)0x0001) /*!<PB[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint16_t)0x0002) /*!<PC[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint16_t)0x0003) /*!<PD[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint16_t)0x0004) /*!<PE[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint16_t)0x0005) /*!<PF[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint16_t)0x0006) /*!<PG[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint16_t)0x0007) /*!<PH[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint16_t)0x0008) /*!<PI[4] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint16_t)0x0009) /*!<PJ[4] pin */\r
+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint16_t)0x000A) /*!<PK[4] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI5 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint16_t)0x0000) /*!<PA[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint16_t)0x0010) /*!<PB[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint16_t)0x0020) /*!<PC[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint16_t)0x0030) /*!<PD[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint16_t)0x0040) /*!<PE[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint16_t)0x0050) /*!<PF[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint16_t)0x0060) /*!<PG[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint16_t)0x0070) /*!<PH[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint16_t)0x0080) /*!<PI[5] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint16_t)0x0090) /*!<PJ[5] pin */\r
+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint16_t)0x00A0) /*!<PK[5] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI6 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint16_t)0x0000) /*!<PA[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint16_t)0x0100) /*!<PB[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint16_t)0x0200) /*!<PC[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint16_t)0x0300) /*!<PD[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint16_t)0x0400) /*!<PE[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint16_t)0x0500) /*!<PF[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint16_t)0x0600) /*!<PG[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint16_t)0x0700) /*!<PH[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint16_t)0x0800) /*!<PI[6] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint16_t)0x0900) /*!<PJ[6] pin */\r
+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint16_t)0x0A00) /*!<PK[6] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI7 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint16_t)0x0000) /*!<PA[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint16_t)0x1000) /*!<PB[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint16_t)0x2000) /*!<PC[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint16_t)0x3000) /*!<PD[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint16_t)0x4000) /*!<PE[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint16_t)0x5000) /*!<PF[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint16_t)0x6000) /*!<PG[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint16_t)0x7000) /*!<PH[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint16_t)0x8000) /*!<PI[7] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint16_t)0x9000) /*!<PJ[7] pin */\r
+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint16_t)0xA000) /*!<PK[7] pin */\r
+#endif /* STM32F429X */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/\r
+#define SYSCFG_EXTICR3_EXTI8            ((uint16_t)0x000F) /*!<EXTI 8 configuration */\r
+#define SYSCFG_EXTICR3_EXTI9            ((uint16_t)0x00F0) /*!<EXTI 9 configuration */\r
+#define SYSCFG_EXTICR3_EXTI10           ((uint16_t)0x0F00) /*!<EXTI 10 configuration */\r
+#define SYSCFG_EXTICR3_EXTI11           ((uint16_t)0xF000) /*!<EXTI 11 configuration */\r
+           \r
+/** \r
+  * @brief   EXTI8 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint16_t)0x0000) /*!<PA[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint16_t)0x0001) /*!<PB[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint16_t)0x0002) /*!<PC[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint16_t)0x0003) /*!<PD[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint16_t)0x0004) /*!<PE[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint16_t)0x0005) /*!<PF[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint16_t)0x0006) /*!<PG[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint16_t)0x0007) /*!<PH[8] pin */\r
+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint16_t)0x0008) /*!<PI[8] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint16_t)0x0009) /*!<PJ[8] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI9 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint16_t)0x0000) /*!<PA[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint16_t)0x0010) /*!<PB[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint16_t)0x0020) /*!<PC[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint16_t)0x0030) /*!<PD[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint16_t)0x0040) /*!<PE[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint16_t)0x0050) /*!<PF[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint16_t)0x0060) /*!<PG[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint16_t)0x0070) /*!<PH[9] pin */\r
+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint16_t)0x0080) /*!<PI[9] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint16_t)0x0090) /*!<PJ[9] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI10 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint16_t)0x0000) /*!<PA[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint16_t)0x0100) /*!<PB[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint16_t)0x0200) /*!<PC[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint16_t)0x0300) /*!<PD[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint16_t)0x0400) /*!<PE[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint16_t)0x0500) /*!<PF[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint16_t)0x0600) /*!<PG[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint16_t)0x0700) /*!<PH[10] pin */\r
+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint16_t)0x0800) /*!<PI[10] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint16_t)0x0900) /*!<PJ[10] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI11 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint16_t)0x0000) /*!<PA[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint16_t)0x1000) /*!<PB[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint16_t)0x2000) /*!<PC[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint16_t)0x3000) /*!<PD[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint16_t)0x4000) /*!<PE[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint16_t)0x5000) /*!<PF[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint16_t)0x6000) /*!<PG[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint16_t)0x7000) /*!<PH[11] pin */\r
+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint16_t)0x8000) /*!<PI[11] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint16_t)0x9000) /*!<PJ[11] pin */\r
+#endif /* STM32F429X */\r
+\r
+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/\r
+#define SYSCFG_EXTICR4_EXTI12           ((uint16_t)0x000F) /*!<EXTI 12 configuration */\r
+#define SYSCFG_EXTICR4_EXTI13           ((uint16_t)0x00F0) /*!<EXTI 13 configuration */\r
+#define SYSCFG_EXTICR4_EXTI14           ((uint16_t)0x0F00) /*!<EXTI 14 configuration */\r
+#define SYSCFG_EXTICR4_EXTI15           ((uint16_t)0xF000) /*!<EXTI 15 configuration */\r
+/** \r
+  * @brief   EXTI12 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint16_t)0x0000) /*!<PA[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint16_t)0x0001) /*!<PB[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint16_t)0x0002) /*!<PC[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint16_t)0x0003) /*!<PD[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint16_t)0x0004) /*!<PE[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint16_t)0x0005) /*!<PF[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint16_t)0x0006) /*!<PG[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint16_t)0x0007) /*!<PH[12] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint16_t)0x0008) /*!<PI[12] pin */\r
+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint16_t)0x0009) /*!<PJ[12] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI13 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint16_t)0x0000) /*!<PA[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint16_t)0x0010) /*!<PB[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint16_t)0x0020) /*!<PC[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint16_t)0x0030) /*!<PD[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint16_t)0x0040) /*!<PE[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint16_t)0x0050) /*!<PF[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint16_t)0x0060) /*!<PG[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint16_t)0x0070) /*!<PH[13] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint16_t)0x0008) /*!<PI[13] pin */\r
+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint16_t)0x0009) /*!<PJ[13] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI14 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint16_t)0x0000) /*!<PA[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint16_t)0x0100) /*!<PB[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint16_t)0x0200) /*!<PC[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint16_t)0x0300) /*!<PD[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint16_t)0x0400) /*!<PE[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint16_t)0x0500) /*!<PF[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint16_t)0x0600) /*!<PG[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint16_t)0x0700) /*!<PH[14] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint16_t)0x0800) /*!<PI[14] pin */\r
+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint16_t)0x0900) /*!<PJ[14] pin */\r
+#endif /* STM32F429X */\r
+\r
+/** \r
+  * @brief   EXTI15 configuration  \r
+  */ \r
+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint16_t)0x0000) /*!<PA[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint16_t)0x1000) /*!<PB[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint16_t)0x2000) /*!<PC[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint16_t)0x3000) /*!<PD[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint16_t)0x4000) /*!<PE[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint16_t)0x5000) /*!<PF[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint16_t)0x6000) /*!<PG[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint16_t)0x7000) /*!<PH[15] pin */\r
+\r
+#if defined (STM32F429X)\r
+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint16_t)0x8000) /*!<PI[15] pin */\r
+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint16_t)0x9000) /*!<PJ[15] pin */\r
+#endif /* STM32F429X */\r
+\r
+/******************  Bit definition for SYSCFG_CMPCR register  ****************/  \r
+#define SYSCFG_CMPCR_CMP_PD             ((uint32_t)0x00000001) /*!<Compensation cell ready flag */\r
+#define SYSCFG_CMPCR_READY              ((uint32_t)0x00000100) /*!<Compensation cell power-down */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                    TIM                                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for TIM_CR1 register  ********************/\r
+#define  TIM_CR1_CEN                         ((uint16_t)0x0001)            /*!<Counter enable        */\r
+#define  TIM_CR1_UDIS                        ((uint16_t)0x0002)            /*!<Update disable        */\r
+#define  TIM_CR1_URS                         ((uint16_t)0x0004)            /*!<Update request source */\r
+#define  TIM_CR1_OPM                         ((uint16_t)0x0008)            /*!<One pulse mode        */\r
+#define  TIM_CR1_DIR                         ((uint16_t)0x0010)            /*!<Direction             */\r
+\r
+#define  TIM_CR1_CMS                         ((uint16_t)0x0060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */\r
+#define  TIM_CR1_CMS_0                       ((uint16_t)0x0020)            /*!<Bit 0 */\r
+#define  TIM_CR1_CMS_1                       ((uint16_t)0x0040)            /*!<Bit 1 */\r
+\r
+#define  TIM_CR1_ARPE                        ((uint16_t)0x0080)            /*!<Auto-reload preload enable     */\r
+\r
+#define  TIM_CR1_CKD                         ((uint16_t)0x0300)            /*!<CKD[1:0] bits (clock division) */\r
+#define  TIM_CR1_CKD_0                       ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CR1_CKD_1                       ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+/*******************  Bit definition for TIM_CR2 register  ********************/\r
+#define  TIM_CR2_CCPC                        ((uint16_t)0x0001)            /*!<Capture/Compare Preloaded Control        */\r
+#define  TIM_CR2_CCUS                        ((uint16_t)0x0004)            /*!<Capture/Compare Control Update Selection */\r
+#define  TIM_CR2_CCDS                        ((uint16_t)0x0008)            /*!<Capture/Compare DMA Selection            */\r
+\r
+#define  TIM_CR2_MMS                         ((uint16_t)0x0070)            /*!<MMS[2:0] bits (Master Mode Selection) */\r
+#define  TIM_CR2_MMS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CR2_MMS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CR2_MMS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CR2_TI1S                        ((uint16_t)0x0080)            /*!<TI1 Selection */\r
+#define  TIM_CR2_OIS1                        ((uint16_t)0x0100)            /*!<Output Idle state 1 (OC1 output)  */\r
+#define  TIM_CR2_OIS1N                       ((uint16_t)0x0200)            /*!<Output Idle state 1 (OC1N output) */\r
+#define  TIM_CR2_OIS2                        ((uint16_t)0x0400)            /*!<Output Idle state 2 (OC2 output)  */\r
+#define  TIM_CR2_OIS2N                       ((uint16_t)0x0800)            /*!<Output Idle state 2 (OC2N output) */\r
+#define  TIM_CR2_OIS3                        ((uint16_t)0x1000)            /*!<Output Idle state 3 (OC3 output)  */\r
+#define  TIM_CR2_OIS3N                       ((uint16_t)0x2000)            /*!<Output Idle state 3 (OC3N output) */\r
+#define  TIM_CR2_OIS4                        ((uint16_t)0x4000)            /*!<Output Idle state 4 (OC4 output)  */\r
+\r
+/*******************  Bit definition for TIM_SMCR register  *******************/\r
+#define  TIM_SMCR_SMS                        ((uint16_t)0x0007)            /*!<SMS[2:0] bits (Slave mode selection)    */\r
+#define  TIM_SMCR_SMS_0                      ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_SMCR_SMS_1                      ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  TIM_SMCR_SMS_2                      ((uint16_t)0x0004)            /*!<Bit 2 */\r
+\r
+#define  TIM_SMCR_TS                         ((uint16_t)0x0070)            /*!<TS[2:0] bits (Trigger selection)        */\r
+#define  TIM_SMCR_TS_0                       ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_SMCR_TS_1                       ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_SMCR_TS_2                       ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_SMCR_MSM                        ((uint16_t)0x0080)            /*!<Master/slave mode                       */\r
+\r
+#define  TIM_SMCR_ETF                        ((uint16_t)0x0F00)            /*!<ETF[3:0] bits (External trigger filter) */\r
+#define  TIM_SMCR_ETF_0                      ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_SMCR_ETF_1                      ((uint16_t)0x0200)            /*!<Bit 1 */\r
+#define  TIM_SMCR_ETF_2                      ((uint16_t)0x0400)            /*!<Bit 2 */\r
+#define  TIM_SMCR_ETF_3                      ((uint16_t)0x0800)            /*!<Bit 3 */\r
+\r
+#define  TIM_SMCR_ETPS                       ((uint16_t)0x3000)            /*!<ETPS[1:0] bits (External trigger prescaler) */\r
+#define  TIM_SMCR_ETPS_0                     ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_SMCR_ETPS_1                     ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  TIM_SMCR_ECE                        ((uint16_t)0x4000)            /*!<External clock enable     */\r
+#define  TIM_SMCR_ETP                        ((uint16_t)0x8000)            /*!<External trigger polarity */\r
+\r
+/*******************  Bit definition for TIM_DIER register  *******************/\r
+#define  TIM_DIER_UIE                        ((uint16_t)0x0001)            /*!<Update interrupt enable */\r
+#define  TIM_DIER_CC1IE                      ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt enable   */\r
+#define  TIM_DIER_CC2IE                      ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt enable   */\r
+#define  TIM_DIER_CC3IE                      ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt enable   */\r
+#define  TIM_DIER_CC4IE                      ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt enable   */\r
+#define  TIM_DIER_COMIE                      ((uint16_t)0x0020)            /*!<COM interrupt enable                 */\r
+#define  TIM_DIER_TIE                        ((uint16_t)0x0040)            /*!<Trigger interrupt enable             */\r
+#define  TIM_DIER_BIE                        ((uint16_t)0x0080)            /*!<Break interrupt enable               */\r
+#define  TIM_DIER_UDE                        ((uint16_t)0x0100)            /*!<Update DMA request enable            */\r
+#define  TIM_DIER_CC1DE                      ((uint16_t)0x0200)            /*!<Capture/Compare 1 DMA request enable */\r
+#define  TIM_DIER_CC2DE                      ((uint16_t)0x0400)            /*!<Capture/Compare 2 DMA request enable */\r
+#define  TIM_DIER_CC3DE                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 DMA request enable */\r
+#define  TIM_DIER_CC4DE                      ((uint16_t)0x1000)            /*!<Capture/Compare 4 DMA request enable */\r
+#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable               */\r
+#define  TIM_DIER_TDE                        ((uint16_t)0x4000)            /*!<Trigger DMA request enable           */\r
+\r
+/********************  Bit definition for TIM_SR register  ********************/\r
+#define  TIM_SR_UIF                          ((uint16_t)0x0001)            /*!<Update interrupt Flag              */\r
+#define  TIM_SR_CC1IF                        ((uint16_t)0x0002)            /*!<Capture/Compare 1 interrupt Flag   */\r
+#define  TIM_SR_CC2IF                        ((uint16_t)0x0004)            /*!<Capture/Compare 2 interrupt Flag   */\r
+#define  TIM_SR_CC3IF                        ((uint16_t)0x0008)            /*!<Capture/Compare 3 interrupt Flag   */\r
+#define  TIM_SR_CC4IF                        ((uint16_t)0x0010)            /*!<Capture/Compare 4 interrupt Flag   */\r
+#define  TIM_SR_COMIF                        ((uint16_t)0x0020)            /*!<COM interrupt Flag                 */\r
+#define  TIM_SR_TIF                          ((uint16_t)0x0040)            /*!<Trigger interrupt Flag             */\r
+#define  TIM_SR_BIF                          ((uint16_t)0x0080)            /*!<Break interrupt Flag               */\r
+#define  TIM_SR_CC1OF                        ((uint16_t)0x0200)            /*!<Capture/Compare 1 Overcapture Flag */\r
+#define  TIM_SR_CC2OF                        ((uint16_t)0x0400)            /*!<Capture/Compare 2 Overcapture Flag */\r
+#define  TIM_SR_CC3OF                        ((uint16_t)0x0800)            /*!<Capture/Compare 3 Overcapture Flag */\r
+#define  TIM_SR_CC4OF                        ((uint16_t)0x1000)            /*!<Capture/Compare 4 Overcapture Flag */\r
+\r
+/*******************  Bit definition for TIM_EGR register  ********************/\r
+#define  TIM_EGR_UG                          ((uint8_t)0x01)               /*!<Update Generation                         */\r
+#define  TIM_EGR_CC1G                        ((uint8_t)0x02)               /*!<Capture/Compare 1 Generation              */\r
+#define  TIM_EGR_CC2G                        ((uint8_t)0x04)               /*!<Capture/Compare 2 Generation              */\r
+#define  TIM_EGR_CC3G                        ((uint8_t)0x08)               /*!<Capture/Compare 3 Generation              */\r
+#define  TIM_EGR_CC4G                        ((uint8_t)0x10)               /*!<Capture/Compare 4 Generation              */\r
+#define  TIM_EGR_COMG                        ((uint8_t)0x20)               /*!<Capture/Compare Control Update Generation */\r
+#define  TIM_EGR_TG                          ((uint8_t)0x40)               /*!<Trigger Generation                        */\r
+#define  TIM_EGR_BG                          ((uint8_t)0x80)               /*!<Break Generation                          */\r
+\r
+/******************  Bit definition for TIM_CCMR1 register  *******************/\r
+#define  TIM_CCMR1_CC1S                      ((uint16_t)0x0003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */\r
+#define  TIM_CCMR1_CC1S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_CC1S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_OC1FE                     ((uint16_t)0x0004)            /*!<Output Compare 1 Fast enable                 */\r
+#define  TIM_CCMR1_OC1PE                     ((uint16_t)0x0008)            /*!<Output Compare 1 Preload enable              */\r
+\r
+#define  TIM_CCMR1_OC1M                      ((uint16_t)0x0070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */\r
+#define  TIM_CCMR1_OC1M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_OC1M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_OC1M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR1_OC1CE                     ((uint16_t)0x0080)            /*!<Output Compare 1Clear Enable                 */\r
+\r
+#define  TIM_CCMR1_CC2S                      ((uint16_t)0x0300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */\r
+#define  TIM_CCMR1_CC2S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_CC2S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_OC2FE                     ((uint16_t)0x0400)            /*!<Output Compare 2 Fast enable                 */\r
+#define  TIM_CCMR1_OC2PE                     ((uint16_t)0x0800)            /*!<Output Compare 2 Preload enable              */\r
+\r
+#define  TIM_CCMR1_OC2M                      ((uint16_t)0x7000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */\r
+#define  TIM_CCMR1_OC2M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_OC2M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_OC2M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR1_OC2CE                     ((uint16_t)0x8000)            /*!<Output Compare 2 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  TIM_CCMR1_IC1PSC                    ((uint16_t)0x000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */\r
+#define  TIM_CCMR1_IC1PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC1PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_IC1F                      ((uint16_t)0x00F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */\r
+#define  TIM_CCMR1_IC1F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC1F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_IC1F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+#define  TIM_CCMR1_IC1F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */\r
+\r
+#define  TIM_CCMR1_IC2PSC                    ((uint16_t)0x0C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */\r
+#define  TIM_CCMR1_IC2PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC2PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR1_IC2F                      ((uint16_t)0xF000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */\r
+#define  TIM_CCMR1_IC2F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR1_IC2F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR1_IC2F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+#define  TIM_CCMR1_IC2F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */\r
+\r
+/******************  Bit definition for TIM_CCMR2 register  *******************/\r
+#define  TIM_CCMR2_CC3S                      ((uint16_t)0x0003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */\r
+#define  TIM_CCMR2_CC3S_0                    ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_CC3S_1                    ((uint16_t)0x0002)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_OC3FE                     ((uint16_t)0x0004)            /*!<Output Compare 3 Fast enable           */\r
+#define  TIM_CCMR2_OC3PE                     ((uint16_t)0x0008)            /*!<Output Compare 3 Preload enable        */\r
+\r
+#define  TIM_CCMR2_OC3M                      ((uint16_t)0x0070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */\r
+#define  TIM_CCMR2_OC3M_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_OC3M_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_OC3M_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR2_OC3CE                     ((uint16_t)0x0080)            /*!<Output Compare 3 Clear Enable */\r
+\r
+#define  TIM_CCMR2_CC4S                      ((uint16_t)0x0300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */\r
+#define  TIM_CCMR2_CC4S_0                    ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_CC4S_1                    ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_OC4FE                     ((uint16_t)0x0400)            /*!<Output Compare 4 Fast enable    */\r
+#define  TIM_CCMR2_OC4PE                     ((uint16_t)0x0800)            /*!<Output Compare 4 Preload enable */\r
+\r
+#define  TIM_CCMR2_OC4M                      ((uint16_t)0x7000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */\r
+#define  TIM_CCMR2_OC4M_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_OC4M_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_OC4M_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+\r
+#define  TIM_CCMR2_OC4CE                     ((uint16_t)0x8000)            /*!<Output Compare 4 Clear Enable */\r
+\r
+/*----------------------------------------------------------------------------*/\r
+\r
+#define  TIM_CCMR2_IC3PSC                    ((uint16_t)0x000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */\r
+#define  TIM_CCMR2_IC3PSC_0                  ((uint16_t)0x0004)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC3PSC_1                  ((uint16_t)0x0008)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_IC3F                      ((uint16_t)0x00F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */\r
+#define  TIM_CCMR2_IC3F_0                    ((uint16_t)0x0010)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC3F_1                    ((uint16_t)0x0020)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_IC3F_2                    ((uint16_t)0x0040)            /*!<Bit 2 */\r
+#define  TIM_CCMR2_IC3F_3                    ((uint16_t)0x0080)            /*!<Bit 3 */\r
+\r
+#define  TIM_CCMR2_IC4PSC                    ((uint16_t)0x0C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */\r
+#define  TIM_CCMR2_IC4PSC_0                  ((uint16_t)0x0400)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC4PSC_1                  ((uint16_t)0x0800)            /*!<Bit 1 */\r
+\r
+#define  TIM_CCMR2_IC4F                      ((uint16_t)0xF000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */\r
+#define  TIM_CCMR2_IC4F_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  TIM_CCMR2_IC4F_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+#define  TIM_CCMR2_IC4F_2                    ((uint16_t)0x4000)            /*!<Bit 2 */\r
+#define  TIM_CCMR2_IC4F_3                    ((uint16_t)0x8000)            /*!<Bit 3 */\r
+\r
+/*******************  Bit definition for TIM_CCER register  *******************/\r
+#define  TIM_CCER_CC1E                       ((uint16_t)0x0001)            /*!<Capture/Compare 1 output enable                 */\r
+#define  TIM_CCER_CC1P                       ((uint16_t)0x0002)            /*!<Capture/Compare 1 output Polarity               */\r
+#define  TIM_CCER_CC1NE                      ((uint16_t)0x0004)            /*!<Capture/Compare 1 Complementary output enable   */\r
+#define  TIM_CCER_CC1NP                      ((uint16_t)0x0008)            /*!<Capture/Compare 1 Complementary output Polarity */\r
+#define  TIM_CCER_CC2E                       ((uint16_t)0x0010)            /*!<Capture/Compare 2 output enable                 */\r
+#define  TIM_CCER_CC2P                       ((uint16_t)0x0020)            /*!<Capture/Compare 2 output Polarity               */\r
+#define  TIM_CCER_CC2NE                      ((uint16_t)0x0040)            /*!<Capture/Compare 2 Complementary output enable   */\r
+#define  TIM_CCER_CC2NP                      ((uint16_t)0x0080)            /*!<Capture/Compare 2 Complementary output Polarity */\r
+#define  TIM_CCER_CC3E                       ((uint16_t)0x0100)            /*!<Capture/Compare 3 output enable                 */\r
+#define  TIM_CCER_CC3P                       ((uint16_t)0x0200)            /*!<Capture/Compare 3 output Polarity               */\r
+#define  TIM_CCER_CC3NE                      ((uint16_t)0x0400)            /*!<Capture/Compare 3 Complementary output enable   */\r
+#define  TIM_CCER_CC3NP                      ((uint16_t)0x0800)            /*!<Capture/Compare 3 Complementary output Polarity */\r
+#define  TIM_CCER_CC4E                       ((uint16_t)0x1000)            /*!<Capture/Compare 4 output enable                 */\r
+#define  TIM_CCER_CC4P                       ((uint16_t)0x2000)            /*!<Capture/Compare 4 output Polarity               */\r
+#define  TIM_CCER_CC4NP                      ((uint16_t)0x8000)            /*!<Capture/Compare 4 Complementary output Polarity */\r
+\r
+/*******************  Bit definition for TIM_CNT register  ********************/\r
+#define  TIM_CNT_CNT                         ((uint16_t)0xFFFF)            /*!<Counter Value            */\r
+\r
+/*******************  Bit definition for TIM_PSC register  ********************/\r
+#define  TIM_PSC_PSC                         ((uint16_t)0xFFFF)            /*!<Prescaler Value          */\r
+\r
+/*******************  Bit definition for TIM_ARR register  ********************/\r
+#define  TIM_ARR_ARR                         ((uint16_t)0xFFFF)            /*!<actual auto-reload Value */\r
+\r
+/*******************  Bit definition for TIM_RCR register  ********************/\r
+#define  TIM_RCR_REP                         ((uint8_t)0xFF)               /*!<Repetition Counter Value */\r
+\r
+/*******************  Bit definition for TIM_CCR1 register  *******************/\r
+#define  TIM_CCR1_CCR1                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 1 Value  */\r
+\r
+/*******************  Bit definition for TIM_CCR2 register  *******************/\r
+#define  TIM_CCR2_CCR2                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 2 Value  */\r
+\r
+/*******************  Bit definition for TIM_CCR3 register  *******************/\r
+#define  TIM_CCR3_CCR3                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 3 Value  */\r
+\r
+/*******************  Bit definition for TIM_CCR4 register  *******************/\r
+#define  TIM_CCR4_CCR4                       ((uint16_t)0xFFFF)            /*!<Capture/Compare 4 Value  */\r
+\r
+/*******************  Bit definition for TIM_BDTR register  *******************/\r
+#define  TIM_BDTR_DTG                        ((uint16_t)0x00FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */\r
+#define  TIM_BDTR_DTG_0                      ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_BDTR_DTG_1                      ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  TIM_BDTR_DTG_2                      ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  TIM_BDTR_DTG_3                      ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  TIM_BDTR_DTG_4                      ((uint16_t)0x0010)            /*!<Bit 4 */\r
+#define  TIM_BDTR_DTG_5                      ((uint16_t)0x0020)            /*!<Bit 5 */\r
+#define  TIM_BDTR_DTG_6                      ((uint16_t)0x0040)            /*!<Bit 6 */\r
+#define  TIM_BDTR_DTG_7                      ((uint16_t)0x0080)            /*!<Bit 7 */\r
+\r
+#define  TIM_BDTR_LOCK                       ((uint16_t)0x0300)            /*!<LOCK[1:0] bits (Lock Configuration) */\r
+#define  TIM_BDTR_LOCK_0                     ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_BDTR_LOCK_1                     ((uint16_t)0x0200)            /*!<Bit 1 */\r
+\r
+#define  TIM_BDTR_OSSI                       ((uint16_t)0x0400)            /*!<Off-State Selection for Idle mode */\r
+#define  TIM_BDTR_OSSR                       ((uint16_t)0x0800)            /*!<Off-State Selection for Run mode  */\r
+#define  TIM_BDTR_BKE                        ((uint16_t)0x1000)            /*!<Break enable                      */\r
+#define  TIM_BDTR_BKP                        ((uint16_t)0x2000)            /*!<Break Polarity                    */\r
+#define  TIM_BDTR_AOE                        ((uint16_t)0x4000)            /*!<Automatic Output enable           */\r
+#define  TIM_BDTR_MOE                        ((uint16_t)0x8000)            /*!<Main Output enable                */\r
+\r
+/*******************  Bit definition for TIM_DCR register  ********************/\r
+#define  TIM_DCR_DBA                         ((uint16_t)0x001F)            /*!<DBA[4:0] bits (DMA Base Address) */\r
+#define  TIM_DCR_DBA_0                       ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  TIM_DCR_DBA_1                       ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  TIM_DCR_DBA_2                       ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  TIM_DCR_DBA_3                       ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  TIM_DCR_DBA_4                       ((uint16_t)0x0010)            /*!<Bit 4 */\r
+\r
+#define  TIM_DCR_DBL                         ((uint16_t)0x1F00)            /*!<DBL[4:0] bits (DMA Burst Length) */\r
+#define  TIM_DCR_DBL_0                       ((uint16_t)0x0100)            /*!<Bit 0 */\r
+#define  TIM_DCR_DBL_1                       ((uint16_t)0x0200)            /*!<Bit 1 */\r
+#define  TIM_DCR_DBL_2                       ((uint16_t)0x0400)            /*!<Bit 2 */\r
+#define  TIM_DCR_DBL_3                       ((uint16_t)0x0800)            /*!<Bit 3 */\r
+#define  TIM_DCR_DBL_4                       ((uint16_t)0x1000)            /*!<Bit 4 */\r
+\r
+/*******************  Bit definition for TIM_DMAR register  *******************/\r
+#define  TIM_DMAR_DMAB                       ((uint16_t)0xFFFF)            /*!<DMA register for burst accesses                    */\r
+\r
+/*******************  Bit definition for TIM_OR register  *********************/\r
+#define TIM_OR_TI4_RMP                       ((uint16_t)0x00C0)            /*!<TI4_RMP[1:0] bits (TIM5 Input 4 remap)             */\r
+#define TIM_OR_TI4_RMP_0                     ((uint16_t)0x0040)            /*!<Bit 0 */\r
+#define TIM_OR_TI4_RMP_1                     ((uint16_t)0x0080)            /*!<Bit 1 */\r
+#define TIM_OR_ITR1_RMP                      ((uint16_t)0x0C00)            /*!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) */\r
+#define TIM_OR_ITR1_RMP_0                    ((uint16_t)0x0400)            /*!<Bit 0 */\r
+#define TIM_OR_ITR1_RMP_1                    ((uint16_t)0x0800)            /*!<Bit 1 */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*         Universal Synchronous Asynchronous Receiver Transmitter            */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for USART_SR register  *******************/\r
+#define  USART_SR_PE                         ((uint16_t)0x0001)            /*!<Parity Error                 */\r
+#define  USART_SR_FE                         ((uint16_t)0x0002)            /*!<Framing Error                */\r
+#define  USART_SR_NE                         ((uint16_t)0x0004)            /*!<Noise Error Flag             */\r
+#define  USART_SR_ORE                        ((uint16_t)0x0008)            /*!<OverRun Error                */\r
+#define  USART_SR_IDLE                       ((uint16_t)0x0010)            /*!<IDLE line detected           */\r
+#define  USART_SR_RXNE                       ((uint16_t)0x0020)            /*!<Read Data Register Not Empty */\r
+#define  USART_SR_TC                         ((uint16_t)0x0040)            /*!<Transmission Complete        */\r
+#define  USART_SR_TXE                        ((uint16_t)0x0080)            /*!<Transmit Data Register Empty */\r
+#define  USART_SR_LBD                        ((uint16_t)0x0100)            /*!<LIN Break Detection Flag     */\r
+#define  USART_SR_CTS                        ((uint16_t)0x0200)            /*!<CTS Flag                     */\r
+\r
+/*******************  Bit definition for USART_DR register  *******************/\r
+#define  USART_DR_DR                         ((uint16_t)0x01FF)            /*!<Data value */\r
+\r
+/******************  Bit definition for USART_BRR register  *******************/\r
+#define  USART_BRR_DIV_Fraction              ((uint16_t)0x000F)            /*!<Fraction of USARTDIV */\r
+#define  USART_BRR_DIV_Mantissa              ((uint16_t)0xFFF0)            /*!<Mantissa of USARTDIV */\r
+\r
+/******************  Bit definition for USART_CR1 register  *******************/\r
+#define  USART_CR1_SBK                       ((uint16_t)0x0001)            /*!<Send Break                             */\r
+#define  USART_CR1_RWU                       ((uint16_t)0x0002)            /*!<Receiver wakeup                        */\r
+#define  USART_CR1_RE                        ((uint16_t)0x0004)            /*!<Receiver Enable                        */\r
+#define  USART_CR1_TE                        ((uint16_t)0x0008)            /*!<Transmitter Enable                     */\r
+#define  USART_CR1_IDLEIE                    ((uint16_t)0x0010)            /*!<IDLE Interrupt Enable                  */\r
+#define  USART_CR1_RXNEIE                    ((uint16_t)0x0020)            /*!<RXNE Interrupt Enable                  */\r
+#define  USART_CR1_TCIE                      ((uint16_t)0x0040)            /*!<Transmission Complete Interrupt Enable */\r
+#define  USART_CR1_TXEIE                     ((uint16_t)0x0080)            /*!<PE Interrupt Enable                    */\r
+#define  USART_CR1_PEIE                      ((uint16_t)0x0100)            /*!<PE Interrupt Enable                    */\r
+#define  USART_CR1_PS                        ((uint16_t)0x0200)            /*!<Parity Selection                       */\r
+#define  USART_CR1_PCE                       ((uint16_t)0x0400)            /*!<Parity Control Enable                  */\r
+#define  USART_CR1_WAKE                      ((uint16_t)0x0800)            /*!<Wakeup method                          */\r
+#define  USART_CR1_M                         ((uint16_t)0x1000)            /*!<Word length                            */\r
+#define  USART_CR1_UE                        ((uint16_t)0x2000)            /*!<USART Enable                           */\r
+#define  USART_CR1_OVER8                     ((uint16_t)0x8000)            /*!<USART Oversampling by 8 enable         */\r
+\r
+/******************  Bit definition for USART_CR2 register  *******************/\r
+#define  USART_CR2_ADD                       ((uint16_t)0x000F)            /*!<Address of the USART node            */\r
+#define  USART_CR2_LBDL                      ((uint16_t)0x0020)            /*!<LIN Break Detection Length           */\r
+#define  USART_CR2_LBDIE                     ((uint16_t)0x0040)            /*!<LIN Break Detection Interrupt Enable */\r
+#define  USART_CR2_LBCL                      ((uint16_t)0x0100)            /*!<Last Bit Clock pulse                 */\r
+#define  USART_CR2_CPHA                      ((uint16_t)0x0200)            /*!<Clock Phase                          */\r
+#define  USART_CR2_CPOL                      ((uint16_t)0x0400)            /*!<Clock Polarity                       */\r
+#define  USART_CR2_CLKEN                     ((uint16_t)0x0800)            /*!<Clock Enable                         */\r
+\r
+#define  USART_CR2_STOP                      ((uint16_t)0x3000)            /*!<STOP[1:0] bits (STOP bits) */\r
+#define  USART_CR2_STOP_0                    ((uint16_t)0x1000)            /*!<Bit 0 */\r
+#define  USART_CR2_STOP_1                    ((uint16_t)0x2000)            /*!<Bit 1 */\r
+\r
+#define  USART_CR2_LINEN                     ((uint16_t)0x4000)            /*!<LIN mode enable */\r
+\r
+/******************  Bit definition for USART_CR3 register  *******************/\r
+#define  USART_CR3_EIE                       ((uint16_t)0x0001)            /*!<Error Interrupt Enable      */\r
+#define  USART_CR3_IREN                      ((uint16_t)0x0002)            /*!<IrDA mode Enable            */\r
+#define  USART_CR3_IRLP                      ((uint16_t)0x0004)            /*!<IrDA Low-Power              */\r
+#define  USART_CR3_HDSEL                     ((uint16_t)0x0008)            /*!<Half-Duplex Selection       */\r
+#define  USART_CR3_NACK                      ((uint16_t)0x0010)            /*!<Smartcard NACK enable       */\r
+#define  USART_CR3_SCEN                      ((uint16_t)0x0020)            /*!<Smartcard mode enable       */\r
+#define  USART_CR3_DMAR                      ((uint16_t)0x0040)            /*!<DMA Enable Receiver         */\r
+#define  USART_CR3_DMAT                      ((uint16_t)0x0080)            /*!<DMA Enable Transmitter      */\r
+#define  USART_CR3_RTSE                      ((uint16_t)0x0100)            /*!<RTS Enable                  */\r
+#define  USART_CR3_CTSE                      ((uint16_t)0x0200)            /*!<CTS Enable                  */\r
+#define  USART_CR3_CTSIE                     ((uint16_t)0x0400)            /*!<CTS Interrupt Enable        */\r
+#define  USART_CR3_ONEBIT                    ((uint16_t)0x0800)            /*!<USART One bit method enable */\r
+\r
+/******************  Bit definition for USART_GTPR register  ******************/\r
+#define  USART_GTPR_PSC                      ((uint16_t)0x00FF)            /*!<PSC[7:0] bits (Prescaler value) */\r
+#define  USART_GTPR_PSC_0                    ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  USART_GTPR_PSC_1                    ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  USART_GTPR_PSC_2                    ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  USART_GTPR_PSC_3                    ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  USART_GTPR_PSC_4                    ((uint16_t)0x0010)            /*!<Bit 4 */\r
+#define  USART_GTPR_PSC_5                    ((uint16_t)0x0020)            /*!<Bit 5 */\r
+#define  USART_GTPR_PSC_6                    ((uint16_t)0x0040)            /*!<Bit 6 */\r
+#define  USART_GTPR_PSC_7                    ((uint16_t)0x0080)            /*!<Bit 7 */\r
+\r
+#define  USART_GTPR_GT                       ((uint16_t)0xFF00)            /*!<Guard time value */\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                            Window WATCHDOG                                 */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/*******************  Bit definition for WWDG_CR register  ********************/\r
+#define  WWDG_CR_T                           ((uint8_t)0x7F)               /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */\r
+#define  WWDG_CR_T0                          ((uint8_t)0x01)               /*!<Bit 0 */\r
+#define  WWDG_CR_T1                          ((uint8_t)0x02)               /*!<Bit 1 */\r
+#define  WWDG_CR_T2                          ((uint8_t)0x04)               /*!<Bit 2 */\r
+#define  WWDG_CR_T3                          ((uint8_t)0x08)               /*!<Bit 3 */\r
+#define  WWDG_CR_T4                          ((uint8_t)0x10)               /*!<Bit 4 */\r
+#define  WWDG_CR_T5                          ((uint8_t)0x20)               /*!<Bit 5 */\r
+#define  WWDG_CR_T6                          ((uint8_t)0x40)               /*!<Bit 6 */\r
+\r
+#define  WWDG_CR_WDGA                        ((uint8_t)0x80)               /*!<Activation bit */\r
+\r
+/*******************  Bit definition for WWDG_CFR register  *******************/\r
+#define  WWDG_CFR_W                          ((uint16_t)0x007F)            /*!<W[6:0] bits (7-bit window value) */\r
+#define  WWDG_CFR_W0                         ((uint16_t)0x0001)            /*!<Bit 0 */\r
+#define  WWDG_CFR_W1                         ((uint16_t)0x0002)            /*!<Bit 1 */\r
+#define  WWDG_CFR_W2                         ((uint16_t)0x0004)            /*!<Bit 2 */\r
+#define  WWDG_CFR_W3                         ((uint16_t)0x0008)            /*!<Bit 3 */\r
+#define  WWDG_CFR_W4                         ((uint16_t)0x0010)            /*!<Bit 4 */\r
+#define  WWDG_CFR_W5                         ((uint16_t)0x0020)            /*!<Bit 5 */\r
+#define  WWDG_CFR_W6                         ((uint16_t)0x0040)            /*!<Bit 6 */\r
+\r
+#define  WWDG_CFR_WDGTB                      ((uint16_t)0x0180)            /*!<WDGTB[1:0] bits (Timer Base) */\r
+#define  WWDG_CFR_WDGTB0                     ((uint16_t)0x0080)            /*!<Bit 0 */\r
+#define  WWDG_CFR_WDGTB1                     ((uint16_t)0x0100)            /*!<Bit 1 */\r
+\r
+#define  WWDG_CFR_EWI                        ((uint16_t)0x0200)            /*!<Early Wakeup Interrupt */\r
+\r
+/*******************  Bit definition for WWDG_SR register  ********************/\r
+#define  WWDG_SR_EWIF                        ((uint8_t)0x01)               /*!<Early Wakeup Interrupt Flag */\r
+\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                                DBG                                         */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/********************  Bit definition for DBGMCU_IDCODE register  *************/\r
+#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)\r
+#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)\r
+\r
+/********************  Bit definition for DBGMCU_CR register  *****************/\r
+#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)\r
+#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)\r
+#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)\r
+#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)\r
+\r
+#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)\r
+#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)/*!<Bit 0 */\r
+#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)/*!<Bit 1 */\r
+\r
+/********************  Bit definition for DBGMCU_APB1_FZ register  ************/\r
+#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP            ((uint32_t)0x00000001)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP            ((uint32_t)0x00000002)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP            ((uint32_t)0x00000004)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP            ((uint32_t)0x00000008)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP            ((uint32_t)0x00000010)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP            ((uint32_t)0x00000020)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM12_STOP           ((uint32_t)0x00000040)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM13_STOP           ((uint32_t)0x00000080)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM14_STOP           ((uint32_t)0x00000100)\r
+#define  DBGMCU_APB1_FZ_DBG_RTC_STOP             ((uint32_t)0x00000400)\r
+#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP            ((uint32_t)0x00000800)\r
+#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP            ((uint32_t)0x00001000)\r
+#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   ((uint32_t)0x00200000)\r
+#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   ((uint32_t)0x00400000)\r
+#define  DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   ((uint32_t)0x00800000)\r
+#define  DBGMCU_APB1_FZ_DBG_CAN1_STOP            ((uint32_t)0x02000000)\r
+#define  DBGMCU_APB1_FZ_DBG_CAN2_STOP            ((uint32_t)0x04000000)\r
+/* Old IWDGSTOP bit definition, maintained for legacy purpose */\r
+#define  DBGMCU_APB1_FZ_DBG_IWDEG_STOP           DBGMCU_APB1_FZ_DBG_IWDG_STOP\r
+\r
+/********************  Bit definition for DBGMCU_APB2_FZ register  ************/\r
+#define  DBGMCU_APB1_FZ_DBG_TIM1_STOP        ((uint32_t)0x00000001)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM8_STOP        ((uint32_t)0x00000002)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM9_STOP        ((uint32_t)0x00010000)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM10_STOP       ((uint32_t)0x00020000)\r
+#define  DBGMCU_APB1_FZ_DBG_TIM11_STOP       ((uint32_t)0x00040000)\r
+\r
+/******************************************************************************/\r
+/*                                                                            */\r
+/*                Ethernet MAC Registers bits definitions                     */\r
+/*                                                                            */\r
+/******************************************************************************/\r
+/* Bit definition for Ethernet MAC Control Register register */\r
+#define ETH_MACCR_WD      ((uint32_t)0x00800000)  /* Watchdog disable */\r
+#define ETH_MACCR_JD      ((uint32_t)0x00400000)  /* Jabber disable */\r
+#define ETH_MACCR_IFG     ((uint32_t)0x000E0000)  /* Inter-frame gap */\r
+#define ETH_MACCR_IFG_96Bit     ((uint32_t)0x00000000)  /* Minimum IFG between frames during transmission is 96Bit */\r
+  #define ETH_MACCR_IFG_88Bit     ((uint32_t)0x00020000)  /* Minimum IFG between frames during transmission is 88Bit */\r
+  #define ETH_MACCR_IFG_80Bit     ((uint32_t)0x00040000)  /* Minimum IFG between frames during transmission is 80Bit */\r
+  #define ETH_MACCR_IFG_72Bit     ((uint32_t)0x00060000)  /* Minimum IFG between frames during transmission is 72Bit */\r
+  #define ETH_MACCR_IFG_64Bit     ((uint32_t)0x00080000)  /* Minimum IFG between frames during transmission is 64Bit */        \r
+  #define ETH_MACCR_IFG_56Bit     ((uint32_t)0x000A0000)  /* Minimum IFG between frames during transmission is 56Bit */\r
+  #define ETH_MACCR_IFG_48Bit     ((uint32_t)0x000C0000)  /* Minimum IFG between frames during transmission is 48Bit */\r
+  #define ETH_MACCR_IFG_40Bit     ((uint32_t)0x000E0000)  /* Minimum IFG between frames during transmission is 40Bit */              \r
+#define ETH_MACCR_CSD     ((uint32_t)0x00010000)  /* Carrier sense disable (during transmission) */\r
+#define ETH_MACCR_FES     ((uint32_t)0x00004000)  /* Fast ethernet speed */\r
+#define ETH_MACCR_ROD     ((uint32_t)0x00002000)  /* Receive own disable */\r
+#define ETH_MACCR_LM      ((uint32_t)0x00001000)  /* loopback mode */\r
+#define ETH_MACCR_DM      ((uint32_t)0x00000800)  /* Duplex mode */\r
+#define ETH_MACCR_IPCO    ((uint32_t)0x00000400)  /* IP Checksum offload */\r
+#define ETH_MACCR_RD      ((uint32_t)0x00000200)  /* Retry disable */\r
+#define ETH_MACCR_APCS    ((uint32_t)0x00000080)  /* Automatic Pad/CRC stripping */\r
+#define ETH_MACCR_BL      ((uint32_t)0x00000060)  /* Back-off limit: random integer number (r) of slot time delays before rescheduling\r
+                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */\r
+  #define ETH_MACCR_BL_10    ((uint32_t)0x00000000)  /* k = min (n, 10) */\r
+  #define ETH_MACCR_BL_8     ((uint32_t)0x00000020)  /* k = min (n, 8) */\r
+  #define ETH_MACCR_BL_4     ((uint32_t)0x00000040)  /* k = min (n, 4) */\r
+  #define ETH_MACCR_BL_1     ((uint32_t)0x00000060)  /* k = min (n, 1) */ \r
+#define ETH_MACCR_DC      ((uint32_t)0x00000010)  /* Defferal check */\r
+#define ETH_MACCR_TE      ((uint32_t)0x00000008)  /* Transmitter enable */\r
+#define ETH_MACCR_RE      ((uint32_t)0x00000004)  /* Receiver enable */\r
+\r
+/* Bit definition for Ethernet MAC Frame Filter Register */\r
+#define ETH_MACFFR_RA     ((uint32_t)0x80000000)  /* Receive all */ \r
+#define ETH_MACFFR_HPF    ((uint32_t)0x00000400)  /* Hash or perfect filter */ \r
+#define ETH_MACFFR_SAF    ((uint32_t)0x00000200)  /* Source address filter enable */ \r
+#define ETH_MACFFR_SAIF   ((uint32_t)0x00000100)  /* SA inverse filtering */ \r
+#define ETH_MACFFR_PCF    ((uint32_t)0x000000C0)  /* Pass control frames: 3 cases */\r
+  #define ETH_MACFFR_PCF_BlockAll                ((uint32_t)0x00000040)  /* MAC filters all control frames from reaching the application */\r
+  #define ETH_MACFFR_PCF_ForwardAll              ((uint32_t)0x00000080)  /* MAC forwards all control frames to application even if they fail the Address Filter */\r
+  #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0)  /* MAC forwards control frames that pass the Address Filter. */ \r
+#define ETH_MACFFR_BFD    ((uint32_t)0x00000020)  /* Broadcast frame disable */ \r
+#define ETH_MACFFR_PAM    ((uint32_t)0x00000010)  /* Pass all mutlicast */ \r
+#define ETH_MACFFR_DAIF   ((uint32_t)0x00000008)  /* DA Inverse filtering */ \r
+#define ETH_MACFFR_HM     ((uint32_t)0x00000004)  /* Hash multicast */ \r
+#define ETH_MACFFR_HU     ((uint32_t)0x00000002)  /* Hash unicast */\r
+#define ETH_MACFFR_PM     ((uint32_t)0x00000001)  /* Promiscuous mode */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table High Register */\r
+#define ETH_MACHTHR_HTH   ((uint32_t)0xFFFFFFFF)  /* Hash table high */\r
+\r
+/* Bit definition for Ethernet MAC Hash Table Low Register */\r
+#define ETH_MACHTLR_HTL   ((uint32_t)0xFFFFFFFF)  /* Hash table low */\r
+\r
+/* Bit definition for Ethernet MAC MII Address Register */\r
+#define ETH_MACMIIAR_PA   ((uint32_t)0x0000F800)  /* Physical layer address */ \r
+#define ETH_MACMIIAR_MR   ((uint32_t)0x000007C0)  /* MII register in the selected PHY */ \r
+#define ETH_MACMIIAR_CR   ((uint32_t)0x0000001C)  /* CR clock range: 6 cases */ \r
+  #define ETH_MACMIIAR_CR_Div42   ((uint32_t)0x00000000)  /* HCLK:60-100 MHz; MDC clock= HCLK/42 */\r
+  #define ETH_MACMIIAR_CR_Div62   ((uint32_t)0x00000004)  /* HCLK:100-150 MHz; MDC clock= HCLK/62 */\r
+  #define ETH_MACMIIAR_CR_Div16   ((uint32_t)0x00000008)  /* HCLK:20-35 MHz; MDC clock= HCLK/16 */\r
+  #define ETH_MACMIIAR_CR_Div26   ((uint32_t)0x0000000C)  /* HCLK:35-60 MHz; MDC clock= HCLK/26 */\r
+  #define ETH_MACMIIAR_CR_Div102  ((uint32_t)0x00000010)  /* HCLK:150-168 MHz; MDC clock= HCLK/102 */  \r
+#define ETH_MACMIIAR_MW   ((uint32_t)0x00000002)  /* MII write */ \r
+#define ETH_MACMIIAR_MB   ((uint32_t)0x00000001)  /* MII busy */ \r
+  \r
+/* Bit definition for Ethernet MAC MII Data Register */\r
+#define ETH_MACMIIDR_MD   ((uint32_t)0x0000FFFF)  /* MII data: read/write data from/to PHY */\r
+\r
+/* Bit definition for Ethernet MAC Flow Control Register */\r
+#define ETH_MACFCR_PT     ((uint32_t)0xFFFF0000)  /* Pause time */\r
+#define ETH_MACFCR_ZQPD   ((uint32_t)0x00000080)  /* Zero-quanta pause disable */\r
+#define ETH_MACFCR_PLT    ((uint32_t)0x00000030)  /* Pause low threshold: 4 cases */\r
+  #define ETH_MACFCR_PLT_Minus4   ((uint32_t)0x00000000)  /* Pause time minus 4 slot times */\r
+  #define ETH_MACFCR_PLT_Minus28  ((uint32_t)0x00000010)  /* Pause time minus 28 slot times */\r
+  #define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020)  /* Pause time minus 144 slot times */\r
+  #define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030)  /* Pause time minus 256 slot times */      \r
+#define ETH_MACFCR_UPFD   ((uint32_t)0x00000008)  /* Unicast pause frame detect */\r
+#define ETH_MACFCR_RFCE   ((uint32_t)0x00000004)  /* Receive flow control enable */\r
+#define ETH_MACFCR_TFCE   ((uint32_t)0x00000002)  /* Transmit flow control enable */\r
+#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001)  /* Flow control busy/backpressure activate */\r
+\r
+/* Bit definition for Ethernet MAC VLAN Tag Register */\r
+#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000)  /* 12-bit VLAN tag comparison */\r
+#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF)  /* VLAN tag identifier (for receive frames) */\r
+\r
+/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ \r
+#define ETH_MACRWUFFR_D   ((uint32_t)0xFFFFFFFF)  /* Wake-up frame filter register data */\r
+/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.\r
+   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */\r
+/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask\r
+   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask\r
+   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask\r
+   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask\r
+   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - \r
+                              RSVD - Filter1 Command - RSVD - Filter0 Command\r
+   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset\r
+   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16\r
+   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */\r
+\r
+/* Bit definition for Ethernet MAC PMT Control and Status Register */ \r
+#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000)  /* Wake-Up Frame Filter Register Pointer Reset */\r
+#define ETH_MACPMTCSR_GU     ((uint32_t)0x00000200)  /* Global Unicast */\r
+#define ETH_MACPMTCSR_WFR    ((uint32_t)0x00000040)  /* Wake-Up Frame Received */\r
+#define ETH_MACPMTCSR_MPR    ((uint32_t)0x00000020)  /* Magic Packet Received */\r
+#define ETH_MACPMTCSR_WFE    ((uint32_t)0x00000004)  /* Wake-Up Frame Enable */\r
+#define ETH_MACPMTCSR_MPE    ((uint32_t)0x00000002)  /* Magic Packet Enable */\r
+#define ETH_MACPMTCSR_PD     ((uint32_t)0x00000001)  /* Power Down */\r
+\r
+/* Bit definition for Ethernet MAC Status Register */\r
+#define ETH_MACSR_TSTS      ((uint32_t)0x00000200)  /* Time stamp trigger status */\r
+#define ETH_MACSR_MMCTS     ((uint32_t)0x00000040)  /* MMC transmit status */\r
+#define ETH_MACSR_MMMCRS    ((uint32_t)0x00000020)  /* MMC receive status */\r
+#define ETH_MACSR_MMCS      ((uint32_t)0x00000010)  /* MMC status */\r
+#define ETH_MACSR_PMTS      ((uint32_t)0x00000008)  /* PMT status */\r
+\r
+/* Bit definition for Ethernet MAC Interrupt Mask Register */\r
+#define ETH_MACIMR_TSTIM     ((uint32_t)0x00000200)  /* Time stamp trigger interrupt mask */\r
+#define ETH_MACIMR_PMTIM     ((uint32_t)0x00000008)  /* PMT interrupt mask */\r
+\r
+/* Bit definition for Ethernet MAC Address0 High Register */\r
+#define ETH_MACA0HR_MACA0H   ((uint32_t)0x0000FFFF)  /* MAC address0 high */\r
+\r
+/* Bit definition for Ethernet MAC Address0 Low Register */\r
+#define ETH_MACA0LR_MACA0L   ((uint32_t)0xFFFFFFFF)  /* MAC address0 low */\r
+\r
+/* Bit definition for Ethernet MAC Address1 High Register */\r
+#define ETH_MACA1HR_AE       ((uint32_t)0x80000000)  /* Address enable */\r
+#define ETH_MACA1HR_SA       ((uint32_t)0x40000000)  /* Source address */\r
+#define ETH_MACA1HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control: bits to mask for comparison of the MAC Address bytes */\r
+  #define ETH_MACA1HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\r
+  #define ETH_MACA1HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\r
+  #define ETH_MACA1HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\r
+  #define ETH_MACA1HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\r
+  #define ETH_MACA1HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\r
+  #define ETH_MACA1HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [7:0] */ \r
+#define ETH_MACA1HR_MACA1H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address1 Low Register */\r
+#define ETH_MACA1LR_MACA1L   ((uint32_t)0xFFFFFFFF)  /* MAC address1 low */\r
+\r
+/* Bit definition for Ethernet MAC Address2 High Register */\r
+#define ETH_MACA2HR_AE       ((uint32_t)0x80000000)  /* Address enable */\r
+#define ETH_MACA2HR_SA       ((uint32_t)0x40000000)  /* Source address */\r
+#define ETH_MACA2HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */\r
+  #define ETH_MACA2HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\r
+  #define ETH_MACA2HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\r
+  #define ETH_MACA2HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\r
+  #define ETH_MACA2HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\r
+  #define ETH_MACA2HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\r
+  #define ETH_MACA2HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA2HR_MACA2H   ((uint32_t)0x0000FFFF)  /* MAC address1 high */\r
+\r
+/* Bit definition for Ethernet MAC Address2 Low Register */\r
+#define ETH_MACA2LR_MACA2L   ((uint32_t)0xFFFFFFFF)  /* MAC address2 low */\r
+\r
+/* Bit definition for Ethernet MAC Address3 High Register */\r
+#define ETH_MACA3HR_AE       ((uint32_t)0x80000000)  /* Address enable */\r
+#define ETH_MACA3HR_SA       ((uint32_t)0x40000000)  /* Source address */\r
+#define ETH_MACA3HR_MBC      ((uint32_t)0x3F000000)  /* Mask byte control */\r
+  #define ETH_MACA3HR_MBC_HBits15_8    ((uint32_t)0x20000000)  /* Mask MAC Address high reg bits [15:8] */\r
+  #define ETH_MACA3HR_MBC_HBits7_0     ((uint32_t)0x10000000)  /* Mask MAC Address high reg bits [7:0] */\r
+  #define ETH_MACA3HR_MBC_LBits31_24   ((uint32_t)0x08000000)  /* Mask MAC Address low reg bits [31:24] */\r
+  #define ETH_MACA3HR_MBC_LBits23_16   ((uint32_t)0x04000000)  /* Mask MAC Address low reg bits [23:16] */\r
+  #define ETH_MACA3HR_MBC_LBits15_8    ((uint32_t)0x02000000)  /* Mask MAC Address low reg bits [15:8] */\r
+  #define ETH_MACA3HR_MBC_LBits7_0     ((uint32_t)0x01000000)  /* Mask MAC Address low reg bits [70] */\r
+#define ETH_MACA3HR_MACA3H   ((uint32_t)0x0000FFFF)  /* MAC address3 high */\r
+\r
+/* Bit definition for Ethernet MAC Address3 Low Register */\r
+#define ETH_MACA3LR_MACA3L   ((uint32_t)0xFFFFFFFF)  /* MAC address3 low */\r
+\r
+/******************************************************************************/\r
+/*                Ethernet MMC Registers bits definition                      */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet MMC Contol Register */\r
+#define ETH_MMCCR_MCFHP      ((uint32_t)0x00000020)  /* MMC counter Full-Half preset */\r
+#define ETH_MMCCR_MCP        ((uint32_t)0x00000010)  /* MMC counter preset */\r
+#define ETH_MMCCR_MCF        ((uint32_t)0x00000008)  /* MMC Counter Freeze */\r
+#define ETH_MMCCR_ROR        ((uint32_t)0x00000004)  /* Reset on Read */\r
+#define ETH_MMCCR_CSR        ((uint32_t)0x00000002)  /* Counter Stop Rollover */\r
+#define ETH_MMCCR_CR         ((uint32_t)0x00000001)  /* Counters Reset */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Register */\r
+#define ETH_MMCRIR_RGUFS     ((uint32_t)0x00020000)  /* Set when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFAES     ((uint32_t)0x00000040)  /* Set when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIR_RFCES     ((uint32_t)0x00000020)  /* Set when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Register */\r
+#define ETH_MMCTIR_TGFS      ((uint32_t)0x00200000)  /* Set when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFMSCS   ((uint32_t)0x00008000)  /* Set when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIR_TGFSCS    ((uint32_t)0x00004000)  /* Set when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */\r
+#define ETH_MMCRIMR_RGUFM    ((uint32_t)0x00020000)  /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFAEM    ((uint32_t)0x00000040)  /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */\r
+#define ETH_MMCRIMR_RFCEM    ((uint32_t)0x00000020)  /* Mask the interrupt when Rx crc error counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */\r
+#define ETH_MMCTIMR_TGFM     ((uint32_t)0x00200000)  /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFMSCM  ((uint32_t)0x00008000)  /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */\r
+#define ETH_MMCTIMR_TGFSCM   ((uint32_t)0x00004000)  /* Mask the interrupt when Tx good single col counter reaches half the maximum value */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */\r
+#define ETH_MMCTGFSCCR_TGFSCC     ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */\r
+#define ETH_MMCTGFMSCCR_TGFMSCC   ((uint32_t)0xFFFFFFFF)  /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */\r
+\r
+/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */\r
+#define ETH_MMCTGFCR_TGFC    ((uint32_t)0xFFFFFFFF)  /* Number of good frames transmitted. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */\r
+#define ETH_MMCRFCECR_RFCEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with CRC error. */\r
+\r
+/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */\r
+#define ETH_MMCRFAECR_RFAEC  ((uint32_t)0xFFFFFFFF)  /* Number of frames received with alignment (dribble) error */\r
+\r
+/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */\r
+#define ETH_MMCRGUFCR_RGUFC  ((uint32_t)0xFFFFFFFF)  /* Number of good unicast frames received. */\r
+\r
+/******************************************************************************/\r
+/*               Ethernet PTP Registers bits definition                       */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Contol Register */\r
+#define ETH_PTPTSCR_TSCNT       ((uint32_t)0x00030000)  /* Time stamp clock node type */\r
+#define ETH_PTPTSSR_TSSMRME     ((uint32_t)0x00008000)  /* Time stamp snapshot for message relevant to master enable */\r
+#define ETH_PTPTSSR_TSSEME      ((uint32_t)0x00004000)  /* Time stamp snapshot for event message enable */\r
+#define ETH_PTPTSSR_TSSIPV4FE   ((uint32_t)0x00002000)  /* Time stamp snapshot for IPv4 frames enable */\r
+#define ETH_PTPTSSR_TSSIPV6FE   ((uint32_t)0x00001000)  /* Time stamp snapshot for IPv6 frames enable */\r
+#define ETH_PTPTSSR_TSSPTPOEFE  ((uint32_t)0x00000800)  /* Time stamp snapshot for PTP over ethernet frames enable */\r
+#define ETH_PTPTSSR_TSPTPPSV2E  ((uint32_t)0x00000400)  /* Time stamp PTP packet snooping for version2 format enable */\r
+#define ETH_PTPTSSR_TSSSR       ((uint32_t)0x00000200)  /* Time stamp Sub-seconds rollover */\r
+#define ETH_PTPTSSR_TSSARFE     ((uint32_t)0x00000100)  /* Time stamp snapshot for all received frames enable */\r
+\r
+#define ETH_PTPTSCR_TSARU    ((uint32_t)0x00000020)  /* Addend register update */\r
+#define ETH_PTPTSCR_TSITE    ((uint32_t)0x00000010)  /* Time stamp interrupt trigger enable */\r
+#define ETH_PTPTSCR_TSSTU    ((uint32_t)0x00000008)  /* Time stamp update */\r
+#define ETH_PTPTSCR_TSSTI    ((uint32_t)0x00000004)  /* Time stamp initialize */\r
+#define ETH_PTPTSCR_TSFCU    ((uint32_t)0x00000002)  /* Time stamp fine or coarse update */\r
+#define ETH_PTPTSCR_TSE      ((uint32_t)0x00000001)  /* Time stamp enable */\r
+\r
+/* Bit definition for Ethernet PTP Sub-Second Increment Register */\r
+#define ETH_PTPSSIR_STSSI    ((uint32_t)0x000000FF)  /* System time Sub-second increment value */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Register */\r
+#define ETH_PTPTSHR_STS      ((uint32_t)0xFFFFFFFF)  /* System Time second */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Register */\r
+#define ETH_PTPTSLR_STPNS    ((uint32_t)0x80000000)  /* System Time Positive or negative time */\r
+#define ETH_PTPTSLR_STSS     ((uint32_t)0x7FFFFFFF)  /* System Time sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp High Update Register */\r
+#define ETH_PTPTSHUR_TSUS    ((uint32_t)0xFFFFFFFF)  /* Time stamp update seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Low Update Register */\r
+#define ETH_PTPTSLUR_TSUPNS  ((uint32_t)0x80000000)  /* Time stamp update Positive or negative time */\r
+#define ETH_PTPTSLUR_TSUSS   ((uint32_t)0x7FFFFFFF)  /* Time stamp update sub-seconds */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Addend Register */\r
+#define ETH_PTPTSAR_TSA      ((uint32_t)0xFFFFFFFF)  /* Time stamp addend */\r
+\r
+/* Bit definition for Ethernet PTP Target Time High Register */\r
+#define ETH_PTPTTHR_TTSH     ((uint32_t)0xFFFFFFFF)  /* Target time stamp high */\r
+\r
+/* Bit definition for Ethernet PTP Target Time Low Register */\r
+#define ETH_PTPTTLR_TTSL     ((uint32_t)0xFFFFFFFF)  /* Target time stamp low */\r
+\r
+/* Bit definition for Ethernet PTP Time Stamp Status Register */\r
+#define ETH_PTPTSSR_TSTTR    ((uint32_t)0x00000020)  /* Time stamp target time reached */\r
+#define ETH_PTPTSSR_TSSO     ((uint32_t)0x00000010)  /* Time stamp seconds overflow */\r
+\r
+/******************************************************************************/\r
+/*                 Ethernet DMA Registers bits definition                     */\r
+/******************************************************************************/\r
+\r
+/* Bit definition for Ethernet DMA Bus Mode Register */\r
+#define ETH_DMABMR_AAB       ((uint32_t)0x02000000)  /* Address-Aligned beats */\r
+#define ETH_DMABMR_FPM        ((uint32_t)0x01000000)  /* 4xPBL mode */\r
+#define ETH_DMABMR_USP       ((uint32_t)0x00800000)  /* Use separate PBL */\r
+#define ETH_DMABMR_RDP       ((uint32_t)0x007E0000)  /* RxDMA PBL */\r
+  #define ETH_DMABMR_RDP_1Beat    ((uint32_t)0x00020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 1 */\r
+  #define ETH_DMABMR_RDP_2Beat    ((uint32_t)0x00040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 2 */\r
+  #define ETH_DMABMR_RDP_4Beat    ((uint32_t)0x00080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+  #define ETH_DMABMR_RDP_8Beat    ((uint32_t)0x00100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+  #define ETH_DMABMR_RDP_16Beat   ((uint32_t)0x00200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+  #define ETH_DMABMR_RDP_32Beat   ((uint32_t)0x00400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */                \r
+  #define ETH_DMABMR_RDP_4xPBL_4Beat   ((uint32_t)0x01020000)  /* maximum number of beats to be transferred in one RxDMA transaction is 4 */\r
+  #define ETH_DMABMR_RDP_4xPBL_8Beat   ((uint32_t)0x01040000)  /* maximum number of beats to be transferred in one RxDMA transaction is 8 */\r
+  #define ETH_DMABMR_RDP_4xPBL_16Beat  ((uint32_t)0x01080000)  /* maximum number of beats to be transferred in one RxDMA transaction is 16 */\r
+  #define ETH_DMABMR_RDP_4xPBL_32Beat  ((uint32_t)0x01100000)  /* maximum number of beats to be transferred in one RxDMA transaction is 32 */\r
+  #define ETH_DMABMR_RDP_4xPBL_64Beat  ((uint32_t)0x01200000)  /* maximum number of beats to be transferred in one RxDMA transaction is 64 */\r
+  #define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000)  /* maximum number of beats to be transferred in one RxDMA transaction is 128 */  \r
+#define ETH_DMABMR_FB        ((uint32_t)0x00010000)  /* Fixed Burst */\r
+#define ETH_DMABMR_RTPR      ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */\r
+  #define ETH_DMABMR_RTPR_1_1     ((uint32_t)0x00000000)  /* Rx Tx priority ratio */\r
+  #define ETH_DMABMR_RTPR_2_1     ((uint32_t)0x00004000)  /* Rx Tx priority ratio */\r
+  #define ETH_DMABMR_RTPR_3_1     ((uint32_t)0x00008000)  /* Rx Tx priority ratio */\r
+  #define ETH_DMABMR_RTPR_4_1     ((uint32_t)0x0000C000)  /* Rx Tx priority ratio */  \r
+#define ETH_DMABMR_PBL    ((uint32_t)0x00003F00)  /* Programmable burst length */\r
+  #define ETH_DMABMR_PBL_1Beat    ((uint32_t)0x00000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */\r
+  #define ETH_DMABMR_PBL_2Beat    ((uint32_t)0x00000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */\r
+  #define ETH_DMABMR_PBL_4Beat    ((uint32_t)0x00000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+  #define ETH_DMABMR_PBL_8Beat    ((uint32_t)0x00000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+  #define ETH_DMABMR_PBL_16Beat   ((uint32_t)0x00001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+  #define ETH_DMABMR_PBL_32Beat   ((uint32_t)0x00002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */                \r
+  #define ETH_DMABMR_PBL_4xPBL_4Beat   ((uint32_t)0x01000100)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */\r
+  #define ETH_DMABMR_PBL_4xPBL_8Beat   ((uint32_t)0x01000200)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */\r
+  #define ETH_DMABMR_PBL_4xPBL_16Beat  ((uint32_t)0x01000400)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */\r
+  #define ETH_DMABMR_PBL_4xPBL_32Beat  ((uint32_t)0x01000800)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */\r
+  #define ETH_DMABMR_PBL_4xPBL_64Beat  ((uint32_t)0x01001000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */\r
+  #define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000)  /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */\r
+#define ETH_DMABMR_EDE       ((uint32_t)0x00000080)  /* Enhanced Descriptor Enable */\r
+#define ETH_DMABMR_DSL       ((uint32_t)0x0000007C)  /* Descriptor Skip Length */\r
+#define ETH_DMABMR_DA        ((uint32_t)0x00000002)  /* DMA arbitration scheme */\r
+#define ETH_DMABMR_SR        ((uint32_t)0x00000001)  /* Software reset */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Poll Demand Register */\r
+#define ETH_DMATPDR_TPD      ((uint32_t)0xFFFFFFFF)  /* Transmit poll demand */\r
+\r
+/* Bit definition for Ethernet DMA Receive Poll Demand Register */\r
+#define ETH_DMARPDR_RPD      ((uint32_t)0xFFFFFFFF)  /* Receive poll demand  */\r
+\r
+/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */\r
+#define ETH_DMARDLAR_SRL     ((uint32_t)0xFFFFFFFF)  /* Start of receive list */\r
+\r
+/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */\r
+#define ETH_DMATDLAR_STL     ((uint32_t)0xFFFFFFFF)  /* Start of transmit list */\r
+\r
+/* Bit definition for Ethernet DMA Status Register */\r
+#define ETH_DMASR_TSTS       ((uint32_t)0x20000000)  /* Time-stamp trigger status */\r
+#define ETH_DMASR_PMTS       ((uint32_t)0x10000000)  /* PMT status */\r
+#define ETH_DMASR_MMCS       ((uint32_t)0x08000000)  /* MMC status */\r
+#define ETH_DMASR_EBS        ((uint32_t)0x03800000)  /* Error bits status */\r
+  /* combination with EBS[2:0] for GetFlagStatus function */\r
+  #define ETH_DMASR_EBS_DescAccess      ((uint32_t)0x02000000)  /* Error bits 0-data buffer, 1-desc. access */\r
+  #define ETH_DMASR_EBS_ReadTransf      ((uint32_t)0x01000000)  /* Error bits 0-write trnsf, 1-read transfr */\r
+  #define ETH_DMASR_EBS_DataTransfTx    ((uint32_t)0x00800000)  /* Error bits 0-Rx DMA, 1-Tx DMA */\r
+#define ETH_DMASR_TPS         ((uint32_t)0x00700000)  /* Transmit process state */\r
+  #define ETH_DMASR_TPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Tx Command issued  */\r
+  #define ETH_DMASR_TPS_Fetching        ((uint32_t)0x00100000)  /* Running - fetching the Tx descriptor */\r
+  #define ETH_DMASR_TPS_Waiting         ((uint32_t)0x00200000)  /* Running - waiting for status */\r
+  #define ETH_DMASR_TPS_Reading         ((uint32_t)0x00300000)  /* Running - reading the data from host memory */\r
+  #define ETH_DMASR_TPS_Suspended       ((uint32_t)0x00600000)  /* Suspended - Tx Descriptor unavailabe */\r
+  #define ETH_DMASR_TPS_Closing         ((uint32_t)0x00700000)  /* Running - closing Rx descriptor */\r
+#define ETH_DMASR_RPS         ((uint32_t)0x000E0000)  /* Receive process state */\r
+  #define ETH_DMASR_RPS_Stopped         ((uint32_t)0x00000000)  /* Stopped - Reset or Stop Rx Command issued */\r
+  #define ETH_DMASR_RPS_Fetching        ((uint32_t)0x00020000)  /* Running - fetching the Rx descriptor */\r
+  #define ETH_DMASR_RPS_Waiting         ((uint32_t)0x00060000)  /* Running - waiting for packet */\r
+  #define ETH_DMASR_RPS_Suspended       ((uint32_t)0x00080000)  /* Suspended - Rx Descriptor unavailable */\r
+  #define ETH_DMASR_RPS_Closing         ((uint32_t)0x000A0000)  /* Running - closing descriptor */\r
+  #define ETH_DMASR_RPS_Queuing         ((uint32_t)0x000E0000)  /* Running - queuing the recieve frame into host memory */\r
+#define ETH_DMASR_NIS        ((uint32_t)0x00010000)  /* Normal interrupt summary */\r
+#define ETH_DMASR_AIS        ((uint32_t)0x00008000)  /* Abnormal interrupt summary */\r
+#define ETH_DMASR_ERS        ((uint32_t)0x00004000)  /* Early receive status */\r
+#define ETH_DMASR_FBES       ((uint32_t)0x00002000)  /* Fatal bus error status */\r
+#define ETH_DMASR_ETS        ((uint32_t)0x00000400)  /* Early transmit status */\r
+#define ETH_DMASR_RWTS       ((uint32_t)0x00000200)  /* Receive watchdog timeout status */\r
+#define ETH_DMASR_RPSS       ((uint32_t)0x00000100)  /* Receive process stopped status */\r
+#define ETH_DMASR_RBUS       ((uint32_t)0x00000080)  /* Receive buffer unavailable status */\r
+#define ETH_DMASR_RS         ((uint32_t)0x00000040)  /* Receive status */\r
+#define ETH_DMASR_TUS        ((uint32_t)0x00000020)  /* Transmit underflow status */\r
+#define ETH_DMASR_ROS        ((uint32_t)0x00000010)  /* Receive overflow status */\r
+#define ETH_DMASR_TJTS       ((uint32_t)0x00000008)  /* Transmit jabber timeout status */\r
+#define ETH_DMASR_TBUS       ((uint32_t)0x00000004)  /* Transmit buffer unavailable status */\r
+#define ETH_DMASR_TPSS       ((uint32_t)0x00000002)  /* Transmit process stopped status */\r
+#define ETH_DMASR_TS         ((uint32_t)0x00000001)  /* Transmit status */\r
+\r
+/* Bit definition for Ethernet DMA Operation Mode Register */\r
+#define ETH_DMAOMR_DTCEFD    ((uint32_t)0x04000000)  /* Disable Dropping of TCP/IP checksum error frames */\r
+#define ETH_DMAOMR_RSF       ((uint32_t)0x02000000)  /* Receive store and forward */\r
+#define ETH_DMAOMR_DFRF      ((uint32_t)0x01000000)  /* Disable flushing of received frames */\r
+#define ETH_DMAOMR_TSF       ((uint32_t)0x00200000)  /* Transmit store and forward */\r
+#define ETH_DMAOMR_FTF       ((uint32_t)0x00100000)  /* Flush transmit FIFO */\r
+#define ETH_DMAOMR_TTC       ((uint32_t)0x0001C000)  /* Transmit threshold control */\r
+  #define ETH_DMAOMR_TTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Transmit FIFO is 64 Bytes */\r
+  #define ETH_DMAOMR_TTC_128Bytes      ((uint32_t)0x00004000)  /* threshold level of the MTL Transmit FIFO is 128 Bytes */\r
+  #define ETH_DMAOMR_TTC_192Bytes      ((uint32_t)0x00008000)  /* threshold level of the MTL Transmit FIFO is 192 Bytes */\r
+  #define ETH_DMAOMR_TTC_256Bytes      ((uint32_t)0x0000C000)  /* threshold level of the MTL Transmit FIFO is 256 Bytes */\r
+  #define ETH_DMAOMR_TTC_40Bytes       ((uint32_t)0x00010000)  /* threshold level of the MTL Transmit FIFO is 40 Bytes */\r
+  #define ETH_DMAOMR_TTC_32Bytes       ((uint32_t)0x00014000)  /* threshold level of the MTL Transmit FIFO is 32 Bytes */\r
+  #define ETH_DMAOMR_TTC_24Bytes       ((uint32_t)0x00018000)  /* threshold level of the MTL Transmit FIFO is 24 Bytes */\r
+  #define ETH_DMAOMR_TTC_16Bytes       ((uint32_t)0x0001C000)  /* threshold level of the MTL Transmit FIFO is 16 Bytes */\r
+#define ETH_DMAOMR_ST        ((uint32_t)0x00002000)  /* Start/stop transmission command */\r
+#define ETH_DMAOMR_FEF       ((uint32_t)0x00000080)  /* Forward error frames */\r
+#define ETH_DMAOMR_FUGF      ((uint32_t)0x00000040)  /* Forward undersized good frames */\r
+#define ETH_DMAOMR_RTC       ((uint32_t)0x00000018)  /* receive threshold control */\r
+  #define ETH_DMAOMR_RTC_64Bytes       ((uint32_t)0x00000000)  /* threshold level of the MTL Receive FIFO is 64 Bytes */\r
+  #define ETH_DMAOMR_RTC_32Bytes       ((uint32_t)0x00000008)  /* threshold level of the MTL Receive FIFO is 32 Bytes */\r
+  #define ETH_DMAOMR_RTC_96Bytes       ((uint32_t)0x00000010)  /* threshold level of the MTL Receive FIFO is 96 Bytes */\r
+  #define ETH_DMAOMR_RTC_128Bytes      ((uint32_t)0x00000018)  /* threshold level of the MTL Receive FIFO is 128 Bytes */\r
+#define ETH_DMAOMR_OSF       ((uint32_t)0x00000004)  /* operate on second frame */\r
+#define ETH_DMAOMR_SR        ((uint32_t)0x00000002)  /* Start/stop receive */\r
+\r
+/* Bit definition for Ethernet DMA Interrupt Enable Register */\r
+#define ETH_DMAIER_NISE      ((uint32_t)0x00010000)  /* Normal interrupt summary enable */\r
+#define ETH_DMAIER_AISE      ((uint32_t)0x00008000)  /* Abnormal interrupt summary enable */\r
+#define ETH_DMAIER_ERIE      ((uint32_t)0x00004000)  /* Early receive interrupt enable */\r
+#define ETH_DMAIER_FBEIE     ((uint32_t)0x00002000)  /* Fatal bus error interrupt enable */\r
+#define ETH_DMAIER_ETIE      ((uint32_t)0x00000400)  /* Early transmit interrupt enable */\r
+#define ETH_DMAIER_RWTIE     ((uint32_t)0x00000200)  /* Receive watchdog timeout interrupt enable */\r
+#define ETH_DMAIER_RPSIE     ((uint32_t)0x00000100)  /* Receive process stopped interrupt enable */\r
+#define ETH_DMAIER_RBUIE     ((uint32_t)0x00000080)  /* Receive buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_RIE       ((uint32_t)0x00000040)  /* Receive interrupt enable */\r
+#define ETH_DMAIER_TUIE      ((uint32_t)0x00000020)  /* Transmit Underflow interrupt enable */\r
+#define ETH_DMAIER_ROIE      ((uint32_t)0x00000010)  /* Receive Overflow interrupt enable */\r
+#define ETH_DMAIER_TJTIE     ((uint32_t)0x00000008)  /* Transmit jabber timeout interrupt enable */\r
+#define ETH_DMAIER_TBUIE     ((uint32_t)0x00000004)  /* Transmit buffer unavailable interrupt enable */\r
+#define ETH_DMAIER_TPSIE     ((uint32_t)0x00000002)  /* Transmit process stopped interrupt enable */\r
+#define ETH_DMAIER_TIE       ((uint32_t)0x00000001)  /* Transmit interrupt enable */\r
+\r
+/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */\r
+#define ETH_DMAMFBOCR_OFOC   ((uint32_t)0x10000000)  /* Overflow bit for FIFO overflow counter */\r
+#define ETH_DMAMFBOCR_MFA    ((uint32_t)0x0FFE0000)  /* Number of frames missed by the application */\r
+#define ETH_DMAMFBOCR_OMFC   ((uint32_t)0x00010000)  /* Overflow bit for missed frame counter */\r
+#define ETH_DMAMFBOCR_MFC    ((uint32_t)0x0000FFFF)  /* Number of frames missed by the controller */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */\r
+#define ETH_DMACHTDR_HTDAP   ((uint32_t)0xFFFFFFFF)  /* Host transmit descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */\r
+#define ETH_DMACHRDR_HRDAP   ((uint32_t)0xFFFFFFFF)  /* Host receive descriptor address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */\r
+#define ETH_DMACHTBAR_HTBAP  ((uint32_t)0xFFFFFFFF)  /* Host transmit buffer address pointer */\r
+\r
+/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */\r
+#define ETH_DMACHRBAR_HRBAP  ((uint32_t)0xFFFFFFFF)  /* Host receive buffer address pointer */\r
+\r
+/**\r
+  *\r
+  */\r
+\r
+ /**\r
+  * @}\r
+  */ \r
+\r
+#ifdef USE_STDPERIPH_DRIVER\r
+  #include "stm32f4xx_conf.h"\r
+#endif /* USE_STDPERIPH_DRIVER */\r
+\r
+/** @addtogroup Exported_macro\r
+  * @{\r
+  */\r
+\r
+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))\r
+\r
+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))\r
+\r
+#define READ_BIT(REG, BIT)    ((REG) & (BIT))\r
+\r
+#define CLEAR_REG(REG)        ((REG) = (0x0))\r
+\r
+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))\r
+\r
+#define READ_REG(REG)         ((REG))\r
+\r
+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif /* __cplusplus */\r
+\r
+#endif /* __STM32F4xx_H */\r
+\r
+/**\r
+  * @}\r
+  */\r
+\r
+  /**\r
+  * @}\r
+  */\r
+\r
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/\r

diff --git a/src/device/system_stm32f4xx.h b/src/device/system_stm32f4xx.h
new file mode 100644 (file)
index 0000000..5e30ef8
--- /dev/null
+++ b/src/device/system_stm32f4xx.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V1.6.1
+  * @date    21-October-2015
+  * @brief   CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.       
+  ******************************************************************************  
+  * @attention
+  *
+  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
+  *
+  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * You may not use this file except in compliance with the License.
+  * You may obtain a copy of the License at:
+  *
+  *        http://www.st.com/software_license_agreement_liberty_v2
+  *
+  * Unless required by applicable law or agreed to in writing, software 
+  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * See the License for the specific language governing permissions and
+  * limitations under the License.
+  *
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/src/main.c b/src/main.c
index 21f4376050f9ddf5a459035e86d4b9302255cf49..3956315a46a60a8b2680ae141639fc511ec603f4 100644 (file)
--- a/src/main.c
+++ b/src/main.c
@@ -1,7 +1,34 @@
-/* Main program. */
+#include "main.h"
+
+/**
+ * Main program.
+ */
 int main(void) {
-  int val = 0;
-  while (1) {
-    val += 1;
+  // Enable the GPIOa and GPIOC peripheral in RCC.
+  RCC->AHB1ENR   |= RCC_AHB1ENR_GPIOAEN ;
+  RCC->AHB1ENR   |= RCC_AHB1ENR_GPIOCEN ;
+
+  // Initialize the GPIOC pins.
+  // C15 should be set to 'input' mode with pull-up.
+  GPIOC->MODER  &= ~(0x3 << (BUTTON_PIN*2));
+  GPIOC->PUPDR  &= ~(0x3 << (BUTTON_PIN*2));
+  GPIOC->PUPDR  |=  (0x1 << (BUTTON_PIN*2));
+
+  // A5 is connected to an LED on the 'Nucleo' board.
+  // It should be set to push-pull low-speed output.
+  GPIOA->MODER  &= ~(0x3 << (LED_PIN*2));
+  GPIOA->MODER  |=  (0x1 << (LED_PIN*2));
+  GPIOA->OTYPER &= ~(1 << LED_PIN);
+
+  // Main loop
+  while (1){
+    // Invert the IDR register since '0' means 'pressed'.
+    uint32_t idr_val = ~GPIOC->IDR;
+    if (idr_val & (1 << BUTTON_PIN)) {
+      GPIOA->ODR = (1 << LED_PIN);
+    }
+    else {
+      GPIOA->ODR = (0 << LED_PIN);
+    }
   }
-}
+}
\ No newline at end of file

diff --git a/src/main.h b/src/main.h
new file mode 100644 (file)
index 0000000..d6332af
--- /dev/null
+++ b/src/main.h
@@ -0,0 +1,8 @@
+#ifndef _VVC_MAIN_H
+#define _VVC_MAIN_H
+#include <stdint.h>
+#include "device/stm32f4xx.h"
+// Define GPIOB pin mappings for our LED and button.
+#define BUTTON_PIN (13) //C13
+#define LED_PIN    (5) //A5
+#endif
\ No newline at end of file