--- /dev/null
+#include "clock.h"
+
+/* This should set the speed to 216MHz intead of just 48MHz */
+void init_clock(){
+ // ACR means flash Access control register
+ FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | // 7 wait states
+ FLASH_ACR_PRFTEN | // prefetch on
+ FLASH_ACR_ARTEN); // ART on
+
+ // enables HSE and wait for it to be ready
+ RCC->CR |= (RCC_CR_HSEON);
+ while (!(RCC->CR & RCC_CR_HSERDY)) {};
+
+ // clear the specified bit
+
+ // (8/4)*108 = 216MHz
+ /*
+ RCC->PLLCFGR |= (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz
+ RCC_PLLCFGR_PLLN_108 | // *108
+ RCC_PLLCFGR_PLLM_25); // /4
+ */
+ RCC->PLLCFGR = 0b00001000010000100110000000001000; // HSE: 8MHz*/
+
+ // enable the RCC clock and wait for it to be ready
+ RCC->CR |= (RCC_CR_PLLON);
+ while (!(RCC->CR & RCC_CR_PLLRDY)) {};
+
+ // set it as the system clock source
+ RCC->CFGR &= ~(RCC_CFGR_SW);
+ RCC->CFGR |= (RCC_CFGR_SW_PLL);
+ while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {};
+}
\ No newline at end of file
--- /dev/null
+/** @file clock.h
+ *
+ * @brief Handle clock init and all
+ *
+ */
+
+#ifndef CLOCK_H
+#define CLOCK_H
+
+#include "stdint.h"
+#include "../device/stm32f730xx.h"
+
+#define PLL_N 384
+#define PLL_M 8
+#define PLL_P 2
+#define PLL_Q 8
+
+/*
+RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/
+ //0b0000/*<-null*/1000/*<-PLLQ*/0/*<-null*/1/*<-PLLPSRC(HSE)*/0000/*<-null*/10/*<-PLLP*/0/*<-null*/110000000/*<-PLLN*/001000/*<-PLLM*/
+
+
+void init_clock();
+
+#endif
\ No newline at end of file
#define RCC_PLLCFGR_PLLN_6 (0x040UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00001000 */\r
#define RCC_PLLCFGR_PLLN_7 (0x080UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00002000 */\r
#define RCC_PLLCFGR_PLLN_8 (0x100UL << RCC_PLLCFGR_PLLN_Pos) /*!< 0x00004000 */\r
+#define RCC_PLLCFGR_PLLN_384 (0x180UL << RCC_PLLCFGR_PLLN_Pos) /*!< ? */\r
#define RCC_PLLCFGR_PLLP_Pos (16U)\r
#define RCC_PLLCFGR_PLLP_Msk (0x3UL << RCC_PLLCFGR_PLLP_Pos) /*!< 0x00030000 */\r
#define RCC_PLLCFGR_PLLP RCC_PLLCFGR_PLLP_Msk\r