From 7a2ef6a22c6f18a1cd4878d61e352ce2d421265d Mon Sep 17 00:00:00 2001 From: ayabusa Date: Fri, 19 Apr 2024 18:26:14 +0200 Subject: [PATCH] made this shitty clock work --- numworks_port/README.md | 8 +++----- numworks_port/build/Laplace/clock.o | Bin 3960 -> 4496 bytes numworks_port/build/Laplace/time.o | Bin 2912 -> 2912 bytes numworks_port/build/main.bin | Bin 67817 -> 68021 bytes numworks_port/build/main.elf | Bin 281112 -> 281340 bytes numworks_port/build/main.o | Bin 2468 -> 2468 bytes numworks_port/src/Laplace/clock.c | 28 ++++++++++++++++++++++++++-- numworks_port/src/Laplace/clock.h | 6 +----- numworks_port/src/Laplace/time.h | 2 +- numworks_port/src/main.c | 4 ++-- 10 files changed, 33 insertions(+), 15 deletions(-) diff --git a/numworks_port/README.md b/numworks_port/README.md index 6957788..7886509 100644 --- a/numworks_port/README.md +++ b/numworks_port/README.md @@ -13,13 +13,11 @@ This is a bare metal os attempt on the numworks n0110 - [x] Working thing - [x] Led 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zCq3hT1O5R0^0H?9-@xx$FR|KxBCaB*A6X>5s;;g>FqNb~LRWHpjR$r~V jaSj}~n#7>q*b6GxruQ?I$?C&6Cl_~-h;aY;Pa*t2uv?#D diff --git a/numworks_port/build/main.o b/numworks_port/build/main.o index a89f7cbc9b9894c74907c3a5e3a271d9da42fe86..b825c0197079124d243ec7b5ed4fa0cecc045dab 100644 GIT binary patch delta 41 xcmZ1?yhM1z8Wu)_$!l4xc#?8TQyFrLOE!OIDP>`_n7oi#cybM=1^_U~4h#SQ delta 41 xcmZ1?yhM1z8Wu+V$!l4xc#2X}7;=l_%M&w87&d=qDP>_apS+M+cybM=1^_8*4V?f0 diff --git a/numworks_port/src/Laplace/clock.c b/numworks_port/src/Laplace/clock.c index e70558e..733768b 100644 --- a/numworks_port/src/Laplace/clock.c +++ b/numworks_port/src/Laplace/clock.c @@ -54,8 +54,32 @@ void init_clock(){ * wait a little bit. * The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */ // clear in first place - FLASH->ACR &= ~(0b0000 0000 0000 0000 - 0000 0011 0000 1111); + FLASH->ACR &= ~(FLASH_ACR_LATENCY_Msk | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN); + FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN); + + // 192MHz is too fast for both APB1 and APB2 so we divide them + // firstly we clear + RCC->CFGR &= ~(0b00000000000000001111110000000000); + /* Then we set + * PPRE1 = 4 = 100 + * PPRE2 = 2 = 10 */ + RCC->CFGR |= 0b00000000000000001001010000000000; + + // We now wait for PLLRDY + while (!(RCC->CR & RCC_CR_PLLRDY)) {}; + + // We select PLL output as a SYSCLK source + RCC->CFGR |= RCC_CFGR_SW_PLL; + // And wait for it !!! + while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}; + + // We can now disable HSI + RCC->CR &= ~(RCC_CR_HSION); + + // Set normal speed + RCC->CFGR &= ~(RCC_CFGR_HPRE_Msk); + + set_led_green(true); } /* OLD diff --git a/numworks_port/src/Laplace/clock.h b/numworks_port/src/Laplace/clock.h index 9120586..da7fd2f 100644 --- a/numworks_port/src/Laplace/clock.h +++ b/numworks_port/src/Laplace/clock.h @@ -9,11 +9,7 @@ #include "stdint.h" #include "../device/stm32f730xx.h" - -#define PLL_N 384 -#define PLL_M 8 -#define PLL_P 2 -#define PLL_Q 8 +#include "led.h" /* RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/ diff --git a/numworks_port/src/Laplace/time.h b/numworks_port/src/Laplace/time.h index 99c1af2..472f8f6 100644 --- a/numworks_port/src/Laplace/time.h +++ b/numworks_port/src/Laplace/time.h @@ -8,7 +8,7 @@ #define TIME_H #define loops_per_microsecond 1 -#define loops_per_millisecond 960 +#define loops_per_millisecond 12000 #include "stdint.h" diff --git a/numworks_port/src/main.c b/numworks_port/src/main.c index 079e576..235f83e 100644 --- a/numworks_port/src/main.c +++ b/numworks_port/src/main.c @@ -33,9 +33,9 @@ void main_entry(){ set_led_red(false); }*/ - set_led_red(true); + set_led_blue(true); ms_wait(5000); - set_led_red(false); + set_led_blue(false); ms_wait(5000); }