diff --git a/numworks_port/build/Laplace/clock.o b/numworks_port/build/Laplace/clock.o
index a3dec50..1bfe123 100644
Binary files a/numworks_port/build/Laplace/clock.o and b/numworks_port/build/Laplace/clock.o differ
diff --git a/numworks_port/build/main.bin b/numworks_port/build/main.bin
index d02b220..662e0c5 100755
Binary files a/numworks_port/build/main.bin and b/numworks_port/build/main.bin differ
diff --git a/numworks_port/build/main.elf b/numworks_port/build/main.elf
index 0eff4a1..2d165be 100755
Binary files a/numworks_port/build/main.elf and b/numworks_port/build/main.elf differ
diff --git a/numworks_port/src/Laplace/clock.c b/numworks_port/src/Laplace/clock.c
index 4d5e0e7..0ad6416 100644
--- a/numworks_port/src/Laplace/clock.c
+++ b/numworks_port/src/Laplace/clock.c
@@ -2,11 +2,38 @@
 
 /* This should set the speed to 216MHz intead of just 48MHz */
 void init_clock(){
-    // ACR means flash Access control register
+    // Enable the HSI and wait for it to be ready to use
+    RCC->CR    |=  (RCC_CR_HSION);
+    while (!(RCC->CR & RCC_CR_HSIRDY)) {};
+
+    // Enable the HSE and wait for it to be ready to use
+    RCC->CR    |=  (RCC_CR_HSEON);
+    while (!(RCC->CR & RCC_CR_HSERDY)) {};
+
+    // enable power interface clock
+    RCC->APB1ENR |= (RCC_APB1ENR_PWREN);
+
+    // SSGR stuf, paragraph taken from upsilon
+    /* To pass electromagnetic compatibility tests, we activate the Spread
+    * Spectrum clock generation, which adds jitter to the PLL clock in order to
+    * "lower peak-energy on the central frequency" and its harmonics.
+    * It must be done before enabling the PLL. */
+   /* Modper = 250
+    * Incstep = 25
+    * SpreadSel = 0
+    * SSCGEN = 1 */
+    RCC->SSCGR = 0b10000000000000110010000011111010;
+
+}
+
+/* OLD
+// ACR means flash Access control register
     FLASH->ACR |=  (FLASH_ACR_LATENCY_7WS | // 7 wait states
                   FLASH_ACR_PRFTEN |        // prefetch on
                   FLASH_ACR_ARTEN);         // ART on
-
+    
+    FLASH->ACR &= ~(0b00000000000000000000101100001111);
+    
     // enables HSE and wait for it to be ready
     RCC->CR    |=  (RCC_CR_HSEON);
     while (!(RCC->CR & RCC_CR_HSERDY)) {};
@@ -14,12 +41,10 @@ void init_clock(){
     // clear the specified bit
 
     // (8/4)*108 = 216MHz
-    /*
     RCC->PLLCFGR  |=  (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz
                   RCC_PLLCFGR_PLLN_108 |        // *108
                   RCC_PLLCFGR_PLLM_25);          // /4
-    */
-    RCC->PLLCFGR  =  0b00001000010000100110000000001000; // HSE: 8MHz*/
+    RCC->PLLCFGR  =  0b00001000010000100110000000001000; // HSE: 8MHz
 
     // enable the RCC clock and wait for it to be ready
     RCC->CR    |=  (RCC_CR_PLLON);
@@ -29,4 +54,4 @@ void init_clock(){
     RCC->CFGR  &= ~(RCC_CFGR_SW);
     RCC->CFGR  |=  (RCC_CFGR_SW_PLL);
     while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {};
-}
\ No newline at end of file
+*/
\ No newline at end of file