From a1182a3193a105381a985a320eb8706a87c9ed7e Mon Sep 17 00:00:00 2001
From: ayabusa <lebgpub@gmail.com>
Date: Thu, 18 Apr 2024 20:31:28 +0200
Subject: [PATCH] Started rewrite of the clock (broken)

---
 numworks_port/build/Laplace/clock.o | Bin 3960 -> 3960 bytes
 numworks_port/build/main.bin        | Bin 67817 -> 67817 bytes
 numworks_port/build/main.elf        | Bin 281112 -> 281112 bytes
 numworks_port/src/Laplace/clock.c   |  37 +++++++++++++++++++++++-----
 4 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/numworks_port/build/Laplace/clock.o b/numworks_port/build/Laplace/clock.o
index a3dec5089e10b0cb1e0eec1464b5f29c4c0a9e06..1bfe1237312dc2ffa1c78e64b8406da1ea3b861e 100644
GIT binary patch
delta 121
zcmew%_d{-ig}SV_RECVFthcZOcY=(!bcVE-^Opu=;RJ^Ll0Y8w7Y1Vn?VlIKCMF8Y
z3W5YaFcgCX_`GLl@OmkKU}m12zzt+`O`NF2Zo}m8;miO38+TN)FqvjfHfD`x<lEfO
UD$2}QIe96^e8!s1uAIhf05~isX#fBK

delta 136
zcmew%_d{-iMWmd!REDgl!zXrQVQ20H8E@$fX)ot54aUL=4ErU3JmxP9#thm&FNk`J
zc||3N07ZnooIf-agX9H3@*fzALGrxbvom<Sls_;tPfp+hvN<RAE3xipuwio8xTBJV
g$)IwwF>5p<@8*71QD(-f$xAurGd65?<uqmk0FMSLUjP6A

diff --git a/numworks_port/build/main.bin b/numworks_port/build/main.bin
index d02b2206ec633b92b2412fab7fa72e431f3779f7..662e0c572141e2360e151b2af06a27e66e8b6d17 100755
GIT binary patch
delta 102
zcmaDkk>%w?mWC;eGt_0hr7~nZWxa(RxD#Z&r8A_xoWC>}3nwt_mjv>dzc3gxX#cz*
zHuWH*u&f|R<O4%7NQBROb_TDP@&{(-$qC#*HrLdTj7sb_Ob#Eu{QtjQf|2neI{=@N
BB4+>q

delta 116
zcmaDkk>%w?mWC;eGa}`@r7~na9X_!e3p;Zs$aqU<NP9VdX)qQ}VAwAK<S~C?FlNyH
zc|p`$%quEE1Slfx<@}+c7$h$MlK;R^43g*do}IztrTl@Jd2#|5kj**uJ);uqeg+#R
LhwT!Kj2GDfrn)5Q

diff --git a/numworks_port/build/main.elf b/numworks_port/build/main.elf
index 0eff4a1e40d7e3aae3a90ca6a645a3c31bb3c724..2d165beeac7fad56fef62a311c184649284a2d75 100755
GIT binary patch
delta 157
zcmbO+MR3Lx!G;#b7N#l8Gt_0hr7~nZWxa(RxD#Z&r8A_xoWC>}3nwt_mjv>dzc3gx
zX#cz*HuWI0u&f|R<O4%7NQBROb_TDP@&{(-$qC#*HrLdT%u4JwOb#Eu{QuuB!N|N_
zf{{g5iODo`y16n-G&dguBjW-_1_ow^-sz62EQ#CyDYLv2WUSo&)|ADal~G{3sWr=E
FJ^<ZAFH8Uc

delta 171
zcmbO+MR3Lx!G;#b7N#l8Ga}`@r7~na9X_!e3p;Zs$aqU<NP9VdX)qQ}VAwAK<S~C?
zFlNyHc|p`$%quEE1Slfx<@}+c7$h$MlK;R^43g*do}IztrTl@Jd2#|5kj**uJ+l()
zeg+#Rhjs}@=Is)UEV4>W29?vzm06;>c^McP7cep~Ff;T{cT{Cb-2P9Q<((j7)%Lfh
QEbgp~BHK-^SswEN0BsyG+W-In

diff --git a/numworks_port/src/Laplace/clock.c b/numworks_port/src/Laplace/clock.c
index 4d5e0e7..0ad6416 100644
--- a/numworks_port/src/Laplace/clock.c
+++ b/numworks_port/src/Laplace/clock.c
@@ -2,11 +2,38 @@
 
 /* This should set the speed to 216MHz intead of just 48MHz */
 void init_clock(){
-    // ACR means flash Access control register
+    // Enable the HSI and wait for it to be ready to use
+    RCC->CR    |=  (RCC_CR_HSION);
+    while (!(RCC->CR & RCC_CR_HSIRDY)) {};
+
+    // Enable the HSE and wait for it to be ready to use
+    RCC->CR    |=  (RCC_CR_HSEON);
+    while (!(RCC->CR & RCC_CR_HSERDY)) {};
+
+    // enable power interface clock
+    RCC->APB1ENR |= (RCC_APB1ENR_PWREN);
+
+    // SSGR stuf, paragraph taken from upsilon
+    /* To pass electromagnetic compatibility tests, we activate the Spread
+    * Spectrum clock generation, which adds jitter to the PLL clock in order to
+    * "lower peak-energy on the central frequency" and its harmonics.
+    * It must be done before enabling the PLL. */
+   /* Modper = 250
+    * Incstep = 25
+    * SpreadSel = 0
+    * SSCGEN = 1 */
+    RCC->SSCGR = 0b10000000000000110010000011111010;
+
+}
+
+/* OLD
+// ACR means flash Access control register
     FLASH->ACR |=  (FLASH_ACR_LATENCY_7WS | // 7 wait states
                   FLASH_ACR_PRFTEN |        // prefetch on
                   FLASH_ACR_ARTEN);         // ART on
-
+    
+    FLASH->ACR &= ~(0b00000000000000000000101100001111);
+    
     // enables HSE and wait for it to be ready
     RCC->CR    |=  (RCC_CR_HSEON);
     while (!(RCC->CR & RCC_CR_HSERDY)) {};
@@ -14,12 +41,10 @@ void init_clock(){
     // clear the specified bit
 
     // (8/4)*108 = 216MHz
-    /*
     RCC->PLLCFGR  |=  (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz
                   RCC_PLLCFGR_PLLN_108 |        // *108
                   RCC_PLLCFGR_PLLM_25);          // /4
-    */
-    RCC->PLLCFGR  =  0b00001000010000100110000000001000; // HSE: 8MHz*/
+    RCC->PLLCFGR  =  0b00001000010000100110000000001000; // HSE: 8MHz
 
     // enable the RCC clock and wait for it to be ready
     RCC->CR    |=  (RCC_CR_PLLON);
@@ -29,4 +54,4 @@ void init_clock(){
     RCC->CFGR  &= ~(RCC_CFGR_SW);
     RCC->CFGR  |=  (RCC_CFGR_SW_PLL);
     while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {};
-}
\ No newline at end of file
+*/
\ No newline at end of file