mirror of
https://github.com/ayabusa/Numworks-zeta-os.git
synced 2024-11-23 19:33:25 +00:00
adding numworks port (valid but not working)
This commit is contained in:
parent
7f4b1fd08c
commit
70d807180e
16
.vscode/c_cpp_properties.json
vendored
Normal file
16
.vscode/c_cpp_properties.json
vendored
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@ -0,0 +1,16 @@
|
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{
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||||
"configurations": [
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{
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"name": "Linux",
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"includePath": [
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"${workspaceFolder}/**"
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],
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"defines": [],
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"compilerPath": "/usr/bin/gcc",
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"cStandard": "c17",
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"cppStandard": "gnu++17",
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"intelliSenseMode": "linux-gcc-x64"
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}
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],
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"version": 4
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}
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21
.vscode/settings.json
vendored
Normal file
21
.vscode/settings.json
vendored
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@ -0,0 +1,21 @@
|
||||
{
|
||||
"files.associations": {
|
||||
"cstdint": "cpp",
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||||
"cstring": "cpp",
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||||
"atomic": "cpp",
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"string": "cpp",
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||||
"unordered_map": "cpp",
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||||
"vector": "cpp",
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||||
"iterator": "cpp",
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||||
"memory_resource": "cpp",
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||||
"string_view": "cpp",
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||||
"functional": "cpp",
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"istream": "cpp",
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"new": "cpp",
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"ostream": "cpp",
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"stdexcept": "cpp",
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"streambuf": "cpp",
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"system_error": "cpp",
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"tuple": "cpp"
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}
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}
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28
chatgpt-try/firmware.ld
Normal file
28
chatgpt-try/firmware.ld
Normal file
@ -0,0 +1,28 @@
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ENTRY(Reset_Handler)
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MEMORY
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{
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FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
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RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
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}
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SECTIONS
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{
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.text :
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{
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*(.text)
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*(.text.*)
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} > FLASH
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.data :
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{
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*(.data)
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*(.data.*)
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} > RAM AT > FLASH
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.bss :
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{
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*(.bss)
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*(.bss.*)
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} > RAM
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}
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5
chatgpt-try/main.c
Normal file
5
chatgpt-try/main.c
Normal file
@ -0,0 +1,5 @@
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// Minimal main.c file
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int main() {
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// Your code here
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return 0;
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}
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538
chatgpt-try/startup_stm32f730xx.s
Normal file
538
chatgpt-try/startup_stm32f730xx.s
Normal file
@ -0,0 +1,538 @@
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/**
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******************************************************************************
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* @file startup_stm32f730xx.s
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* @author MCD Application Team
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* @brief STM32F730xx Devices vector table for GCC based toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually
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* calls main()).
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* After Reset the Cortex-M7 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m7
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
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/**
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* @brief This is the code that gets called when the processor first
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* starts execution following a reset event. Only the absolutely
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* necessary set is performed, after which the application
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* supplied main() routine is called.
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* @param None
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* @retval : None
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*/
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr sp, =_estack /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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bx lr
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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* @param None
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* @retval None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M7. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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*******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler
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.word NMI_Handler
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.word HardFault_Handler
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.word MemManage_Handler
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.word BusFault_Handler
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.word UsageFault_Handler
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.word 0
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.word 0
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.word 0
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.word 0
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.word SVC_Handler
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.word DebugMon_Handler
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.word 0
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.word PendSV_Handler
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.word SysTick_Handler
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/* External Interrupts */
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.word WWDG_IRQHandler /* Window WatchDog */
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.word PVD_IRQHandler /* PVD through EXTI Line detection */
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.word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */
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.word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */
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.word FLASH_IRQHandler /* FLASH */
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.word RCC_IRQHandler /* RCC */
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.word EXTI0_IRQHandler /* EXTI Line0 */
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.word EXTI1_IRQHandler /* EXTI Line1 */
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.word EXTI2_IRQHandler /* EXTI Line2 */
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.word EXTI3_IRQHandler /* EXTI Line3 */
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.word EXTI4_IRQHandler /* EXTI Line4 */
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.word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */
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.word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */
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.word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */
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.word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */
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.word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */
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.word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */
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.word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */
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.word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */
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.word CAN1_TX_IRQHandler /* CAN1 TX */
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.word CAN1_RX0_IRQHandler /* CAN1 RX0 */
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.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
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.word CAN1_SCE_IRQHandler /* CAN1 SCE */
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.word EXTI9_5_IRQHandler /* External Line[9:5]s */
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.word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */
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.word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */
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.word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */
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.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
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.word TIM2_IRQHandler /* TIM2 */
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.word TIM3_IRQHandler /* TIM3 */
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.word TIM4_IRQHandler /* TIM4 */
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.word I2C1_EV_IRQHandler /* I2C1 Event */
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.word I2C1_ER_IRQHandler /* I2C1 Error */
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.word I2C2_EV_IRQHandler /* I2C2 Event */
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.word I2C2_ER_IRQHandler /* I2C2 Error */
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.word SPI1_IRQHandler /* SPI1 */
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.word SPI2_IRQHandler /* SPI2 */
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.word USART1_IRQHandler /* USART1 */
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.word USART2_IRQHandler /* USART2 */
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.word USART3_IRQHandler /* USART3 */
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.word EXTI15_10_IRQHandler /* External Line[15:10]s */
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.word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */
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.word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */
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.word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */
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.word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */
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.word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */
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.word TIM8_CC_IRQHandler /* TIM8 Capture Compare */
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.word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */
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.word FMC_IRQHandler /* FMC */
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.word SDMMC1_IRQHandler /* SDMMC1 */
|
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.word TIM5_IRQHandler /* TIM5 */
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.word SPI3_IRQHandler /* SPI3 */
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.word UART4_IRQHandler /* UART4 */
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||||
.word UART5_IRQHandler /* UART5 */
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||||
.word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */
|
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.word TIM7_IRQHandler /* TIM7 */
|
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.word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */
|
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.word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */
|
||||
.word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */
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.word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */
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.word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */
|
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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||||
.word 0 /* Reserved */
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||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word OTG_FS_IRQHandler /* USB OTG FS */
|
||||
.word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */
|
||||
.word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */
|
||||
.word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word I2C3_EV_IRQHandler /* I2C3 event */
|
||||
.word I2C3_ER_IRQHandler /* I2C3 error */
|
||||
.word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */
|
||||
.word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */
|
||||
.word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */
|
||||
.word OTG_HS_IRQHandler /* USB OTG HS */
|
||||
.word 0 /* Reserved */
|
||||
.word AES_IRQHandler /* AES */
|
||||
.word RNG_IRQHandler /* RNG */
|
||||
.word FPU_IRQHandler /* FPU */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word SPI5_IRQHandler /* SPI5 */
|
||||
.word 0 /* Reserved */
|
||||
.word SAI1_IRQHandler /* SAI1 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SAI2_IRQHandler /* SAI2 */
|
||||
.word QUADSPI_IRQHandler /* QUADSPI */
|
||||
.word LPTIM1_IRQHandler /* LPTIM1 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word SDMMC2_IRQHandler /* SDMMC2 */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDG_IRQHandler
|
||||
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVD_IRQHandler
|
||||
.thumb_set PVD_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMP_STAMP_IRQHandler
|
||||
.thumb_set TAMP_STAMP_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_WKUP_IRQHandler
|
||||
.thumb_set RTC_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak RCC_IRQHandler
|
||||
.thumb_set RCC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI0_IRQHandler
|
||||
.thumb_set EXTI0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI1_IRQHandler
|
||||
.thumb_set EXTI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI2_IRQHandler
|
||||
.thumb_set EXTI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI3_IRQHandler
|
||||
.thumb_set EXTI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI4_IRQHandler
|
||||
.thumb_set EXTI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream0_IRQHandler
|
||||
.thumb_set DMA1_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream1_IRQHandler
|
||||
.thumb_set DMA1_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream2_IRQHandler
|
||||
.thumb_set DMA1_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream3_IRQHandler
|
||||
.thumb_set DMA1_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream4_IRQHandler
|
||||
.thumb_set DMA1_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream5_IRQHandler
|
||||
.thumb_set DMA1_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream6_IRQHandler
|
||||
.thumb_set DMA1_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC_IRQHandler
|
||||
.thumb_set ADC_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_TX_IRQHandler
|
||||
.thumb_set CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX0_IRQHandler
|
||||
.thumb_set CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SCE_IRQHandler
|
||||
.thumb_set CAN1_SCE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.thumb_set EXTI9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_BRK_TIM9_IRQHandler
|
||||
.thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_UP_TIM10_IRQHandler
|
||||
.thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_TRG_COM_TIM11_IRQHandler
|
||||
.thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM2_IRQHandler
|
||||
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM3_IRQHandler
|
||||
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM4_IRQHandler
|
||||
.thumb_set TIM4_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.thumb_set I2C1_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.thumb_set I2C1_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.thumb_set I2C2_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.thumb_set I2C2_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_IRQHandler
|
||||
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.thumb_set EXTI15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_Alarm_IRQHandler
|
||||
.thumb_set RTC_Alarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_WKUP_IRQHandler
|
||||
.thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_BRK_TIM12_IRQHandler
|
||||
.thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_UP_TIM13_IRQHandler
|
||||
.thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_TRG_COM_TIM14_IRQHandler
|
||||
.thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM8_CC_IRQHandler
|
||||
.thumb_set TIM8_CC_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Stream7_IRQHandler
|
||||
.thumb_set DMA1_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak FMC_IRQHandler
|
||||
.thumb_set FMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC1_IRQHandler
|
||||
.thumb_set SDMMC1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM5_IRQHandler
|
||||
.thumb_set TIM5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_IRQHandler
|
||||
.thumb_set SPI3_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM6_DAC_IRQHandler
|
||||
.thumb_set TIM6_DAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak TIM7_IRQHandler
|
||||
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream0_IRQHandler
|
||||
.thumb_set DMA2_Stream0_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream1_IRQHandler
|
||||
.thumb_set DMA2_Stream1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream2_IRQHandler
|
||||
.thumb_set DMA2_Stream2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream3_IRQHandler
|
||||
.thumb_set DMA2_Stream3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream4_IRQHandler
|
||||
.thumb_set DMA2_Stream4_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_FS_IRQHandler
|
||||
.thumb_set OTG_FS_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream5_IRQHandler
|
||||
.thumb_set DMA2_Stream5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream6_IRQHandler
|
||||
.thumb_set DMA2_Stream6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Stream7_IRQHandler
|
||||
.thumb_set DMA2_Stream7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EV_IRQHandler
|
||||
.thumb_set I2C3_EV_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ER_IRQHandler
|
||||
.thumb_set I2C3_ER_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_OUT_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_EP1_IN_IRQHandler
|
||||
.thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_WKUP_IRQHandler
|
||||
.thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
|
||||
|
||||
.weak OTG_HS_IRQHandler
|
||||
.thumb_set OTG_HS_IRQHandler,Default_Handler
|
||||
|
||||
.weak AES_IRQHandler
|
||||
.thumb_set AES_IRQHandler,Default_Handler
|
||||
|
||||
.weak RNG_IRQHandler
|
||||
.thumb_set RNG_IRQHandler,Default_Handler
|
||||
|
||||
.weak FPU_IRQHandler
|
||||
.thumb_set FPU_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI5_IRQHandler
|
||||
.thumb_set SPI5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI1_IRQHandler
|
||||
.thumb_set SAI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SAI2_IRQHandler
|
||||
.thumb_set SAI2_IRQHandler,Default_Handler
|
||||
|
||||
.weak QUADSPI_IRQHandler
|
||||
.thumb_set QUADSPI_IRQHandler,Default_Handler
|
||||
|
||||
.weak LPTIM1_IRQHandler
|
||||
.thumb_set LPTIM1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDMMC2_IRQHandler
|
||||
.thumb_set SDMMC2_IRQHandler,Default_Handler
|
||||
|
||||
|
||||
90
numworks_port/Makefile
Normal file
90
numworks_port/Makefile
Normal file
@ -0,0 +1,90 @@
|
||||
TARGET = main
|
||||
|
||||
# Directories
|
||||
SRC_DIR = src
|
||||
BUILD_DIR = build
|
||||
|
||||
# Define the linker script location and chip architecture.
|
||||
LD_SCRIPT = $(SRC_DIR)/linker.ld
|
||||
MCU_SPEC = cortex-m7
|
||||
|
||||
# Toolchain definitions (ARM bare metal defaults)
|
||||
TOOLCHAIN = /usr
|
||||
CP = $(TOOLCHAIN)/bin/arm-none-eabi-g++
|
||||
CC = $(TOOLCHAIN)/bin/arm-none-eabi-gcc
|
||||
AS = $(TOOLCHAIN)/bin/arm-none-eabi-as
|
||||
LD = $(TOOLCHAIN)/bin/arm-none-eabi-ld
|
||||
OC = $(TOOLCHAIN)/bin/arm-none-eabi-objcopy
|
||||
OD = $(TOOLCHAIN)/bin/arm-none-eabi-objdump
|
||||
OS = $(TOOLCHAIN)/bin/arm-none-eabi-size
|
||||
|
||||
# Assembly directives.
|
||||
ASFLAGS += -c
|
||||
ASFLAGS += -O0
|
||||
ASFLAGS += -mcpu=$(MCU_SPEC)
|
||||
ASFLAGS += -march=armv7e-m
|
||||
ASFLAGS += -mfpu=fpv5-sp-d16
|
||||
ASFLAGS += -mfloat-abi=softfp
|
||||
ASFLAGS += -mthumb
|
||||
ASFLAGS += -Wall
|
||||
# (Set error messages to appear on a single line.)
|
||||
ASFLAGS += -fmessage-length=0
|
||||
|
||||
# C compilation directives
|
||||
CFLAGS += -mcpu=$(MCU_SPEC)
|
||||
CFLAGS += -march=armv7e-m
|
||||
CFLAGS += -mfpu=fpv5-sp-d16
|
||||
CFLAGS += -mfloat-abi=softfp
|
||||
CFLAGS += -mthumb
|
||||
CFLAGS += -Wall
|
||||
CFLAGS += -g
|
||||
# (Set error messages to appear on a single line.)
|
||||
CFLAGS += -fmessage-length=0
|
||||
# (Set system to ignore semihosted junk)
|
||||
CFLAGS += --specs=nosys.specs
|
||||
|
||||
# Linker directives.
|
||||
LSCRIPT = $(LD_SCRIPT)
|
||||
LFLAGS += -mcpu=$(MCU_SPEC)
|
||||
LFLAGS += -mthumb
|
||||
LFLAGS += -Wall
|
||||
LFLAGS += --specs=nosys.specs
|
||||
LFLAGS += -nostdlib
|
||||
LFLAGS += -lgcc
|
||||
LFLAGS += -T$(LSCRIPT)
|
||||
|
||||
# AS_SRC = $(SRC_DIR)/core.S
|
||||
#C_SRC = $(SRC_DIR)/main.c
|
||||
CPP_SRC := $(wildcard $(SRC_DIR)/*.cpp)
|
||||
|
||||
INCLUDE = -I./
|
||||
INCLUDE += -I./device
|
||||
|
||||
#OBJS = $(BUILD_DIR)/$(notdir $(AS_SRC:.S=.o))
|
||||
#OBJS += $(BUILD_DIR)/$(notdir $(C_SRC:.c=.o))
|
||||
OBJS += $(patsubst $(SRC_DIR)/%.cpp, $(BUILD_DIR)/%.o, $(CPP_SRC))
|
||||
|
||||
.PHONY: all
|
||||
all: $(BUILD_DIR)/$(TARGET).bin
|
||||
|
||||
#$(BUILD_DIR)/%.o: $(SRC_DIR)/%.S
|
||||
# $(CC) -x assembler-with-cpp $(ASFLAGS) $< -o $@
|
||||
|
||||
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.c
|
||||
$(CC) -c $(CFLAGS) $(INCLUDE) $< -o $@
|
||||
|
||||
$(BUILD_DIR)/%.o: $(SRC_DIR)/%.cpp
|
||||
$(CP) -c $(CFLAGS) $(INCLUDE) $< -o $@
|
||||
|
||||
$(BUILD_DIR)/$(TARGET).elf: $(OBJS)
|
||||
$(CC) $^ $(LFLAGS) -o $@
|
||||
|
||||
$(BUILD_DIR)/$(TARGET).bin: $(BUILD_DIR)/$(TARGET).elf
|
||||
$(OC) -S -O binary $< $@
|
||||
$(OS) $<
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
rm -f $(BUILD_DIR)/*.o
|
||||
rm -f $(BUILD_DIR)/$(TARGET).elf
|
||||
rm -f $(BUILD_DIR)/$(TARGET).bin
|
||||
BIN
numworks_port/build/info_headers.o
Normal file
BIN
numworks_port/build/info_headers.o
Normal file
Binary file not shown.
BIN
numworks_port/build/main.bin
Executable file
BIN
numworks_port/build/main.bin
Executable file
Binary file not shown.
BIN
numworks_port/build/main.elf
Executable file
BIN
numworks_port/build/main.elf
Executable file
Binary file not shown.
BIN
numworks_port/build/rt0.o
Normal file
BIN
numworks_port/build/rt0.o
Normal file
Binary file not shown.
BIN
numworks_port/build/vector_table.o
Normal file
BIN
numworks_port/build/vector_table.o
Normal file
Binary file not shown.
79
numworks_port/src/core.S.BAK
Normal file
79
numworks_port/src/core.S.BAK
Normal file
@ -0,0 +1,79 @@
|
||||
/*
|
||||
* Test program to boot an STM32 chip with the absolute
|
||||
* minimum required code for teaching about the chips.
|
||||
*
|
||||
* Copyright William Ransohoff, Vivonomicon, LLC, 2017
|
||||
*
|
||||
* Open source under the MIT License
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m7
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
// Global values.
|
||||
.global vtable
|
||||
.global reset_handler
|
||||
|
||||
/*
|
||||
* The vector table.
|
||||
* Most entries are ommitted for simplicity.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The Reset handler. Called on reset.
|
||||
*/
|
||||
.type reset_handler, %function
|
||||
reset_handler:
|
||||
// Set the stack pointer to the end of the stack.
|
||||
// The '_estack' value is defined in our linker script.
|
||||
LDR r0, =_estack
|
||||
MOV sp, r0
|
||||
|
||||
// Copy data from flash to RAM data init section.
|
||||
// R2 will store our progress along the sidata section.
|
||||
MOVS r0, #0
|
||||
// Load the start/end addresses of the data section,
|
||||
// and the start of the data init section.
|
||||
LDR r1, =_sdata
|
||||
LDR r2, =_edata
|
||||
LDR r3, =_sidata
|
||||
B copy_sidata_loop
|
||||
|
||||
copy_sidata:
|
||||
// Offset the data init section by our copy progress.
|
||||
LDR r4, [r3, r0]
|
||||
// Copy the current word into data, and increment.
|
||||
STR r4, [r1, r0]
|
||||
ADDS r0, r0, #4
|
||||
|
||||
copy_sidata_loop:
|
||||
// Unless we've copied the whole data section, copy the
|
||||
// next word from sidata->data.
|
||||
ADDS r4, r0, r1
|
||||
CMP r4, r2
|
||||
BCC copy_sidata
|
||||
|
||||
// Once we are done copying the data section into RAM,
|
||||
// move on to filling the BSS section with 0s.
|
||||
MOVS r0, #0
|
||||
LDR r1, =_sbss
|
||||
LDR r2, =_ebss
|
||||
B reset_bss_loop
|
||||
|
||||
// Zero out the BSS segment.
|
||||
reset_bss:
|
||||
// Store a 0 and increment by a word.
|
||||
STR r0, [r1]
|
||||
ADDS r1, r1, #4
|
||||
|
||||
reset_bss_loop:
|
||||
// We'll use R1 to count progress here; if we aren't
|
||||
// done, reset the next word and increment.
|
||||
CMP r1, r2
|
||||
BCC reset_bss
|
||||
|
||||
// Branch to the 'main' method.
|
||||
B main
|
||||
.size reset_handler, .-reset_handler
|
||||
1373
numworks_port/src/device/cmsis_gcc.h
Normal file
1373
numworks_port/src/device/cmsis_gcc.h
Normal file
File diff suppressed because it is too large
Load Diff
2512
numworks_port/src/device/core_cm7.h
Normal file
2512
numworks_port/src/device/core_cm7.h
Normal file
File diff suppressed because it is too large
Load Diff
87
numworks_port/src/device/core_cmFunc.h
Normal file
87
numworks_port/src/device/core_cmFunc.h
Normal file
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmFunc.h
|
||||
* @brief CMSIS Cortex-M Core Function Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMFUNC_H
|
||||
#define __CORE_CMFUNC_H
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
87
numworks_port/src/device/core_cmInstr.h
Normal file
87
numworks_port/src/device/core_cmInstr.h
Normal file
@ -0,0 +1,87 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
96
numworks_port/src/device/core_cmSimd.h
Normal file
96
numworks_port/src/device/core_cmSimd.h
Normal file
@ -0,0 +1,96 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cmSimd.h
|
||||
* @brief CMSIS Cortex-M SIMD Header File
|
||||
* @version V4.30
|
||||
* @date 20. October 2015
|
||||
******************************************************************************/
|
||||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CMSIMD_H
|
||||
#define __CORE_CMSIMD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/*------------------ RealView Compiler -----------------*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
/*------------------ ARM Compiler V6 -------------------*/
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#include "cmsis_armcc_V6.h"
|
||||
|
||||
/*------------------ GNU Compiler ----------------------*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
/*------------------ ICC Compiler ----------------------*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
/*------------------ TI CCS Compiler -------------------*/
|
||||
#elif defined ( __TMS470__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
/*------------------ TASKING Compiler ------------------*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
/*------------------ COSMIC Compiler -------------------*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CMSIMD_H */
|
||||
15788
numworks_port/src/device/stm32f730xx.h
Normal file
15788
numworks_port/src/device/stm32f730xx.h
Normal file
File diff suppressed because it is too large
Load Diff
273
numworks_port/src/device/stm32f7xx.h
Normal file
273
numworks_port/src/device/stm32f7xx.h
Normal file
@ -0,0 +1,273 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file stm32f7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
|
||||
*
|
||||
* The file is the unique include file that the application programmer
|
||||
* is using in the C source code, usually in main.c. This file contains:
|
||||
* - Configuration section that allows to select:
|
||||
* - The STM32F7xx device used in the target application
|
||||
* - To use or not the peripheral's drivers in application code(i.e.
|
||||
* code will be based on direct access to peripheral's registers
|
||||
* rather than drivers API), this option is controlled by
|
||||
* "#define USE_HAL_DRIVER"
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f7xx
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifndef __STM32F7xx_H
|
||||
#define __STM32F7xx_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif /* __cplusplus */
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief STM32 Family
|
||||
*/
|
||||
#if !defined (STM32F7)
|
||||
#define STM32F7
|
||||
#endif /* STM32F7 */
|
||||
|
||||
/* Uncomment the line below according to the target STM32 device used in your
|
||||
application
|
||||
*/
|
||||
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F765xx) && \
|
||||
!defined (STM32F767xx) && !defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && \
|
||||
!defined (STM32F722xx) && !defined (STM32F723xx) && !defined (STM32F732xx) && !defined (STM32F733xx) && \
|
||||
!defined (STM32F730xx) && !defined (STM32F750xx)
|
||||
|
||||
/* #define STM32F756xx */ /*!< STM32F756VG, STM32F756ZG, STM32F756ZG, STM32F756IG, STM32F756BG,
|
||||
STM32F756NG Devices */
|
||||
/* #define STM32F746xx */ /*!< STM32F746VE, STM32F746VG, STM32F746ZE, STM32F746ZG, STM32F746IE, STM32F746IG,
|
||||
STM32F746BE, STM32F746BG, STM32F746NE, STM32F746NG Devices */
|
||||
/* #define STM32F745xx */ /*!< STM32F745VE, STM32F745VG, STM32F745ZG, STM32F745ZE, STM32F745IE, STM32F745IG Devices */
|
||||
/* #define STM32F765xx */ /*!< STM32F765BI, STM32F765BG, STM32F765NI, STM32F765NG, STM32F765II, STM32F765IG,
|
||||
STM32F765ZI, STM32F765ZG, STM32F765VI, STM32F765VG Devices */
|
||||
/* #define STM32F767xx */ /*!< STM32F767BG, STM32F767BI, STM32F767IG, STM32F767II, STM32F767NG, STM32F767NI,
|
||||
STM32F767VG, STM32F767VI, STM32F767ZG, STM32F767ZI Devices */
|
||||
/* #define STM32F769xx */ /*!< STM32F769AG, STM32F769AI, STM32F769BG, STM32F769BI, STM32F769IG, STM32F769II,
|
||||
STM32F769NG, STM32F769NI, STM32F768AI Devices */
|
||||
/* #define STM32F777xx */ /*!< STM32F777VI, STM32F777ZI, STM32F777II, STM32F777BI, STM32F777NI Devices */
|
||||
/* #define STM32F779xx */ /*!< STM32F779II, STM32F779BI, STM32F779NI, STM32F779AI, STM32F778AI Devices */
|
||||
/* #define STM32F722xx */ /*!< STM32F722IE, STM32F722ZE, STM32F722VE, STM32F722RE, STM32F722IC, STM32F722ZC,
|
||||
STM32F722VC, STM32F722RC Devices */
|
||||
/* #define STM32F723xx */ /*!< STM32F723IE, STM32F723ZE, STM32F723VE, STM32F723IC, STM32F723ZC, STM32F723VC Devices */
|
||||
/* #define STM32F732xx */ /*!< STM32F732IE, STM32F732ZE, STM32F732VE, STM32F732RE Devices */
|
||||
/* #define STM32F733xx */ /*!< STM32F733IE, STM32F733ZE, STM32F733VE Devices */
|
||||
/* #define STM32F730xx */ /*!< STM32F730R, STM32F730V, STM32F730Z, STM32F730I Devices */
|
||||
/* #define STM32F750xx */ /*!< STM32F750V, STM32F750Z, STM32F750N Devices */
|
||||
#endif
|
||||
|
||||
/* Tip: To avoid modifying this file each time you need to switch between these
|
||||
devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if !defined (USE_HAL_DRIVER)
|
||||
/**
|
||||
* @brief Comment the line below if you will not use the peripherals drivers.
|
||||
In this case, these drivers will not be included and the application code will
|
||||
be based on direct access to peripherals registers
|
||||
*/
|
||||
/*#define USE_HAL_DRIVER */
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.2.8
|
||||
*/
|
||||
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
|
||||
#define __STM32F7_CMSIS_VERSION_SUB2 (0x08) /*!< [15:8] sub2 version */
|
||||
#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|
||||
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|
||||
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
|
||||
|(__STM32F7_CMSIS_VERSION_RC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Device_Included
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32F722xx)
|
||||
#include "stm32f722xx.h"
|
||||
#elif defined(STM32F723xx)
|
||||
#include "stm32f723xx.h"
|
||||
#elif defined(STM32F732xx)
|
||||
#include "stm32f732xx.h"
|
||||
#elif defined(STM32F733xx)
|
||||
#include "stm32f733xx.h"
|
||||
#elif defined(STM32F756xx)
|
||||
#include "stm32f756xx.h"
|
||||
#elif defined(STM32F746xx)
|
||||
#include "stm32f746xx.h"
|
||||
#elif defined(STM32F745xx)
|
||||
#include "stm32f745xx.h"
|
||||
#elif defined(STM32F765xx)
|
||||
#include "stm32f765xx.h"
|
||||
#elif defined(STM32F767xx)
|
||||
#include "stm32f767xx.h"
|
||||
#elif defined(STM32F769xx)
|
||||
#include "stm32f769xx.h"
|
||||
#elif defined(STM32F777xx)
|
||||
#include "stm32f777xx.h"
|
||||
#elif defined(STM32F779xx)
|
||||
#include "stm32f779xx.h"
|
||||
#elif defined(STM32F730xx)
|
||||
#include "stm32f730xx.h"
|
||||
#elif defined(STM32F750xx)
|
||||
#include "stm32f750xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
RESET = 0U,
|
||||
SET = !RESET
|
||||
} FlagStatus, ITStatus;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DISABLE = 0U,
|
||||
ENABLE = !DISABLE
|
||||
} FunctionalState;
|
||||
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
|
||||
|
||||
typedef enum
|
||||
{
|
||||
SUCCESS = 0U,
|
||||
ERROR = !SUCCESS
|
||||
} ErrorStatus;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
|
||||
|
||||
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
|
||||
|
||||
#define READ_BIT(REG, BIT) ((REG) & (BIT))
|
||||
|
||||
#define CLEAR_REG(REG) ((REG) = (0x0))
|
||||
|
||||
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
|
||||
|
||||
#define READ_REG(REG) ((REG))
|
||||
|
||||
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
|
||||
|
||||
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
|
||||
|
||||
/* Use of CMSIS compiler intrinsics for register exclusive access */
|
||||
/* Atomic 32-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SET_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEAR_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 32-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint32_t val; \
|
||||
do { \
|
||||
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to set one or several bits */
|
||||
#define ATOMIC_SETH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear one or several bits */
|
||||
#define ATOMIC_CLEARH_BIT(REG, BIT) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/* Atomic 16-bit register access macro to clear and set one or several bits */
|
||||
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
|
||||
do { \
|
||||
uint16_t val; \
|
||||
do { \
|
||||
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
|
||||
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
|
||||
} while(0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef USE_HAL_DRIVER
|
||||
#include "stm32f7xx_hal.h"
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif /* __cplusplus */
|
||||
|
||||
#endif /* __STM32F7xx_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
105
numworks_port/src/device/system_stm32f7xx.h
Normal file
105
numworks_port/src/device/system_stm32f7xx.h
Normal file
@ -0,0 +1,105 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file system_stm32f7xx.h
|
||||
* @author MCD Application Team
|
||||
* @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* Copyright (c) 2016 STMicroelectronics.
|
||||
* All rights reserved.
|
||||
*
|
||||
* This software is licensed under terms that can be found in the LICENSE file
|
||||
* in the root directory of this software component.
|
||||
* If no LICENSE file comes with this software, it is provided AS-IS.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32f7xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Define to prevent recursive inclusion
|
||||
*/
|
||||
#ifndef __SYSTEM_STM32F7XX_H
|
||||
#define __SYSTEM_STM32F7XX_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Variables
|
||||
* @{
|
||||
*/
|
||||
/* The SystemCoreClock variable is updated in three ways:
|
||||
1) by calling CMSIS function SystemCoreClockUpdate()
|
||||
2) by calling HAL API function HAL_RCC_GetSysClockFreq()
|
||||
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
|
||||
Note: If you use this function to configure the system clock; then there
|
||||
is no need to call the 2 first functions listed above, since SystemCoreClock
|
||||
variable is updated automatically.
|
||||
*/
|
||||
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||
|
||||
extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
||||
extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32F7xx_System_Exported_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__SYSTEM_STM32F7XX_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
130
numworks_port/src/info_headers.cpp
Normal file
130
numworks_port/src/info_headers.cpp
Normal file
@ -0,0 +1,130 @@
|
||||
#include <assert.h>
|
||||
#include <cstdint>
|
||||
#include <stddef.h>
|
||||
|
||||
#define byte4 0xFF, 0xFF, 0xFF, 0xFF
|
||||
#define byte8 byte4, byte4
|
||||
#define byte16 byte8, byte8
|
||||
#define byte32 byte16, byte16
|
||||
#define byte64 byte32, byte32
|
||||
#define byte128 byte64, byte64
|
||||
#define byte256 byte128, byte128
|
||||
#define byte512 byte256, byte256
|
||||
#define byte1K byte512, byte512
|
||||
#define byte2K byte1K, byte1K
|
||||
#define byte4K byte2K, byte2K
|
||||
|
||||
#define EXAM_BUFFER_CONTENT byte4K
|
||||
|
||||
constexpr static int ExamModeBufferSize = 4*1024;
|
||||
|
||||
uint32_t staticStorageArea = {0};
|
||||
|
||||
class KernelHeader {
|
||||
public:
|
||||
constexpr KernelHeader() :
|
||||
m_header(Magic),
|
||||
m_version{"0.0.0"},
|
||||
m_patchLevel{"zeta"},
|
||||
m_footer(Magic) { }
|
||||
const char * version() const {
|
||||
assert(m_header == Magic);
|
||||
assert(m_footer == Magic);
|
||||
return m_version;
|
||||
}
|
||||
const char * patchLevel() const {
|
||||
assert(m_header == Magic);
|
||||
assert(m_footer == Magic);
|
||||
return m_patchLevel;
|
||||
}
|
||||
private:
|
||||
constexpr static uint32_t Magic = 0xDEC00DF0;
|
||||
uint32_t m_header;
|
||||
const char m_version[8];
|
||||
const char m_patchLevel[8];
|
||||
uint32_t m_footer;
|
||||
};
|
||||
|
||||
class UserlandHeader {
|
||||
public:
|
||||
constexpr UserlandHeader():
|
||||
m_header(Magic),
|
||||
m_expectedEpsilonVersion{"0.0.1"},
|
||||
m_storageAddressRAM(0x20000AE8),
|
||||
m_storageSizeRAM(0x0000EA60),
|
||||
m_externalAppsFlashStart(0xFFFFFFFF),
|
||||
m_externalAppsFlashEnd(0xFFFFFFFF),
|
||||
m_externalAppsRAMStart(0xFFFFFFFF),
|
||||
m_externalAppsRAMEnd(0xFFFFFFFF),
|
||||
m_footer(Magic),
|
||||
m_omegaMagicHeader(OmegaMagic),
|
||||
m_omegaVersion{"0.0.2"},
|
||||
m_username{"Ayabusa"},
|
||||
|
||||
m_omegaMagicFooter(OmegaMagic),
|
||||
m_upsilonMagicHeader(UpsilonMagic),
|
||||
m_UpsilonVersion{"0.0.3"},
|
||||
m_osType(OSType),
|
||||
m_upsilonMagicFooter(UpsilonMagic) { }
|
||||
|
||||
const char * omegaVersion() const {
|
||||
assert(m_header == Magic);
|
||||
assert(m_footer == Magic);
|
||||
assert(m_omegaMagicHeader == OmegaMagic);
|
||||
assert(m_omegaMagicFooter == OmegaMagic);
|
||||
return m_omegaVersion;
|
||||
}
|
||||
const char * upsilonVersion() const {
|
||||
assert(m_header == Magic);
|
||||
assert(m_footer == Magic);
|
||||
assert(m_omegaMagicHeader == OmegaMagic);
|
||||
assert(m_omegaMagicFooter == OmegaMagic);
|
||||
return m_UpsilonVersion;
|
||||
}
|
||||
const volatile char * username() const volatile {
|
||||
assert(m_header == Magic);
|
||||
assert(m_footer == Magic);
|
||||
assert(m_omegaMagicHeader == OmegaMagic);
|
||||
assert(m_omegaMagicFooter == OmegaMagic);
|
||||
return m_username;
|
||||
}
|
||||
const void * storage_address() const {
|
||||
return &staticStorageArea;
|
||||
}
|
||||
|
||||
private:
|
||||
constexpr static uint32_t Magic = 0xDEC0EDFE; // FEEDCODE in hex editor
|
||||
constexpr static uint32_t OmegaMagic = 0xEFBEADDE; // DEADBEEF in hex editor
|
||||
constexpr static uint32_t UpsilonMagic = 0x55707369; // Upsi (reverse) in hex editor (ASCII)
|
||||
constexpr static uint32_t OSType = 0x79827178;
|
||||
uint32_t m_header;
|
||||
const char m_expectedEpsilonVersion[8];
|
||||
uint32_t m_storageAddressRAM;
|
||||
uint32_t m_storageSizeRAM;
|
||||
/* We store the range addresses of external apps memory because storing the
|
||||
* size is complicated due to c++11 constexpr. */
|
||||
uint32_t m_externalAppsFlashStart;
|
||||
uint32_t m_externalAppsFlashEnd;
|
||||
uint32_t m_externalAppsRAMStart;
|
||||
uint32_t m_externalAppsRAMEnd;
|
||||
uint32_t m_footer;
|
||||
uint32_t m_omegaMagicHeader;
|
||||
const char m_omegaVersion[16];
|
||||
const volatile char m_username[16];
|
||||
uint32_t m_omegaMagicFooter;
|
||||
uint32_t m_upsilonMagicHeader;
|
||||
const char m_UpsilonVersion[16];
|
||||
uint32_t m_osType;
|
||||
uint32_t m_upsilonMagicFooter;
|
||||
};
|
||||
|
||||
// kernel header defined in linker
|
||||
const KernelHeader __attribute__((section(".kernel_header"), used)) k_kernelHeader;
|
||||
// userland header defined in linker
|
||||
const UserlandHeader __attribute__((section(".userland_header"), used)) k_userlandHeader;
|
||||
|
||||
// Exam mode defined in linker
|
||||
char ones[ExamModeBufferSize]
|
||||
__attribute__((section(".exam_mode_buffer")))
|
||||
__attribute__((used))
|
||||
= {EXAM_BUFFER_CONTENT};
|
||||
151
numworks_port/src/linker.ld
Normal file
151
numworks_port/src/linker.ld
Normal file
@ -0,0 +1,151 @@
|
||||
/* Label for the program's entry point */
|
||||
/*ENTRY(reset_handler)*/
|
||||
/* End of RAM / Start of stack */
|
||||
/* (4KB SRAM) */
|
||||
_estack = 0x20262144;
|
||||
|
||||
/* epsilon stuff */
|
||||
STACK_SIZE = 32K;
|
||||
FIRST_FLASH_SECTOR_SIZE = 4K;
|
||||
SIGNED_PAYLOAD_LENGTH = 8;
|
||||
USERLAND_OFFSET = 64K;
|
||||
|
||||
/* Set minimum size for stack and dynamic memory. */
|
||||
/* (The linker will generate an error if there is
|
||||
* less than this much RAM leftover.) */
|
||||
/* (1KB) */
|
||||
_Min_Leftover_RAM = 0x400;
|
||||
MEMORY
|
||||
{
|
||||
FLASH ( rx ) : ORIGIN = 0x90400000, LENGTH = 4M /* This is for the B slot */
|
||||
RAM ( rxw ) : ORIGIN = 0x20000000, LENGTH = 256K
|
||||
}
|
||||
SECTIONS
|
||||
{
|
||||
/* epsilon stuff */
|
||||
.signed_payload_prefix ORIGIN(FLASH) : {
|
||||
FILL(0xFF);
|
||||
BYTE(0xFF)
|
||||
. = ORIGIN(FLASH) + SIGNED_PAYLOAD_LENGTH;
|
||||
} >FLASH
|
||||
|
||||
.kernel_header : {
|
||||
KEEP(*(.kernel_header))
|
||||
} >FLASH
|
||||
|
||||
.slot_info : {
|
||||
*(.slot_info*)
|
||||
} >RAM
|
||||
|
||||
/* The vector table goes at the start of flash. */
|
||||
.isr_vector_table ORIGIN(RAM) + 512 : AT(ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header)) {
|
||||
/* When booting, the STM32F412 fetches the content of address 0x0, and
|
||||
* extracts from it various key infos: the initial value of the PC register
|
||||
* (program counter), the initial value of the stack pointer, and various
|
||||
* entry points to interrupt service routines. This data is called the ISR
|
||||
* vector table.
|
||||
*
|
||||
* Note that address 0x0 is always an alias. It points to the beginning of
|
||||
* Flash, SRAM, or integrated bootloader depending on the boot mode chosen.
|
||||
* (This mode is chosen by setting the BOOTn pins on the chip).
|
||||
*
|
||||
* We're generating the ISR vector table in code because it's very
|
||||
* convenient: using function pointers, we can easily point to the service
|
||||
* routine for each interrupt. */
|
||||
_isr_vector_table_start_flash = LOADADDR(.isr_vector_table);
|
||||
_isr_vector_table_start_ram = .;
|
||||
KEEP(*(.isr_vector_table))
|
||||
_isr_vector_table_end_ram = .;
|
||||
} >RAM
|
||||
|
||||
.exam_mode_buffer ORIGIN(FLASH) + SIZEOF(.signed_payload_prefix) + SIZEOF(.kernel_header) + SIZEOF(.isr_vector_table) : {
|
||||
. = ALIGN(4K);
|
||||
_exam_mode_buffer_start = .;
|
||||
KEEP(*(.exam_mode_buffer))
|
||||
/* Note: We don't increment "." here, we set it. */
|
||||
. = . + FIRST_FLASH_SECTOR_SIZE;
|
||||
_exam_mode_buffer_end = .;
|
||||
} >FLASH
|
||||
|
||||
/* External flash memory */
|
||||
.userland_header : {
|
||||
. = ORIGIN(FLASH) + USERLAND_OFFSET;
|
||||
KEEP(*(.userland_header));
|
||||
} > FLASH
|
||||
|
||||
.text : {
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
} >FLASH
|
||||
/* The 'rodata' section contains read-only data,
|
||||
* constants, strings, information that won't change. */
|
||||
.rodata : {
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
} >FLASH
|
||||
|
||||
/* The 'data' section is space set aside in RAM for
|
||||
* things like variables, which can change. */
|
||||
.data : {
|
||||
/* The data section is written to Flash but linked as if it were in RAM.
|
||||
*
|
||||
* This is required because its initial value matters (so it has to be in
|
||||
* persistant memory in the first place), but it is a R/W area of memory
|
||||
* so it will have to live in RAM upon execution (in linker lingo, that
|
||||
* translates to the data section having a LMA in Flash and a VMA in RAM).
|
||||
*
|
||||
* This means we'll have to copy it from Flash to RAM on initialization.
|
||||
* To do this, we'll need to know the source location of the data section
|
||||
* (in Flash), the target location (in RAM), and the size of the section.
|
||||
* That's why we're defining three symbols that we'll use in the initial-
|
||||
* -ization routine. */
|
||||
. = ALIGN(4);
|
||||
_data_section_start_flash = LOADADDR(.data);
|
||||
_data_section_start_ram = .;
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
_data_section_end_ram = .;
|
||||
} >RAM AT> FLASH
|
||||
|
||||
/* The 'bss' section is similar to the 'data' section,
|
||||
* but its space is initialized to all 0s at the
|
||||
* start of the program. */
|
||||
.bss : {
|
||||
/* The bss section contains data for all uninitialized variables
|
||||
* So like the .data section, it will go in RAM, but unlike the data section
|
||||
* we don't care at all about an initial value.
|
||||
*
|
||||
* Before execution, crt0 will erase that section of memory though, so we'll
|
||||
* need pointers to the beginning and end of this section. */
|
||||
. = ALIGN(4);
|
||||
_bss_section_start_ram = .;
|
||||
*(.bss)
|
||||
*(.bss.*)
|
||||
/* The compiler may choose to allocate uninitialized global variables as
|
||||
* COMMON blocks. This can be disabled with -fno-common if needed. */
|
||||
*(COMMON)
|
||||
_bss_section_end_ram = .;
|
||||
} >RAM
|
||||
|
||||
.heap : {
|
||||
_heap_start = .;
|
||||
/* Note: We don't increment "." here, we set it. */
|
||||
. = (ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE);
|
||||
_heap_end = .;
|
||||
} >RAM
|
||||
|
||||
.stack : {
|
||||
. = ALIGN(8);
|
||||
_stack_end = .;
|
||||
. += (STACK_SIZE - 8);
|
||||
. = ALIGN(8);
|
||||
_stack_start = .;
|
||||
} >RAM
|
||||
|
||||
/DISCARD/ : {
|
||||
/* exidx and extab are needed for unwinding, which we don't use */
|
||||
*(.ARM.exidx*)
|
||||
*(.ARM.extab*)
|
||||
}
|
||||
}
|
||||
21
numworks_port/src/main.c.BAK
Normal file
21
numworks_port/src/main.c.BAK
Normal file
@ -0,0 +1,21 @@
|
||||
#include "main.h"
|
||||
|
||||
/* Main program. */
|
||||
int main(void) {
|
||||
// Enable the GPIOa and GPIOC peripheral in RCC.
|
||||
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOBEN ;
|
||||
|
||||
// C0 is connected to the LED
|
||||
// It should be set to push-pull low-speed output.
|
||||
GPIOB->MODER &= ~(0x3 << (LED_PIN*2));
|
||||
GPIOB->MODER |= (0x1 << (LED_PIN*2));
|
||||
GPIOB->OTYPER &= ~(1 << LED_PIN);
|
||||
|
||||
// set the led on
|
||||
GPIOB->ODR = (1 << LED_PIN);
|
||||
while (0)
|
||||
{
|
||||
GPIOB->ODR = (1 << LED_PIN);
|
||||
}
|
||||
|
||||
}
|
||||
7
numworks_port/src/main.h.BAK
Normal file
7
numworks_port/src/main.h.BAK
Normal file
@ -0,0 +1,7 @@
|
||||
#ifndef _VVC_MAIN_H
|
||||
#define _VVC_MAIN_H
|
||||
#include <stdint.h>
|
||||
#include "device/stm32f730xx.h"
|
||||
// Define GPIOB pin mappings for our LED and button.
|
||||
#define LED_PIN (3) // led on PC0
|
||||
#endif
|
||||
59
numworks_port/src/rt0.cpp
Normal file
59
numworks_port/src/rt0.cpp
Normal file
@ -0,0 +1,59 @@
|
||||
#include "vector_table.h"
|
||||
#include <stddef.h>
|
||||
|
||||
typedef void (*cxx_constructor)();
|
||||
|
||||
extern "C" {
|
||||
extern char _data_section_start_flash;
|
||||
extern char _data_section_start_ram;
|
||||
extern char _data_section_end_ram;
|
||||
extern char _bss_section_start_ram;
|
||||
extern char _bss_section_end_ram;
|
||||
extern cxx_constructor _init_array_start;
|
||||
extern cxx_constructor _init_array_end;
|
||||
}
|
||||
|
||||
|
||||
void* memcpy_custom(void* destination, const void* source, size_t num_bytes) {
|
||||
char* dest_ptr = (char*)destination;
|
||||
const char* src_ptr = (const char*)source;
|
||||
|
||||
// Copy each byte from source to destination
|
||||
for (size_t i = 0; i < num_bytes; ++i) {
|
||||
dest_ptr[i] = src_ptr[i];
|
||||
}
|
||||
|
||||
return destination;
|
||||
}
|
||||
|
||||
void* memset_custom(void* ptr, int value, size_t num_bytes) {
|
||||
unsigned char* p = (unsigned char*)ptr;
|
||||
unsigned char v = (unsigned char)value;
|
||||
|
||||
// Set each byte in the memory block to the specified value
|
||||
for (size_t i = 0; i < num_bytes; ++i) {
|
||||
p[i] = v;
|
||||
}
|
||||
|
||||
return ptr;
|
||||
}
|
||||
|
||||
void __attribute__((noinline)) start() {
|
||||
/* Copy data section to RAM
|
||||
* The data section is R/W but its initialization value matters. It's stored
|
||||
* in Flash, but linked as if it were in RAM. Now's our opportunity to copy
|
||||
* it. Note that until then the data section (e.g. global variables) contains
|
||||
* garbage values and should not be used. */
|
||||
size_t dataSectionLength = (&_data_section_end_ram - &_data_section_start_ram);
|
||||
memcpy_custom(&_data_section_start_ram, &_data_section_start_flash, dataSectionLength);
|
||||
|
||||
/* Zero-out the bss section in RAM
|
||||
* Until we do, any uninitialized global variable will be unusable. */
|
||||
size_t bssSectionLength = (&_bss_section_end_ram - &_bss_section_start_ram);
|
||||
memset_custom(&_bss_section_start_ram, 0, bssSectionLength);
|
||||
|
||||
while (0)
|
||||
{
|
||||
/* code */
|
||||
}
|
||||
}
|
||||
129
numworks_port/src/vector_table.cpp
Normal file
129
numworks_port/src/vector_table.cpp
Normal file
@ -0,0 +1,129 @@
|
||||
#include "vector_table.h"
|
||||
extern const void * _estack;
|
||||
|
||||
/* Interrupt Service Routines are void->void functions */
|
||||
typedef void(*ISR)(void);
|
||||
|
||||
/* Notice: The Cortex-M4 expects all jumps to be made at an odd address when
|
||||
* jumping to Thumb code. For example, if you want to execute Thumb code at
|
||||
* address 0x100, you'll have to jump to 0x101. Luckily, this idiosyncrasy is
|
||||
* properly handled by the C compiler that will generate proper addresses when
|
||||
* using function pointers. */
|
||||
|
||||
#define INITIALISATION_VECTOR_SIZE 0x71
|
||||
|
||||
ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
|
||||
__attribute__((section(".isr_vector_table")))
|
||||
__attribute__((used))
|
||||
= {
|
||||
(ISR)&_estack, // Stack start
|
||||
start, // Reset service routine,
|
||||
0, // NMI service routine,
|
||||
0, // HardFault service routine,
|
||||
0, // MemManage service routine,
|
||||
0, // BusFault service routine,
|
||||
0, // UsageFault service routine,
|
||||
0, 0, 0, 0, // Reserved
|
||||
0, // SVCall service routine,
|
||||
0, // DebugMonitor service routine,
|
||||
0, // Reserved
|
||||
0, // PendSV service routine,
|
||||
0, // SysTick service routine
|
||||
0, // WWDG service routine
|
||||
0, // PVD service routine
|
||||
0, // TampStamp service routine
|
||||
0, // RtcWakeup service routine
|
||||
0, // Flash service routine
|
||||
0, // RCC service routine
|
||||
0, // EXTI0 service routine
|
||||
0, // EXTI1 service routine
|
||||
0, // EXTI2 service routine
|
||||
0, // EXTI3 service routine
|
||||
0, // EXTI4 service routine
|
||||
0, // DMA1Stream0 service routine
|
||||
0, // DMA1Stream1 service routine
|
||||
0, // DMA1Stream2 service routine
|
||||
0, // DMA1Stream3 service routine
|
||||
0, // DMA1Stream4 service routine
|
||||
0, // DMA1Stream5 service routine
|
||||
0, // DMA1Stream6 service routine
|
||||
0, // ADC1 global interrupt
|
||||
0, // CAN1 TX interrupt
|
||||
0, // CAN1 RX0 interrupt
|
||||
0, // CAN1 RX1 interrupt
|
||||
0, // CAN1 SCE interrupt
|
||||
0, // EXTI Line[9:5] interrupts
|
||||
0, // TIM1 Break interrupt and TIM9 global interrupt
|
||||
0, // TIM1 update interrupt and TIM10 global interrupt
|
||||
0, // TIM1 Trigger & Commutation interrupts and TIM11 global interrupt
|
||||
0, // TIM1 Capture Compare interrupt
|
||||
0, // TIM2 global interrupt
|
||||
0, // TIM3 global interrupt
|
||||
0, // TIM4 global interrupt
|
||||
0, // I2C1 global event interrupt
|
||||
0, // I2C1 global error interrupt
|
||||
0, // I2C2 global event interrupt
|
||||
0, // I2C2 global error interrupt
|
||||
0, // SPI1 global interrupt
|
||||
0, // SPI2 global interrupt
|
||||
0, // USART1 global interrupt
|
||||
0, // USART2 global interrupt
|
||||
0, // USART3 global interrupt
|
||||
0, // EXTI Line[15:10] interrupts
|
||||
0, // EXTI Line 17 interrupt RTC Alarms (A and B) through EXTI line interrupt
|
||||
0, // EXTI Line 18 interrupt / USB On-The-Go FS Wakeup through EXTI line interrupt
|
||||
0, // TIM8 Break interrupt TIM12 global interrupt
|
||||
0, // TIM8 Update interrupt TIM13 global interrupt
|
||||
0, // TIM8 Trigger & Commutation interrupt TIM14 global interrupt
|
||||
0, // TIM8 Cap/Com interrupt
|
||||
0, // DMA1 global interrupt Channel 7
|
||||
0, // FSMC global interrupt
|
||||
0, // SDIO global interrupt
|
||||
0, // TIM5 global interrupt
|
||||
0, // SPI3 global interrupt
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // TIM6 global interrupt
|
||||
0, // TIM7 global interrupt
|
||||
0, // DMA2 Stream0 global interrupt
|
||||
0, // DMA2 Stream1 global interrupt
|
||||
0, // DMA2 Stream2 global interrupt
|
||||
0, // DMA2 Stream3 global interrupt
|
||||
0, // DMA2 Stream4 global interrupt
|
||||
0, // SD filter0 global interrupt
|
||||
0, // SD filter1 global interrupt
|
||||
0, // CAN2 TX interrupt
|
||||
0, // BXCAN2 RX0 interrupt
|
||||
0, // BXCAN2 RX1 interrupt
|
||||
0, // CAN2 SCE interrupt
|
||||
0, // USB On The Go FS global interrupt
|
||||
0, // DMA2 Stream5 global interrupts
|
||||
0, // DMA2 Stream6 global interrupt
|
||||
0, // DMA2 Stream7 global interrupt
|
||||
0, // USART6 global interrupt
|
||||
0, // I2C3 event interrupt
|
||||
0, // I2C3 error interrupt
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // RNG global interrupt
|
||||
0, // FPU global interrupt
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // SPI4 global interrupt
|
||||
0, // SPI5 global interrupt
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // Quad-SPI global interrupt
|
||||
0, // ?
|
||||
0, // ?
|
||||
0, // I2CFMP1 event interrupt
|
||||
0 // I2CFMP1 error interrupt
|
||||
};
|
||||
23
numworks_port/src/vector_table.h
Normal file
23
numworks_port/src/vector_table.h
Normal file
@ -0,0 +1,23 @@
|
||||
#ifndef VECTOR_TABLE_H
|
||||
#define VECTOR_TABLE_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void start();
|
||||
void abort();
|
||||
void isr_systick();
|
||||
|
||||
// Fault handlers
|
||||
|
||||
void hard_fault_handler();
|
||||
void mem_fault_handler();
|
||||
void usage_fault_handler();
|
||||
void bus_fault_handler();
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user