mirror of
https://github.com/ayabusa/Numworks-zeta-os.git
synced 2024-11-21 18:53:24 +00:00
made this shitty clock work
This commit is contained in:
parent
f597ef0805
commit
7a2ef6a22c
@ -13,13 +13,11 @@ This is a bare metal os attempt on the numworks n0110
|
|||||||
- [x] Working thing
|
- [x] Working thing
|
||||||
- [x] Led interface
|
- [x] Led interface
|
||||||
- [x] Keyboard interface
|
- [x] Keyboard interface
|
||||||
- [ ] Set clock and all
|
- [x] Set clock and all
|
||||||
- [ ] adapt ms_wait() and us_wait()
|
- [x] adapt ms_wait() and us_wait()
|
||||||
- [ ] Screen interface
|
- [ ] Screen interface
|
||||||
- [ ] UI toolkit
|
- [ ] UI toolkit
|
||||||
- [ ] set pixel
|
- [ ] set pixel
|
||||||
- [ ] text display
|
- [ ] text display
|
||||||
- [ ] fill rect
|
- [ ] fill rect
|
||||||
- [ ] image display
|
- [ ] image display
|
||||||
- [ ] File system
|
|
||||||
- [ ] Plan what to do
|
|
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -54,8 +54,32 @@ void init_clock(){
|
|||||||
* wait a little bit.
|
* wait a little bit.
|
||||||
* The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */
|
* The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */
|
||||||
// clear in first place
|
// clear in first place
|
||||||
FLASH->ACR &= ~(0b0000 0000 0000 0000
|
FLASH->ACR &= ~(FLASH_ACR_LATENCY_Msk | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
|
||||||
0000 0011 0000 1111);
|
FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
|
||||||
|
|
||||||
|
// 192MHz is too fast for both APB1 and APB2 so we divide them
|
||||||
|
// firstly we clear
|
||||||
|
RCC->CFGR &= ~(0b00000000000000001111110000000000);
|
||||||
|
/* Then we set
|
||||||
|
* PPRE1 = 4 = 100
|
||||||
|
* PPRE2 = 2 = 10 */
|
||||||
|
RCC->CFGR |= 0b00000000000000001001010000000000;
|
||||||
|
|
||||||
|
// We now wait for PLLRDY
|
||||||
|
while (!(RCC->CR & RCC_CR_PLLRDY)) {};
|
||||||
|
|
||||||
|
// We select PLL output as a SYSCLK source
|
||||||
|
RCC->CFGR |= RCC_CFGR_SW_PLL;
|
||||||
|
// And wait for it !!!
|
||||||
|
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {};
|
||||||
|
|
||||||
|
// We can now disable HSI
|
||||||
|
RCC->CR &= ~(RCC_CR_HSION);
|
||||||
|
|
||||||
|
// Set normal speed
|
||||||
|
RCC->CFGR &= ~(RCC_CFGR_HPRE_Msk);
|
||||||
|
|
||||||
|
set_led_green(true);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* OLD
|
/* OLD
|
||||||
|
@ -9,11 +9,7 @@
|
|||||||
|
|
||||||
#include "stdint.h"
|
#include "stdint.h"
|
||||||
#include "../device/stm32f730xx.h"
|
#include "../device/stm32f730xx.h"
|
||||||
|
#include "led.h"
|
||||||
#define PLL_N 384
|
|
||||||
#define PLL_M 8
|
|
||||||
#define PLL_P 2
|
|
||||||
#define PLL_Q 8
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/
|
RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/
|
||||||
|
@ -8,7 +8,7 @@
|
|||||||
#define TIME_H
|
#define TIME_H
|
||||||
|
|
||||||
#define loops_per_microsecond 1
|
#define loops_per_microsecond 1
|
||||||
#define loops_per_millisecond 960
|
#define loops_per_millisecond 12000
|
||||||
|
|
||||||
#include "stdint.h"
|
#include "stdint.h"
|
||||||
|
|
||||||
|
@ -33,9 +33,9 @@ void main_entry(){
|
|||||||
set_led_red(false);
|
set_led_red(false);
|
||||||
}*/
|
}*/
|
||||||
|
|
||||||
set_led_red(true);
|
set_led_blue(true);
|
||||||
ms_wait(5000);
|
ms_wait(5000);
|
||||||
set_led_red(false);
|
set_led_blue(false);
|
||||||
ms_wait(5000);
|
ms_wait(5000);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user