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https://github.com/ayabusa/Numworks-zeta-os.git
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made this shitty clock work
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@ -13,13 +13,11 @@ This is a bare metal os attempt on the numworks n0110
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- [x] Working thing
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- [x] Led interface
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- [x] Keyboard interface
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- [ ] Set clock and all
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- [ ] adapt ms_wait() and us_wait()
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- [x] Set clock and all
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- [x] adapt ms_wait() and us_wait()
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- [ ] Screen interface
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- [ ] UI toolkit
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- [ ] set pixel
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- [ ] text display
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- [ ] fill rect
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- [ ] image display
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- [ ] File system
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- [ ] Plan what to do
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@ -54,8 +54,32 @@ void init_clock(){
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* wait a little bit.
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* The spec tells us that at 2.8V and over 210MHz the flash expects 7 WS. */
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// clear in first place
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FLASH->ACR &= ~(0b0000 0000 0000 0000
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0000 0011 0000 1111);
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FLASH->ACR &= ~(FLASH_ACR_LATENCY_Msk | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
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FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | FLASH_ACR_PRFTEN | FLASH_ACR_ARTEN);
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// 192MHz is too fast for both APB1 and APB2 so we divide them
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// firstly we clear
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RCC->CFGR &= ~(0b00000000000000001111110000000000);
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/* Then we set
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* PPRE1 = 4 = 100
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* PPRE2 = 2 = 10 */
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RCC->CFGR |= 0b00000000000000001001010000000000;
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// We now wait for PLLRDY
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while (!(RCC->CR & RCC_CR_PLLRDY)) {};
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// We select PLL output as a SYSCLK source
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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// And wait for it !!!
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {};
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// We can now disable HSI
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RCC->CR &= ~(RCC_CR_HSION);
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// Set normal speed
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RCC->CFGR &= ~(RCC_CFGR_HPRE_Msk);
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set_led_green(true);
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}
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/* OLD
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@ -9,11 +9,7 @@
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#include "stdint.h"
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#include "../device/stm32f730xx.h"
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#define PLL_N 384
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#define PLL_M 8
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#define PLL_P 2
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#define PLL_Q 8
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#include "led.h"
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/*
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RCC->PLLCFGR |= 0b00001000010000100110000000001000; // HSE: 8MHz*/
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@ -8,7 +8,7 @@
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#define TIME_H
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#define loops_per_microsecond 1
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#define loops_per_millisecond 960
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#define loops_per_millisecond 12000
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#include "stdint.h"
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@ -33,9 +33,9 @@ void main_entry(){
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set_led_red(false);
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}*/
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set_led_red(true);
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set_led_blue(true);
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ms_wait(5000);
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set_led_red(false);
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set_led_blue(false);
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ms_wait(5000);
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}
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