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Started rewrite of the clock (broken)

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ayabusa 2024-04-18 20:31:28 +02:00
parent ee23bf80fd
commit a1182a3193
4 changed files with 31 additions and 6 deletions
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numworks_port/build/Laplace/clock.o
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numworks_port/build/main.bin
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numworks_port/build/main.elf
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33
numworks_port/src/Laplace/clock.c
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@ -2,11 +2,38 @@
/* This should set the speed to 216MHz intead of just 48MHz */ /* This should set the speed to 216MHz intead of just 48MHz */
void init_clock(){ void init_clock(){
// Enable the HSI and wait for it to be ready to use
RCC->CR |= (RCC_CR_HSION);
while (!(RCC->CR & RCC_CR_HSIRDY)) {};
// Enable the HSE and wait for it to be ready to use
RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {};
// enable power interface clock
RCC->APB1ENR |= (RCC_APB1ENR_PWREN);
// SSGR stuf, paragraph taken from upsilon
/* To pass electromagnetic compatibility tests, we activate the Spread
* Spectrum clock generation, which adds jitter to the PLL clock in order to
* "lower peak-energy on the central frequency" and its harmonics.
* It must be done before enabling the PLL. */
/* Modper = 250
* Incstep = 25
* SpreadSel = 0
* SSCGEN = 1 */
RCC->SSCGR = 0b10000000000000110010000011111010;
}
/* OLD
// ACR means flash Access control register // ACR means flash Access control register
FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | // 7 wait states FLASH->ACR |= (FLASH_ACR_LATENCY_7WS | // 7 wait states
FLASH_ACR_PRFTEN | // prefetch on FLASH_ACR_PRFTEN | // prefetch on
FLASH_ACR_ARTEN); // ART on FLASH_ACR_ARTEN); // ART on
FLASH->ACR &= ~(0b00000000000000000000101100001111);
// enables HSE and wait for it to be ready // enables HSE and wait for it to be ready
RCC->CR |= (RCC_CR_HSEON); RCC->CR |= (RCC_CR_HSEON);
while (!(RCC->CR & RCC_CR_HSERDY)) {}; while (!(RCC->CR & RCC_CR_HSERDY)) {};
@ -14,12 +41,10 @@ void init_clock(){
// clear the specified bit // clear the specified bit
// (8/4)*108 = 216MHz // (8/4)*108 = 216MHz
/*
RCC->PLLCFGR |= (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz RCC->PLLCFGR |= (RCC_PLLCFGR_PLLSRC_HSE | // HSE: 8MHz
RCC_PLLCFGR_PLLN_108 | // *108 RCC_PLLCFGR_PLLN_108 | // *108
RCC_PLLCFGR_PLLM_25); // /4 RCC_PLLCFGR_PLLM_25); // /4
*/ RCC->PLLCFGR = 0b00001000010000100110000000001000; // HSE: 8MHz
RCC->PLLCFGR = 0b00001000010000100110000000001000; // HSE: 8MHz*/
// enable the RCC clock and wait for it to be ready // enable the RCC clock and wait for it to be ready
RCC->CR |= (RCC_CR_PLLON); RCC->CR |= (RCC_CR_PLLON);
@ -29,4 +54,4 @@ void init_clock(){
RCC->CFGR &= ~(RCC_CFGR_SW); RCC->CFGR &= ~(RCC_CFGR_SW);
RCC->CFGR |= (RCC_CFGR_SW_PLL); RCC->CFGR |= (RCC_CFGR_SW_PLL);
while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {}; while (!(RCC->CFGR & RCC_CFGR_SWS_PLL)) {};
} */